1
2193A–BDC–06/03
Main Features
•8-bit Resolution
•500 Msps (min) Sampling Rate
•Power Consumption: 3.8W Typ
•500 mVpp Differential or Single-ended Analog Inputs
•Differ enti al or Single-ended 50Ω ECL Compatible Clock Inputs
•ECL or LVDS/HSTL Output Compatibility
•ADC Gain Adjust
•Data Ready Output with Asynchronous Reset
•Gray or Binary Selectable Output Data; NRZ Output Mode
•Enhanced CBGA Packa ge with Ceramic Lid
•Evaluation Board: TSEV83085 00GL (Detai led Spec ifica tion on Reques t)
•Demultiplexer TS81102G0: Companion Device Available
Performance
•1.3 GHz Full Power Input Bandwidth
•Band Flatness: 0.5 dB up to 500 MHz
•SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc
at FS = 500 Msps, FIN = 20 MHz
•SINAD = 43 dB (7.1 Effective Bits), SFDR = 53 dBc
at FS = 500 Msps, FIN = 250 MHz
•SINAD = 42 dB (7.0 Effective Bits), SFDR = 52 dBc
at FS = 500 Msps, FIN = 500 MHz (-3 dB FS)
•2-tone IMD: TBD (199.5 MHz, 200.5 MHz) at 500 Msps
•DNL = ±0.3 LSB INL = ±0.7 LSB
•Low Bit Error Rate (10-13) at 500 Msps, Tj = 90°C
Applications
• Digital Sampling Oscilloscopes
• Satellite Receiver
• Electronic Countermeasures/Electronic Warfare
• Direct RF Down-conversion
Screening
• Atmel Standard Screening Level
• Temperature Range:
–0°C < Tc; Tj < +90°C
–-40°C < Tc ; Tj < + 110°C
Description
The TS8308500 is a monolithic 8-bit analog-to-digital converter, designed for digitizing
wide bandwidth analog signals at very high sampling rates of up to 500 Msps.
The TS830 8500 is usi ng an in novative archite ctur e, includ ing an o n-ch ip Sampl e and
Hold (S/H), and is fabricated with an advanced high-speed bipolar process.
The on-chip S/H has a 1.3 GH z full power input bandwidth, providing excellent
dynamic performance in undersampling applications (High IF digitizing).
ADC 8-bit
500 Msps
TS8308500
Rev. 2193A–BDC–04/03
2TS8308500 2193A–BDC–04/03
Functional
Description
Block Diagram
Figure 1. Simplified Block Diagram
Functional
Description The TS8308500 is an 8-bit 500 Msps ADC based on an advanced high-speed bipolar technol-
ogy featuring a cutoff frequency of 25 GHz.
The TS8308500 includes a front-end master/slave Track and Hold stage (S/H), followed by an
analog encoding stage and interpolation circuitry.
Successive banks of latches are regenerating the analog residues into logical data before
entering an error correction circuitry and a resynchronization stage followed by 75Ω differential
output buff ers.
The TS8308500 works in fully differential mode from analog inputs up to digital outputs.
The TS8308500 features a full-power input bandwidth of 1.3 GHz.
Control pin GORB is provided to select eithe r the Gray or Binary data output for mat.
The gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8308500.
The TS83 08500 us es only ve rtical is olated NPN transis tors toge ther with oxide isol ated pol y-
silicon resistors, whi ch allow enhan ced radiati on tolerance (no perform ance drift meas ured at
150 kRad total dose).
Master/Slave Track & Hold Amplifier
V
IN
, V
INB
Clock
Buffer
GAIN
GORB DATA, DATAB OR, ORB
DRRB DR, DRB
CLK, CLKB
4
45
45
8
8
Resistor
Chain Analog
Encoding
Block
Interpolation
Stages
Regeneration
Latches
Error Correction &
Decode Logic
Output Latches &
Buffers
3
TS8308500
2193A–BDC–04/03
Specifications
Absolute
Maximum Ratings
Note: Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within sp eci fied opera ting co nditions . Lon g ex po su re to max im um rat ing s m ay af fect dev ic e re lia bil ity. The use of a therm al hea t
sink is mandatory (see Thermal characteristics).
Recommended
Conditions of Use
Table 1. Absolute Maximum Ratings
Parameter Symbol Comments Value Unit
Positive supply voltage VCC GND to 6 V
Digital negative supply voltage DVEE GND to -5.7 V
Digital positive supply voltage VPLUSD GND -0.3 to 2.8 V
Negative supply voltage VEE GND to -6 V
Maximum difference between negative supply voltages DVEE to VEE 0.3 V
Analog input voltages VIN or VINB -1 to 1 V
Maximum difference between VIN and VINB VIN - VINB -2 to 2 V
Digital input voltage VDGORB -0.3 to VCC 0.3 V
Digital input voltage VDDRRB VEE -0.3 to 0.9 V
Digital output voltage VOVPLUSD -3 to VPLUSD -0.5 V
Clock input voltage VCLK or VCLKB -3 to 1.5 V
Maximum difference between VCLK and VCLKB VCLK - VCLKB -2 to 2 V
Maximum junction temperature Tj135 °C
Storage temperature Tstg -65 to 150 °C
Lead temperature (soldering 10s) Tleads 300 °C
Table 2. Recommended Conditions of Use
Parameter Symbol Comments
Recommended Value
UnitMin Typ Max
Positive supply voltage VCC 4.75 5 5.25 V
Positive digital supply voltage VPLUSD ECL output compatibility – GND – V
Positive digital supply voltage VPLUSD LVDS output compatibility 1.4 2.4 2.6 V
Negative supply voltages VEE, DVEE -5.25 -5 -4.75 V
Differential analog input voltage
(full-scale) VIN, VINB
VIN - VINB
50Ω differential or single-ended ±113
450 ±125
500 ±137
550 mV
mVpp
Clock input power level PCLK, PCLKB 50Ω single-ended clock input 3 4 10 dBm
Operating temperature range TJCommerci al grade: “C”
Industrial gr ade “ V“ 0 < Tc; Tj < 90
-40 < Tc; Tj < 110 °C
4TS8308500 2193A–BDC–04/03
Electrical
Operating
Characteristics
VEE = DVEE = -5V; VCC = +5V; VIN -VINB = 500 mVpp Full Scale differential input
50Ω differentially terminated digital outputs
Tj (typical) = 70°C
Table 3. Electrical Specifications
Parameter Symbol Test
Level
Value
Unit NoteMin Typ Max
Power Requireme nts
Positive supply voltage Analog
Digital (ECL)
Digital (LVDS)
VCC
VPLUSD
VPLUSD
1
4
4
4.5
–
1.4
5
0
2.4
5.5
–
2.6
V
V
V
Positive supply current Analog
Digital ICC
IPLUSD
1
1–
–420
130 445
145 mA
mA
Negative supply voltage VEE 1 -5.5 -5 -4.5 V
Negative supply current Analog
Digital AIEE
DIEE
1
1–
–185
160 200
180 mA
mA
Nominal power dissipation PD 1 – 3.9 4.1 W
Power supply rejection ratio PSRR 4 – 0.5 2 mW
Resolution ––––8bits
(2)
Analog Inputs
Full-sca le input voltage range (differential mode)
(0V common mode voltage) VIN
VINB
4
–-125
-125 –
–125
125 mV
mV
Full-sca le input voltage range (single-ended input
option) (14) VIN
VINB
4
–-250
––
0250
–mV
mV
Analog input capacitance CIN 4– 33.5pF
Input bias current IIN 4 – 10 20 µA
Input Resistance RIN 40.5 1 – MΩ
Full Power input Bandwidth (-3 dB) FPBW 4 – 1.8 – GHz
Small signal input Bandwidth (10% full-scale) SSBW 4 – 1.7 – GHz
Clock Inputs
Logic comp atib ility for cl ock inputs (14) ––
ECL or specified clock input
power leve l in dBm –(8)
ECL Clock inp uts voltages (VCLK or VCLKB): – 4 – – – –
Logic 0 v oltage VIL –– –-1.5V
Logic 1 v oltage VIH –-1.1 – – V
Logic 0 c urrent IIL –– 550µA
Logic 1 c urrent IIH –– 550µA
Clock input power level into 50Ω termination – – dBm into 50Ω–
5
TS8308500
2193A–BDC–04/03
Clock input power level – 4 -2 4 10 dBm
Clock input capacitance CCLK 4– 33.5pF
Digital Outputs
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), binary output data format,
Tj (typical) = 70°C. Full temperature range: 0°C < Tc; Tj < +90°C or -4 0°C < Tc ; Tj < 110°C
(1)(6)
Logic compatibility for digital outputs
(Depending on the value of VPLUSD) (14) –– ECL or LVDS –
Differential output voltage swings
(assuming VPLUSD = 0V) : –4––––
75Ω open transmission lines (ECL levels) – – 1.5 1.620 – V
75Ω differentially termina t ed – – 0.70 0.825 – V
50Ω differentially termina t ed – – 0.54 0.660 – V
Output levels (assuming VPLUSD = 0V)
75Ω open transmission lines: –4––––
(6)
Logic 0 v oltage VOL ––-1.62-1.54V
Logic 1 v oltage VOH –-0.88-0.8 – V
Output levels (assuming VPLUSD = 0V)
75Ω differenti all y term ina ted : –4––––
(6)
Logic 0 v oltage VOL ––-1.41-1.34V
Logic 1 v oltage VOH –-1.07 -1 – V
Output levels (assuming VPLUSD = 0V)
50Ω differenti all y term ina ted : ––––––
(6)
Logic 0 v oltage VOL 1, 2 – -1.40 -1.32 V
Logic 1 v oltage VOH 1, 2 -1.16 -1.10 – V
Differential Output Swing DOS 4 270 300 – mV
Output level drift with temperature – 4 – – 1.6 mV/°C
DC Accuracy
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
Tj (typical) = 70°C
Differential non linearity DNL- 1 -0.6 -0.4 – lsb/V (2)(3)
Differential non linearity DNL+ 1 – 0.4 0.6 lsb/V
Integr al non linea rity INL- 1 -1.2 -0.7 – lsb/ V (2)(3)
Integral non linearity INL+ 1 – 0.7 1.2 lsb/V
No missing codes – Guaranteed over specified temperature range (3)
Gain – 1, 2 90 98 110 %/V
Input offset voltage – 1, 2 -26 -5 26 mV/V
Table 3. Electrical Specifications (Continued)
Parameter Symbol Test
Level
Value
Unit NoteMin Typ Max
6TS8308500 2193A–BDC–04/03
Gain error drift
Offset error drift –
–4
4100
40 125
50 150
60 ppm/°C
ppm/°C
Transient Performance
Bit error rate
FS = 500 Msps, FIN = 62.5 MHz BER 4 – – 1E-13 Error/
sample (2)(4)
ADC settling time
VIN -VINB = 400 mVpp TS 4 – 0.5 1 ns (2)
Overvo ltage recovery time TOR 4 – 0.5 1 ns (2)
AC Performance
Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), binary output data format,
Tj = 70°C, unless otherwise specified
Signal to noise and distortion ratio SINAD – – – – – (2)
FS = 500 Msps, FIN = 20 MHz – 4 43 45 – dB
FS = 500 Msps, FIN = 500 MHz – 4 42 44 – dB
FS = 500 Msps, FIN = 1000 MHz (-1 dBFS) – 4 38 40 – dB
FS = 50 Msps, FIN = 25 MHz – 1 43 46 – dB
Effective number of bits ENOB – – – – –
FS = 500 Msps, FIN = 20 MHz – 4 7.0 7.2 – Bits
FS = 500 Msps, FIN = 500 MHz – 4 6.8 7.0 – Bits
FS = 500 Msps, FIN = 1000 MHz (-1 dBFS) – 4 6.0 6.3 – Bits
FS = 50 Msps, FIN = 25 MHz – 1 7.0 7.4 – Bits
Signal to noise ratio SNR – – – – – (2)
FS = 500 Msps, FIN = 20 MHz – 4 44 46 – dB
FS = 500 Msps, FIN = 500 MHz – 4 44 45 – dB
FS = 500 Msps, FIN = 1000 MHz (-1 dBFS) – 4 40 43 – dB
FS = 50 Msps, FIN = 25 MHz – 1 44 45 – dB
Total harmonic distortion |THD| – – – – – (2)
FS = 500 Msps, FIN = 20 MHz – 45053 – dB
FS = 500 Msps, FIN = 500 MHz – 4 48 50 – dB
FS = 500 Msps, FIN = 1000 MHz (-1 dBFS) – 4 38 40 – dB
FS = 50 Msps, FIN = 25 MHz – 1 44 54 – dB
Table 3. Electrical Specifications (Continued)
Parameter Symbol Test
Level
Value
Unit NoteMin Typ Max
7
TS8308500
2193A–BDC–04/03
Notes: 1. Differential output buffers are internally loaded by 75Ω resistors. Buffer bias current = 11 mA
2. See “Definition of Terms” on page 46
3. Histogram testing based on sampling of a 10 MHz sinewave at 50 Msps
4. Output error amplitude < ±4 lsb around worst code
5. Maximum jitter value obtained for single-ended clock input on the die (chip on board): 200 fs
6. Digital output back termination options depicted in Application Notes
7. At 500 Msps, 50/50 clock duty cycle, TC2 = 2 ns (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate
8. Specified loading conditions for digital outputs:
- 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated, or unterminated 75Ω controlled impedance traces
- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input
parasitic capacitance of 1.5 pF including package and ESD protections.)
9. Termination load parasitic capacitance derating values:
- 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated: 60 ps/pF or 75 ps per additionnal ECLinPS load
Spurious free dynamic range SFDR – – – – – (2)
FS = 500 Msps, FIN = 20 MHz – 4 50 56 – dBc
FS = 500 Msps, FIN = 500 MHz – 4 50 53 – dBc
FS = 500 Msps, FIN = 1000 MHz (-1 dBFS) – 4 38 40 – dBc
FS = 50 Msps, FIN = 25 MHz – 1 50 55 – dBc
Two-tone inter-modulation distortion IMD 4 – – – – (2)
FIN1 = 199.5 MHz at FS = 500 Msps,
FIN2 = 200.5 MHz at FS = 500 Msps ––-47-52–dBc
Switching Performance and Characteristics – See Figure 2 and Figure 3 on page 9
Maximum clock frequency FS– 500 – 700 Msps (12)
Minimum clock frequency FS410 – 50Msps
(13)
Minimum clock pulse width (high) TC1 4 1.71 2 50 ns
Minimum c lock pulse width (low) TC2 4 1.71 2 5 0 n s
Aperture delay Ta 4 100 +250 400 ps (2)
Aperture uncertainty Jitter 4 – 0.4 0.6 ps (rms) (2)(5)
Data output delay TDO 4 1150 1360 1660 ps (2)(8)
(9)(10)
Output rise/fall ti me for data (20%-80%) TR/TF 4 250 350 550 ps (9)
Output rise/fall ti me for data ready (20%-80%) TR/TF 4 250 350 550 ps (9)
Data ready output delay TDR 4 1110 1320 1620 ps (2)(8)
(9)(10)
Data ready reset delay TRDR 4 – 720 1000 ps
Data to data ready – Clock low pulse width
(See “Timing Diagrams” on page 9) TOD-TDR 4 0 40 80 ps (7)(11)
(12)
Data to data ready output delay (50% duty cycle) at
1 Gsps (See “Timing Diagrams” on page 9) TD1 4 920 960 1000 ps (2)(13)
Data pipeline delay TPD 4 4 clock
cycles
Table 3. Electrical Specifications (Continued)
Parameter Symbol Test
Level
Value
Unit NoteMin Typ Max
8TS8308500 2193A–BDC–04/03
- Unterminat ed (s ou rce term in ate d) 75Ω c ontrolled impedanc e l ine s: 100 ps/pF or 150 ps pe r additionnal ECLin PS term in a-
tion load
10.Apply pr ope r 50 /75 Ω im ped anc e trac es pr opagation time de rati ng va lue s: 6 ps/mm (155 ps /inch) for TSEV830 850 0G L Eva l-
uation Board
11. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100°C te mp era t ure v ar i ati o n).
Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between
each Data TODs and TDR effect can be considered negligible. Consequently, minimum values for TOD and TDR are never
more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about
“TOD-TDR Variation Over Temperature” on page 22).
12.Min value guarantees performance. Max value guarantees functionality
13.Min value guarantees functionality. Max value guarantees performance
14.Refer to product Application Notes
9
TS8308500
2193A–BDC–04/03
T iming Diagrams
Figure 2. TS8308500 Timing Diagram (500 Msps Clock Rate), Data Ready Reset, Clock Held at LOW Level
Figure 3. TS8308500 Timing Diagram (500 Msps Clock Rate), Data Ready Reset, Clock Held at HIGH Level
TC1 TC2
TA = 250 ps
XX
N+1
XN+2
XN+3
N
DIGITAL
OUTPUTS
(VIN, VINB)
Data Ready
(DR, DRB)
(CLK, CLKB)
XN+5
N-4 N-3 N
N-2 N-1
TC = 1000 ps
XX
N+4
TOD = 1360 ps
1360 ps
DRRB 1 ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
1000 ps
TRDR = 720 ps
N-1
TD2 = TC2+TOD-TDR
= TC2+40 ps = 540 ps
TDR = 1320 ps
DATA DATA DATA DATA DATADATA DAT
A
N-5 N+1
TD1 = TC1+TDR-TOD
= TC1-40 ps = 460 ps
TC1 TC2
TA = 250 ps
N+1 N+2 N+3
N
DIGITAL
OUTPUTS
(VIN, VINB)
Data Ready
(DR, DRB)
(CLK, CLKB)
N+5
N-4 N-3 N
N-1N-2
TC = 1000 ps
N+4
TOD = 1360 ps
1360 ps
DRRB
1 ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
TRDR = 720 ps
N-1
TD2 = TC2+TOD-T
D
= TC2+40 ps = 540
TDR = 1320 ps
DATA DATA DATA DATA DATADATA DAT
A
N-5 N+1
1000 ps
XX
X
X
XXX
TD1 = TC1+TDR-TOD
= TC1-40 ps = 460 ps
10 TS8308500 2193A–BDC–04/03
Explanation of
Test Levels
Note: 1. Unl ess ot herwi se spe cif ied, a ll test s a re puls ed test s : t herefore TC = TA where TC and T A are
case and ambient temperature.
2. Refer to “Ordering Information” on page 48.
3. Only min and max values are guaranteed (typical values are issued from characterization
results).
Functions
Description
Table 4. Explanation of Test Levels(3)
Num Characteristics
1 100% production tested at +25°C(1) (for “C” Temperature rang e(2))
2100% production tested at +25°C(1), and sa mple tested at specified temperatures
(for “V” Temperature rang e(2))
3 Sample tested only at specified temperatures
4Parameter is guaranteed by design and characterization testing (thermal steady-state
conditions at specified temperature)
5 Parameter is a typical value only
Table 5. Functions Description
Name Function
VCC Positive power supply
VEE Analog negative power supply
VPLUSD Digital positive power supply
GND Ground
VIN, VINB Differenti al analog inputs
CLK, CLKB Differential clock inputs
<D0:D7>
<D0B:D7B> Differential output da ta port
DR, DRB Differential data ready outputs
OR, ORB Out of range outputs
GAIN ADC gain adjust
GORB Gray or binary digit al out put se lect
DIOD/DRRB Die junction temperature measurement/
asynchronous data ready reset
V
IN
V
INB
CLK
CLKB D0 D7
D0B D7B
16
DVEE = -5V
VCC = +5V VPLUSD = +0V (ECL)
VPLUSD = +2.4V (LVDS)
TS8308500
VEE = -5V GND
GAIN
GORG
DIOD/
DRRB
OR
ORB
DR
DRB
11
TS8308500
2193A–BDC–04/03
Digital Output
Coding NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity volt-
age errors.
Table 6. Digital Output Coding
Differential
Analog Input Voltage Level
Digital Output
Out of
Range
Binary
GORB = VCC or Floating Gray
GORB = GND
> +251 mV > Positive full-sca le + 1/2 LSB 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1
+251 mV
+249 mV Positive full-s cale + 1/2 LSB
Positive full-scale - 1/2 LSB 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 1 0
0
+126 mV
+124 mV Positive 1/2 scale + 1/2 LSB
Positive 1/2 scale - 1/2 LSB 1 1 0 0 0 0 0 0
1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0
1 1 1 0 0 0 0 0 0
0
+1 mV
-1 mV Bipolar zero + 1/2 LSB
Bipolar zero - 1/2 LSB 1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0
0
-124 mV
-126 mV Negative 1/2 scale + 1/2 LSB
Negative 1/2 scale - 1/2 LSB 0 1 0 0 0 0 0 0
0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 0
0 0 1 0 0 0 0 0 0
0
-249 mV
-251 mV Negative full-scale + 1/2 LSB
Negative full-scale - 1/2 LSB 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0
0
< -251 mV < Negative full-scale - 1/2
LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
12 TS8308500 2193A–BDC–04/03
Typical
Characterization
Results
50/50 clock duty cycle, Binary output coding, Tj = 70°C, single-ended analog and clock inputs,
unless otherwise specified.
Static Linearity FS = 50 Msps/FIN = 10 MHz
Figure 4. Integral Non-linearity
Note: Clock frequency = 50 Msps; signal frequency = 10 MHz
Positive peak: -0.68 LSB; Negative peak: -0.69 LSB
Figure 5. Differenti al Non-l ine arity
Note: Clock frequency = 50 Msps; signal frequency = 10 MHz;
Positive peak: 0.3 LSB; negative peak: -0.29 LSB
13
TS8308500
2193A–BDC–04/03
Effective Num b er
of Bits Versus
Power Supply
Variation
Figure 6. Effective Number of Bits = f (VEEA); FS = 500 Msps; FIN = 100 MHz
Figure 7. Effective Number of Bits = f (VCC); FS = 500 Msps; FIN = 100 MHz
Figure 8. Effective Number of Bits = f (VEED); FS = 500 Msps; FIN = 100 MHz
0
1
2
3
4
5
6
7
8
-7 -6.5 -6 -5.5 -5 -4.5 -4
VEEA (V)
ENOB (bits)
0
1
2
3
4
5
6
7
8
3 3.5 4 4.5 5 5.5 6 6.5 7
VCC (V)
ENOB (bits)
0
1
2
3
4
5
6
7
8
-6 -5.5 -5 -4.5 -4 -3.5 -3
VEED (V)
ENOB (bits)
14 TS8308500 2193A–BDC–04/03
Typical FFT
Results
Figure 9. Spectrum for FS = 500 Msps, FIN = 498 MHz (Full Scale Input)
Note: Acquisition of 4096 points; THD = -49.67 dBc; Fs = 500 Msps; SINAD = 44.01 dB; FIN = 498 MHz; SFDR = -54.31 dBc;
SFSR = -0.94 dB; ENOB = 7.13 bits; SNR = 45.39 dB
Figure 10. Reconstructed Signal for FS = 500 Msps, FIN = 498 MHz (Full Scale Input)
Note: Acquisition of 4096 samples; FS = 500 Msps; Amplitude: 0.221V (114.5 LSB); FIN = 498 MHz; Offset: 0V (122.5 LSB)
LSB
250
200
150
100
50
0
01 ns
15
TS8308500
2193A–BDC–04/03
Figure 11. Spectrum for FS = 500 Msps, FIN = 250 MHz (Full Scale Input)
Figure 12. Reconstructed Signal for FS = 500 Msps, FIN = 250 MHz (Full Scale Input)
Note: Acquisition of 4096 samples; FS = 500 Msps ; Amplitude: 0.189V (113.5 LSB); FIN = 250 MHz ; Offset: 0V (122 .5 LSB)
Lsb
250
200
150
100
50
0
0123 ns
16 TS8308500 2193A–BDC–04/03
Dynamic
Performance
Versus Analog
Input Frequency
Figure 13. SFDR: F s = 500 Msps, FIN = 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C
Figure 14. THD: Fs = 500 Msps, FIN = 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C
Figure 15. SINAD and SNR: Fs = 500 Msps, FIN = 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C
SFDR
dBc
60
55
45
50
40 2 100 200 400 500
Fin (MHz)
600 700 800 900 1000300
2 100 200 300 400 500 600 700 800 900 1000
0
-10
-20
-30
-40
-50
-60
Fin (MHz)
THD
dBc
2 100 200 300 400 500 600 700 800 900 1000
36
38
40
42
44
46
48
SINAD SNR
Fin (MHz)
dB
17
TS8308500
2193A–BDC–04/03
Figure 16. Fs = 500 Msps, FIN = 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C
SFDR and THD
Versus Sampling Frequency
Figure 17. Analog Input Frequency: FIN = 250 MHz and Fs = 200 Msps to 1400 Msps
Effective Number of Bits (ENOB)
Versus Sampling Frequency
Figure 18. Analog Input Frequency: FIN = 250 MHz and Fs = 200 Msps to 1400 Msps
2 100 200 300 400 500 600 700 800 900 1000
5,5
6
6,5
7
7,5
Bits
Fin (MHz)
ENOB
200 400 600 800 1000 1200 1400
dBc
THD SFDR
Fs (Msps)
-60
-50
-40
-30
-20
-10
Bits
8
7
6
5
4
3
2
1
ENOB
Fs Msps
200 400 600 800 1000 1200 1400
18 TS8308500 2193A–BDC–04/03
Sinad and SNR
Versus Sampling Frequency
Figure 19. Analog Input Frequency: FIN = 250 MHz and FS = 200 Msps to 1400 Msps
TS83085 00 ADC Performa nces
Versus Junction Temperature
Figure 20. SFDR: F S = 500 Msps, FIN = 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C
10
15
20
25
30
35
40
45
50
200 400 600 800 1000 1200 1400
dB
SINAD SNR
Fs (Msps)
1250 25 50 75 100
50.0
50.5
51.0
51.5
52.0
52.5
53.0
Tj(°C)
SFDR
dBc
19
TS8308500
2193A–BDC–04/03
Figure 21. THD: FS = 500 Msps, FIN = 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C
Figure 22. SINAD and SNR: FS = 500 Msps, FIN = 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C
Figure 23. ENOB: FS = 500 Msps, FIN = 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C
-60
-50
-40
-30
-20
dBc
-10
0
0255075
Tj (°C)
THD
100 125
43.5
44.0
44.5
45.0
45.5
46.0
46.5
dB
0255075
Tj (°C)
100 125
SINAD SNR
7.00
7.05
7.10
7.15
7.20
7.25
7.30
Bits
ENOB
Tj (°C)
0 25 50 75 100 125
20 TS8308500 2193A–BDC–04/03
Figure 24. Power Consumption Versus Junction Temperature: FS = 500 Msps; FIN = 250 MHz; Duty cycle = 50%
Typical Full Power
Input Bandwidth
Figure 25. Band Flatness at 1.3 GHz ; -3 dB (-2 dBm Full Power Input)
Power Consumption (W)
Temperature (°C)
0
1
2
3
4
5
-40 -20 0 20 40 60 80 100 120 140 160
-6
-5
-4
-3
-2
-1
0
SFSR (dB FS)
0 200 400 600 800 1000 1200 1400 1600
Frequency (MHz)
21
TS8308500
2193A–BDC–04/03
ADC Step
Response Test pulse input characteristics: 20% to 80% input full scale and rise time ~ 200 ps.
Note: This step respon se was obtain ed with the TSEV83 085 00 ch ip on-b oard (device in die form).
Figure 26. Test Pulse Digitized with 20 GHz DSO
Figure 27. Same Test Pulse Digitized with TS8308500 ADC
Note: Ripples are due to the test setup (they are present on both measurements).
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.50
Time (ns)
Tr ~ 270 ps
50 mV/div
Vpp ~ 260 mV
600 ps/div
0
50
100
150
200
250
mV
0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.00
200
150
100
50
0
ADC
Time (ns)
Tr ~ 330 ps
50 codes/div (Vpp ~ 260 mV)
600 ps/div
22 TS8308500 2193A–BDC–04/03
TS8308500
Main Features
Timing
Information
Timin g Va lu e f or
TS8308500 Timing val ues as defi ned in Tabl e 3 on page 4 ar e adva nced da ta, issuin g from elec tric si mu-
lations and are the first characterization results fitted with measurements.
Timing values are given for CBGA68 package inputs/outputs, taking into account package
internal controlled impedance traces propagation delays, and specified termination loads.
Propagation delays in 50/75Ω impedance traces are NOT taken into account for TOD and
TDR.
Apply proper derating values corresponding to termination topology.
The min/max timing values are valid over the full temperature range in the following
conditions:
– Specified termination load (differential output Data and Data Ready):
50Ω resistor in parallel with 1 standard ECLinPS register from Motorola, (i.e.:
10E452). (Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF
(including package and ESD protections). If addressing an output Dmux, take care
if some Digital outputs do not have the same termination load and apply
corresponding derating value given below
– Output Termination Load derating values for TOD and TDR:
~ 35 ps/pF or 50 ps per additional ECLinPS load
– Propagation time delay derating values have also to be applied for TOD and TDR:
~ 6 ps/mm (155 ps/inch) for TSEV8308500 Evaluation Board
Apply proper time delay derating value if a different dielectric layer is used.
Propagation Time
Considerations TOD and TDR timing values are given from pin to pin and DO NOT include the additional
propagation times between device pins and input/output termination loads. For the
TSEV8308500 Evaluation Board, the propagation time delay is 6 ps/mm (155 ps/inch) corre-
sponding to 3.4 (at 10 GHz) dielectric constant of the RO4003 used for the Board.
If a differ ent dielectri c layer is used (for insta nce Teflon) , use appropri ate propag ation time
values.
TD does NOT depend on propagation times because it is a differential data.
(TD is the time difference between Data Ready output delay and digital Data output delay)
TD is also the most straightforward data to measure, again because it is differential: TD can be
measured directly onto termination loads, with matched oscilloscopes probes.
TOD-TDR Variation
Over Temperature Values for TOD and TDR track each other over temperature (1% variation for TOD-TDR per
100°C temperature variation).
Therefor e TOD-TDR v ariation ov er tempera ture is negli gible. Mor eover, the in ternal (on- chip)
and package skews between each Data TODs and TDR affect can be considered as
negligible.
23
TS8308500
2193A–BDC–04/03
Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The
same is true for the TOD and TDR maximum values.
In other words:
– If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR).
– If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR).
However, external TOD-TDR values may be dictated by total digital data skews
between every TODs (each digital data) and TDR: MCM board , bonding wires and
output lines lengths differences, and output termination impedance mismatches.
The ext ernal (on bo ard) ske w effect has NOT been taken into ac count for the specif ication of
the minimum and maximum values for TOD-TDR.
Principle of Operation The An alog inpu t is samp led on th e rising edge of the e xternal clock in put (CLK , CLKB) aft er
TA (aperture delay) of typically 250 ps .
The digi tized da ta is ava il abl e afte r 4 cloc k pe riods latenc y (pipel in e del ay (TPD) , on clo ck ri s-
ing edge, after 1360 ps typical propagation delay TOD.)
The Data Ready differential output signal frequency (DR, DRB) is half the external c lock fre-
quency, that is it switches at the same rate as the digital outputs.
The Data Ready output signal (DR, DRB) switches on the external clock falling edge after a
propagation delay TDR of typically 1320 ps.
A Master Async hrono us Reset i nput co mmand D RRB (E CL comp atible sing le-ended input) is
available for initializing the differential Data Ready output signal (DR, DRB).
This feature is mandatory in certain applications using interleaved ADCs or using a single
ADC with demulti plexed ou tputs. A ctual ly, withou t Data Ready sign al initia lizat ion, it i s impo s-
sible to store the output digital data in a defined order.
Principle of Data
Ready Signal
Control by DRRB
Input Command
Data Ready Output
Signal Reset The Data Ready signal is reset on the falling edge of the DRRB input command, on the ECL
logica l low level ( -1.8V). DRR B may also be tied to V EE = -5V for Data Ready outpu t signa l
Master Reset. So long as DRRB remains at a logical low level, (or tied to VEE = -5V), the Data
Ready output remains at logical zero and is independent of the external free running encoding
clock.
The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 720 ps typical.
TRDR is measured between the -1.3V point of the falling edge of the DRRB input command
and the zero crossing point of the differential Data Ready output signal (DR, DRB).
The Data Ready Reset command may be a pulse of 1 ns minimum time width.
24 TS8308500 2193A–BDC–04/03
Data Ready Output
Signal Restart The Data Ready output sign al restarts on the DRRB com mand’ s rising edge, ECL lo gi cal high
levels (-0.8V). DRRB may also be grounded, or is allowed to float, for a normal free running
Data Ready output signal.
The Data Ready signal restart sequence depends on the logical level of the external encoding
clock, at DRRB rising edge instant:
• The DRRB rising edge occurs when the external encoding clock input (CLK,CLKB) is
LOW: The Data Ready output’s first rising edge occurs after half a clock period on the
clock falling edge, after a delay time TDR = 1320 ps already defined hereabove.
• The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is HIGH:
The Data Ready output’s first rising edge occurs after one clock period on the clock falling
edge, and a delay TDR = 1320 ps.
Consequently, as the analog input is sampled on the clock’s rising edge, the first digitized data
corresponding to the first acquisition ( N) after a Data Ready signal restart (rising edge) is
always strobed by the third rising edge of the Data Ready signal.
The tim e delay (T D1) is spe cified be tween the l ast point of a change in the differ ential ou tput
data (zero crossing point) to the rising or falling edge of the differential Data Ready signal
(DR,DRB) (zero crossing point).
Note: 1. For normal initialization of the Data Ready output signal, the external encoding clock signal
frequency and level must be controlled. The minimum encoding cloc k sampling rate for the
ADC is 10 Msps and consequently the clock cannot be stopped.
2. One single pin is used for both the DRRB input command and die junction temperature
monitoring. Pin denomination will be DRRB/DIOD. (On former versions the denomination
was DIOD.). Temperature monitoring and Data Ready control by DRRB is not possible
simultaneously.
Analog Inputs (VIN,
VINB)The analog input Full Scale range is 0.5V, or -2 dBm into the 50Ω termination resistor.
In diff erential mode input configuration, that means 0.25V on each input, or ±125 mV around
0V. The input common mode is ground.
The typical input capacitance is 3 pF for TS8308500 in a CBGA package.
Differential Input
Voltage Span Figure 28. Differential Input Voltage Span
-125
125
[mV]
-250 mV
VIN
(VIN, VINB) = ±250 mV = 500 mV diff
500 mV
Full Scale
analog input
t
VINB
0V
250 mV
25
TS8308500
2193A–BDC–04/03
Differential Versus
Single-ended Analog
Input Operation
The TS8308500 can operate at full speed in either the differential or single-ended
configuration.
This is e xplained by the fact the A DC uses a high in put impedanc e differenti al preampli fier
stage, (preceeding the sample and hold stage), which has been designed in order to be
entered either in differential mode or single-ended mode.
This is true so long as the out-of-phase analog input pin VINB is 50Ω terminated very closely to
one of the neighboring s hield ground pins (52, 53, 5 8, 59) which constitute the loca l ground
reference for the in-phase analog input pin (VIN).
Thus the differential analog input preamplifier will fully reject the local ground noise (and any
capacitively and inductively coupled noise) as common mode effects.
In a ty pical si ngle-ended config uration, enter on the (VIN) input pin, with the inver ted phase
input pin (VINB) grounded through the 50Ω termination resistor.
In a single-ended input configuration, the in-phase input amplitude is 0.5V, centered on 0V (or
-2 dBm into 50Ω). The inverted phase input is at ground potential through the 50Ω termination
resistor.
However, dynamic performances can be somewhat improved by entering either analog or
clock inputs in differential mode.
Typical Single-ended
Analog Input
Configuration
Figure 29. Typical Single-ended Analog Input Configuration
Clock Inputs (CLK,
CLKB) The TS8308500 can be clocked at full speed without noticeable performance degradation in
either the differential or single-ended configuration.
This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer,
which has been designed in order to be entered either in differential or single-ended mode.
The recom mende d sinewave ge nerator characte ristics are typica lly -120 dBc /Hz phas e noise
floor spec tral dens ity, at 1 kHz from carr ier, assu ming a singl e tone 4 dBm in put for the clo ck
signal.
Single-ended Clock
Input (Ground
Common Mode)
Althoug h the cl ock inpu ts were i ntended t o be dr iven diffe rentially with no minal -0 .8V/-1.8V
ECL lev els, the TS8308500 clock b uffer ca n manage a single- ended si newave clo ck signa l
centered around 0V. This is the most convenient clock input configuration as it does not
require the use of a power splitter.
50Ω
(on package)
1 MΩ3 pF
-250
250
500 mV
t
[mV] VIN
VIN = ±250 mV = 500 mV diff
VIN or VINB double pad (pins 54, 55 or 56, 57)
VIN or VINB
50Ω reverse termination
500 mV
Full Scale
analog input VINB = 0V
VINB
26 TS8308500 2193A–BDC–04/03
No performance degr adation (i.e.: due to timing jitter) is observed in this particular single-
ended configuration up to 500 Msps Nyquist Conditions (FIN = 250 MHz).
This is all the more so since the inverted phase clock input pin is 50Ω terminated on the pack-
age (that is very close to one of the neighboring shield ground pins, which constitutes the local
ground reference for the inphase clock input).
Thus the TS8308 500 diff erential clock in put buffe r will f ully rejec t the loc al ground noise (an d
any capaciti vely and ind uctively coupled noise) as comm on mode effect s. Moreover, a very
low phase noise sinewave generator must be used for enhanced jitter performance.
The typical in-phase clock input amplitude is 1V, centered on 0V (ground) common mode. This
corresponds to a typical clock input power level of 4 dBm into the 50Ω termination resistor. Do
not exceed 10 dBm to avoid saturation of the preamplifier input transistors.
Figure 30. Single-ended Clock Input (Ground Common Mode):
VCLK common mode = 0V; VCLKB = 0V; 4 dBm typical clock input power level (into 50Ω terminati on resis tor )
Note: Do not exceed 10 dBm into the 50Ω termination resistor for the single clock input power level.
Differential ECL Clock
Input The clock inputs can be driven differentially with nominal -0.8V/-1.8V ECL levels.
In this mode, a low-phase noise sinewave generator can be used to drive the clock inputs, fol-
lowed b y a power splitter (hybrid junction) i n order to obtain 1 80° out of phase sinewave
signals. Biasing tees can be used for offseting the common mode voltage to ECL levels.
Note: As the biasing tees propagation times are not matching, a tunable delay line is required
in order to ensure the signals are 180° out of phase, especially at fast clock rates in the
500 Msps range.
Figure 31. Differential Clock Inputs (ECL Levels)
50Ω
(on package)
1 MΩ0.4 pF
-0.5V
+0.5V
t
[V] VCLK
CLK or CLKB double pad (pins 37, 38 or 39, 40)
CLK or CLKB
50Ω reverse termination
VCLK = 0V
VCLK
50Ω
(on package)
1 MΩ0.4 pF
CLK or CLKB double pad (pins 37, 38 or 39, 40)
CLK or CLKB
-2V
50Ω reverse termination
-1.8V
-0.8V
[mV]
VCLK
t
VCLKB
Common mode = -1.3V
27
TS8308500
2193A–BDC–04/03
Single-ended ECL
Clock Input In a singl e-end ed c onfig ura tion, ente r a t CLK (res p. C LKB) pin, with the inver ted phas e clo ck
input pin CLKB (respectively CLK) connected to -1.3V through the 50Ω termi nati on resis tor .
The in-phase input amplitude is 1V, centered on -1.3V common mode.
Figure 32. Single-ended Clock Input (ECL):
VCLK common mode = -1.3V; VCLKB = -1.3V
Noise Immunity
Information Circuit noise immunity performance begins at design level.
Efforts have been made to the design to make it as insensitive as possible to chip environment
perturbations resulting from the circuit itself or induced by external circuitry. (Cascode stage
isolati on, inter nal dampi ng resi st or s, cl amp s, int er nal (on-c hip ) decoup li ng ca pac ito rs .)
Furthe rmore, the fully differ ential operat ion from the ana lo g input up to the digi tal outpu ts pro-
vides enhanced noise immunity with common mode noise rejection.
Common mode noise voltage induced on the differential analog and clock inputs will be can-
celed out by these balanced differential amplifiers.
Moreov er, prop er acti ve si gnal s hieldi ng has been p rovided on the chip to red uce th e amou nt
of coupled noise on the active inputs.
The analog inputs and clock inputs of the TS8308500 device have been surrounded by ground
pins, which must be directly connected to the external ground plane.
Digital Outputs The TS8308500 differential output buffers are internally loaded with 75Ω. The 75Ω resistors
are c onne cted to the digi tal grou nd p ins th roug h a -0.8V lev el sh ift d iode (see Fi gure 3 3, F ig-
ure 34, Figure 35 on page 29).
The TS8308500 output buffers are designed for driving 75Ω (default) or 50Ω properly termi-
nated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of
the 75Ω res i sto rs whe n s witching ens ur es a 0 .825 V v ol tag e dr op ac ross the r esi st or ( unte rm i-
nated outputs).
The V PLUSD positive supply voltage allows the adjus tment of the output common mode leve l
from -1.2V (VPLUSD = 0V f o r E CL ou t p ut compatib il it y) t o +1. 2V (V PLUSD = 2.4V for LV DS ou tpu t
compatibility).
Therefore, the single-ended output voltages vary approximately between -0.8V and -1.625V,
(outputs unterminated), around -1.2V common mode voltage.
-1.8V
-0.8V
t
[V] VCLK
VCLKB = -1.3V
28 TS8308500 2193A–BDC–04/03
Three possible line driving and back-termination scenarios are proposed
(assuming VPLUSD = 0V):
1. 75Ω impeda nc e transmissi on lines , 75 Ω differentially terminated (Figure 33):
Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading
to ±0.41V = 0.8 25V i n d iff er enti al, a round - 1.2 1V ( resp ec tiv el y +1 .21V ) c om mon mode for
VPLUSD = 0V (respe cti v ely 2.4V)
2. 50Ω impeda nc e transmissi on lines , 50 Ω differentially terminated (Figure 34):
Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V),
leading to ±0 .33 V = 660 mV in differ ential , aro und -1.18V ( respec tive ly + 1.21V ) commo n
mode for VPLUSD = 0V (respectively 2.4V)
3. 75Ω impedance open transmission lines (Figure 35):
Each ou tput voltag e varies between -1.6V and -0.8 V (respecti vely +0.8V an d +1.6V),
which are true ECL levels, leading to ±0.8V = 1.6V in differential, around -1.2V (respec-
tively +1.2V) common mode for VPLUSD = 0V (respecti vely 2.4V )
Therefore , it is possible to directly d rive h igh input im pedance s toring re gisters, wi thout
terminating the 75Ω transmission lines.
In the time doma in, that means that the incident wave wi ll reflect at the 75Ω transmission
line output and travel back to the generator (i.e.: the 75Ω data output buffer). As the buffer
output impedance is 75Ω, no back reflection will occur.
Note: This is no longer true if a 50Ω transmission line is used, as the latter is not matching the buffer
75Ω output impedance.
Each differential output termination length must be kept identical.
It is recommended to decouple the midpoint of the differential termination with a 10 nF capaci-
tor to avoid common mode perturbation in case of slight mismatch in the differential output line
lengths.
Too large mismat ches (keep < a few mm) in the differential line lengths will lead to switching
currents flowin g into the decoup li ng cap ac ito r leadi ng to switc hi ng groun d nois e.
The differential output voltage levels (75Ω or 50Ω termination) are not ECL standard voltage
level s, howe ver, it is possi ble to dr ive standa rd logi c ECL ci rcuitr y like the E CLinPS logic l ine
from Motorola®.
29
TS8308500
2193A–BDC–04/03
Differential Output Loading Configurations (Levels for ECL Compatibility)
Figure 33. Differential Output: 75Ω Terminated
Figure 34. Differential Output: 50Ω Terminated
Figure 35. Differential Output: Open Loaded
-0.8V
75Ω75Ω
-+
11 mA
DVEE
75Ω
75Ω
impedance
Out
OutB
75Ω
75Ω
-1V/-1.41V
10 nF
Differential output:
+0.41V = 0.825V
-1.41V/-1V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 0V
-0.8V
75Ω75Ω
-+
11 mA
DVEE
50Ω
50Ω
impedance
Out
OutB
50Ω
50Ω
-1.02V/-1.35V
10 nF
Differential output:
+0.33V = 0.660V
-1.35V/-1.02V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 0V
-0.8V
75Ω75Ω
-+
11 mA
DVEE
75Ω
75Ω
impedance
Out
OutB
-0.8V/-1.6V
Differential output:
+0.8V = 1.6V
-1.6V/-0.8V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 0V
30 TS8308500 2193A–BDC–04/03
Differential Output Loading Configurations (Levels for LVDS Compatibility)
Figure 36. Differential Output: 75Ω Terminated
Figure 37. Differential Output: 50Ω Terminated
Figure 38. Differential Output: Open Loaded
1.6V
75Ω75Ω
-+
11 mA
DVEE
75Ω
75Ω
impedance
Out
OutB
75Ω
75Ω
1.4V/0.99V
10 nF
Differential output:
+0.41V = 0.825V
0.99V/1.4V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 2.4V
1.6V
75Ω75Ω
-+
11 mA
DVEE
50Ω
50Ω
impedance
Out
OutB
50Ω
50Ω
1.38V/1.05V
10 nF
Differential output:
+0.33V = 0.660V
1.05V/1.38V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 2.4V
1.6V
75Ω75Ω
-+
11 mA
DVEE
75Ω
75Ω
impedance
Out
OutB
1.6V/0.8V
Differential output:
+0.8V = 1.6V
0.8V/1.6V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 2.4V
31
TS8308500
2193A–BDC–04/03
Out of Range Bit An Out of Range (OR, ORB) bit that goes to logical high state when the input exceeds the pos-
itive full scale or falls below the negative full scale is available.
When the analog input exceeds the positive full-scale, the digital output datas remain at a high
logical state, with (OR, ORB) at logical one.
When the analog input falls below the negative full-scale, the digital outputs remain at a logical
low state, with (OR, ORB) at logical one again.
Gray or Binary
Output Data
Format Select
The TS8308500 internal regene ration latches indec isions (for inp uts very close to a latch
threshold) that can produce errors in the logic encoding circuitry and lead to large amplitude
output erro rs.
This is due to the fact that the latches are regenerating the internal analog residues into logical
states with a finite voltage gain value (Av) within a given positive amount of time (t):
Av = exp(∆(t)/τ), where τ is the positive feedback regeneration time constant.
The TS8308500 has been designed to reduce the probability of occurrence of such errors to
approximately 10-13 (targeted for the TS8308500 at 500 Msps).
A standard tec hnique for reducing the amplitu de of such e rrors down to ±1 LSB consists i n
outputi ng the di gital da ta in Gray c ode format . Thoug h the TS830 8500 has be en desi gned to
featur e a bit error ra te of 10 -13 with a binary output format, it is possible for the user to select
between the Binary or Gray output data format, in order to reduce the amplitude of such errors
when they occur, by storing Gray output codes.
Digital Data format selection:
• BINARY output format if GORB is floating or VCC.
• GRAY output format if GORB is connected to ground (0V).
Diode Pin K1 A si ngle pin is used for both the DRRB input command and die junction monitoring. The pin
denomination is DRRB/DIOD. Temperature monitoring and Data Ready control by DRRB is
not possible simultaneously.
(See “Principle of Data Ready Sig nal Control by DRRB Inpu t Comma nd” on page 23 for Data
Ready Reset input command).
The operating die junction temperature must be kept below 145°C, therefore an adequate
cooling system has to be set up. The diode mou nted transistor measur ed Vbe value ver sus
junction temperature is given below.
32 TS8308500 2193A–BDC–04/03
Figure 39. Diode Pin K1
ADC Gain Control
Pin K6 The ADC gain is adjustable by means of the pin K6 (input impedance is 1 MΩ in parallel with 2
pF).
The gain adjust transfer function is given below:
Figure 40. ADC Gain Control Pin K6
600
640
680
720
760
800
840
880
920
960
1000
-55 -35 -15 5 25 45 65 85 105 125
VBE (mV)
Junction temperature (°C)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
-500 -400 -300 -200 -100 0 100 200 300 400 500
ADC Gain
Vgain (command voltage) (mV)
33
TS8308500
2193A–BDC–04/03
Equivalent
Input/Output
Schematics
Figure 41. Equivalent Analog Input Circuit and ESD Protections
Note: The ESD protection equivalent capacitance is 150 fF.
Figure 42. Equivalent Analog Clock Input Circuit and ESD Protections
Note: The ESD protection equivalent capacitance is 150 fF.
VEE VEE
5.8V
0.8V
200Ω200Ω
50Ω50Ω
E21V
E21G E21G
E21V
VIN
GND = 0V
VINB
Pad
capacitance
340 fF
Pad
capacitance
340 fF
VCC = +5V
-0.8V
-5.8V
5.8V
0.8V
-0.8V
-5.8V
VCLAMP = +2.4V
+1.65V
-1.55V
VEE = -5V
GND
VCC
VEE VEE
5.8V
0.8V
150Ω150Ω
E31V
E21GE21G
E31V
CLK CLKB
Pad
capacitance
340 fF
Pad
capacitance
340 fF
VCC = +5V
-5.8V
-5.8V
-5.8V
5.8V
0.8V
-0.8V
-5.8V
-5.8V
+0.8V
GND = 0V
380 µA
VEE = -5V
VCC
34 TS8308500 2193A–BDC–04/03
Figure 43. Equivalent Data Output Buffer Circuit and ESD Protections
Note: The ESD protection equivalent capacitance is 150 fF.
Figure 44. ADC Gain Adjust Equivalent Input Circuits and ESD Protections
Note: The ESD protection equivalent capacitance is 150 fF.
5.8V
0.8V
0.8V
VEE VEE
-5.8V
E01V E01V
-5.8V
OUT
Pad
capacitance
180 fF
DVEE = -5V
VPLUSD = 0V to 2.4V
VEE = -5V VEE = -5V
5.8V
0.8V
0.8V
OUTB
Pad
capacitance
180 fF
VEE
1 kΩ
GA
Pad
capacitance
180 fF 2 pF
NP1032C2 +0.8V
500 µA 500 µA
VEE = -5V
E22V
VCC = +5V
GND
GND
-0.8V
-5.8V
0.8V
0.8V
5.8V
E22GA
35
TS8308500
2193A–BDC–04/03
Figure 45. GORB Equivalent Input Schematic and ESD Protections
GORB: gray or binary select input; floating or tied to VCC -> binary
Note: The ESD protection equivalent capacitance is 150 fF.
Figure 46. DRRB Equivalent Input Schematic and ESD Protections
Actual protection range: 6.6V above VEE, in fact stress above GND are clipped by the CB diode used for Tj monitoring
Note: The ESD protection equivalent capacitance is 150 fF.
5.8V
5.8V
5.8V
VEE
E21VA
-0.8V
-0.8V
-5.8V
E31G
1 kΩ
5 kΩ
1 kΩ
1 kΩ
GORB
Pad
capacitance
180 fF
VCC = +5V
250 µA 250 µA
GND = 0V
VEE = -5V
5.8V
-2.6V
-1.3V
0.8V
200Ω
10 kΩ
E21G
DRRB
VEE
GND = 0V
VCC = +5V
VEE = -5V
Pad
capacitance
180 fF
NP1032C2
36 TS8308500 2193A–BDC–04/03
TSEV8308500:
Device Evaluation Board
For complete specification, see the separate “TSEV8308500” document.
General
Description The TSEV8308500 Evaluation Board (EB) is a board which has been designed in order to
facilitate the evaluation and the characterization of the TS8308500 device up to its 1.3 GHz full
power bandwidth at up to 500 Msps in the commercial temperature range.
The high speed of th e TS8308500 requires careful attention to circuit design and layout to
achieve optimal performance.
This four metal layer board with internal ground plane has the adequate functions in order to
allow a quick and simpl e evalua tion of the TS8 308500 ADC per formanc es over the temp era-
ture range.
The TSEV8308500 Evaluation Board is very straightforward as it only implements the
TS8308500 ADC, SMA connectors for input/output accesses and a 2.54 mm pitch connector
compatible with HP16500C high frequency probes.
The board also implements a de-embedding fixture in order to facilitate the evaluation of the
high frequency insertion loss of the input microstrip lines, and a die junction temperature mea-
surement setting.
The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and
enhance d thermal cha ract eristics for opera tion in the high frequ ency domai n and exte nded
temperature range.
The board dim ensi ons are 130 mm x 130 mm.
The board set comes fully assembled and tested, with the TS8308500 and its heatsink
installed.
37
TS8308500
2193A–BDC–04/03
Package
Description
Table 7. TS8308500 Pad Description
Pad number Chip Pad Name Chip Pad Function
1V
PLUSD Positive digital supply (double pad)(2)
2D5
In-phase (+) digital output, bit 5
(D7 is the MSB; Bit 7, D0 is the LSB; Bit 0)
3 D5B Inverted pha se (-) digit al outp ut, bit 5
4 D4 In-phase (+) digital output, bit 4
5 D4B Inverted pha se (-) digit al outp ut, bit 4
6DV
EE -5V digital supply (double pad)
7 DR In-phase (+) Data Ready
8 DRB Inverted phase (-) Data Ready
9 D3 In-phase (+) digital output, bit 3
10 D3B Inverted pha se (-) digital outp ut, bit 3
11 VPLUSD Positive digital supply (double pad)(2)
12 D2 In-phase (+) digital output, bit 2
13 D2B Inverted pha se (-) digital outp ut, bit 2
14 D1 In-phase (+) digital output, bit 1
15 D1B Inverted pha se (-) digital outp ut, bit 1
16 D0 In-phase (+) digital output, bit 0, Least Significant Bit
17 D0B Inverted phase (-) digital output, bit 0, Least Significant Bit
18 GORG Gray or Binary data output format select(1)
19 VCC +5V supply (double pad)
20 GND Analog ground (double pad)
21 VCC +5V supply (double pad)
22 VEE -5V analog supp ly (dou ble pad)
23 VCC +5V supply (double pad)
24 GND Analog ground (double pad)
25 CLK In-phase (+) clock input (double pad)
26 GND Analog ground
27 CLKB Inverted pha se (-) clock input (dou ble pad)
28 GND Analog ground (double pad)
29 VEE -5V analog supp ly (dou ble pad)
30 VCC +5V supply (double pad)
31 VEE -5V analog supp ly (dou ble pad)
32 DIOD/DRRB Diode input for Tj monitoring/Input for asynchronous Data Ready Reset
33 GND Analog ground
38 TS8308500 2193A–BDC–04/03
Notes: 1. GORB tied to VCC or floating: Binary output data format. GORB tied to GND: Gray output data format.
2. The common mode level of the output buffers is 1.2V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0V (ground).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.If the subsequent
LVDS circuitry can with stand a lower level for input common mode, it is remmended to lower the positive digital supply level
in the name proporti on in orde r to spar e power dis sipation.
34 VIN In-phase (+) analog input (double pad)
35 GND Analog ground
36 VINB Inverted phase (-) analog input (double pad)
37 GND Analog ground (double pad)
38 GAIN ADC gain adjust input
39 VCC +5V supply (double pad)
40 VCC +5V supply
41 OR In-phase (+) Out of Range digital output
42 ORB Inverted phase (-) Out of Range digital output
43 D7 In-phase (+) digital output, bit 7, Most Significant Bit
44 D7B Inverted pha se (-) digital outp ut bit 7
45 D6 In-phase (+) digital output, bit 6
46 D6B Inverted pha se (-) digital outp ut, bit 6
Table 7. TS8308500 Pad Description (Continued)
Pad number Chip Pad Name Chip Pad Function
39
TS8308500
2193A–BDC–04/03
TS8308500
Pin Descript ion
(CBGA68 packa ge)
Note: 1. The common mode level of the output buffers is 1.2V below the positive digital supply
For ECL compatibility the positive digital supply must be set at 0V (ground )
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V
If the subsequent LVDS circuitry can withstand a lower level for the input common mode, it is recommended to lower the
positive digital supply level in the same proportion in order to spare power dissipation
Table 8. TS8308500 Pin Description
Symbol Pin number Function
GND A2, A5, B1, B5, B10, C2, D2, E1, E2, E11,
F1, F2, G11, K2, K3, K4, K5, K10, L2, L5 Ground pins, to be connected to external ground plane
VCC A4, A6, B2, B4, B6, H1, H2, L6, L7 +5V positive supply
VEE A3, B3, G1, G2, J1, J2 5V analog negative supply
DVEE F10, F11 -5V digital negative supply
VIN L3 In-phase (+) analog input signal of the Sample and Hold
dif fere nti al prea mp lifier
VINB L4 Inverted phase (-) of ECL clock input signal (CLK)
CLK C1 In-phase (+) ECL clock input signal. The analog input is
sampled and held on the rising edge of the CLK signal
CLKB D1 Inverted phase (-) of ECL clock input signal (CLK)
B0, B1, B2, B3, B4, B5,
B6, B7 A8, A9, A10, D10, H11, J11, K9, K8 In-phase (+) digital outputs. B0 is the LSB, B7 is the MSB
B0B, B1B, B2B, B3B,
B4B, B5B, B6B, B7B B7, B8, B9, C11, G10, H10, L10, L9 Inverted phase (-) Digital outputs. B0B is the inverted LSB
B7B is the inverted MSB
OR K7 In-phase (+) Out of Range bit. Out of Range is high on the
leading edge of code 0 and code 256
ORB L8 Inverted phase (+) of Out of Range bit (OR)
DR E10 In-phase (+) output of Data Ready signal
DRB D11 Inverted phase (-) output of Data Ready signal (DR)
GORB A7 Gray or Binary select output format control pin
– Binary output format if GORB is floating or VCC
– Gray output format if GORB is connected at ground (0V)
GAIN K6 ADC gain adjust pin. The gain pin is grounded by default,
the ADC gain transfer fuction is nominally cl ose to one
DIOD/DRRB K1 Die function temperature measurement pin and
asynchronous data ready reset active low, single ended
ECL input
VPLUSD B11, C10, J10, K11 + 2.4V for LVDS output levels otherwise to GND(1)
NC A1, A11, L1, L11 Not connected
40 TS8308500 2193A–BDC–04/03
TS8308500GL
Pinout of CBGA68
Package
Figure 47. TS8308500 Pinout of CBGA68 Package
1
2
3
4
5
6
7
8
9
10
11
VPLUSD VPLUSD
NC B3b DRb GND GND B4 B5 NCDVEE
GND GNDB2
VPLUSD
B3 DR B4b B5b
VPLUSD
B6b
B2b B6B1 B7b
B1b B7B0 ORb
B0b ORGorb VCC
VCC GAINVCC VCC
GND GNDGND GND
VCC GNDVCC VINB
VEE GNDVEE VIN
DVEE
VCC GNDGND GND GND GND VEE VCC VEE GNDGND
GND DiodeNC
Ball
A1 Index
other side
BOTTOM VIEW
CLK CLKB GND VEE VCC VEE NCGND
ABCDEFGHJKL
41
TS8308500
2193A–BDC–04/03
TS8308500
Capacitors and
Resistors Implan t
Figure 48. TS8308500 Capacitors and Resistors Implant
Note: R and C discrete components are 0603 size (1.6 x 0.8mm)
GND
100 pF
DVEE
CLK
50Ω
GND
CLKB
50Ω
GND
VEE
100 pF
GND
VCC
100 pF
GND
VEE
100 pF
GND
GND
100 pF
GORB
VCC
100 pF
GND
VCC
100 pF
GND
VEE
100 pF
GND
VCC
100 pF
GND
GND
100 pF
GAIN
GND
50Ω
VINB
GND
50Ω
VIN
VCC
100 pF
GND
Only on-package marking
electrically isolated
0.9 mm
0.9 mm
0.9 mm
∅ 7.0 mm
0.9 mm
42 TS8308500 2193A–BDC–04/03
Outline Dimensions
Figure 49. Outline Dimensions - 68 Pins CBGA
CBGA 68 package.
AL203 substrate.
Package design.
Corner balls (x4) are not connected (mechanical ball).
Balls : 1.27 mm pitch on 11x11 grid. Top side with
soldered R, C
devices
(using solder
Sn/Pb 63/37)
Balls side
Balls
Sn/Pb 63/37
AI203 substrate
AI203 Ceramic
Cap. Glued and embedded
in substrate
1.45 ± 0.12
0.63 ± 0.10
Detail of
ball x2
All units in mm
1.27
View balls side
15.00 ± 0.15 mm
0.95 max
15.00 ± 0.15 mm
1.27 ref
7.84
7.84
ABCDEFGHJKL
1
2
3
4
5
6
7
8
9
10
11
- A -
Ball
A1 Index
other side
68 x ∅ D = 0.80 ± 0.10 mm
0.40
0.15 TAB
T
(Position of array of balls/edges A and B)
(Position of balls within array)
- B -
50 Ω
0.20 T
100 pF
- T -
D
0.15
1.00
43
TS8308500
2193A–BDC–04/03
Cross Section Figure 50. Cross Section
Top side with soldered R, C devices
(using solder Sn/Pb 63/37) 0.95 max
0.20 T
- T -
Balls side
Balls
Sn/Pb 63/37
AI203 substrate
AI203 Ceramic Cap.
Glued on substrate
0.15
(0.400)
100 pF
All units in mm
50 Ω
(0.20)
(0.25) (2 x 0.20)
(0.20)
1.45 ± 0.12
44 TS8308500 2193A–BDC–04/03
Thermal And
Moisture
Characteristics
Thermal Resistance
from Junction to
Ambient: RTHJA
The fol lowing ta ble lists the conve ction ther mal per formance s param eters of the de vice its elf,
with no external heatsink added.
Thermal Resistance
from Junction to
Case: RTHJC
The typical value for Rthjc is given as 6.7°C/W (8°C/W max).
This value does not include thermal contact resistance between package and external compo-
nent (heatsink or PC Board).
As an example, 2.0°C/W can be taken for 50 µm of thermal grease.
CBGA68 Board
Assembly with
Extern al Heatsi nk
It is recomm ended that an e xternal he atsink or sp ecificall y designed PCB be used. Co oling
system efficiency can be monitored using the Temperature Sensing Diode, integrated in the
device.
Figure 51. CBGA68 Board Assembly
Note: Units = mm
Table 9. Thermal Resistance
Air Flow (m/s) Estimated ja Thermal Resistance (°C/W)
045
0.5 35.8
1 30.8
1.5 27.4
2 24.9
2.5 23
3 21.5
4 19.3
5 17.7
0
10
20
30
40
50
012
34 5
Air Flow (m/s)
Rthja (deg.C/W)
31
32.5
Board
50.5
20.224.2
6.8
45
TS8308500
2193A–BDC–04/03
Moisture
Characteristics This device is sensitive to moisture (MSL3 according to JEDEC standard):
Shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH).
After thi s bag is open ed, dev ices th at will be s ubjected to infr ared r eflow, vapor- phase reflow ,
or equivalent processing (peak package body temperature 220°C) must be:
• mounted within 198 hours at factory conditions of ≤30°C/60% RH, or
• stored at ≤20% RH
Devices require baking, before mounting, if Humidity Indicator Card is >20% when read at
23°C ±5°C.
If baking is required, devices may be baked for:
• 192 hours at 40°C +5°C/-0°C and <5% RH for low-temperature device containers, or
• 24 hours at 125°C ±5°C for high temperature device containers
46 TS8308500 2193A–BDC–04/03
Definitions
Definition of Terms
(BER) Bit Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that dif-
fers by more than ±4 LSB from the correct code.
(BW) Full-Pow er Input
Bandwidth
(DG) Differential Gain
Analog input frequency at which the fundamental component in the digitally reconstructed out-
put has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for
input at full -sc ale.
The peak gain va riation (in percent) at five different DC lev els for an AC signal of 20% F ull-
Scale peak to peak amplitude. FIN = 5 MHz (TBC).
(DNL) Differential Non-
Linearity The Differential Non-Linearity for an output code (i) is the difference between the measured
step si ze of code (i) and the id eal LSB st ep size. DN L (i) is expr essed in LSB s. DNL is th e
maximum value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there
are no missing output codes and that the transfer function is monotonic.
(DP) Differential Phase Peak Phase variation ( in degrees) at five different DC level s for an A C sign al of 20 % Full-
Scale peak to peak amplitude. FIN = 5 MHz (TBC).
(ENOB) Effecti ve
Number of Bits
Where A is the actual input amplitude and V is the full-scale range of the ADC under test.
(IMD) InterModulation
Distortion The two tones intermodulation distortion (IMD) rejection is the ratio of either inpu t tone to the
worst third order intermodulation products. The input tones levels are at -7 dB full-scale.
(INL) Integral Non-
Linearity T he In teg ral Non -L inear it y fo r a n outp ut code (i ) is the diffe re nc e bet ween the m eas ured inp ut
voltage at which the transition occurs and the ideal value of this transition.
INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.
(JITTER) Aperture
Uncertainty Sample to sample variation in aperture delay. The voltage error due to jitter depends on the
slew rate of the signal at the sampling point.
(NPR) Noise Power
Ratio The NPR is measured to characterize the ADC performance in response to broad bandwidth
signals. When using a notch-filtered broadband white-noise generator as the input to the ADC
under tes t, the Noise Power Ratio is defined as the ratio of the avera ge out-of-notc h to the
avera ge in- notc h pow er sp ectral den sity m agni tudes f or the F FT spectr um o f the ADC outpu t
sample test.
(NRZ) Non-Return to
Zero When the i npu t s igna l is l ar ger tha n t he upper b oun d o f t he ADC i npu t r an ge, the o utpu t c od e
is iden tical to t he m aximum c ode a nd the O ut of Ra nge bit is set t o logic one. When t he inp ut
signal is smaller than the lower bound of the ADC input range, the output code is identical to
the minimum code, and the Out of Range bit is set to logic one. ( It is assumed that the input
signal amplitude remains within the absolute maximum ratings).
(ORT) Overvoltage
Recovery Time Time to reco ver 0.2% a ccur ac y at th e ou tput, after a 15 0% fu ll -sc ale st ep a ppl ied on the i np ut
is reduced to midscale.
SINAD - 1.76 + 20 log (A/V/2)
6.02
ENOB =
47
TS8308500
2193A–BDC–04/03
(PSRR) Power Supply
Rejection Ratio Ratio of input offset variation to a change in power supply voltage.
(SFDR) Spurious Free
Dynamic Range Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the RMS
value of the next hig hest spectral component (peak spurious spec tral component). SFDR is
the key par ameter for selecting a converter to be used in a frequency domain application
(Radar systems, digital receiver, network analyzer, etc.). It may be reported in dBc (i.e.:
degrades as signal level is lowered), or in dBFS (i.e.: always relate d back to converter full
scale)
(SINAD) Signal to Noise
and Distortion Ratio Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the RMS
sum of all other spectral components, including the harmonics except DC.
(SNR) Signal to Noise
Ratio Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the RMS
sum of all other spectral components excluding the five first harmonics.
(TA) Aperture Delay Delay between the rising edge of the differe ntial clock inputs (CLK, CLKB ) (zero crossing
point), and the tim e at which (VIN, VINB) is sampled.
(TC) Encoding Clock
Period TC1 = Minimum clock pulse width (high) TC = TC1 + TC2
TC2 = Minimum clock pulse width (low)
(TD1) Time Delay from
Data to Data Ready Time delay from Data transition to Data Ready.
(TD2) Time Delay from
Data Ready to Data General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock
period.
(TF) Fall Time Time delay for the ou tput Da ta s i gna ls to fa ll fr om 80 % t o 2 0% o f d el ta betwe en lo w lev el an d
high level.
(TH D ) Total Harmonic
Distorsion Ratio expressed in dBc of the RMS su m of the first fi ve har monic co mponen ts, to t he RMS
value of the measured fundamental spectral component.
(TOD) Digital Data
Output Delay Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to
the next point of change in the differential output data (zero crossing) with a specified load.
(TPD) Pipeline Delay Number of clock cycles between the sampling edge of an input data and the associated output
data be ing ma de ava ilab le, (not takin g in acc ount th e TOD ). For the TS8388 BF th e TPD is 4
clock periods.
(TR) Rise Time Time delay for the output Data signals to rise from 20% to 80% of delta between low level and
high level.
(TRDR) Data Ready
Reset Delay Delay bet ween the f allin g edge o f the Data Read y outpu t asyn chro nous R eset s ignal (DDRB)
and the reset to digital zero transition of the Data Ready output signal (DR).
(TS) Settling Time Time delay to achieve 0.2% accuracy at the converter output when a 80% full-scale step func-
tion is applied to the differential analog input.
48 TS8308500 2193A–BDC–04/03
Ordering
Information
Part Number Package Temperature Range Screening Comments
TSX8308500GL CBGA 68 Ambient Prototype Prototype version
TS8308500CGL CBGA 68 "C" grade
0°C < Tc ; Tj < 90°CStandard
TS8308500VGL CBGA 68 "V" grade
-40°C < Tc ; Tj < 110°CStandard
TSEV8308500GL CBGA 68 Ambient Prototype Evaluation Board (delivered with a heat sink)
TSEV8308500GLZA2 CBGA 68 Ambient Prototype Evaluation Board with digital output buffers
(delive r ed with a heat si nk)
49
TS8308500
2193A–BDC–04/03
Datasheet
Status
Description
Life Support
Applications These pro ducts ar e not des ig ned for use in lif e su ppo rt appliances , devic es or s ys tem s wh er e
malfunction of these products can reasonably be expected to result in personal injury. Atmel
custo mers us ing or sellin g these product s for use in such applica tions do so at th eir ow n risk
and agree to fully indemnify Atmel for any damages resulting from such improper use or sale.
Table 10. Datasheet Status
Datasheet Status Validity
Objective specification This datasheet contains target and
goal sp ecifications f or discussion with
customer and application validation.
Before design phase
Target specification This datasheet contains target or
goal specifications for product
development.
Valid during the design phase
Preliminary specification
α-site
This datasheet contains preliminary
data. Additional data may be
published later could include
simulation results.
Valid before characterization
phase
Preliminary specification
β-site This datasheet also contains
characterization results. Valid before the
industrialization phase
Product specification This datasheet contains final product
specification Vali d for p roducti on purposes
Limiting Values
Limitin g value s give n are in accordanc e with th e Absolu te Maxi mum Rati ng Syste m (IEC 134). Stres s
above one or more of the limiting values may cause permanent damage to the device. These are
stress r atings on ly and ope ration of th e device at these o r at any oth er conditi ons abov e those gi ven in
the Characteristics sections of the specification is not implied. Exposure to limiting values for
extended periods may affect device reliability.
Application Information
Where application information is given, it is advisory and does not form part of the specification.
Printed on recycled paper.
Disclaimer: Atmel Corporation makes no warrant y for the use of its products, other than those express ly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibilit y fo r a ny
errors which m ay app ear in this document, re serves the r ight to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
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