MT45W1MW16BDGB-708WTES - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Features

PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

Async/Page/Burst CellularRAM™ Memory

MT45W1MW16BDGB

For the latest data sheet, refer to Micr on’s Web site: www.micron.com/products/psram/cellularram/

Features

• Si ngle device supports asynchr o nous, page, and

burst operations

• Random access time: 70ns

•V

CC, VCCQ voltages:

–1.7–1.95V VCC

–1.7–3.3V VCCQ

• Page mode read access

–Sixteen-word page size

–Interpage read access: 70ns

–Intrapage read access: 20ns

•Burst mode write access: continuous burst

• Burst mode read acce ss:

–4, 8, or 16 words, or continuous burst

–MAX clock rate: 104 MHz (tCLK = 9.62ns)

–Burst initial latency: 39ns (4 clocks) @ 104 MHz

–tACLK: 7ns @ 104 MHz

•Low power consumption

–Asynchronous read: <20mA

–Intrapage read: <15mA

–Intrapage read initial access, burst read:

–(39ns [4 clocks] @ 104 MHz) < 35mA

–Continuous burst read: <28mA

–Standby: 70µA

–Deep power-down: <10µA (TYP @ 25°C)

•Low-power features

–Temperature-compensated refresh (TCR)

–On-chip temperature sensor

–Partial-array refresh (PAR)

–Deep power-down (DPD) mode

Options Designator

•Configuration

–1 M eg x 16 MT45W1MW16BD

•Package

–54-ball VFBGA (“green”) GB

•Access time

–70ns access -70

•Frequency

–80 MHz 8

–104 MHz 1

Figure 1: 54-Ball VFBGA

Notes: 1. –30°C exceeds the CellularRAM Workgroup

1.0 specification of –25°C.

2. Contact factory.

Part Num ber Example:

MT45W1MW16BDGB-701WT

Options (continued) Designator

•Standby power

–Standard None

• Operating temperature range

–Wireless (–30°C to +85°C) WT1

–Industrial (–40°C to +85°C) IT2

1 2 3 4 5 6

Top View

(Ball Down)

LB#

DQ8

DQ9

VSSQ

VCCQ

DQ14

DQ15

A18

WAIT

OE#

UB#

DQ10

DQ11

DQ12

DQ13

A19

CLK

A17

A14

A12

ADV#

CE#

DQ1

DQ3

DQ4

DQ5

WE#

A11

CRE

DQ0

DQ2

VCC

VSS

DQ6

DQ7

A16

A15

A13

A10

PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Device Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Bus Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

LB#/UB# Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Deep Power-Down Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Access Using CRE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Burst Wrap (BCR[3]) Default = BurstN o Wrap (Within Burst Length) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .25

WAIT Polarity (BCR[10]) Default = WAIT Active HIGH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Latency Counter (BCR[13:11]) Default = Three-Clock Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Refresh Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Temperature-Compensated Refresh (RCR[6:5]) Default = On-Chip Tempera ture Sensor. . . . . . . . . . . . . . . .28

Page Mode Operation (RCR[7]) Default = Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Maximum and Typical Standby Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

List of Figur es

List of Figures

Figure 1: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: Functional Block Diag ram – 1 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 3: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 4: Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 5: READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 6: WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 7: Page Mode READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 8: Burst Mode READ (4-word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 9: Burst Mode WRITE (4-word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 10: Wired-OR WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 11: Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 12: Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 13: Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY Operation . . . .19

Figure 14: Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation . . . . .20

Figure 15: Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 16: Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 17: Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 18: WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 19: WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 20: WAIT Configuration During Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 21: Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 22: Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 23: Typical Refresh Current vs. Temperature (ITCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 24: AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 25: Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 26: Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 27: Asynchrono us READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 28: Asynchrono us READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 29: Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 30: S ingle-Access B u rs t REA D Ope r at ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 31: 4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 32: READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 33: Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition . .43

Figure 34: CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 35: LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 36: WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 37: Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 38: Burst WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 39: Continuous Burst WRITE Showing an Output Delay with BCR[8 ] = 0 for End-of-R ow Condi tion .49

Figure 40: Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 41: Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 42: Asynchronous WRITE Followed by Burst READ – ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 43: Burst REA D Fo ll owed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 44: Burst REA D Fo ll owed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 45: Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 46: Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 47: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

List of Tables

Table 1: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 2: Bus Operations – Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3: Bus Operations – Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 4: Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 5: Latency Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 6: 16Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 7: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 8: Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 9: Maximum Standby Currents for Applying PAR and TCR Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 10: Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 11: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 12: Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 13: Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 14: Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 15: Burst WRITE Cycle Tim ing Req uirem e n ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 16: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

General Description

Micron® CellularRAM™ is a high-speed, CMOS PSRAM memory developed for low-

power, portable applications. The MT45W1MW16BDGB is a 16Mb DRAM core

device organized as 1 Meg x 16 bits. This device includes an ind ustry-standard

burst mode Flash interface that dramatically increases read/write bandwidth compared

with other low-power SRAM or P seudo SRAM offerings.

For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans-

parent self-refresh mechanism. The hidden refr esh requir es no additional support from

the system memory controller and has no significant impac t on de vic e read/write

performance.

Two user-accessible control registers define device operation. The bus configuration

bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh

configuration register (RCR) is used to control how refresh is performed on the DRAM

array. These registers are au tomatically loaded with default setti ng s during power-up

and can be updated anytime during normal operatio n.

S p ecial attention has been focused on stand by current consumption during self refresh.

CellularRAM prod ucts include three system-accessible mechanisms to minimi ze

standby current . Partial-array refresh (PAR) limits refresh to only that part of the DRAM

array that contains essential data. Temperature-compensated refresh (TCR) uses an on-

chip sensor to adjust the refresh rate to match the device temperature. The refresh ra te

decr eases at lower temperatures to minimize curr ent consum pti on during s t andby. TCR

can also be set by the system for maximum device temperatures of +85°C, +45°C, and

+15°C. Deep power-d own (DPD) halts the REFRESH operation altogether and is used

when no vital information is stored in the device. These three refresh mechanisms are

accessed through the RCR.

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Functional Block Diagrams

Figure 2: Functional Block Diagram – 1 Meg x 16

Note: Functional block diagrams illustrate simplified device operation. See truth table, ball

descript ions, and tim ing diagrams for detailed in formation.

A[19:0] Input/

Output

MUX

and

Buffers

Control

Logic

1,024K x 16

DRAM

MEMORY

ARRAY

CE#

WE#

OE#

CLK

ADV#

CRE

WAIT

LB#

UB#

DQ[7:0]

DQ[15:8]

Refresh Configuration

Bus Configuration

Address Decode

Logic

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Ball Descriptions

Note: The CLK and ADV# inputs can be tied to VSS if the device is always operatin g in asynchro-

nous or page mode. WAIT will be asserted but should be ignored during asynchronous and

page mode operations.

Ta ble 1: VFBGA Ball Descriptions

VFBGA

Assignment Symbol Type Description

G2, H1, D3, E4,

F4, F3, G4, G3,

H5, H4, H3, H2,

D4, C4, C3, B4,

B3, A5, A4, A3

A[19:0] Input Address in puts: Inputs for addresse s during READ and WRITE operations.

Addresses are internally latched during READ and WRITE cycles. The address lines

are also used to define the value to be load ed into the bus co nfig uration register

or the refresh configuration register.

J2 CLK Input Clock: Synchronizes the memory to the system operating frequency during

synchronous o perations. When configured for synchronous operation, the address

is latched on the first rising CLK edge when ADV# is active. CLK is static LOW or

HIGH during asynchronous access READ and WRITE operations and during PAGE

READ ACCESS operations.

J3 ADV# Input Address valid: Indicates that a valid address is present on the address inputs.

Addresses ca n be latched on the rising edge of ADV# during asynchronous READ

and WRITE operat ions. ADV# can be held LOW du ring asynchronous READ and

WRITE operations.

A6 CRE Input Configuration register enable: When CRE is HIGH, WRITE operations load the

refresh configuration register or bus configurati on register.

B5 CE# Input Chip enable: Activates the device when LOW. When CE# is HIGH, the device is

disabled and goes into standby or deep power-down mode.

A2 OE# Input Output enable: Enables the output buffers when LOW. When OE# is HIGH, the

output buffers are disabled.

G5 WE# Input Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW , the cycle

is a WRITE to either a configuration register or to the memory array.

A1 LB# Input Lower byte enable: DQ[7:0].

B2 UB# Input Upper byte enab le: DQ[15:8].

G1, F1, F2, E2,

D2, C2, C1, B1,

G6, F6, F5, E5,

D5, C6, C5, B6

DQ[15:0] Input/

Output Data inputs/outputs.

J1 WAIT Output Wait: Prov ides data-valid feedback during burst READ and WRITE operations. The

signal is gate d by CE#. WAIT is used to arbitrate collisions between REFRESH and

READ/WRITE operations. W AIT is asserted when a burst crosses a row boundary.

WAIT is also used to mask the delay associated with opening a new internal page.

WAIT is asserted and should be ignored during asynchronou s and page mode

operations. WAIT is High-Z when CE# is HIGH.

E3, H6, J4, J5, J6 NC – Not internally connected.

D6 VCC Supply Device power supply (1.7–1.95V): Power supply for device core operati on.

E1 VCCQ Supply I/O power supply (1.7–3.3V): Power supply for input/output buffers.

E6 VSS Supply VSS must be connected to ground.

D1 VSSQ Supply VSSQ must be connected to ground.

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Bus Operations

Notes: 1. CLK must be LOW during async read and async write modes, and to achieve standby power

during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend.

2. The WAIT polarity is configured through the bus configuration register (BCR[10]).

3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in

select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are

affected.

4. The device will consume active power in this mode whenever addresses are changed.

5. When the device is in standby mode, address inputs and data inputs/outputs are internally

isolated from any external influence.

6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achi eve standby

current.

7. DPD is maintained until RCR is reconfigured.

8. Burst mode operation is initialized through the bus configuration register (BCR[15]).

Table 2: Bus Operations – Asynchronous Mode

Mode Power CLK1ADV# CE# OE# WE# CRE LB#/

UB# WAIT2DQ[15:0]3Notes

Read Active L L L L H L L Low-Z Data-Out 4

Write Active L L L X L L L Low-Z Data-In 4

Standby Standby L X H X X L X High-Z High-Z 5, 6

No operation Idle L X L X X L X Low-Z X 4, 6

Configuration

DPD Deep

power-down L X H X X X X High-Z High-Z 7

Table 3: Bus Operations – Burst Mode

Mode Power CLK1ADV# CE# OE# WE# CRE LB#/

UB# WAIT2DQ[15:0]3Notes

Async read Active L L L L H L L Low-Z Data-Out 4

Async write Active L L L X L L L Low-Z Data-In 4

Standby Standby L X H X X L X High-Z High-Z 5, 6

No operation Idle L X L X X L X Low-Z X 4, 6

Initial burst

read Active L L X H L L Low-Z X 4, 8

Initial burst

write Active L L H L L X Low-Z X 4, 8

Burst

continue Active H L X X X L Low-Z Data-In or

Data-Out 4, 8

Burst suspend Active X X L H X L X Low-Z High-Z 4, 8

Configuration

DPD Deep

power-down LXHXXXXHigh-ZHigh-Z7

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Part Numbering Information

Micron CellularRAM devices are available in several different configurations and densi-

ties (see Figure 3).

Figure 3: Part Number Chart

Notes: 1. –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C.

Valid Part Number Combinations

After building the part number from the part numbering chart abo ve , visit to the Micron

Part Marking Decoder Web site at www.micron.com/partsearch to verify that the part

number is offered and valid. If the device required is not on this list, contact the factory.

Device Marking

Due to the size of the package, the Micron standard part number is not printed on the

top of the device. Instead, an abbreviated device mark comprised of a five-digit alpha-

numeric code is used. The abbreviated device mar ks are cross-referenced to the Micron

part numbers at www.micron.com/partsearch. To view the location of the abbreviated

mark on the device, refer to customer ser vice note, CSN-11, “Product Mark/Label” at

www.micron.com/csn.

MT 45 W 1M W 16 BD GB -70 8 WT ES

Micron Technology

Product Family

45 = PSRAM/CellularRAM Memory

Operating Core Voltage

W = 1.7–1.95V

Address Locations

M = Megabits

Operating Voltage

W = 1.7–3.3V

Bus Configuration

16 = x16

READ/WRITE Operation Mode

BD = Asynchronous/Page/Burst

Package Codes

GB = VFBGA “green” (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 54-ball

Production Status

Blank = Production

ES = Engineering Sample

MS = Mechanical Sample

Operating Temperature

WT = –30°C to +85°C (see Note 1)

IT = –40°C to +85°C (contact factory)

Standby Power Options

Blank = Standard

Frequency

8 = 80 MHz

1 = 104 MHz

Access/Cycle Time

70 = 70ns

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Functional Description

In general, the MT45W1MW16BDGB de vic e s are high-density alternatives to SRAM and

Pseudo SRAM products, popular in low-power, portable applications.

The MT45W1MW16BDGB contains a 16,777,216-bit DRAM core organized as 1,048,576

addresses by 16 bits. This device impl ements the same high-speed bus interface found

on burst mode Flash products.

The CellularRAM bus interface supports both asynchronous and burst mode transfers.

Page mode accesses are also included as a bandwidth-enhancing extension to the asyn-

chronous read protocol.

Power-Up Initialization

CellularRAM products include an on-chip voltage sensor used to launch the power-up

initialization proc ess. Initialization will configure the BCR and the RCR with their

default settings (see Figure17 on page 23 and Figure 22 on page 27). VCC and V CCQ must

be applied simultaneously. When they reach a stable level at or above 1.7V, the device

will requir e 150µs to complete its self-initialization process. During the initialization

period, CE# should remain HIGH. When initialization is complete, the device is ready for

normal operation.

Figure 4: Power-Up Initialization Timing

Bus Operating Modes

The MT45W1MW16BDGB CellularRAM products incorporate a burst mode interface

found on Flash products targeting low-power, wireless applications. This bus interface

supports asynchronous, page mode, and burst mode read and write transfers. The

specific interface supported is defined by the value loaded in to the bus configuration

Asynchronous Mode

CellularRAM products power up in the asynchronous operating mode. This mode uses

the industry-standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations

(Figure 5) are initiated by bringing CE#, OE#, and LB#/UB# LOW wh ile keeping WE#

HIGH. Valid data will be driven out of the I/Os after the specified access time has

elapsed. WRITE operations (Figure 6 on page 11) occur when CE#, WE#, and LB#/UB#

are driven LOW. During asynchronous WRITE operations, the OE# level is a “Don't

Care,” and WE# will override OE#. The data to be written is latched on the rising edge of

CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode

disabled) can either use the ADV input to latch the address, or ADV can be driven LOW

during the en tire READ/WRIT E operation.

During asynchronous operation, the CLK input must be he ld static LOW or HIGH. WAIT

will be driven while the device is enabled and its state should be ignored. WE# LO W time

must be limited to tCEM.

Vcc

VccQDevice Initialization

Vcc = 1.7V Device ready for

normal operation

tPU >150µs

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Bus Operating Modes

Figure 5: READ Operation (ADV = LOW)

Note: ADV must remain LOW for page mode operation.

Figure 6: WRITE Operation (ADV = LOW)

Page Mode READ Operation

Page mode is a performance-enhancing extension to the legacy asynchronous READ

operation. In page-mode-capable products, an initial asynchronous read access is

performed, then adjacent addresses can be r ead quickly by simply changing the low-

order address. Addresses A[3:0] are used to determi ne the members of the 16-address

CellularRAM page. Any change in addresses A[4] or higher will initiate a new tAA access

time. Figure 7 shows the timing for a page mode access. Page mode takes advantage of

the fact that adjacent addresses can be read in a shorter period of time than random

addresses. WRITE operations do not include comparable page mode functionality.

During asynchronous page mode operation, the CLK input must be held static LOW or

HIGH. CE# must be driven HIGH upon completion of a page mode access. WAIT will be

driven while the device is enab led and its stat e should be ignored. Page mode is enabled

by setting RCR[7] to HIGH. ADV must be driven LOW during all page mode read

accesses.

ADDRESS VALID

DATA

CE#

DATA VALID

OE#

WE#

LB#/UB#

tRC = READ Cycle Time

ADDRESS

ADDRESS VALID

DATA

CE#

DON’T CARE

DATA VALID

OE#

WE#

LB#/UB#

tWC = WRITE Cycle Time

ADDRESS

CEM

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Bus Operating Modes

The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer

than tCEM.

Figure 7: Page Mode READ Operation (ADV = LOW)

Burst Mode Operation

Burst mode operations enable high-s pe ed synchronous READ and WRITE operations.

Burst operations consist of a multi-clock sequence that must be performed in an

ordered fashion. After CE# goes LOW, the addr ess to access is latched on the next rising

edge of CLK that ADV# is LOW. During this first clock rising edge, WE# indicates whether

the operation is going to be a READ (WE# = HIGH, Figure8 on page 13) or WRITE (WE# =

LOW, Figure 9 on page 14).

The size of a burst can be specified in the BCR as either fixed-length or continuous.

Fixed-length bursts consist of four, eight, or sixteen words. Continuous bursts have the

ability to start at a specified address and burst through the entire memory. The lat ency

count stored in the BCR defines the number of clock cycles that elaps e be fore the initial

data value is transferred between the processor and CellularRAM device.

The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to

indicate when data is to be transferre d int o (or out of) the memory. WAIT will again be

asserted if the burst crosses the boundary between 128-word rows. Once the Cellu-

larRAM device has restored the previous row’s data and accessed the next row, WAIT

will be de-asserted and the burst can continue (see Figure 33 on page 43).

The processor can access other device s without incurring the timing penalty of the

initial latency for a new burst by suspending burst mode. Bursts are suspended by stop-

ping CLK. CLK can be stopped HIGH o r LOW. If another device will use the data bus

while the burst is suspended, OE# should be taken HIGH to disable the Cellular RAM

outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be

active, and as a result no other devices should directly share the WAIT connection to the

controller. To continue the burst sequence, OE# is taken LOW, then CLK is restarted

after valid data is available on the bus.

DATA

CE#

DON’T CARE

OE#

WE#

LB#/UB#

ADDRESS ADDRESS[0] ADDRESS

[1] ADDRESS

[2] ADDRESS

[3]

D[1] D[2] D[3]

tAA tAPA

<tCEM

tAPA tAPA

D[0]

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Bus Operating Modes

The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer

than tCEM unless row boundaries are crossed at least every tCEM. If a burst suspension

will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the

burst restarted with a new CE# LOW/ADV# LOW cycle.

Figure 8: Burst Mode READ (4-word Burst)

Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT

asserted during delay.

A[19:0]

D[0]

ADV#

CE#

OE#

D[1] D[2] D[3]

WE#

WAIT

DQ[15:0]

LB#/UB#

Latency Code 2 (3 clocks)

CLK

UNDEFINEDDON’T CARE

READ Burst Identified

(WE# = HIGH)

ADDRESS

VALID

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Bus Operating Modes

Figure 9: Burst Mode WRITE (4-word Burst)

Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT

asserted during delay.

A[19:0]

D[0]

ADV#

CE#

OE#

D[1] D[2] D[3]

WE#

WAIT

DQ[15:0]

LB#/UB#

ADDRESS

VALID

Latency Code 2 (3 clocks)

CLK

DON’T CARE

WRITE Burst Identified

(WE# = LOW)

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Bus Operating Modes

Mixed-Mode Operation

The device can support a combination of synchronous READ and asynchronous WRITE

operations when the BCR is configured for synchronous operation. The asynchronous

WRITE operation requires that the clock (CLK) be held static LOW or HIGH during the

entire sequence. The ADV# signal can be used to latch the target address, or it can

remain LOW during the en tire WRITE operation. CE# must return HIGH when transi-

tioning between mixed-mode operations. Note that the tCKA period is the same as a

READ or WRITE cycle. This time is required to ensure adequate refresh. Mixed-mode

operation facilitates a seamless interface to legacy burst mode Flash memory control-

lers. See Figure 41 on page 51.

WAIT Operation

The WAIT output on a CellularRAM device is typically connected to a shared, system-

level WAIT signal (see Figure 10). The shared WAIT signal is used by the processor to

coordinate transactions with multiple memories on the synchronous bus.

Figure 10: Wire d-OR WAIT Configuration

Once a READ or WRITE operation has been ini tiated, WAIT goes active to indic ate tha t

the CellularRA M device requires additional time before data can be transferred. For

READ operations, WAIT will remain active until valid data is output from the device. For

WRITE operations, WAIT will indicate to the memory controller when data will be

accepted into the CellularRAM device. When WAIT transitions to an inactive state, the

data burst will progress on successive clock edge s.

During a Burst cycle, CE# must remain asserted until the first data is valid. Bringing CE#

HIGH during this initial latency may cause data corrup tion.

The WAIT output also performs an arbitration role when a READ or WRITE operation is

launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted

for additional clock cycles until the refr esh has completed (s e e Fig u res 1 1 a n d 1 2 o n

page17). When the refresh operation has completed, the READ or WRITE operation will

continue normally.

WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary.

The WAIT assertion allo ws time for the new r o w to be acces sed and permits any pending

refresh operations to be per formed.

LB#/UB# Operation

The LB# enable and UB# enable signals support byte-wide data transfers. During READ

operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a

disabled byte are put into a High-Z state during a READ operation. During WRITE oper-

CellularRAM External

Pull-Up/

Pull-Down

Resistor

Processor

READY

Other

Device

WAIT

Other

Device

WAIT

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Bus Operating Modes

ations, any disabled bytes will not be transferred to the RAM array and the internal value

will remain unchanged. During an asynchronous WRITE cycle, the data to be writte n is

latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.

When both the LB# and UB# are disabled (HIGH) during an operation, the device will

disable the data bus from receiving or transmitting data. Although the device will seem

to be deselecte d, it remains in an active mode as long as CE# remains LOW.

Figure 11: Refresh Collision During READ Operation

Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT

asserted during delay.

A[19:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

CLK VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

D[2]D[1] D[3]

VALID

ADDRESS

Additional WAIT states inserted to allow refresh completion.

LB#/UB#

UNDEFINED DON’T CARE

D[0]

High-Z

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Bus Operating Modes

Figure 12: Refresh Collision During WRITE Operation

Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT

asserted during delay.

A[19:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

CLK

D[1]D[0] D[3]D[2]

VALID

ADDRESS

Additional WAIT states inserted to allow refresh completion.

LB#/UB#

DON’T CARE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL High-Z

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Low-Power Operation

Standby Mode Operation

During standby, the device current consumption is reduced to the level necessary to

perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH.

The device will enter a reduced power state upon completion of a READ or WRITE oper-

ation or when the address and control inputs remain static for an extended period of

time. This mode will continue until a change occurs to the address or control inputs.

Temperature-Compensated Refresh

Temperature-compensated refresh (TCR) allows for adequate r efresh at differe nt

temperatures. This CellularRAM device includes an on-chip temperatur e sensor. When

the sensor is enabled, it continuall y adjusts the refresh rate according to the operat ing

temperature. The on-chip sensor is enabled by default.

Three fixed refresh rates are also available, corresponding to temperature thresholds of

+15°C, +45°C, and +85°C. The setting selected must be for a temperature higher than the

case temperatur e of the CellularRAM device. If the case temperatur e i s +35°C, the system

can minimize sel f refr esh curr ent consumption b y selecting the +45°C setting. The +15°C

setting would r esult in inadequate refreshing and cause data corruption.

Partial-Array Refresh

Partial-array r ef resh (PAR) restricts refresh operation to a portion of the total memory

array. This feature enables the device to reduce standby current by refreshing only that

part of the memory array required by the host system. The refresh options are full array,

one-half array, one-quarter array, one-eighth array, or none of the array. The mapping

of these partitions can start at either the begi nning or the end of the address map (see

Table 6 on page 28). READ and WRITE operations to address ranges receiving refresh

will not be affected. Data stored in addresses not rece iving refresh will become

corrupted. When re-enabling additi onal portions of the array, the new portions are

available immediately upon writing to the RCR.

Deep Power-Down Operation

Deep power-down (DPD) operation disables all refresh-related activity. This mode is

used if the system does not require the stor age provided by the CellularRAM device. Any

stor ed data will become corrupted when DPD is enabled. When r efr esh activity has been

re-enabled b y rewriting the RCR, the CellularRAM device will require 150µs to perform

an initialization procedure before normal operations can resume. During this 150µs

period, the current consumption will be higher than the specified standby levels, but

considerably lower than the active current specification.

DPD cannot be enabled or disabled by writing to the RCR using the software access

sequence; the RCR should be accessed using CRE instead.

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Configuration Registers

Two user-accessible configuration r egisters define the device oper ation. The bus co nfig-

uration r egister (BCR) defines how the CellularRAM inter acts with the system memory bus

and is nearly identical to its counterpart on burst mode Flash devices. The r efr esh configu-

ration register (RCR) i s used to control how refresh is performed on the DRAM array.

These registers are automatically loaded with defaul t setti n gs during power-up and can

be updated any time the devices are operating in a standby state.

Access Using CRE

The configuration registers are loaded using either a synchronous or an asynchronous

WRITE operation when the configuration register enable (CRE) input is HIGH (see

Figure 13 on page 19 and Figure 14 on page 20). When CRE is LOW, a READ or WRITE

operation will access the memory array. The register values are placed on address pins

A[19:0]. In an asynchronous WRITE, the values are latched into the configuration

are “Don’t Care.” Access using CRE is WRITE only. The BCR is accessed when A[19] is

HIGH; the RCR is accessed when A[19] is LOW.

Figure 13: Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY

Operation

Note: A[19] = LOW to load RCR; A[19] = HIGH to load BCR.

A[18:0]

CLK

OPCODE ADDRESS

ADDRESS

DATA VALID

A191

ADV#

CE#

OE#

WE#

LB#/UB#

DQ[15:0]

Initiate Control Register Access

Write Address Bus Value

to Control Register

CRE

tAVStAVH

tAVH

tAVS

tVP

tVPH

tCPH

tWP

tCW

DON’T CARE

Select Control Register

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Configuration Registers

Figure 14: Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY

Operation

Notes: 1. Non-default BCR settings for CR WRITE in synchronous mode followed by READ ARRAY

operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.

3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—addi-

tional WAIT cycles caused by refresh collisions require a corresponding number of addi-

tional CE# LOW cycle s .

CLK

A[18:0]

A192

CRE

ADV#

CE#

OE#

WE#

LB#/UB#

WAIT

DQ[15:0]

tSP

tHD

tCSP

tSP

tHD

High-Z

OPCODE ADDRESS

High-Z

tCEW

Latch Control Register Value

Latch Control Register Address

tCBPH3

DATA

VALID

ADDRESS

DON’T CARE

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Configuration Registers

Software Access

Software access of the configuration registers uses a sequence of asynchronous READ

and asynchronous WRITE operations . The contents of the confi guration r egi sters can be

read or modified using the software sequence.

The configuration registers are loaded using a four-step sequence consisting of two

asynchronous READ operations followed by two asynchronous WRITE operations (see

Figure15). The read sequence is virtually identical except that an asynchronous READ is

performed during the fourth operation (see Figure16 ). Note that a third READ cycle of

the highest address will cancel the access sequence until a different address is read.

The address used during all READ and WRITE operations is the highest address of the

CellularRAM de vice being access ed (FFFFFh for 16Mb); the content at this addr ess is not

changed by using this sequence.

The data value presented during the third operation (WRITE) in the sequence defines

whether the BCR or the RCR is to be accessed. If the data is 0000h, the sequence will

access the RCR; if the data is 0001h, the sequence will access the BCR. During the fourth

operation, DQ[15:0] transfer data into or out of bits 15–0 of the configuration registers.

The use of the software sequence does not affect the ability to perform the standard

(CRE-controlled) method of loading the configuration registers. However, the software

nature of this access mechanism eliminates the need for the control register enable

(CRE) pin. If the software mechanism is used, the CRE pin can simply be tied to VSS. The

port line often used for CRE control purposes is no longer required.

Software access of the RCR should not be used to enter or exit DPD.

Figure 15: Load Configuration Register

ADDRESS

(MAX) ADDRESS

(MAX)

XXXXh XXXXh

RCR: 0000h

BCR: 0001h

CR VALUE

ADDRESS

CE#

OE#

WE#

LB#/UB#

DATA

DON'T CARE

READ READ WRITE WRITE

ADDRESS

(MAX)

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Configuration Registers

Figure 16: Read Configuration Register

ADDRESS

(MAX) ADDRESS

(MAX)

XXXXh XXXXh CR VALUE

OUT

ADDRESS

CE#

OE#

WE#

LB#/UB#

DATA

DON'T CARE

READ READ WRITE READ

RCR: 0000h

BCR: 0001h

ADDRESS

(MAX)

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Configuration Registers

Bus Configuration Register

The BCR defines how the CellularRAM device interacts with the system memory bus.

Page mode operation is enabled by a bit contained in the RCR. F igure17 describes the

control bits in the BCR. At power-up, the BCR is set to 9D4Fh.

The BCR is accessed using CRE and A[1 9] HIGH or through the configuration register

software sequence with DQ = 0001h on the third cy cle.

Figure 17: Bus Configuration Register Definition

Note: All burst WRITEs are continuous.

A13

13 12 11 0

Latency

Counter

321

WAIT

Polarity

WAIT

Configuration (WC)Clock

Configuration (CC)

Output

ImpedanceBurst

Wrap (BW)*

A12A11 A10 A9 A8 A7 A6A5 A4 A3 A2 A1A0

Operation Mode

Synchronous burst access mode

Asynchronous access mode (default)

BCR[12] BCR[11]

Latency Counter

BCR[13]

Code 0–Reserved

Code 1–Reserved

Code 2

Code 3 (Default)

Code 4–Reserved

Code 5–Reserved

Code 6–Reserved

Code 7–Reserved

WAIT Polarity

Active LOW

Active HIGH (default)

BCR[10]

WAIT Configuration

Asserted during delay

Asserted one data cycle before delay (default)

Output Impedance

Full Drive (default)

1/4 Drive

BCR[5]

Burst Wrap (Note 1)

Burst wraps within the burst length

Burst no wrap (default)

BCR[3]

BCR[1] BCR[0] Burst Length (Note 1)

BCR[2]

Burst

Length (BL)*

Reserved

Operating

Mode

Reserved

A14A15

A[18:16]

Select RCR

Select BCR

Must be set to "0"

19 18–16

Select

A19

Reserved

Must be set to "0"Must be set to "0"Must be set to "0"Must be set to "0"

BCR[8]

Clock Configuration

Not supported

Rising edge (default)

BCR[6]

BCR[15]

BCR[19]

4 words

8 words

16 words

Continuous burst (default)

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Configuration Registers

Burst Length (BCR[2:0]) Default = Continuous Burst

Burst lengths define the number of words the device outputs during a burst READ oper -

ation. The device supports a burst length of 4, 8, or 16 words. The device can also be set

in continuous burst mode where data is output sequentially without regard to address

boundaries; the internal address wraps to 000000h if the device is read past the last

address. WRITE bursts are always performed using continuous burst mode.

Burst Wrap (BCR[3]) Default = Burst No Wrap (Within Burst Length)

The burst wrap option determines if a 4-, 8-, or 16-word burst READ wraps within the

burst length or steps through sequential addres ses. If the wrap option is not enabled, the

device outputs data from sequential addresses without regard to burst boundaries; the

internal address wraps to 000000h if the device is read past the last address.

Ta ble 4: Sequence and Burst Length

Burst Wrap Starting

Address

4-Word

Burst

Length 8-Word

Burst Length 16-Word Burst length Continuous Burst

BCR[3] Wrap (Decimal) Linear Linear Linear Linear

0Yes

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-…

1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-…

2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-…

3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-…

4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-…

5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-8-9-10-11-…

6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-9-10-11-12-

7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-…

... ... ...

14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-17-18-19-20-

...

15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-

21...

1No

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-…

1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-…

2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-

17 2-3-4-5-6-7-8-…

3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-

18 3-4-5-6-7-8-9-…

4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-

18-19 4-5-6-7-8-9-10-…

5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-

19-20 5-6-7-8-9-10-11…

6 6-7-8-9-10-11-12-

13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-

20-21 6-7-8-9-10-11-12…

7 7-8-9-10-11-12-13-

14 7-8-9-10-11-12-13-14-...-17-18-19-20-

21-22 7-8-9-10-11-12-13…

... ... ...

14 14-15-16-17-18-19-...-23-24-25-26-27-

28-29 14-15-16-17-18-19-20-

…

15 15-16-17-18-19-20-...-24-25-26-27-28-

29-30 15-16-17-18-19-20-21-

…

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Configuration Registers

Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength

The output driver strength can be altered to adjust for different data bus loading

scenarios. The reduced-strength option should be more than adequate in stacked chip

(Flash + C ellularRAM) e nvironments when ther e is a dedicated memory bus. The r educed -

drive-strength opti on is included to mi nimiz e noise gener a ted on the data bus during

READ operations. Normal output impedance should be se le c ted when using a disc rete

CellularRAM device in a more heavily loaded data bus environment. Partial drive is

approximately one-quarter full drive strength. Outputs are configured at full drive

strength during testing.

WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid

The WAIT c onfig uration bit is used to determine when WAIT transitions between the

asserted and the de-asserted state with respect to valid data presented on the data bus.

The memory controller will use the WAIT signal to coordinate data transfer during

synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid

on the clock edge immed ia tel y afte r WAIT transitions to the de-ass erted or asser te d

state, respectively (see Figures 18 and 20). Wh en BCR [8] = 1, the WAIT signal transitions

one clock period prior to the data bus going valid or invalid (see Figures 19 and 20).

WAIT Polarity (BCR[10]) Default = WAIT Active HIGH

The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or

LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down

resi stor to maintain the de-asserted state.

Figure 18: WA IT Configuration (BCR[8] = 0)

Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 20 on

page 26.

Figure 19: WA IT Configuration (BCR[8] = 1)

Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 20

on page 26.

WAIT

DQ[15:0]

CLK

Data[0] Data[1]

Data immediately valid (or invalid)

High-Z

WAIT

D[15:0]

CLK

Data[0]

Data valid (or invalid) after one clock delay

High-Z

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Configuration Registers

Figure 20: WA IT Configuration During Burst Operation

Note: Non-default BCR setting for WAIT during BURST operation: WAIT active LOW .

Latency Counter (BCR[13:11]) Default = Three-Clock Latency

The latency counter bits determine how many clocks occur between the beginning of a

READ or WRITE operation and the first data value transferred. Only latency code two

(three clocks) or latency code three (four clocks) is allowed (see Table 5 and Figure21).

Operating Mode (BCR[15]) Default = Asynchronous Operation

The operating mode bit selects either synchronous BURST operation or the default

asynchronous mode of operation.

Figure 21: Latency Counter

Ta ble 5: Latency Configuration

Latency Configuration Code

Max Input CLK Frequency (MHz)

104 MHz 80 MHz

2 (3 clocks) 66 (15ns) 53 (18.75ns)

3 (4 clocks) – default 104 (9.62ns) 80 (12.50ns)

WAIT

DQ[15:0]

CLK

D[0] D[1]

BCR[8] = 0

Data valid in current cycle.

BCR[8] = 1

Data valid in next cycle.

DON’T CARE

D[2] D[3] D[4]

A[19:0]

ADV#

DQ[15:0]

CLK

Code 2

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

Code 3 (Default)

DQ[15:0]

DON’T CARE UNDEFINED

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

VALID

ADDRESS

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Configuration Registers

Refresh Configuration Register

The refresh configuration register (RCR) defines how the Cellul arRAM device performs

its transparent self refresh. Altering the refres h parameters can dramatically reduce

curr ent consumption during standby mode. Page mode control is also embedded into

the RCR. Figure 22 describes the control bits used in the RCR. At power-up, the RCR is

set to 0010h.

The RCR is access ed using CRE and A[19] LOW; or through the configuration register

software acces s sequenc e with DQ = 0000h on the third cycle (see “Configuration Regis-

ters” on page 19.)

Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh

The PAR bits restrict refresh operation to a portion of the total memory array. This

feature allows the device to reduce standby current by refreshing only that part of the

memory array required by the host system. The refresh options are full array, one-half

array, one-quarter array, one-eighth array, or none of the array. The mapping of these

partitions can start at either the beginning or the end of the address map (see Table 6 on

page 28).

Figure 22: Refresh Configuration Register Mapping

PAR

A4 A3 A2 A1 A0 Address Bus

45 1

RESERVED RESERVED

Deep Power-Down

DPD Enable

DPD Disable (default)

RCR[4]

TCR

RCR[6] RCR[5]

Maximum Case Temp.

+85°C

Internal sensor (default)

+45°C

+15°C

All must be set to "0"

A[18:8]

18–8

Select

A19

Select RCR

Select BCR

RCR[19] RCR[1]

RCR[0]

Refresh Coverage

Full array (default)

Bottom 1/2 array

Bottom 1/4 array

Bottom 1/8 array

RCR[2]

None of array

Top 1/2 array

Top 1/4 array

Top 1/8 array

DPD

Must be set to "0"

PAGE

Page Mode Enable/Disable

Page Mode Disabled (default)

Page Mode Enable

RCR[7]

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Configuration Registers

Deep Power-Down (RCR[4]) Default = DPD Disabled

The deep po wer -down bit enables and disables all refresh-relate d activity. This mode is

used if the system does not require the stor age provided by the CellularRAM device. Any

stor ed data will become corrupted when DPD is enabled. When r efr esh activity has been

re-enabled, the CellularRAM device will require 150µs to perform an initialization

procedure before normal operations can resume.

Deep po wer -do wn is enabled when R CR[4] = 0, and r emains enabled until RCR[4] is set to

“1.” DPD should not be enabled or disabled with the software access sequence; instead,

use CRE to access the RCR.

Temperature-Compensated Refresh (RCR[6:5]) Default = On-Chip Temperature Sensor

This CellularRAM device includes an on-chip temperature sensor that automatically

adjusts the refresh rate according to the operating temperature. The on-chip TCR is

enabled by clearing both of the TCR bits in the refr esh configur ation r egister (RCR[6:5] =

00b). Any other TCR setting enables a fixed refresh rate. When the on-chip temperature

sensor is enabled, the device continually adjusts the refresh rate according to the oper-

ating temperature.

The TCR bits also allow for adequate fixed-rate refresh at three different temperature

thresholds (+15°C, +45°C, and +85°C) . The setting selected must be for a temperature

higher than the case temperature of the CellularRAM device. If the case temperature

is +35°C, the system can minimize self refresh current consumption by selecting the

+45°C setting. The +15°C setting would result in inadequate refreshing and cause

data corruption.

Page Mode Operation (RCR[7]) Default = Disabled

The page mode operation bit determines whether page mode is enabled for asynchro-

nous READ operations. In the power-up default state, page mode is disabled.

Table 6: 16Mb Address Patterns for PAR (RCR[4] = 1)

RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density

0 0 0 Full die 000000h–0FFFFFh 1 Meg x 16 16Mb

0 0 1 One-half of die 000000h–07FFFFh 512K x 16 8Mb

0 1 0 One-quarter of die 000000h–03FFFFh 256K x 16 4Mb

0 1 1 One-eighth of die 000000h–01FFFFh 128K x 16 2Mb

1 0 0 None of die 0 0 Meg x 16 0Mb

1 0 1 One-half of die 80000h–0FFFFFh 512K x 16 8Mb

1 1 0 One-quarter of die C0000h–0FFFFFh 256K x 16 4Mb

1 1 1 One-eighth of die E0000h–0FFFFFh 128K x 16 2Mb

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Electrical Characteristics

Notes: 1. –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C.

S tresses gr eater than those listed may cause permanent damage to the device . This is a

stress rating only, and functional operation of the device at these or any other condi-

tions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may

affect reli ability.

Ta ble 7: Absolute Maximum Ratings

Parameter Rating

Voltage to any ball except VCC, VCCQ relative

to VSS –0.5V to (4.0V or VCCQ + 0.3V, whichever is

less)

Voltage on VCC supply relative to VSS –0.2V to +2.45V

Voltage on VCCQ supply relative to VSS –0.2V to +4.0V

Storage temperature (plastic) –55ºC to +150ºC

Operating temperature (case)

Wireless1

Industrial –30ºC to +85ºC

–40ºC to +85ºC

Soldering temperature and time

10 seconds (solder ball only) +260ºC

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Electrical Characteristics

Notes: 1. –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C.

2. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.

3. VIH (MIN) value is not aligned with CellularRAM work group 1.0 specification of VCCQ - 0.4V.

4. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions.

5. BCR[5] = 0b.

6. This parameter is specified with the outputs disabled to avoid external loading effects. The

user must add the current required to drive output capacitance expected in the actual sys-

tem.

7. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85°C. In order to

achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB might be

slightly higher for up to 500ms after power-up, after changes to the P AR array partition, or

when entering standby mode.

Table 8: Electrical Characteristics and Operating Conditions

Wireless Temperature1 (–30ºC < TC < +85ºC); Industrial Temperature (–40ºC < TC < +85ºC)

Description Conditions Symbol Min Max Units Notes

Supply voltage VCC 1.7 1.95 V

I/O supply voltage VCCQ1.73.3V

Input high volt ag e VIH 1.4 VCCQ + 0.2 V 2, 3

Input low voltage VIL –0.2 0.4 V 4

Output high voltage IOH = –0.2mA VOH 0.8 VCCQV5

Output low voltage IOL = +0.2mA VOL 0.2 VCCQV 5

Input leakage current VIN = 0 to VCCQILI 1µA

Output leakage current OE# = VIH or

Chip disabled ILO 1µA

Operating Current

Asynchronous random READ/

WRITE VIN = VCCQ or 0V

Chip enabled,

IOUT = 0

ICC1–70 20mA6

Asynchronous page READ ICC1P –70 15 mA 6

Initial access, burst READ/WRITE ICC2 104 MHz 35 mA 6

80 MHz 30

Continuous burst READ ICC3R 104 MHz 28 mA 6

80 MHz 22

Continuous burst WRITE ICC3W 104 MHz 33 mA 6

80 MHz 25

Standby current VIN = VCCQ or 0V

CE# = VCCQISB Standard 70 µA 7

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Electrical Characteristics

Maximum and Typical Standby Currents

The follo wing table and figur e r efer to the maximu m and typical standb y cur re nts for the

MT45W1MW16BDGB device . The typical values shown in Figure23 are measur ed with

the default on-chip temper atur e sens or control enabled. The maximum val ues shown in

Table 9 are measured with the relevant TCR bits set in the configuration register.

Notes: 1. For RCR[6:5] = 00b (default) refer to Figure 23, T ypical Refresh Current vs. Temperature (Itcr)

for typical values.

2. In order to achieve low standby current, all inputs must be driven to VCCQ or VSS. ISB might

be slightly higher for up to 500ms after power-up, after changes to the PAR array portion,

or when entering standby mode.

3. TCR values for 85°C are 100 perce nt tested. TCR values for 15°C and 45°C are sampled only.

4. Typical ISB currents for each PAR setting with the appr opriate TC R se le cted, or temp erature

sensor enabled.

Figure 23: Typical Refresh Current vs. Temperature (ITCR)

Note: Typical ISB currents for each PAR setting with the appropriate TCR selected, or temperature

sensor enabled.

Table 9: Maximum Standby Currents for Applying PA R and TCR Settings

PAR

TCR

Units+15°C (RCR[6:5] = 10b) +45°C (RCR[6:5] = 01b) +85°C (RCR[6:5] = 11b)

Full array 45 60 70 µA

1/2 array 40 55 65 µA

1/4 array 37 50 60 µA

1/8 array 37 50 60 µA

0 array 35 45 55 µA

-45°C

-35°C

-25°C

-15°C

-05°C

05°C

15°C

25°C

35°C

45°C

55°C

65°C

75°C

85°C

Tem pe rature (°C)

ISB (µA)

PAR FULL

PAR 1/2

PAR 1/4

PAR 0

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Electrical Characteristics

Notes: 1. These parameters are verified in device characterization and are not 100-percent tested.

Figure 24: AC Input/Output Reference Waveform

Notes: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fal l

times (10% to 90%) < 1.6ns.

2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ,

the input test point may not be shown to scale.

3. Output timing ends at VCCQ/2.

Figure 25: Output Load Circuit

Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b).

Table 10: Deep Power-Down Specifications

Description Conditions Symbol Typ Units

Deep power-down VIN = VCCQ or 0V; +25°C IZZ 10 µA

Ta ble 11: Capacitance

Description Conditions Symbol Min Max Units Notes

Input capacitance TC = +25ºC; f = 1 MHz;

VIN = 0V CIN 2.0 6.5 pF 1

Input/output capacitance (DQ) CIO 3.0 6.5 pF 1

Output

Test Points

Input

Q/2

DUT VccQ/2

30pF

Test Point

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Timing Requirements

Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b).

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The

High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.

3. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The Low-

Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either

VOH or VOL.

4. Page mode enabled only.

Ta ble 12: Asynchronous READ Cycle Timing Requirements

Parameter1Symbol

70ns

Units NotesMin Max

Address access time tAA 70 ns

ADV# access time tAADV 70 ns

Page access time tAPA 20 ns

Address hold from ADV# HIGH tAVH 5 ns

Address setup to ADV# HIGH tAVS 10 ns

LB#/UB# access time tBA 70 ns

LB#/UB# disable to DQ High-Z output tBHZ 8 ns 4

LB#/UB# enable to Low-Z output tBLZ 10 ns 3

Maximum CE# pu lse width tCEM 8 µs 2

CE# LOW to WAIT valid tCEW 1 7.5 ns

Chip select access time tCO 70 ns

CE# LOW to ADV# HIGH tCVS 10 ns

Chip disable to DQ and WAIT High-Z output tHZ 8 ns 4

Chip enable to Low-Z output tLZ 10 ns 3

Output enable to valid output tOE 20 ns

Output hold from address change tOH 5 ns

Output disable to DQ High-Z output tOHZ 8 ns 4

Output enable to Low-Z output tOLZ 3 ns 3

Page cycle time tPC 20 ns

READ cycle time tRC 70 ns

ADV# pulse wid t h L OW tVP 10 ns

ADV# pulse width HIGH tVPH 10 ns

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Timing Requirements

Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b).

2. When configure d for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-

vided every tCEM. A refresh opportunity is satisfied by either of the following two condi-

tions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns.

3. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The

High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.

4. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The Low-

Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either

VOH or VOL.

Table 13: Burst READ Cycle Timing Requirements

Parameter1Symbol

104 MHz 80 MHz

Units NotesMin Max Min Max

Burst to READ access time tABA 35 46.5 ns

CLK to output delay tACLK 7 9 ns

Burst OE# LOW to output delay tBOE 20 20 ns

CE# HIGH between subsequent burst and

mixed-mode operations

tCBPH 5 5 ns 2

Maximum CE# pu lse width tCEM 8 8 µs

CE# LOW to WAIT valid tCEW 1 7.5 1 7.5 ns

CLK period tCLK 9.62 20 12.5 20 ns

CE# setup time to active CLK edge tCSP 3 20 4.5 20 ns

Hold time from active CLK edge tHD 2 2 ns

Chip disable to DQ and WAIT High-Z output tHZ 8 8 ns 3

CLK rise or fall time tKHKL 1.6 1.8 ns

CLK to WAIT valid tKHTL 7 9 ns

Output HOLD from CLK tKOH 2 2 ns

CLK HIGH or LOW time tKP 3 4 ns

Output disable to DQ High-Z output tOHZ 8 8 ns 3

Output enable to Low-Z output tOLZ 3 3 ns 4

Setup time to active CLK edge tSP 3 3 ns

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Timing Requirements

Notes: 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The Low-

Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either

VOH or VOL.

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The

High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.

3. WE# LOW time must be limited to tCEM (8µs).

Table 14: As ynchronous WRITE Cycle Timing Requirements

Parameter Symbol

70ns

Units NotesMin Max

Address and ADV# LOW setup time tAS 0 ns

Address hold from ADV# going HIGH tAVH 5 ns

Address setup to ADV# going HIGH tAVS 10 ns

Address valid to end of WRITE tAW 70 ns

LB#/UB# select to end of WRITE tBW 70 ns

CE# LOW to WAIT valid tCEW 1 7.5 ns

Async address-to-burst transition time tCKA 70 ns

CE# HIGH between subsequent asynchronous operations tCPH 5 ns

CE# LOW to ADV# HIGH tCVS 10 ns

Chip enable to end of WRITE tCW 70 ns

Data hold from WRITE time tDH 0 ns

Data WRITE setup time tDW 23 ns

Chip disable to WAIT High-Z output tHZ 8 ns

Chip enable to Low-Z output tLZ 10 ns 1

End WRITE to Low-Z output tOW 5 ns 1

ADV# pulse wid t h tVP 10 ns

ADV# pulse width HIGH tVPH 10 ns

ADV# setup to End of WRITE tVS 70 ns

WRITE cycle time tWC 70 ns

WRITE to DQ High-Z output tWHZ 8 ns 2

WRITE pulse width tWP 46 ns 3

WRITE pulse width HIGH tWPH 10 ns

WRITE recovery time tWR 0 ns

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Timing Requirements

Notes: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-

vided every tCEM. A refresh opportunity is satisfied by either of the following two condi-

tions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns.

Figure 26: Initialization Period

Table 15: Burst WRITE Cycle Timing Requirements

Parameter Symbol

104 MHz 80 MHz

Units NotesMin Max Min Max

CE# HIGH between subsequent burst and

mixed-mode operations

tCBPH 5 5 ns 1

Minimum CE# pulse width tCEM 8 8 µs 1

CE# LOW to WAIT valid tCEW 1 7.5 1 7.5 ns

Clock period tCLK 9.62 20 12.5 20 ns

CE# setup to CLK active edge tCSP 3 20 4.5 20 ns

Hold time from active CLK edge tHD 2 2 ns

Chip disable to WAIT High-Z output tHZ 8 8 ns

CLK rise or fall time tKHKL 1.6 1.8 ns

Clock to WAIT valid tKHTL 7 9 ns

CLK HIGH or LOW time tKP 3 4 ns

Setup time to active CLK edge tSP 3 3 ns

Table 16: Initialization Timing Parameters

Parameter Symbol

-70

UnitsMin Max

Initialization period (required before normal operations) tPU 150 µs

tPU

Vcc, VccQ = 1.7V

Vcc (MIN)

Device ready for

normal operation

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Timing Diagrams

Figure 27: Asynchronous READ

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

A[19:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

tAA

tHZ

tBA

High-Z High-Z

tRC

tCO tBHZ

tOHZ

tOE

tCEW tHZ

VALID OUTPUT

High-Z

UNDEFINED

DON’T CARE

tBLZ

tLZ

tOLZ

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Timing Diagrams

Figure 28: Asynchronous READ Using ADV#

A[19:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

tVPH

tAADV

tAA

tVP

tHZ

tBA

High-Z High-Z

tCVS

tCO

tBLZ

tBHZ

tOHZ

tLZ

tOE

tOLZ

VALID OUTPUT

tAVH

tAVS

High-Z

UNDEFINED

DON’T CARE

tCEW tHZ

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

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Timing Diagrams

Figure 29: Page Mode READ

A[3:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

tAA

tHZ

tBA

High-Z High-Z

tCO

tCEM

tBLZ

tBHZ

tOHZ

tLZ

tOE

tOLZ

tCEW tHZ

High-Z

UNDEFINED

DON’T CARE

A[19:4] VALID ADDRESS

VALID

ADDRESS VALID

ADDRESS

tRC

VALID

OUTPUT

tAPA

tPC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

tOH

VALID

OUTPUT VALID

OUTPUT

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Timing Diagrams

Figure 30: Single-Access Burst READ Operation

Notes: 1. Non-default BCR settings for single-access burst READ opera tion: Latency code two (three

clocks); WAIT active LOW; WAIT asserted during delay.

A[19:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK

VIH

VIL

VOH

VOL

CLK

ACLK

CEW

ABA

VALID

OUTPUT

VALID

ADDRESS

High-Z

KOH

OHZ

LB#/UB#

VIH

VIL

CSP

CEM

High-Z

OLZ

High-Z

KHKL

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

KHTL

BOE

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Timing Diagrams

Figure 31: 4-Word Burst READ Operation

Note: Non-default BCR settings for 4-word burst READ operation: Latency code two (three

clocks); WAIT active LOW; WAIT asserted during delay.

A[19:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tSP

tCLK

tKHKL

tHD

tABA

VALID

ADDRESS

High-Z

tKOH

tHZ

tHD

tSPtHD

LB#/UB# VIH

VIL

High-Z

tOLZ

tCBPH

tCSP

tCEM

tSPtHD

tOHZ

tKP tKP

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

tCEW

tACLK

tKHTL

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

tBOE

High-Z

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Timing Diagrams

Figure 32: READ Burst Suspend

Note: Non-default BCR settings for READ burst suspend: Latency code two (three clocks); WAIT

active LOW; WAIT asserted during delay.

A[19:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tSPtHD

High-Z

tOLZ

tACLK

LB#/UB# VIH

VIL

tCLK

tSPtHD

tCSP

tCEM

tSPtHD

tKOH

VALID

OUTPUT VALID

OUTPUT

VALID

ADDRESS

High-Z

tCBPH

tOHZ

VALID

OUTPUT VALID

OUTPUT

tBOE

OHZ

tBOE

tOLZ

VALID

ADDRESS

High-Z

DON’T CARE UNDEFINED

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Timing Diagrams

Figure 33: Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row

Condition

Notes: 1. Non-default BCR settings for continuous burst READ showing an output delay, BCR[8] = 0

for end-of-row condition: Latency code two (three clocks); WAIT active LOW; WAIT asserted

during delay.

2. WAIT will be asserted a maximum of (2 × LC) cycles (BCR[8] = 0; WAIT asserted during

delay). LC = latency code (BCR[13:11]).

3. CE# must not remain LOW longer than tCEM.

tACLK tKOH

A[19:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tKHTL tKHTL

tCLK

LB#/UB# VIH

VIL

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

Note 2

Note 3

DON’T CARE

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Timing Diagrams

Figure 34: CE#-Controlled Asynchronous WRITE

A[19:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

High-Z High-Z

tWC

tCEW tHZ

VALID INPUT

tAW

DON’T CARE

tWR

tCW

tDW

DQ[15:0]

OUT

tWHZ

tBW

tLZ

tDH

tAS

tWP

tWPH

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

High-Z

tCPH

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Timing Diagrams

Figure 35: LB#/UB#-Co ntrolled Asynch ronous WRITE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

A[19:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

IN VIH

VIL

VALID ADDRESS

High-Z

tWC

tCEW tHZ

VALID INPUT

tAW

DON’T CARE

tWR

tCW

tDW

DQ[15:0]

OUT VOH

VOL

tWHZ

tBW

tLZ

tDH

tAS

tWP

tWPH

High-Z

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Timing Diagrams

Figure 36: WE#-C ontrolled Asynchronous WRITE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

A[19:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VIH

VIL

VALID ADDRESS

tWC

tCEW tHZ

VALID INPUT

tAW

DON’T CARE

tWR

tDW

DQ[15:0]

OUT

VOH

VOL

tWHZ

tBW

tCW

tLZ

tWP

tDH

tOW

tAS

tWPH

High-Z

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Timing Diagrams

Figure 37: Asynchronous WR ITE Using AD V#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

A[19:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

IN VIH

VIL

VALID ADDRESS

High-Z High-Z

tCEW tHZ

VALID INPUT

tVS

DON’T CARE

tCW

tDW

DQ[15:0]

OUT VOH

VOL

tWHZ

tBW

tLZ

tWP

tDH

tOW

tAS

tWPH

tAS

tVPH

tAVH

tAVS

tVP

tAW

High-Z

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Timing Diagrams

Figure 38: Burst WRITE Operation

Note: Non-default BCR settings for burst WRITE operation: Latency code two (three clocks);

WAIT active LOW; WAIT asserted.

A[19:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

CLK tKP

tSP tHD

tCSP

tCEM

D[3] D[2] D[1] D[0]

VALID

ADDRESS

tHD

tSP

tHD

tSP

tHD

tSP

High-Z High-Z

LB#/UB# VIH

VIL

tSP tHD

tHD

DON’T CARE

WRITE Burst Identified

(WE# = LOW)

tCBPH

tKHTL tHZ

tCEW

tKP tKHKL

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Timing Diagrams

Figure 39: Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row

Condition

Notes: 1. Non-default BCR settings for continuous burst WRITE , BCR[8] = 0; WAIT active LOW; WAIT

asserted during delay. Do not cross row boundaries with fixed latency.

2. CE# must not remain LOW longer than tCEM.

3. W A IT as se r ts fo r anywhere from LC to 2LC cyc l e s. LC = lat en cy co de (BCR [1 3:11]).

4. Taking CE# HIGH or ADV# LOW on the start-of-row cycle will abort the burst and not write

the start-of-row data. Devices from different CellularRAM vendors can assert WAIT so that

the start-of-row data is input just before (as shown), or just after WAIT asserts. This differ-

ence in behavior will not be noticed by controllers that monitor WAIT, or that use WAIT to

abort on the start-of-row input cycle.

A[19:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

tKHTL tKHTL

tCLK

tSP tHD

VALID INPUT VALID INPUT

Start of row

(A[6:0] = 00h)

(NOTE 4)

End of row

(A[6:0] = 7Fh)

Note 3

Note 4

VALID INPUT VALID INPUT

DON’T CARE

VIH

VIL

LB#/UB#

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Timing Diagrams

Figure 40: Burst WRITE Followed by Burst READ

Notes: 1. Non-default BCR settings for burst WRITE followed by burst READ: Latency code two (three

clocks); WAIT active LOW; WAIT asserted during delay.

2. When configure d for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-

vided every tCEM. A refresh opportunity is satisfied by either of the following two condi-

tions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that the CellularRAM

Workgroup 1.0 specification requires CE# to be clocked HIGH to terminate the burst.

3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

A[19:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL

tCLK

tSP

tSPtHD

tCSP

D[3]D[2]D[1]

D[0]

VALID

ADDRESS

tHD

tSP

tHD

tSP

tSPtHD

VALID

ADDRESS

tABA

tCSPtOHZ

tKOH

tACLK VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

High-Z

High-Z VOH

VOL

LB#/UB# VIH

VIL

tHD

tSPtHD

tHD

High-Z

UNDEFINED

DON’T CARE

tBOE

tCBPH

High-Z

tSPtHD

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Timing Diagrams

Figure 41: Asynchronous WR ITE Followed by Burst READ

Notes: 1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Latency code

two (three clocks); W AIT active LOW; WAIT asserted during delay.

2. When configure d for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-

vided every tCEM. A refresh opportunity is satisfied by either of the following two condi-

tions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that the CellularRAM

Workgroup 1.0 specification requires CE# to be clocked HIGH to terminate the burst.

3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

tCLK

tSPtHD

VALID

ADDRESS

tOHZ

tKOH

tACLK

High-Z

VALID ADDRESS VALID ADDRESS

tAVStAVH tAW tWR

tVP tVS

tCKA

A[19:0] VIH

VIL

ADV# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL

VOH

VOL

CE# VIH

VIL

LB#/UB# VIH

VIL tCW

tWPH

tAS

tWP

tWC

tDH tDW

DATA DATA

High-Z

tCVStHD

tSP

tCEW

tSPtHD

tCSP

tWC

tBW

tWHZ

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

DON’T CARE UNDEFINED

tABA

tBOE

tCBPH2

tVPH

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Timing Diagrams

Figure 42: Asynchronous WR ITE Followed by Burst READ – ADV# LOW

Notes: 1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Latency code

two (three clocks); W AIT active LOW; WAIT asserted during delay.

2. When configure d for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-

vided every tCEM. A refresh opportunity is satisfied by either of these conditions: a) clocked

CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0

specification requires CE# to be clocked HIGH to terminate the burst.

3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.

VALID ADDRESS VALID ADDRESS

A[19:0] VIH

VIL

ADV# VIH

VIL

OE#

WE#

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB# VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCW

tWPH

tWP

tWC

tDH tDW

tHZ

DATA

tHZ

High-Z

VALID ADDRESS

tAA

tBHZ

tCPH1tCO

VALID

OUTPUT

High-Z

tOE

tOLZ

tLZ

tBLZ

tOHZ

tHZ

tAW tWR

tBW

DON’T CARE UNDEFINED

DATA

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Timing Diagrams

Figure 43: Burst READ Followed by Asynchronous WRITE (WE#-Controlled)

Notes: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-

vided every tCEM. A refresh opportunity is satisfied by either of the following two condi-

tions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that CellularRAM

Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burst.

A[19:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

CLK

ACLK

CEW

ABA

tCW

VALID

OUTPUT

VALID

ADDRESS

High-Z

KOH

OHZ

LB#/UB#

CSP

High-Z

OLZ

WPH

READ Burst Identified

(WE# = HIGH)

KHTL

BOE

VALID

ADDRESS

VALID

INPUT

High-Z

CEW

CBPH

DON’T CARE UNDEFINED

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Timing Diagrams

Figure 44: Burst READ Followed by Asynchronous WRITE Using ADV#

Notes: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-

vided every tCEM. A refresh opportunity is satisfied by either of the following two condi-

tions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that CellularRAM

Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burst.

A[19:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

CLK

tSP

tCLK

tCEW

tHD

tABA

tVPH tVS

tAVStAVH

tAW

tCW

VALID

OUTPUT

VALID

ADDRESS

High-Z

tKOH tDW

tOHZ

tSPtHD tVP

LB#/UB#

tCSP

High-Z

OLZ

tHD

WPH

tHD tBW

tSP

tHZ

tHD

tSP

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

tKHTL

VALID

ADDRESS

VALID

INPUT

High-Z

tCEW tHZ

tCBPH

tACLK

tBOE

tAS

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Timing Diagrams

Figure 45: Asynchronous WR ITE Followed by Asynchronous READ – ADV# LOW

Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least

5ns (tCPH) to schedule the appropriate internal refresh operation. Otherwise, tCPH is only

required after CE#-controlled WRITEs.

VALID ADDRESS VALID ADDRESS

A[19:0] VIH

VIL

ADV# VIH

VIL

OE#

WE#

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB# VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCW

tWPH

tWP

tWC

tDH tDW

tHZ

DATA

tHZ

High-Z

VALID ADDRESS

tAA

tBHZ

tCPH1tCO

VALID

OUTPUT

High-Z

tOE

tOLZ

tLZ

tBLZ

tOHZ

tHZ

tAW tWR

tBW

DON’T CARE UNDEFINED

DATA

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Timing Diagrams

Figure 46: Asynchronous WR ITE Followed by Asynchronous READ

Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least

5ns (tCPH) to schedule the appropriate internal refresh operation. Otherwise, tCPH is only

required after CE#-controlled WRITEs.

VALID ADDRESS VALID ADDRESS

tAVS tAVH

tVPH tVP tVS

A[19:0] VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADV#

OE#

WE#

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB#

tVP

tAVH

tCW

tWPH

tAS tWP

tWC

tDH tDW

DATA DATA

High-Z

VALID ADDRESS tAA

tBHZ

tAADV

tCPH1 tCO

VALID

OUTPUT

High-Z

tCVS

tOLZ

tLZ

tAS

tBLZ

tOHZ

tHZ

tAW tWR

tBW

UNDEFINED

DON’T CARE

tOE

tAVS

tCVS

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comm ent Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron

Technology, Inc. inside the U.S. and a trademark of Infineon Technologies outside the U.S. All other trademarks are the prop-

erty of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power

supply and temperature range for production devices. Alt hough consider ed final, the se specific ations ar e subjec t to change,

as further product development and data characterization sometimes occur.

16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Package Dimensions

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Package Dimensions

Figure 47: 54-Ball VFBGA

Notes: 1. All dime nsions in millimeters; MAX/MIN, or typical, as noted.

2. Package width and length do not incl ude mold protrusion; allowable mold protrusion is

0.25mm per side.

3. The MT45W1MW16BDGB uses “green” packaging.

BALL A1 ID

0.70 ±0.05

SEATING

PLANE

0.10 A

1.00 MAX

BALL A6 BALL A1

BALL A1 ID

0.75

TYP

0.75 TYP

1.875

3.75

6.00 ±0.10

3.00 ±0.05

DIMENSIONS APPLY

TO SOLDER BALLS

POST REFLOW.

PRE-REFLOW BALL

DIAMETER IS 0.35

ON A 0.30 SMD

BALL PAD.

54X Ø0.37

SOLDER BALL MATERIAL:

96.5% Sn, 3% Ag, 0.5% Cu

MOLD COMPOUND:

EPOXY NOVOLAC

SUBSTRATE MATERIAL:

PLASTIC LAMINATE

6.00

3.00

4.00 ±0.05

8.00 ±0.10

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Revision History

Rev. F, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1/06

•Updated Rev. letter to F

Rev. F, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 6/06

• Changed the title of Figure 10 to “Wired-OR Wait Configuration”

• Updated wording in the third paragraph of “WAIT Operation” on page 15 to the

follo wing : “ D uring a Burs t cycle, CE# must remain asserted until the first data is vali d.

Bringing CE# HIGH during this initial latency may cause data corruption.”

•Changed WAIT from “

tCW” to “tCEW” in Figure 14

• Changed Min/Max columns from “-701” and “-708,” to “104 MHz” and “80 MHz” in

Table 5

• Changed “Output enable to Low-Z output” MIN value from 5 to 3 in Table 12

• Changed Min/Max columns from “-70” to “70ns” in Table 12

• Removed “CLK to DQ High-Z Output” and “CLK to Low-Z Output” rows from

Table 13

• Changed “Output enable to Low-Z output” MIN value from 5 to 3 in Table 13

• Changed Min/Max columns from “-701” and “-708,” to “104 MHz” and “80 MHz” in

Table 13

• Changed Min/Max columns from “-70” to “70ns” in Table 14

• Changed Min/Max columns from “-701” and “-708,” to “104 MHz” and “80 MHz” in

Table 15

• Changed Min/Max columns from “-70” to “70ns” in Table 16

• Re moved tWHZ lines and arrows in Figure 42

• Re moved tWHZ lines and arrows in Figure 45

• Re moved tWHZ lines and arrows in Figure 46

Rev. E, Production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .02/06

Rev. D, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .01/06

•Changed V

IH and VIL to VOH and VOL in Figure 27, 28, 29, 34, 35, 36, 37

• Updated Continuous burst READ and Standby specifications in “Features” section

• Updated document designator to Preliminary

• Deleted Tables 17–43.

Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/05

• Deleted “4-Word Burst READ Operation (with LB#/UB# )” ti ming diagram

• Changed file name to new standard: p23z16_b_cr1-0 to 16mb_burst_cr1_0_p23z

Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/05

• Fixed exceptions to template (primarily mi nor formatti ng on page 1)

• Page 1, Figur e 1: changed E3 ball color to white

• Page 1: changed mu lti pl e “-” to “–” for negative n umbers (per style)

• Eliminated holdover refere nces to dual par ts (pgs. 10 and 30)

• U pdated to state that “ CLK must be held static L O W or HIGH” during async READ and

WRITE (pgs. 7, 10, 11, 14)

• Updated note 4 in Table 8 to eliminate reference to dual part (was “BCR[5:4] = 00b”)

Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .08/05

• Initial release with “Advance” designation.