AN180 - Cirrus Logic, Inc.



Cirrus Logic, Inc. 2000

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

AN180

Application Note

USING A PLL TO GENERATE CLOCKS FOR DIGITAL AUDIO

Note: Cirrus Logic assumes no responsibility for the attached information which is

provided “AS IS” without warranty of any kind (expressed or implied).

SEP ‘00

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TABLE OF CONTENTS

1. INTRODUCTION .......................................................................................................................3

2. BACKGROUND ........................................................................................................................3

3. CIRCUIT DESCRIPTION ..........................................................................................................3

LIST OF TABLES

Table 1. List of Audio Sample Rates and Corresponding Frequency Select Bits ...........................5

LIST OF FIGURES

Figure 1. Typical PLL Circui t ............ ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ................... .. ..... ....4

Figure 2. EP7209/12/7312 ICS548-02 Interface .............................................................................4

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mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information

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1. INTRODUCTION

This application note describes how to use a low-

cost PLL (Phase Lock Loop) circuit to generate

sample freq uencies required for high qua lity digital

audio for use with MP3.

2. BACKGROUND

Cirrus Logic EPD-7209/12/7312 ARM®-based

microcontrollers are capable of decoding MP3

digital audio in real time. The decoded bit stream is

sent to a Crystal CS43L41 DAC using a high-speed

Digital Audio Interface (DAI). The DAC requires

an MCLK clock signal that is 256 times the desired

sample rate. A typical sample rate for MP3 digital

audio is 44.1 kHz, but other frequencies are used as

well, including 8-, 16-, 22.05-, 24-, 32-, and

48 kHz. A PLL clocking scheme is capable of

producing these clocks with little or no error.

Although it is possible to use the DSP capabilities

of the ARM processor to do software sample rate

conversion (SRC), a hardware approach is much

simpler and reduces the number of MIPS (and

thereby the power consumption) required of the

processor. (Software SRC is supported by Cirrus

Logic’s MP3 player software.)

A brute-force (and potentially more expensive)

method of providing multiple clocks is to switch

between separate crystal oscillators. A better

choice is to take advantage of PLL technology to

synthesize the desired frequencies using one crystal

source.

A PLL can be used to multiply a reference

frequency by placing a divider circuit in the

feedback loop from the VCO (voltage controlled

oscillator) output to the phase comparator input as

shown in Figure 1. If the divider circuit is

programmable, then multiple frequency outputs are

generated.

3. CIRCUIT DESCRIPTION

Refer to Figure 2 while reading this section.

The circuit is based upon the Integrated Circuit

Systems ICS548-02, a low-cost, low-jitter, high-

performance clock synthesizer designed to produce

audio sampling rates for MP3 and other digital

audio systems. Using analog/digital Phase-Locked

Loop (PLL) techniques, the device uses an

inexpensive 14.7456 MHz or 3.6864 MHz crystal

input to produce 256x all of the popular audio

sampling frequencies. With a separate 3.6864 MHz

input, the chip provides a clock output, allowing it

to drive the MCLK input on the CS43L41 directly.

Alternatively, the MOSCOUT oscillator drive

output of the EP7209/12/7312 can provide the

clock to the ICS548-02. This approach may be the

preferred method to use since the EP7209/12/7312

manages the power consumption by going into a

Standby mode when not in use. This mode

effectively disables the 3.6864 MHz oscillator that

reduces overall system power consumption. Using

the external 14.7456 MHz oscillator, the PLL w ill

generate MCLK for all sampling frequencies

except 8 KHz.

The ISC548-02 uses 4 digital inputs to select the

frequency (S0, S1, S2, and S3). The control inputs

can be connected directly to four GPIO output pins

of the EP72xx and adjusted under software control.

Table 1 lists the frequencies generated by the

ICS548-02 PLL circuit as a function of the four

input select pins. Notice that S3 is always a one.

This pin could be wired to Vdd freeing up an e xtra

72xx/7312 GPIO pin.

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Figure 1. Typical PLL Circuit

Reference

Clock Phase

Comparator

Programmable Divide

by N Counter

VCO

(Voltage Control

Oscillator)

Loop

Filter

S[3..0] F

OUT

=CLK

REF

CLK

REF

IC548-02

MOSCOUT

GPIO[0..3]

SYNC

SCLK

SDTX

MCLK

CS43L41

DAC

S[0:3]

CLK

EP7209

3.6864 MHz

0.01

F10K

Figure 2. EP7209/12/7312 ICS548-02 Interface

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NOTE: Actual values are 256 times the desired sample rate. Reference clock for this table is 3.6864 MHz.

Desired Sampling Rate

(Kilo-Hertz) Output Clock 256 x SR

(Mega-Hertz) Frequency Select Pins

S3 S2 S1 S0

8 2.048 1111

16 4.096 1000

22.05 5.6448 1001

24 6.144 1010

32 8.192 1100

44.1 11.2896 1101

48 12.288 1110

Table 1. List of Audio Sample Rates and Corresponding Frequency Sel ect Bit s