5962R0722701VZA - NATIONAL SEMICONDUCTOR

ADC128S102QML

ADC128S102QML 8-Channel, 50 kSPS to 1 MSPS, 12-Bit A/D Converter

Literature Number: SNAS411M

ADC128S102QML

January 13, 2011

8-Channel, 50 kSPS to 1 MSPS, 12-Bit A/D Converter

General Description

The ADC128S102 is a low-power, eight-channel CMOS 12-

bit analog-to-digital converter specified for conversion

throughput rates of 50 kSPS to 1 MSPS. The converter is

based on a successive-approximation register architecture

with an internal track-and-hold circuit. It can be configured to

accept up to eight input signals at inputs IN0 through IN7.

The output serial data is straight binary and is compatible with

several standards, such as SPI™, QSPI™, MICROWIRE™,

and many common DSP serial interfaces.

The ADC128S102 may be operated with independent analog

and digital supplies. The analog supply (VA) can range from

+2.7V to +5.25V, and the digital supply (VD) can range from

+2.7V to VA. Normal power consumption using a +3V or +5V

supply is 2.3 mW and 10.7 mW, respectively. The power-

down feature reduces the power consumption to 0.06 µW

using a +3V supply and 0.25 µW using a +5V supply.

Features

■Total Ionizing Dose 100 krad(Si)

■Single Event Latch-up 120 MeV-cm2/mg

■Eight input channels

■Variable power management

■Independent analog and digital supplies

■SPI/QSPI/MICROWIRE/DSP compatible

■Packaged in 16-lead Ceramic SOIC

Key Specifications

■Conversion Rate 50 kSPS to 1 MSPS

■DNL (VA = VD = 5.0 V) +1.5 / −0.9 LSB (max)

■INL (VA = VD = 5.0 V) +1.4 / −1.25 LSB (max)

■Power Consumption

—3V Supply 2.3 mW (typ)

—5V Supply 10.7 mW (typ)

Applications

■Automotive Navigation

■Portable Systems

■Medical Instruments

■Mobile Communications

■Instrumentation and Control Systems

Ordering Information

NS Part Number SMD Part Number NS Package Number Package Description

ADC128S102WGRQV

Flight Part

5962R0722701VZA

100 krad(Si) WG16A 16LD Ceramic SOIC

ADC128S102WGMPR

Pre-Flight Prototype

WG16A 16LD Ceramic SOIC

ADC128S102CVAL

Ceramic Evaluation Board

16LD Ceramic SOIC

on Evaluation Board

Connection Diagram

30018105

SPI™ is a trademark of Motorola, Inc.

ADC128S102QML 8-Channel, 50 kSPS to 1 MSPS, 12-Bit A/D Converter

Block Diagram

30018107

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to VREF.

DIGITAL I/O

16 SCLK

Digital clock input. The guaranteed performance range of

frequencies for this input is 0.8 MHz to 16 MHz. This clock directly

controls the conversion and readout processes.

15 DOUT Digital data output. The output samples are clocked out of this pin

on the falling edges of the SCLK pin.

14 DIN Digital data input. The ADC128S102QML's Control Register is

loaded through this pin on rising edges of the SCLK pin.

1 CS Chip select. On the falling edge of CS, a conversion process

begins. Conversions continue as long as CS is held low.

POWER SUPPLY

2VA

Positive analog supply pin. This voltage is also used as the

reference voltage. This pin should be connected to a quiet +2.7V

to +5.25V source and bypassed to GND with 1 µF and 0.1 µF

monolithic ceramic capacitors located within 1 cm of the power pin.

13 VD

Positive digital supply pin. This pin should be connected to a +2.7V

to VA supply, and bypassed to GND with a 0.1 µF monolithic

ceramic capacitor located within 1 cm of the power pin.

3 AGND The ground return for the analog supply and signals.

12 DGND The ground return for the digital supply and signals.

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ADC128S102QML

Absolute Maximum Ratings (Note 1)

Analog Supply Voltage VA−0.3V to 6.5V

Digital Supply Voltage VD−0.3V to VA + 0.3V,

max 6.5V

Voltage on Any Pin to GND −0.3V to VA +0.3V

Input Current at Any Pin (Note 3) ±10 mA

Power Dissipation (Note 4) TA = 25°C

Package Input Current (Note 3) ±20 mA

ESD Susceptibility (Note 5)

Human Body Model

(Class 3A) 8000V

Soldering Temperature

10 seconds 260°C

Junction Temperature +175°C

Storage Temperature −65°C to +150°C

Operating Ratings (Note 1, Note 2)

Operating Temperature

TMIN −55°C

TMAX +125°C

VA Supply Voltage +2.7V to +5.25V

VD Supply Voltage +2.7V to VA

Digital Input Voltage 0V to VA

Analog Input Voltage 0V to VA

Clock Frequency 0.8 MHz to 16 MHz

Package Thermal Resistance

Package θJA θJC

16-lead Cerpack

Gullwing 127°C/W 11.2°C/ W

Quality Conformance Inspection

MIL-STD-883, Method 5005 - Group A

Subgroup Description Temp (°C)

1 Static tests at +25

2 Static tests at +125

3 Static tests at -55

4 Dynamic tests at +25

5 Dynamic tests at +125

6 Dynamic tests at -55

7 Functional tests at +25

8A Functional tests at +125

8B Functional tests at -55

9 Switching tests at +25

10 Switching tests at +125

11 Switching tests at -55

12 Setting time at +25

13 Setting time at +125

14 Setting time at -55

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ADC128S102QML

ADC128S102QML Converter Electrical Characteristics

The following specifications apply for AGND = DGND = 0V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, CL = 50pF,

unless otherwise noted.

Symbol Parameter Conditions Notes Typical

(Note 6)Min Max Units Sub-

groups

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing

Codes 12 Bits

INL Integral Non-Linearity (End

Point Method)

VA = VD = +3.0V ±0.6 −1.0 +1.1 LSB 1, 2, 3

VA = VD = +5.0V ±0.9 −1.25 +1.4 LSB 1, 2, 3

DNL Differential Non-Linearity

VA = VD = +3.0V +0.5 +0.9 LSB 1, 2, 3

−0.3 −0.7 LSB 1, 2, 3

VA = VD = +5.0V +0.9 +1.5 LSB 1, 2, 3

−0.5 −0.9 LSB 1, 2, 3

VOFF Offset Error VA = VD = +3.0V +0.8 −2.3 +2.3 LSB 1, 2, 3

VA = VD = +5.0V +1.1 −2.3 +2.3 LSB 1, 2, 3

OEM Offset Error Match VA = VD = +3.0V ±0.1 −1.5 +1.5 LSB 1, 2, 3

VA = VD = +5.0V ±0.3 −1.5 +1.5 LSB 1, 2, 3

FSE Full Scale Error VA = VD = +3.0V +0.8 −2.0 +2.0 LSB 1, 2, 3

VA = VD = +5.0V +0.3 −2.0 +2.0 LSB 1, 2, 3

FSEM Full Scale Error Match VA = VD = +3.0V ±0.1 −1.5 +1.5 LSB 1, 2, 3

VA = VD = +5.0V ±0.3 −1.5 +1.5 LSB 1, 2, 3

DYNAMIC CONVERTER CHARACTERISTICS

FPBW Full Power Bandwidth

(−3dB)

VA = VD = +3.0V 6.8 MHz

VA = VD = +5.0V 10 MHz

SINAD Signal-to-Noise Plus

Distortion Ratio

VA = VD = +3.0V,

fIN = 40.2 kHz, −0.02 dBFS 72 68 dB 4, 5, 6

VA = VD = +5.0V,

fIN = 40.2 kHz, −0.02 dBFS 72 68 dB 4, 5, 6

SNR Signal-to-Noise Ratio

VA = VD = +3.0V,

fIN = 40.2 kHz, −0.02 dBFS 72 69 dB 4, 5, 6

VA = VD = +5.0V,

fIN = 40.2 kHz, −0.02 dBFS 72 68.5 dB 4, 5, 6

THD Total Harmonic Distortion

VA = VD = +3.0V,

fIN = 40.2 kHz, −0.02 dBFS −86 −74 dB 4, 5, 6

VA = VD = +5.0V,

fIN = 40.2 kHz, −0.02 dBFS −87 −74 dB 4, 5, 6

SFDR Spurious-Free Dynamic

Range

VA = VD = +3.0V,

fIN = 40.2 kHz, −0.02 dBFS 91 75 dB 4, 5, 6

VA = VD = +5.0V,

fIN = 40.2 kHz, −0.02 dBFS 90 75 dB 4, 5, 6

ENOB Effective Number of Bits

VA = VD = +3.0V,

fIN = 40.2 kHz 11.6 11.1 Bits 4, 5, 6

VA = VD = +5.0V,

fIN = 40.2 kHz, −0.02 dBFS 11.6 11.1 Bits 4, 5, 6

ISO Channel-to-Channel

Isolation

VA = VD = +3.0V,

fIN = 20 kHz 84 dB

VA = VD = +5.0V,

fIN = 20 kHz, −0.02 dBFS 85 dB

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ADC128S102QML

Symbol Parameter Conditions Notes Typical

(Note 6)Min Max Units Sub-

groups

IMD

Intermodulation Distortion,

Second Order Terms

VA = VD = +3.0V,

fa = 19.5 kHz, fb = 20.5 kHz −93 −78 dB 4, 5, 6

VA = VD = +5.0V,

fa = 19.5 kHz, fb = 20.5 kHz −93 −78 dB 4, 5, 6

Intermodulation Distortion,

Third Order Terms

VA = VD = +3.0V,

fa = 19.5 kHz, fb = 20.5 kHz −91 −70 dB 4, 5, 6

VA = VD = +5.0V,

fa = 19.5 kHz, fb = 20.5 kHz −91 −70 dB 4, 5, 6

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VA V

IDCL DC Leakage Current ±0.01 ±1.0 µA 1, 2, 3

CINA Input Capacitance

Track Mode (Note

7)38 pF

Hold Mode (Note

7)4.5 pF

DIGITAL INPUT CHARACTERISTICS

VIH Input High Voltage VA = VD = +2.7V to +3.6V 2.1 V 1, 2, 3

VA = VD = +4.75V to +5.25V 2.4 V 1, 2, 3

VIL Input Low Voltage VA = VD = +2.7V to +5.25V 0.8 V 1, 2, 3

IIN Input Current VIN = 0V or VD ±1.0 ±1.0 µA 1, 2, 3

CIND Digital Input Capacitance (Note

7)3.5 pF

(max)

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA,

VA = VD = +2.7V to +5.25V VD −0.5 V 1, 2, 3

VOL Output Low Voltage ISINK = 200 µA to 1.0 mA,

VA = VD = +2.7V to +5.25V 0.4 V 1, 2, 3

IOZH, IOZL

Hi-Impedance Output

Leakage Current VA = VD = +2.7V to +5.25V ±0.01 ±1.0 µA 1, 2, 3

COUT

Hi-Impedance Output

Capacitance (Note

7)3.5 pF

(max)

Output Coding Straight (Natural) Binary

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ADC128S102QML

Symbol Parameter Conditions Notes Typical

(Note 6)Min Max Units Sub-

groups

POWER SUPPLY CHARACTERISTICS (CL = 10 pF)

VA, VD

Analog and Digital Supply

Voltages VA ≥ VD

2.7 V 1, 2, 3

5.25 V 1, 2, 3

IA + ID

Total Supply Current

Normal Mode ( CS low)

VA = VD = +2.7V to +3.6V,

fSAMPLE = 1 MSPS, fIN = 40 kHz 0.9 1.5 mA 1, 2, 3

VA = VD = +4.75V to +5.25V,

fSAMPLE = 1 MSPS, fIN = 40 kHz 2.2 3.1 mA 1, 2, 3

Total Supply Current

Shutdown Mode (CS high)

VA = VD = +2.7V to +3.6V,

fSCLK = 0 kSPS 0.11 1.0 μA1, 2, 3

VA = VD = +4.75V to +5.25V,

fSCLK = 0 kSPS 0.12 1.4 μA1, 2, 3

Power Consumption

Normal Mode ( CS low)

VA = VD = +3.0V

fSAMPLE = 1 MSPS, fIN = 40 kHz 2.7 4.5 mW 1, 2, 3

VA = VD = +5.0V

fSAMPLE = 1 MSPS, fIN = 40 kHz 11.0 15.5 mW 1, 2, 3

Power Consumption

Shutdown Mode (CS high)

VA = VD = +3.0V

fSCLK = 0 kSPS 0.33 3.0 µW 1, 2, 3

VA = VD = +5.0V

fSCLK = 0 kSPS 0.6 7.0 µW 1, 2, 3

AC ELECTRICAL CHARACTERISTICS

fSCLKMIN Minimum Clock Frequency VA = VD = +2.7V to +5.25V 0.8 MHz 9, 10, 11

fSCLK Maximum Clock Frequency VA = VD = +2.7V to +5.25V 16 MHz 9, 10, 11

Sample Rate

Continuous Mode VA = VD = +2.7V to +5.25V 50 kSPS 9, 10, 11

1MSPS 9, 10, 11

tCONVERT Conversion (Hold) Time VA = VD = +2.7V to +5.25V 13 SCLK

cycles 9, 10, 11

DC SCLK Duty Cycle VA = VD = +2.7V to +5.25V 40 %

60 %

tACQ Acquisition (Track) Time VA = VD = +2.7V to +5.25V 3 SCLK

cycles 9, 10, 11

Throughput Time

Acquisition Time + Conversion

Time

VA = VD = +2.7V to +5.25V

16 SCLK

cycles 9, 10, 11

tAD Aperture Delay VA = VD = +2.7V to +5.25V 4 ns

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ADC128S102QML

Timing Specifications

The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50

kSPS to 1 MSPS, and CL = 50pF.

Symbol Parameter Conditions Notes Typical

(Note 6)Min Max Units Sub-

groups

tCSH

CS Hold Time after SCLK

Rising Edge (Note

8)010 ns 9, 10, 11

tCSS

CS Setup Time prior to SCLK

Rising Edge (Note

8)4.5 10 ns 9, 10, 11

tEN

CS Falling Edge to DOUT

enabled 5 30 ns 9, 10, 11

tDACC

DOUT Access Time after

SCLK Falling Edge 17 27 ns 9, 10, 11

tDHLD

DOUT Hold Time after SCLK

Falling Edge 4 11 ns 9, 10, 11

tDS

DIN Setup Time prior to

SCLK Rising Edge 3 10 ns 9, 10, 11

tDH

DIN Hold Time after SCLK

Rising Edge 3 10 ns 9, 10, 11

tCH SCLK High Time 0.4 X

tSCLK

ns (min)

tCL SCLK Low Time 0.4 X

tSCLK

ns (min)

tDIS

CS Rising Edge to DOUT

High-Impedance

DOUT falling 2.4 20 ns 9, 10, 11

DOUT rising 0.9 20 ns 9, 10, 11

Radiation Electrical Characteristics (Note 9)

The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50

kSPS to 1 MSPS, and CL = 50pF.

Symbol Parameter Conditions Notes Typical Min Max Units Sub-

groups

IA + ID

Total Supply Current

Shutdown Mode (CS high)

VA = VD = +2.7V to +3.6V,

fSCLK = 0 kSPS 30 µA 1

VA = VD = +4.75V to +5.25V,

fSCLK = 0 kSPS 100 µA 1

IOZH, IOZL

Hi-Impedance Output

Leakage Current VA = VD = +2.7V to +5.25V ±10 µA 1

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ADC128S102QML

Burn In Delta Parameters TA @ 25°C (Note 10)

The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50

kSPS to 1 MSPS, and CL = 50pF.

Symbol Parameter Conditions Notes Typical Mim Max Units Sub-

groups

INL Integral Non-LInearity VA = VD = 3.0V .106 −0.5 +0.5 LSB

VA = VD = +5.0V .016 −0.35 +0.35 LSB

IMD Intermodulation Distortion,

Second Order Terms

VA = VD = 3.0V 1.35 −14 +14 dB

VA = VD = 5.0V 1.67 −17 +17 dB

IMD Intermodulation Distortion,

Third Order Terms

VA = VD = 3.0V .47 −10 +10 dB

VA = VD = 5.0V .90 −10 +10 dB

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be limited to 10 mA.

The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 175°C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values

for maximum power dissipation listed above will be reached only when the ADC128S102QML is operated in a severe fault condition (e.g. when input or output

pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms

Note 6: Typical figures are at TJ = 25°C, and represent most likely parametric norms.

Note 7: This parameter is guaranteed by design and/or characterization and is not tested in production.

Note 8: Clock may be in any state (high or low) when CS goes high. Setup and hold time restrictions apply only to CS going low.

Note 9: Pre and post irradiation limits are identical to those listed in the “DC Parameters” and “AC and Timing Characteristics” tables, except as listed in the

“Radiation Electrical Characteristics” table. When performing post irradiation electrical measurements for any RHA level, TA = +25°C.

Note 10: This is worse case drift, Deltas are performed at room temperature post operational life. All other parameters, no deltas are required.

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ADC128S102QML

Timing Diagrams

30018151

FIGURE 1. ADC128S102 Operational Timing Diagram

30018106

FIGURE 2. ADC128S102 Serial Timing Diagram

30018150

FIGURE 3. SCLK and CS Timing Parameters

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ADC128S102QML

Specification Definitions

ACQUISITION TIME is the time required for the ADC to ac-

quire the input voltage. During this time, the hold capacitor is

charged by the input voltage.

APERTURE DELAY is the time between the fourth falling

edge of SCLK and the time when the input signal is internally

acquired or held for conversion.

CONVERSION TIME is the time required, after the input volt-

age is acquired, for the ADC to convert the input voltage to a

digital word.

CHANNEL-TO-CHANNEL ISOLATION is resistance to cou-

pling of energy from one channel into another channel.

CROSSTALK is the coupling of energy from one channel into

another channel. This is similar to Channel-to-Channel Isola-

tion, except for the sign of the data.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital

waveform is high to the total time of one period. The specifi-

cation here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02

and says that the converter is equivalent to a perfect ADC of

this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

GAIN ERROR is the deviation of the last code transition

(111...110) to (111...111) from the ideal (VREF - 1.5 LSB), after

adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from negative

full scale (½ LSB below the first code transition) through pos-

itive full scale (½ LSB above the last code transition). The

deviation of any given code from this straight line is measured

from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to an individual ADC input at the

same time. It is defined as the ratio of the power in either the

second or the third order intermodulation products to the sum

of the power in both of the original frequencies. Second order

products are fa ± fb, where fa and fb are the two sine wave

input frequencies. Third order products are (2fa ± fb ) and

(fa ± 2fb). IMD is usually expressed in dB.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADC128S102 is guaranteed not

to have any missing codes.

OFFSET ERROR is the deviation of the first code transition

(000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the desired signal amplitude

to the amplitude of the peak spurious spectral component,

where a spurious spectral component is any signal present in

the output spectrum that is not present at the input and may

or may not be a harmonic.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dBc, of the rms total of the first five harmonic

components at the output to the rms level of the input signal

frequency as seen at the output. THD is calculated as

where Af1 is the RMS power of the input frequency at the out-

put and Af2 through Af10 are the RMS power in the first 9

harmonic frequencies.

THROUGHPUT TIME is the minimum time required between

the start of two successive conversions. It is the acquisition

time plus the conversion time.

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ADC128S102QML

Typical Performance Characteristics TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz

unless otherwise stated.

DNL

30018140

DNL

30018141

INL

30018142

INL

30018143

DNL vs. Supply

30018121

INL vs. Supply

30018120

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ADC128S102QML

SNR vs. Supply

30018122

THD vs. Supply

30018132

ENOB vs. Supply

30018133

DNL vs. SCLK Duty Cycle

30018155

INL vs. SCLK Duty Cycle

30018158

SNR vs. SCLK Duty Cycle

30018161

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ADC128S102QML

THD vs. SCLK Duty Cycle

30018164

ENOB vs. SCLK Duty Cycle

30018152

DNL vs. SCLK

30018156

INL vs. SCLK

30018159

DNL vs. SCLK

30018130

INL vs. SCLK

30018131

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ADC128S102QML

SNR vs. SCLK

30018162

SNR vs. SCLK

30018123

THD vs. SCLK

30018165

THD vs SCLK

30018124

ENOB vs. SCLK

30018153

ENOB vs. SCLK

30018145

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ADC128S102QML

ENOB vs. Temperature

30018154

DNL vs. Temperature

30018157

INL vs. Temperature

30018160

SNR vs. Temperature

30018163

THD vs. Temperature

30018166

Power Consumption vs. SCLK

30018144

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ADC128S102QML

1.0 Functional Description

The ADC128S102 is a successive-approximation analog-to-

digital converter designed around a charge-redistribution dig-

ital-to-analog converter.

1.1 ADC128S102 OPERATION

Simplified schematics of the ADC128S102 in both track and

hold operation are shown in Figure 4 and Figure 5 respec-

tively. In Figure 4, the ADC128S102 is in track mode: switch

SW1 connects the sampling capacitor to one of eight analog

input channels through the multiplexer, and SW2 balances

the comparator inputs. The ADC128S102 is in this state for

the first three SCLK cycles after CS is brought low.

Figure 5 shows the ADC128S102 in hold mode: switch SW1

connects the sampling capacitor to ground, maintaining the

sampled voltage, and switch SW2 unbalances the compara-

tor. The control logic then instructs the charge-redistribution

DAC to add or subtract fixed amounts of charge to or from the

sampling capacitor until the comparator is balanced. When

the comparator is balanced, the digital word supplied to the

DAC is the digital representation of the analog input voltage.

The ADC128S102 is in this state for the last thirteen SCLK

cycles after CS is brought low.

30018109

FIGURE 4. ADC128S102 in Track Mode

30018110

FIGURE 5. ADC128S102 in Hold Mode

1.2 SERIAL INTERFACE

An operational timing diagram and a serial interface timing

diagram for the ADC128S102 are shown in The Timing Dia-

grams section. CS, chip select, initiates conversions and

frames the serial data transfers. SCLK (serial clock) controls

both the conversion process and the timing of serial data.

DOUT is the serial data output pin, where a conversion result

is sent as a serial data stream, MSB first. Data to be written

to the ADC128S102's Control Register is placed on DIN, the

serial data input pin. New data is written to DIN with each

conversion.

A serial frame is initiated on the falling edge of CS and ends

on the rising edge of CS. Each frame must contain an integer

multiple of 16 rising SCLK edges. The ADC's DOUT pin is in

a high impedance state when CS is high and is active when

CS is low. Thus, CS acts as an output enable. Similarly, SCLK

is internally gated off when CS is brought high.

During the first 3 cycles of SCLK, the ADC is in the track

mode, acquiring the input voltage. For the next 13 SCLK cy-

cles the conversion is accomplished and the data is clocked

out. SCLK falling edges 1 through 4 clock out leading zeros

while falling edges 5 through 16 clock out the conversion re-

sult, MSB first. If there is more than one conversion in a frame

(continuous conversion mode), the ADC will re-enter the track

mode on the falling edge of SCLK after the N*16th rising edge

of SCLK and re-enter the hold/convert mode on the N*16+4th

falling edge of SCLK. "N" is an integer value.

The ADC128S102 enters track mode under three different

conditions. In Figure 1, CS goes low with SCLK high and the

ADC enters track mode on the first falling edge of SCLK. In

the second condition, CS goes low with SCLK low. Under this

www.national.com 16

ADC128S102QML

condition, the ADC automatically enters track mode and the

falling edge of CS is seen as the first falling edge of SCLK. In

the third condition, CS and SCLK go low simultaneously and

the ADC enters track mode. While there is no timing restriction

with respect to the falling edges of CS and SCLK, see Figure

3 for setup and hold time requirements for the falling edge of

CS with respect to the rising edge of SCLK.

During each conversion, data is clocked into a control register

through the DIN pin on the first 8 rising edges of SCLK after

the fall of CS. The control register is loaded with data indicat-

ing the input channel to be converted on the subsequent

conversion (see Tables 1, 2, 3).

Although the ADC128S102 is able to acquire the input signal

to full resolution in the first conversion immediately following

power-up, the first conversion result after power-up will be

that of a randomly selected channel. Therefore, the user

needs to incorporate a dummy conversion to set the required

channel that will be used on the subsequent conversion.

TABLE 1. Control Register Bits

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

TABLE 2. Control Register Bit Descriptions

Bit #: Symbol: Description

7, 6, 2, 1, 0 DONTC Don't care. The values of these bits do not affect the device.

5 ADD2 These three bits determine which input channel will be sampled and converted

at the next conversion cycle. The mapping between codes and channels is

shown in Table 3.

4 ADD1

3 ADD0

TABLE 3. Input Channel Selection

ADD2 ADD1 ADD0 Input Channel

0 0 0 IN0

0 0 1 IN1

0 1 0 IN2

0 1 1 IN3

1 0 0 IN4

1 0 1 IN5

1 1 0 IN6

1 1 1 IN7

1.3 ADC128S102 TRANSFER FUNCTION

The output format of the ADC128S102 is straight binary.

Code transitions occur midway between successive integer

LSB values. The LSB width for the ADC128S102 is VA / 4096.

The ideal transfer characteristic is shown in Figure 6. The

transition from an output code of 0000 0000 0000 to a code

of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA / 8192.

Other code transitions occur at steps of one LSB.

30018111

FIGURE 6. Ideal Transfer Characteristic

1.4 ANALOG INPUTS

An equivalent circuit for one of the ADC128S102's input chan-

nels is shown in Figure 7. Diodes D1 and D2 provide ESD

protection for the analog inputs. The operating range for the

analog inputs is 0 V to VA. Going beyond this range will cause

the ESD diodes to conduct and result in erratic operation.

The capacitor C1 in Figure 7 has a typical value of 3 pF and

is mainly the package pin capacitance. Resistor R1 is the on

resistance of the multiplexer and track / hold switch and is

typically 500 ohms. Capacitor C2 is the ADC128S102 sam-

pling capacitor, and is typically 30 pF. The ADC128S102 will

deliver best performance when driven by a low-impedance

source (less than 100 ohms). This is especially important

when using the ADC128S102 to sample dynamic signals. Al-

so important when sampling dynamic signals is a band-pass

or low-pass filter which reduces harmonics and noise in the

input. These filters are often referred to as anti-aliasing filters.

30018114

FIGURE 7. Equivalent Input Circuit

1.5 DIGITAL INPUTS AND OUTPUTS

The ADC128S102's digital inputs (SCLK, CS, and DIN) have

an operating range of 0 V to VA. They are not prone to latch-

up and may be asserted before the digital supply (VD) without

any risk. The digital output (DOUT) operating range is con-

trolled by VD. The output high voltage is VD - 0.5V (min) while

the output low voltage is 0.4V (max).

17 www.national.com

ADC128S102QML

2.0 Applications Information

2.1 TYPICAL APPLICATION CIRCUIT

A typical application is shown in Figure 8. The split analog and

digital supply pins are both powered in this example by the

National LP2950 low-dropout voltage regulator. The analog

supply is bypassed with a capacitor network located close to

the ADC128S102. The digital supply is separated from the

analog supply by an isolation resistor and bypassed with ad-

ditional capacitors. The ADC128S102 uses the analog supply

(VA) as its reference voltage, so it is very important that VA be

kept as clean as possible. Due to the low power requirements

of the ADC128S102, it is also possible to use a precision ref-

erence as a power supply.

30018113

FIGURE 8. Typical Application Circuit

2.2 POWER SUPPLY CONSIDERATIONS

There are three major power supply concerns with this prod-

uct: power supply sequencing, power management, and the

effect of digital supply noise on the analog supply.

2.2.1 Power Supply Sequence

The ADC128S102 is a dual-supply device. The two supply

pins share ESD resources, so care must be exercised to en-

sure that the power is applied in the correct sequence. To

avoid turning on the ESD diodes, the digital supply (VD) can-

not exceed the analog supply (VA) by more than 300 mV,

during a conversion cycle. Therefore, VA must ramp up before

or concurrently with VD.

2.2.2 Power Management

The ADC128S102 is fully powered-up whenever CS is low

and fully powered-down whenever CS is high, with one ex-

ception. If operating in continuous conversion mode, the AD-

C128S102 automatically enters power-down mode between

SCLK's 16th falling edge of a conversion and SCLK's 1st

falling edge of the subsequent conversion (see Figure 1).

In continuous conversion mode, the ADC128S102 can per-

form multiple conversions back to back. Each conversion

requires 16 SCLK cycles and the ADC128S102 will perform

conversions continuously as long as CS is held low. Contin-

uous mode offers maximum throughput.

In burst mode, the user may trade off throughput for power

consumption by performing fewer conversions per unit time.

This means spending more time in power-down mode and

less time in normal mode. By utilizing this technique, the user

can achieve very low sample rates while still utilizing an SCLK

frequency within the electrical specifications. The Power Con-

sumption vs. SCLK curve in the Typical Performance Curves

section shows the typical power consumption of the AD-

C128S102. To calculate the power consumption (PC), simply

multiply the fraction of time spent in the normal mode (tN) by

the normal mode power consumption (PN), and add the frac-

tion of time spent in shutdown mode (tS) multiplied by the

shutdown mode power consumption (PS) as shown in Figure

30018115

FIGURE 9. Power Consumption Equation

2.2.3 Power Supply Noise Considerations

The charging of any output load capacitance requires current

from the digital supply, VD. The current pulses required from

the supply to charge the output capacitance will cause voltage

variations on the digital supply. If these variations are large

enough, they could degrade SNR and SINAD performance of

the ADC. Furthermore, if the analog and digital supplies are

tied directly together, the noise on the digital supply will be

coupled directly into the analog supply, causing greater per-

formance degradation than would noise on the digital supply

alone. Similarly, discharging the output capacitance when the

digital output goes from a logic high to a logic low will dump

current into the die substrate, which is resistive. Load dis-

charge currents will cause "ground bounce" noise in the sub-

strate that will degrade noise performance if that current is

large enough. The larger the output capacitance, the more

current flows through the die substrate and the greater the

noise coupled into the analog channel.

The first solution to keeping digital noise out of the analog

supply is to decouple the analog and digital supplies from

each other or use separate supplies for them. To keep noise

out of the digital supply, keep the output load capacitance as

small as practical. If the load capacitance is greater than 50

pF, use a 100 Ω series resistor at the ADC output, located as

close to the ADC output pin as practical. This will limit the

charge and discharge current of the output capacitance and

improve noise performance. Since the series resistor and the

www.national.com 18

ADC128S102QML

load capacitance form a low frequency pole, verify signal in-

tegrity once the series resistor has been added.

2.3 LAYOUT AND GROUNDING

Capacitive coupling between the noisy digital circuitry and the

sensitive analog circuitry can lead to poor performance. The

solution is to keep the analog circuitry separated from the

digital circuitry and the clock line as short as possible.

Digital circuits create substantial supply and ground current

transients. The logic noise generated could have significant

impact upon system noise performance. To avoid perfor-

mance degradation of the ADC128S102 due to supply noise,

do not use the same supply for the ADC128S102 that is used

for digital logic.

Generally, analog and digital lines should cross each other at

90° to avoid crosstalk. However, to maximize accuracy in high

resolution systems, avoid crossing analog and digital lines al-

together. It is important to keep clock lines as short as possi-

ble and isolated from ALL other lines, including other digital

lines. In addition, the clock line should also be treated as a

transmission line and be properly terminated.

The analog input should be isolated from noisy signal traces

to avoid coupling of spurious signals into the input. Any ex-

ternal component (e.g., a filter capacitor) connected between

the converter's input pins and ground or to the reference input

pin and ground should be connected to a very clean point in

the ground plane.

We recommend the use of a single, uniform ground plane and

the use of split power planes. The power planes should be

located within the same board layer. All analog circuitry (input

amplifiers, filters, reference components, etc.) should be

placed over the analog power plane. All digital circuitry and I/

O lines should be placed over the digital power plane. Fur-

thermore, all components in the reference circuitry and the

input signal chain that are connected to ground should be

connected together with short traces and enter the analog

ground plane at a single, quiet point.

3.0 Radiation Environments

Careful consideration should be given to environmental con-

ditions when using a product in a radiation environment.

3.1 TOTAL IONIZING DOSE

Radiation hardness assured (RHA) products are those part

numbers with a total ionizing dose (TID) level specified in the

Ordering Information table on the front page. Testing and

qualification of these products is done on a wafer level ac-

cording to MIL-STD-883G, Test Method 1019.7. Testing is

done according to Condition A and the “Extended room tem-

perature anneal test” described in section 3.11 for application

environment dose rates less than 0.16 rad(Si)/s. Wafer level

TID data is available with lot shipments.

3.2 SINGLE EVENT LATCH-UP

One time single event latchup testing (SEL) was performed

according to EIA/JEDEC Standard, EIA/JEDEC57. Testing

was done at maximum operating temperature and supply

voltage. The linear energy transfer threshold (LETth) shown

in the Key Specifications table on the front page is the maxi-

mum LET tested. A test report is available upon request.

3.3 SINGLE EVENT UPSET

A report on single event upset (SEU) is available upon re-

quest.

19 www.national.com

ADC128S102QML

Revision History

Date Released Revision Section Changes

08/21/08 A New Data Sheet, Initial Release New product data sheet, Initial Release

11/03/08 B Timing Diagrams Typo, Changed Figure 2, tDIS lower left hand side

changed to tDS and tDIH lower left hand side

change to tDH. Revision A will be Archived.

01/09/09 C Features, Ordering Information Corrected package reference from 16-lead

TSSOP to 16-lead Ceramic SOIC, Removed QV

NSID reference and Added SMD Number to RQV

NSID. Revision B will be Archived.

06/02/09 D Features, Ordering Information, Electrical

Section

Moved Rad information from Key Specifications to

Features. Deleted ADC128S102WGMLS

reference. Added Burn In Delta Table. Revision C

will be Archived.

10/27/09 E Operating Ratings, Electricals, Note and

Typical Performance Characteristics

Spec Typo for Clock Frequency range, Electrical

headings, currently shows 8 Mhz to 16 Mhz,

Should be 0.8 Mhz and 16 Mhz. Reword Note 10.

Reformatted Burn In Delta table. Added new

ENOB vs SCLK Plot. Revision D will be Archived.

03/11/2010 F AC Electrical Characteristics - SCLK Duty

Cycle

AC Electrical Characteristics - SCLK Duty Cycle,

typ limits. Revision E will be Archived.

01/13/2011 G Electrical Characteristics Removed reference to Ta Min & Ta Max under

titled sections.

www.national.com 20

ADC128S102QML

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Ceramic SOIC

NS Package Number WG16A

21 www.national.com

ADC128S102QML

Notes

ADC128S102QML 8-Channel, 50 kSPS to 1 MSPS, 12-Bit A/D Converter

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