DG2517E
www.vishay.com Vishay Siliconix
S17-0460-Rev. A, 03-Apr-17 1Document Number: 74518
For technical questions, contact: analogswitchtechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
2.5 , High Bandwidth, Dual SPDT Analog Switch
DESCRIPTION
The DG2517E is low-voltage dual single-pole /
double-throw monolithic CMOS analog switches. Designed
to operate from 1.8 V to 5.5 V power supply, the DG2517E
achieves a bandwidth of 221 MHz while providing low
on-resistance (2.5 ), excellent on-resistance matching
(0.3 ) and flatness (1 ) over the entire signal range.
The DG2517E offers the advantage of high linearity that
reduces signal distortion, making ideal for audio, video, and
USB signal routing applications.
Built on Vishay Siliconix’s proprietary sub-micron
high-density process, the DG2517E brings low power
consumption at the same time as reduces PCB spacing with
the MSOP10 and DFN10 packages.
As a committed partner to the community and the
environment, Vishay Siliconix manufactures this product
with the lead (Pb)-free device terminations. The DFN
package has a nickel-palladium-gold device termination
and is represented by the lead (Pb)-free “-GE4” suffix. The
MSOP package uses 100 % matte Tin device termination
and is represented by the lead (Pb)- free “-GE3” suffix. Both
the matte Tin and nickel-palladium-gold device terminations
meet all JEDEC® standards for reflow and MSL ratings.
FEATURES
• 1.8 V to 5.5 V single supply operation
•Low R
ON: 2.5 at 4.5 V
• 221 MHz, -3 dB bandwidth
• Low off-isolation, -58 dB at 1 MHz
• +1.6 V logic compatible
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
BENEFITS
• High linearity
• Low power consumption
• High bandwidth
• Full rail signal swing range
APPLICATIONS
• USB / UART signal switching
• Audio / video switching
•Cellular phone
• Media players
•Modems
• Hard drives
• PCMCIA
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Notes
a. Signals on NC, NO, or COM or IN exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings
b. All leads welded or soldered to PC board
c. Derate 4 mW/°C above 70 °C
d. Derate 14.9 mW/°C above 70 °C
COM1
NC1
V+
1
2
3
10
9
Top View
IN1
NO1
GND 8
NC2
COM2
4
5
7
NO2
IN2 6
DG2517E
TRUTH TABLE
LOGIC NC1 AND NC2 NO1 AND NO2
0ONOFF
1OFF ON
ORDERING INFORMATION
TEMP. RANGE PACKAGE PART NUMBER
-40 °C to 85 °C MSOP-10 DG2517EDQ-T1-GE3
DFN-10 DG2517EDN-T1-GE4
ABSOLUTE MAXIMUM RATINGS
PARAMETER LIMIT UNIT
Reference to GND
V+ -0.3 to +6 V
IN, COM, NC, NO a-0.3 to (V+ + 0.3)
Continuous current (any terminal) ± 50 mA
Peak current (pulsed at 1 ms, 10 % duty cycle) ± 200
Storage temperature (D suffix) -65 to +150 °C
Power dissipation (packages) bMSOP-10 c320 mW
DFN-10 d1191
ESD / HBM EIA / JESD22-A114-A 7.5k V
ESD / CDM EIA / JESD22-C101-A 1.5k
Latch up JESD78 300 mA