1. General description
The 74LVC1T45; 74LVCH1T45 are single bit, dual supply transceivers with 3-state
outputs that enable bidirectional level translation. They feature two 1-bit input-output port s
(A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both
VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the
device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V,
2.5 V, 3.3 V and 5.0 V). Pins A and DIR are referenc ed to VCC(A) and pin B is referenced
to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows
transmission from B to A.
The devices are fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH1T45 holds unused or floating data input s at a valid
logic level.
2. Features and benefits
Wide supply voltage range:
VCC(A): 1.2 V to 5.5 V
VCC(B): 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4000 V
CDM JESD22-C101E exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
Suspend mode
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Rev. 6 — 6 August 2012 Product data sheet
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 2 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Latch-up pe rform a nc e exceeds 100 mA per JESD 78 Class II
24 mA output drive (VCC =3.0V)
Inputs accept voltages up to 5.5 V
Low power consum ption: 16 A maximum ICC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 Cto+85C and 40 Cto+125C
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Tabl e 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC1T45GW 40 Cto+125C SC-88 plastic surface-mounted package; 6 leads SOT363
74LVCH1T45GW
74LVC1T45GM 40 Cto+125C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm SOT886
74LVCH1T45GM
74LVC1T45GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 10.5 mm SOT891
74LVCH1T45GF
74LVC1T45GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm SOT1115
74LVCH1T45GN
74LVC1T45GS 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm SOT1202
74LVCH1T45GS
Table 2. Marking
Type number Marking code[1]
74LVC1T45GW V5
74LVCH1T45GW X5
74LVC1T45GM V5
74LVCH1T45GM X5
74LVC1T45GF V5
74LVCH1T45GF X5
74LVC1T45GN V5
74LVCH1T45GN X5
74LVC1T45GS V5
74LVCH1T45GS X5
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 3 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
5. Functional diagram
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 1. Logic symbol Fig 2. Logic diagra m
001aag885
VCC(B)
VCC(A)
5
DIR
3
A
B
4
001aag886
VCC(B)
VCC(A)
DIR
A
B
Fig 3. Pin configuration SOT363
(SC-88) Fig 4. Pin configuratio n SOT 886
(XSON6) Fig 5. Pi n configuration SOT891,
SOT1115 and SOT 1202
74LVC1T45
74LVCH1T45
VCC(A) VCC(B)
GND
AB
001aaj991
1
2
3
6
DIR
5
4
74LVC1T45
74LVCH1T45
GND
001aaj992
V
CC(A)
A
DIR
V
CC(B)
B
Transparent top view
2
3
1
5
4
6
74LVC1T45
74LVCH1T45
GND
001aaj993
VCC(A)
A
DIR
VCC(B)
B
Transparent top view
2
3
1
5
4
6
Table 3. Pin description
Symbol Pin Description
VCC(A) 1 supply voltage port A and DIR
GND 2 ground (0 V)
A 3 data input or output
B 4 data input or output
DIR 5 direction control
VCC(B) 6 supply voltage port B
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 4 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The input circuit of the data I/O is always active.
[3] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
8. Limiting values
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 6.5 V.
[4] For SC-88 package: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 4. Function table[1]
Supply voltage Input Input/output[2]
VCC(A), VCC(B) DIR A B
1.2 V to 5.5 V L A = B input
1.2 V to 5.5 V H input B = A
GND[3] XZZ
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC(A) supply voltage A 0.5 +6.5 V
VCC(B) supply voltage B 0.5 +6.5 V
IIK input clamping current VI<0V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO<0V 50 - mA
VOoutput voltage Active mode [1][2][3] 0.5 VCCO +0.5 V
Suspend or 3-state mode [1] 0.5 +6.5 V
IOoutput current VO=0VtoV
CCO [2] -50 mA
ICC supply current ICC(A) or ICC(B) -100mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[4] -250mW
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VCC(A) supply voltage A 1.2 5.5 V
VCC(B) supply voltage B 1.2 5.5 V
VIinput voltage 0 5.5 V
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 5 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
10. Static characteristics
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH.
VOoutput voltage Active mode [1] 0V
CCO V
Suspend or 3-state mode 0 5.5 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCCI = 1.2 V [2] - 20 ns/V
VCCI = 1.4 V to 1.95 V - 20 ns/V
VCCI = 2.3 V to 2.7 V - 20 ns/V
VCCI = 3 V to 3.6 V - 10 ns/V
VCCI = 4.5 V to 5.5 V - 5 ns/V
Table 6. Recommended operating conditions …continued
Symbol Parameter Conditions Min Max Unit
Table 7. Typical static characteristics at Tamb = 25 C
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level output voltage VI = VIH or VIL
IO=3 mA; VCCO =1.2V [1] -1.09-V
VOL LOW-level output voltage VI = VIH or VIL
IO = 3 mA; VCCO =1.2V [1] -0.07-V
IIinput leakage current DIR input; VI = 0 V to 5.5 V;
VCCI = 1.2 V to 5.5 V [2] -- 1A
IBHL bus hold LOW current A or B port; VI=0.42V;V
CCI =1.2V [2] -19-A
IBHH bus hold HIGH current A or B port; VI=0.78V;V
CCI =1.2V [2] -19 - A
IBHLO bus hold LOW overdrive
current A or B port; VCCI = 1.2 V [2][3] -19-A
IBHHO bus hold HIGH overdrive
current A or B port; VCCI = 1.2 V [2][3] -19 - A
IOZ OFF-state output current A or B port; VO=0 Vor V
CCO;
VCCO = 1.2 V to 5.5 V [1] -- 1A
IOFF power-off leakage current A port; VI or VO = 0 V to 5.5 V;
VCC(A) =0V;V
CC(B) = 1.2 V to 5.5 V -- 1A
B port; VI or VO = 0 V to 5.5 V;
VCC(B) =0V;V
CC(A) = 1.2 V to 5.5 V -- 1A
CIinput capacitance DIR input; VI= 0 V or 3.3 V;
VCC(A) =V
CC(B) =3.3V -2.2-pF
CI/O input/output capacitance A and B port; suspend mode;
VO=3.3Vor0V; V
CC(A) =V
CC(B) =3.3V -6.0-pF
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 6 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Max Min Max
VIH HIGH-level
input voltage data input [1]
VCCI = 1.2 V 0.8VCCI -0.8V
CCI -V
VCCI = 1.4 V to 1.95 V 0.65VCCI -0.65V
CCI -V
VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V
VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V
VCCI = 4.5 V to 5.5 V 0.7VCCI -0.7V
CCI -V
DIR input
VCCI = 1.2 V 0.8VCC(A) -0.8V
CC(A) -V
VCCI = 1.4 V to 1.95 V 0.65VCC(A) -0.65V
CC(A) -V
VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V
VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V
VCCI = 4.5 V to 5.5 V 0.7VCC(A) -0.7V
CC(A) -V
VIL LOW-level
input voltage data input [1]
VCCI = 1.2 V - 0.2VCCI -0.2V
CCI V
VCCI = 1.4 V to 1.95 V - 0.35VCCI -0.35V
CCI V
VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V
VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V
VCCI = 4.5 V to 5.5 V - 0.3VCCI -0.3V
CCI V
DIR input
VCCI = 1.2 V - 0.2VCC(A) -0.2V
CC(A) V
VCCI = 1.4 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V
VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V
VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V
VCCI = 4.5 V to 5.5 V - 0.3VCC(A) -0.3V
CC(A) V
VOH HIGH-level
output voltage VI = VIH
IO=100 A;
VCCO = 1.2 V to 4.5 V [2] VCCO 0.1 - VCCO 0.1 - V
IO = 6mA; V
CCO = 1.4 V 1.0 - 1.0 - V
IO = 8mA; V
CCO = 1.65 V 1.2 - 1.2 - V
IO = 12 mA; VCCO = 2.3 V 1.9 - 1.9 - V
IO = 24 mA; VCCO = 3.0 V 2.4 - 2.4 - V
IO = 32 mA; VCCO = 4.5 V 3.8 - 3.8 - V
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 7 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
VOL LOW-level
output voltage VI = VIL [2]
IO = 100 A;
VCCO = 1.2 V to 4.5 V - 0.1 - 0.1 V
IO = 6 mA; VCCO = 1.4 V - 0.3 - 0.3 V
IO = 8 mA; VCCO = 1.65 V - 0.45 - 0.45 V
IO = 12 mA; VCCO = 2.3 V - 0.3 - 0.3 V
IO = 24 mA; VCCO = 3.0 V - 0.55 - 0.55 V
IO = 32 mA; VCCO = 4.5 V - 0.55 - 0.55 V
IIinput leakage
current DIR input; VI= 0 V to 5.5 V;
VCCI = 1.2 V to 5.5 V -2-10 A
IBHL bus hold LOW
current A or B port [1]
VI = 0.49 V; VCCI =1.4V 15 - 10 - A
VI = 0.58 V; VCCI =1.65V 25 - 20 - A
VI = 0.70 V; VCCI =2.3V 45 - 45 - A
VI = 0.80 V; VCCI =3.0V 100 - 80 - A
VI = 1.35 V; VCCI =4.5V 100 - 100 - A
IBHH bus hold HIGH
current A or B port [1]
VI = 0.91 V; VCCI =1.4V 15 - 10 - A
VI = 1.07 V; VCCI =1.65V 25 - 20 - A
VI = 1.60 V; VCCI =2.3V 45 - 45 - A
VI = 2.00 V; VCCI =3.0V 100 - 80 - A
VI = 3.15 V; VCCI =4.5V 100 - 100 - A
IBHLO bus hold LOW
overdrive
current
A or B port [1][3]
VCCI = 1.6 V 125 - 125 - A
VCCI = 1.95 V 200 - 200 - A
VCCI = 2.7 V 300 - 300 - A
VCCI = 3.6 V 500 - 500 - A
VCCI = 5.5 V 900 - 900 - A
IBHHO bus hold HIGH
overdrive
current
A or B port [1][3]
VCCI = 1.6 V 125 - 125 - A
VCCI = 1.95 V 200 - 200 - A
VCCI = 2.7 V 300 - 300 - A
VCCI = 3.6 V 500 - 500 - A
VCCI = 5.5 V 900 - 900 - A
IOZ OFF-state
output current A or B port ; VO=0VorV
CCO;
VCCO = 1.2 V to 5.5 V [2] -2-10 A
Table 8. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 8 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH.
[4] For non bus hold parts only (74LVC1T45).
IOFF power-off
leakage
current
A port; VIor VO=0Vto5.5V;
VCC(A) =0V;
VCC(B) = 1.2 V to 5.5 V
-2-10 A
B port; VIor VO=0Vto5.5V;
VCC(B) =0V;
VCC(A) = 1.2 V to 5.5 V
-2-10 A
ICC supply current A port; VI = 0 V or VCCI; IO = 0 A [1]
VCC(A), VCC(B) = 1.2 V to 5.5 V - 8 - 8 A
VCC(A), VCC(B) = 1.65 V to 5.5 V - 3 - 3 A
VCC(A) = 5.5 V; VCC(B) = 0 V - 2 - 2 A
VCC(A) = 0 V; VCC(B) = 5.5 V 2-2-A
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A), VCC(B) = 1.2 V to 5.5 V - 8 - 8 A
VCC(A), VCC(B) = 1.65 V to 5.5 V - 3 - 3 A
VCC(B) = 5.5 V; VCC(A) = 0 V - 2 - 2 A
VCC(B) = 0 V; VCC(A) = 5.5 V 2-2-A
A plus B port (ICC(A) ICC(B));
IO=0A; V
I=0 Vor V
CCI
VCC(A), VCC(B) = 1.2 V to 5.5 V - 16 - 16 A
VCC(A), VCC(B) = 1.65 V to 5.5 V - 4 - 4 A
ICC additional
supply current VCC(A), VCC(B) = 3.0 V to 5.5 V
A port; A port at VCC(A) 0.6 V;
DIR at VCC(A); B port = open [4] -50-75A
DIR input; DIR at VCC(A) 0.6 V;
Aportat V
CC(A) or GND;
B port = open
-50-75A
B port; B port at VCC(B) 0.6 V;
DIR at GND; A port = open [4] -50-75A
Table 8. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 9 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
11. Dynamic characteristics
[1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”
[1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”
Table 9. Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for waveforms see Figure 6 and Figure 7
Symbol Parameter Conditions VCC(B) Unit
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
tPLH LOW to HIGH
propagation delay A to B 10.6 8.1 7.0 5.8 5.3 5.1 ns
B to A 10.6 9.5 9.0 8.5 8.3 8.2 ns
tPHL HIGH to LOW
propagation delay A to B 10.1 7.1 6.0 5.3 5.2 5.4 ns
B to A 10.1 8.6 8.1 7.8 7.6 7.6 ns
tPHZ HIGH to OFF-state
propagation delay DIRtoA 9.49.49.49.49.49.4ns
DIR to B 12.0 9.4 9.0 7.8 8.4 7.9 ns
tPLZ LOW to OFF-state
propagation delay DIRtoA 7.17.17.17.17.17.1ns
DIRtoB 9.57.87.76.97.67.0ns
tPZH OFF-state to HIGH
propagation delay DIR to A [1] 20.1 17.3 16.7 15.4 15.9 15.2 ns
DIR to B [1] 17.7 15.2 14.1 12.9 12.4 12.2 ns
tPZL OFF-state to LOW
propagation delay DIR to A [1] 22.1 18.0 17.1 15.6 16.0 15.5 ns
DIR to B [1] 19.5 16.5 15.4 14.7 14.6 14.8 ns
Table 10. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for waveforms see Figure 6 and Figure 7
Symbol Parameter Conditions VCC(A) Unit
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
tPLH LOW to HIGH
propagation delay A to B 10.6 9.5 9.0 8.5 8.3 8.2 ns
B to A 10.6 8.1 7.0 5.8 5.3 5.1 ns
tPHL HIGH to LOW
propagation delay A to B 10.1 8.6 8.1 7.8 7.6 7.6 ns
B to A 10.1 7.1 6.0 5.3 5.2 5.4 ns
tPHZ HIGH to OFF-state
propagation delay DIRtoA 9.46.55.74.14.13.0ns
DIR to B 12.0 6.1 5.4 4.6 4.3 4.0 ns
tPLZ LOW to OFF-state
propagation delay DIRtoA 7.14.94.53.23.42.5ns
DIRtoB 9.57.36.65.95.75.6ns
tPZH OFF-state to HIGH
propagation delay DIR to A [1] 20.1 15.4 13.6 11.7 11.0 10.7 ns
DIR to B [1] 17.7 14.4 13.5 11.7 11.7 10.7 ns
tPZL OFF-state to LOW
propagation delay DIR to A [1] 22.1 13.2 11.4 9.9 9.5 9.4 ns
DIR to B [1] 19.5 15.1 13.8 11.9 11.7 10.6 ns
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74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 10 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of the outputs.
[2] fi = 10 MHz; VI=GNDtoV
CC; tr = tf = 1 ns; CL = 0 pF; RL = .
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions VCC(A) and VCC(B) Unit
1.8 V 2.5 V 3.3 V 5.5 V
CPD power dissipation
capacitance A port: (direction A to B);
B port: (direction B to A) 2334pF
A port: (direction B to A);
B port: (direction A to B) 15 16 16 18 pF
Table 12. Dynamic characteristics for temperatu re range 40 C to +85 C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter Conditions VCC(B) Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.4 V to 1.6 V
tPLH LOW to HIGH
propagation delay A to B 2.8 21.3 2.4 17.6 2.0 13.5 1.7 11.8 1.6 10.5 ns
B to A 2.8 21.3 2.6 19.1 2.3 14.9 2.3 12.4 2.2 12.0 ns
tPHL HIGH to LOW
propagation delay A to B 2.6 19.3 2.2 15.3 1.8 11.8 1.7 10.9 1.7 10.8 ns
B to A 2.6 19.3 2.4 17.3 2.3 13.2 2.2 11.3 2 .3 11.0 ns
tPHZ HIGH to OFF-state
propagation delay DIR to A 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 ns
DIR to B 3.5 24.8 3.5 23.6 3.0 11.0 3.3 11.3 2.8 10.3 ns
tPLZ LOW to OFF-state
propagation delay DIR to A 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 ns
DIR to B 2.8 18.3 3.0 17.2 2.5 9.4 3.0 10.1 2.5 9.4 ns
tPZH OFF-statetoHIGH
propagation delay DIR to A [1] - 39.6 - 36.3 - 24.3 - 22.5 - 21.4 ns
DIR to B [1] - 32.7 - 29.0 - 24.9 - 23.2 - 21.9 ns
tPZL OFF-state to LOW
propagation delay DIR to A [1] - 44.1 - 40.9 - 24.2 - 22.6 - 21.3 ns
DIR to B [1] - 38.0 - 34.0 - 30.5 - 29.6 - 29.5 ns
VCC(A) = 1.65 V to 1.95 V
tPLH LOW to HIGH
propagation delay A to B 2.6 19.1 2.2 17.7 2.2 9.3 1.7 7.2 1.4 6.8 ns
B to A 2.4 17.6 2.2 17.7 2.3 16.0 2.1 15.5 1.9 15.1 ns
tPHL HIGH to LOW
propagation delay A to B 2.4 17.3 2.0 14.3 1.6 8.5 1.8 7.1 1.7 7.0 ns
B to A 2.2 15.3 2.0 14.3 2.1 12.9 2.0 12.6 1.8 12.2 ns
tPHZ HIGH to OFF-state
propagation delay DIR to A 2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 ns
DIR to B 3.2 24.1 3.2 21.9 2.7 11.5 3.0 10.3 2.5 8.2 ns
tPLZ LOW to OFF-state
propagation delay DIR to A 2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 ns
DIR to B 2.5 17.6 2.6 16.0 2.2 9.2 2.7 8.4 2.4 6.4 ns
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 11 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
tPZH OFF-statetoHIGH
propagation delay DIR to A [1] - 35.2 - 33.7 - 25.2 - 23.9 - 21.8 ns
DIR to B [1] - 29.6 - 28.2 - 19.8 - 17.7 - 17.3 ns
tPZL OFF-state to LOW
propagation delay DIR to A [1] - 39.4 - 36.2 - 24.4 - 22.9 - 20.4 ns
DIR to B [1] - 34.4 - 31.4 - 25.6 - 24.2 - 24.1 ns
VCC(A) = 2.3 V to 2.7 V
tPLH LOW to HIGH
propagation delay A to B 2.3 17.9 2.3 16.0 1.5 8.5 1.3 6.2 1.1 4.8 ns
B to A 2.0 13.5 2.2 9.3 1.5 8.5 1.4 8.0 1.0 7.5 ns
tPHL HIGH to LOW
propagation delay A to B 2.3 15.8 2.1 12.9 1.4 7.5 1.3 5.4 0.9 4.6 ns
B to A 1.8 11.8 1.9 8.5 1.4 7.5 1.3 7.0 0.9 6.2 ns
tPHZ HIGH to OFF-state
propagation delay DIR to A 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 ns
DIR to B 3.0 22.5 3.0 21.4 2.5 11.0 2.8 9.3 2.3 6.9 ns
tPLZ LOW to OFF-state
propagation delay DIR to A 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 ns
DIR to B 2.3 14.6 2.5 13.2 2.0 9.0 2.5 8.4 1.8 5.3 ns
tPZH OFF-statetoHIGH
propagation delay DIR to A [1] - 28.1 - 22.5 - 17.5 - 16.4 - 12.8 ns
DIR to B [1] - 23.7 - 21.8 - 14.3 - 12.0 - 10.6 ns
tPZL OFF-state to LOW
propagation delay DIR to A [1] - 34.3 - 29.9 - 18.5 - 16.3 - 13.1 ns
DIR to B [1] - 23.9 - 21.0 - 15.6 - 13.5 - 12.7 ns
VCC(A) = 3.0V to 3.6V
tPLH LOW to HIGH
propagation delay A to B 2.3 17.1 2.1 15.5 1.4 8.0 0.8 5.6 0.7 4.4 ns
B to A 1.7 11.8 1.7 7.2 1.3 6.2 0.7 5.6 0.6 5.4 ns
tPHL HIGH to LOW
propagation delay A to B 2.2 15.6 2.0 12.6 1.3 7.0 0.8 5.0 0.7 4.0 ns
B to A 1.7 10.9 1.8 7.1 1.3 5.4 0.8 5.0 0.7 4.5 ns
tPHZ HIGH to OFF-state
propagation delay DIR to A 2.3 7.3 2.3 7.3 2.3 7.3 2.3 7.3 2.7 7.3 ns
DIR to B 2.9 18.0 2.9 16.5 2.3 10.1 2.7 8.6 2.2 6.3 ns
tPLZ LOW to OFF-state
propagation delay DIR to A 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 ns
DIR to B 2.3 13.6 2.4 12.5 1.9 7.8 2.3 7.1 1.7 4.9 ns
tPZH OFF-statetoHIGH
propagation delay DIR to A [1] - 25.4 - 19.7 - 14.0 - 12.7 - 10.3 ns
DIR to B [1] - 22.7 - 21.1 - 13.6 - 11.2 - 10.0 ns
tPZL OFF-state to LOW
propagation delay DIR to A [1] - 28.9 - 23.6 - 15.5 - 13.6 - 10.8 ns
DIR to B [1] - 22.9 - 19.9 - 14.3 - 12.3 - 11.3 ns
VCC(A) = 4.5V to 5.5V
tPLH LOW to HIGH
propagation delay A to B 2.2 16.6 1.9 15.1 1.0 7.5 0.7 5.4 0.5 3.9 ns
B to A 1.6 10.5 1.4 6.8 1.0 4.8 0.7 4.4 0.5 3.9 ns
tPHL HIGH to LOW
propagation delay A to B 2.3 15.3 1.8 12.2 1.0 6.2 0.7 4.5 0.5 3.5 ns
B to A 1.7 10.8 1.7 7.0 0.9 4.6 0.7 4.0 0.5 3.5 ns
tPHZ HIGH to OFF-state
propagation delay DIR to A 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 ns
DIR to B 2.9 17.3 2.9 16.1 2.3 9.7 2.7 8.0 2.5 5.7 ns
Table 12. Dynamic characteristics for temperatu re range 40 C to +85 C …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter Conditions VCC(B) Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 12 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
[1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”
tPLZ LOW to OFF-state
propagation delay DIR to A 1.4 3.7 1.4 3.7 1.3 3.7 1.0 3.7 0.9 3.7 ns
DIR to B 2.3 13.1 2.4 12.1 1.9 7.4 2.3 7.0 1.8 4.5 ns
tPZH OFF-statetoHIGH
propagation delay DIR to A [1] - 23.6 - 18.9 - 12.2 - 11.4 - 8.4 ns
DIR to B [1] - 20.3 - 18.8 - 11.2 - 9.1 - 7.6 ns
tPZL OFF-state to LOW
propagation delay DIR to A [1] - 28.1 - 23.1 - 14.3 - 12.0 - 9.2 ns
DIR to B [1] - 20.7 - 17.6 - 11.6 - 9.9 - 8.9 ns
Table 12. Dynamic characteristics for temperatu re range 40 C to +85 C …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter Conditions VCC(B) Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
Table 13. Dynamic characteristics for temperatu re range 40 C to +125 C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter Conditions VCC(B) Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.4 V to 1.6 V
tPLH LOW to HIGH
propagation delay A to B 2.5 23.5 2.1 19.4 1 .8 14.9 1.5 13.0 1.4 11.6 ns
B to A 2.5 23.5 2.3 21.1 2.0 16.4 2.0 13.7 1.9 13.2 ns
tPHL HIGH to LOW
propagation delay A to B 2.3 21.3 1.9 16.9 1 .6 13.0 1.5 12.0 1.5 11.9 ns
B to A 2.3 21.3 2.1 19.1 2.0 14.6 1.9 12.5 2.0 12.1 ns
tPHZ HIGH to OFF-state
propagation delay DIR to A 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 ns
DIR to B 3.1 27.3 3.1 26.0 2.7 12.1 2.9 12.5 2.5 11.4 ns
tPLZ LOW to OFF-state
propagation delay DIR to A 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 ns
DIR to B 2.5 20.2 2.7 19.0 2.2 10.4 2.7 11.2 2.2 10.4 ns
tPZH OFF-statetoHIGH
propagation delay DIR to A [1] - 43.7 - 40.1 - 26.8 - 24.9 - 23.6 ns
DIR to B [1] - 36.1 - 32.0 - 27.5 - 25.6 - 24.2 ns
tPZL OFF-state to LOW
propagation delay DIR to A [1] - 48.6 - 45.1 - 26.7 - 25.0 - 23.5 ns
DIR to B [1] - 41.9 - 37.5 - 33.6 - 32.6 - 32.5 ns
VCC(A) = 1.65 V to 1.95 V
tPLH LOW to HIGH
propagation delay A to B 2.3 21.1 1.9 19.5 1.9 10.3 1.5 8.0 1.2 7.5 ns
B to A 2.1 19.4 1.9 19.5 2.0 17.6 1.8 17.1 1.7 16.7 ns
tPHL HIGH to LOW
propagation delay A to B 2.1 19.1 1.8 15.8 1.4 9.4 1.6 7.9 1.5 7.7 ns
B to A 1.9 16.9 1.8 15.8 1.8 14.2 1.8 13.9 1.6 13.5 ns
tPHZ HIGH to OFF-state
propagation delay DIR to A 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 ns
DIR to B 2.8 26.6 2.8 24.1 2.4 12.7 2.7 11.4 2.2 9.1 ns
tPLZ LOW to OFF-state
propagation delay DIR to A 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 ns
DIR to B 2.2 19.4 2.3 17.6 1.9 10.2 2.4 9.3 2.1 7.4 ns
tPZH OFF-statetoHIGH
propagation delay DIR to A [1] - 38.8 - 37.1 - 27.8 - 26.4 - 24.1 ns
DIR to B [1] - 32.7 - 31.1 - 21.9 - 19.6 - 19.1 ns
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 13 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
tPZL OFF-state to LOW
propagation delay DIR to A [1] - 43.5 - 39.9 - 26.9 - 25.3 - 22.6 ns
DIR to B [1] - 38.0 - 34.7 - 28.3 - 26.8 - 26.6 ns
VCC(A) = 2.3 V to 2.7 V
tPLH LOW to HIGH
propagation delay A to B 2.0 19.7 2.0 17.6 1.3 9.4 1.1 6.9 0.9 5.3 ns
B to A 1.8 14.9 1.9 10.3 1.3 9.4 1.2 8.8 0.9 8.3 ns
tPHL HIGH to LOW
propagation delay A to B 2.0 17.4 1.8 14.2 1.2 8.3 1.1 6.0 0.8 5.1 ns
B to A 1.6 13.0 1.7 9.4 1.2 8.3 1.1 7.7 0.8 6.9 ns
tPHZ HIGH to OFF-state
propagation delay DIR to A 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 ns
DIR to B 2.7 24.8 2.7 23.6 2.2 12.1 2.5 10.3 2.0 7.6 ns
tPLZ LOW to OFF-state
propagation delay DIR to A 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 ns
DIR to B 2.0 16.1 2.2 14.6 1.8 9.9 2.2 9.3 1.6 5.9 ns
tPZH OFF-statetoHIGH
propagation delay DIR to A [1] - 31.0 - 24.9 - 19.3 - 18.1 - 14.2 ns
DIR to B [1] - 26.1 - 24.0 - 15.8 - 13.3 - 11.7 ns
tPZL OFF-state to LOW
propagation delay DIR to A [1] - 37.8 - 33.0 - 20.4 - 18.0 - 14.5 ns
DIR to B [1] - 26.4 - 23.2 - 17.3 - 15.0 - 14.1 ns
VCC(A) = 3.0V to 3.6V
tPLH LOW to HIGH
propagation delay A to B 2.0 18.9 1.8 17.1 1.2 8.8 0.7 6.2 0.6 4.9 ns
B to A 1.5 13.0 1.5 8.0 1.1 6.9 0.6 6.2 0.5 6.0 ns
tPHL HIGH to LOW
propagation delay A to B 1.9 17.2 1.8 13.9 1.1 7.7 0.7 5.5 0.6 4.4 ns
B to A 1.5 12.0 1.6 7.9 1.1 6.0 0.7 5.5 0.6 5.0 ns
tPHZ HIGH to OFF-state
propagation delay DIR to A 2.0 8.1 2.0 8.1 2.0 8.1 2.0 8.1 2.4 8.1 ns
DIR to B 2.6 19.8 2.6 18.2 2.0 11.2 2.4 9.5 1.9 7.0 ns
tPLZ LOW to OFF-state
propagation delay DIR to A 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 ns
DIR to B 2.0 15.0 2.1 13.8 1.7 8.6 2.0 7.9 1.5 5.4 ns
tPZH OFF-statetoHIGH
propagation delay DIR to A [1] - 28.0 - 21.8 - 15.5 - 14.1 - 11.4 ns
DIR to B [1] - 25.1 - 23.3 - 15.0 - 12.4 - 11.1 ns
tPZL OFF-state to LOW
propagation delay DIR to A [1] - 31.8 - 26.1 - 17.2 - 15.0 - 12.0 ns
DIR to B [1] - 25.3 - 22.0 - 15.8 - 13.6 - 12.5 ns
VCC(A) = 4.5V to 5.5V
tPLH LOW to HIGH
propagation delay A to B 1.9 18.3 1.7 16.7 0.9 8.3 0.6 6.0 0.4 4.3 ns
B to A 1.4 11.6 1.2 7.5 0.9 5.3 0.6 4.9 0.4 4.3 ns
tPHL HIGH to LOW
propagation delay A to B 2.0 16.9 1.6 13.5 0.9 6.9 0.6 5.0 0.4 3.9 ns
B to A 1.5 11.9 1.5 7.7 0.8 5.1 0.6 4.4 0.4 3.9 ns
tPHZ HIGH to OFF-state
propagation delay DIR to A 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 ns
DIR to B 2.6 19.1 2.6 17.8 2.0 10.7 2.4 8.8 2.2 6.3 ns
tPLZ LOW to OFF-state
propagation delay DIR to A 1.2 4.1 1.2 4.1 1.1 4.1 0.9 4.1 0.8 4.1 ns
DIR to B 2.0 14.5 2.1 13.4 1.7 8.2 2.0 7.7 1.6 5.0 ns
Table 13. Dynamic characteristics for temperatu re range 40 C to +125 C …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter Conditions VCC(B) Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 14 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
[1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”
12. Waveforms
tPZH OFF-statetoHIGH
propagation delay DIR to A [1] - 26.1 - 20.9 - 13.5 - 12.6 - 9.3 ns
DIR to B [1] - 22.4 - 20.8 - 12.4 - 10.1 - 8.4 ns
tPZL OFF-state to LOW
propagation delay DIR to A [1] - 31.0 - 25.5 - 15.8 - 13.2 - 10.2 ns
DIR to B [1] - 22.9 - 19.5 - 12.9 - 11.0 - 9.9 ns
Table 13. Dynamic characteristics for temperatu re range 40 C to +125 C …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter Conditions VCC(B) Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. The data input (A, B) to output (B, A) propagation delay ti mes
001aae967
A, B input
B, A output
tPLH
tPHL
GND
VI
VOH
VM
VM
VOL
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Enable and disable times
001aae968
t
PZL
t
PZH
t
PHZ
t
PLZ
GND
GND
V
I
V
CCO
V
OL
V
OH
V
M
V
M
V
M
V
X
V
Y
outputs
disabled outputs
enabled
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
DIR input
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 15 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt 1.0 V/ns
[3] VCCO is the supply voltage associated with the output port.
Table 14. Measurement points
Supply voltage Input[1] Output[2]
VCC(A), VCC(B) VMVMVXVY
1.2 V to 1.6 V 0.5VCCI 0.5VCCO VOL +0.1V V
OH 0.1 V
1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL +0.15V V
OH 0.15 V
3.0 V to 5.5 V 0.5VCCI 0.5VCCO VOL +0.3V V
OH 0.3 V
Test data is given in Table 15.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 8. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
CL
RT
RL
RL
G
Table 15. Test data
Supply voltage Input Load VEXT
VCC(A), VCC(B) VI[1] t/V[2] CLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ[3]
1.2 V to 5.5 V VCCI 1.0ns/V 15pF 2kopen GND 2VCCO
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 16 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
13. Typical propagation delay characteristics
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 9. Typical propagation delay vs load capacitance; Tamb = 25 C; VCC(A) =1.2V
CL (pF)
035
001aai907
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(2)
(3)
(4)
(5)
(6)
CL (pF)
035
001aai908
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(2)
(3)
(4)
(5)
(6)
CL (pF)
035
001aai909
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(3)
(4)
(5)
(6)
(2)
CL (pF)
035
001aai910
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(6)
(3)
(4)
(2)
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 17 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 10. Typical propagation delay vs load capacitance; Tamb = 25 C; VCC(A) =1.5V
CL (pF)
035
001aai911
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(6)
(3)
(4)
(2)
CL (pF)
035
001aai912
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(6)
(3)
(4)
(2)
CL (pF)
035
001aai913
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(6)
(3)
(4)
(2)
CL (pF)
035
001aai914
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(6)
(3)
(4)
(2)
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 18 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 11. Typical propagation delay vs load capacitance; Tamb = 25 C; VCC(A) =1.8V
CL (pF)
035
001aai915
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(6)
(3)
(4)
(2)
CL (pF)
035
001aai916
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(6)
(3)
(4)
(2)
CL (pF)
035
001aai917
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(6)
(4)
(2)
(3)
CL (pF)
035
001aai918
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(6)
(4)
(2)
(3)
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 19 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 12. Typical propagation delay vs load capacitance; Tamb = 25 C; VCC(A) =2.5V
CL (pF)
035
001aai919
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
CL (pF)
035
001aai920
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
CL (pF)
035
001aai921
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
CL (pF)
035
001aai922
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 20 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 13. Typical propagation delay vs load capacitance; Tamb = 25 C; VCC(A) =3.3V
CL (pF)
035
001aai923
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
CL (pF)
035
001aai924
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
CL (pF)
035
001aai925
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
CL (pF)
035
001aai926
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 21 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 14. Typical propagation delay vs load capacitance; Tamb = 25 C; VCC(A) =5V
CL (pF)
035
001aai927
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
CL (pF)
035
001aai928
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
CL (pF)
035
001aai929
14
tPHL
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
CL (pF)
035
001aai930
14
tPLH
(ns)
0
2
4
6
8
10
12
5 1015202530
(1)
(5)
(4)
(2)
(3)
(6)
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 22 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
14. Application information
14.1 Unidirectional logic level-shifting application
The circuit given in Figure 15 is an example of the 74LVC1T45; 74LVCH1T45 being used
in a unidirectional logic level-shifting application.
Fig 15. U ni directional logic level-shifting application
Table 16. Description unidirectional logic level-shifting application
Pin Name Function Description
1V
CC(A) VCC1 supply voltage of system-1 (1.2 V to 5.5 V)
2 GND GND device GND
3 A OUT output level depends on VCC1 voltage
4 B IN input threshold value depends on VCC2 voltage
5 DIR DIR the GND (LOW level) determines B port to A port direction
6V
CC(B) VCC2 supply voltage of system-2 (1.2 V to 5.5 V)
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 23 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
14.2 Bidirectional logic level-shifting application
Figure 16 shows the 74LVC1T45; 74LVCH1T45 being used in a bidirectional logic
level-shifting application. Since the device does not have an output enable pin, the system
designer should take precautions to avoid bus contention between system-1 and
system-2 when changing directions.
Table 17 provides a sequence that illustrates data transmission from system-1 to
system-2 and then from system-2 to system-1.
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
Pull-up or pull-down only needed for 74LVC1T45.
Fig 16. Bidirectional logic level-shifting application
Table 17. Description bidirect ional logic leve l-shifting application[1]
State DIR CTRL I/O-1 I/O-2 Description
1 H output input system-1 data to system-2
2 H Z Z system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled. The bus-line state
depends on bus hold.
3 L Z Z DIR bit is set LOW. I/ O-1 and I/O-2 are still disabled.
The bus-line state depends on bus hold.
4 L input output system-2 data to system-1
001aaj995
74LVC1T45
74LVCH1T45
VCC1
VCC1 VCC2
VCC2
1
2
3
VCC(A)
GND
system-1 system-2
A
6
5
4
VCC(B)
DIR
B
I/O-1 I/O-2
PULL-UP/DOWN
DIR CTRL
PULL-UP/DOWN
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 24 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
14.3 Power-up considerations
The device is designed such that no special power-up sequence is required other than
GND being applied first.
14.4 Enable times
Calculate the enable times for the 74LVC1T45; 74LVCH1T45 using the following
formulas:
•tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
•tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
•tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
•tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the
time the DIR bit is switched until an output is expected. For example, if the 74LVC1T45;
74LVCH1T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of
the device must be disabled before presenting it with an input. After the B port has been
disabled, an input signal applied to it appears on the corresponding A port after the
specified propagation delay.
Table 18. Typical total supply current (ICC(A) + ICC(B))
VCC(A) VCC(B) Unit
0 V 1.8 V 2.5 V 3.3 V 5.0 V
0 V0 < 1< 1< 1< 1A
1.8 V < 1 < 2 < 2 < 2 2 A
2.5 V < 1 < 2 < 2 < 2 < 2 A
3.3 V < 1 < 2 < 2 < 2 < 2 A
5.0 V < 1 2 < 2 < 2 < 2 A
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 25 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
15. Package outline
Fig 17. Package outline SOT363 (SC-88)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT363 SC-88
wBM
bp
D
e1
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
456
Plastic surface-mounted package; 6 leads SOT363
UNIT A1
max bpcDEe1HELpQywv
mm 0.1 0.30
0.20 2.2
1.8
0.25
0.10 1.35
1.15 0.65
e
1.3 2.2
2.0 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.25
0.15
A
1.1
0.8
04-11-08
06-03-16
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 26 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Fig 18. Package outline SOT886 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT886 MO-252
sot886_po
04-07-22
12-01-05
Unit
mm max
nom
min
0.5 0.04 1.50
1.45
1.40
1.05
1.00
0.95
0.35
0.30
0.27
0.40
0.35
0.32
0.6
A(1)
Dimensions (mm are the original dimensions)
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886
A1b
0.25
0.20
0.17
DEee
1
0.5
LL
1
terminal 1
index area
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
1
6
2
5
3
4
6x
(2)
4x
(2)
A
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 27 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Fig 19. Package outline SOT891 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT891
SOT891
05-04-06
07-05-15
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm 0.20
0.12 1.05
0.95 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.350.55
A
max
0.5 0.04
1
6
2
5
3
4
A
6×
(1)
4×
(1)
Note
1. Can be visible in some manufacturing processes.
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 28 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Fig 20. Package outline SOT1115 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1115
sot1115_po
10-04-02
10-04-07
Unit
mm max
nom
min
0.35 0.04 0.95
0.90
0.85
1.05
1.00
0.95 0.55 0.3 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
L1
b
321
6 5 4
(6×)(2) A1A
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 29 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Fig 21. Package outline SOT1202 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1202
sot1202_po
10-04-02
10-04-06
Unit
mm max
nom
min
0.35 0.04 1.05
1.00
0.95
1.05
1.00
0.95 0.55 0.35 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
b
123
L1
6 5 4
(6×)(2)
A
A1
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 30 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
16. Abbreviations
17. Revision history
Table 19. Abbreviations
Acronym Description
CDM Charged Device Mo del
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
Table 20. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC_ LVCH1T45 v.6 20120806 Product data sheet - 74LVC_LVCH1T45 v.5
Modifications: •Package outline drawing of SOT886 (Figure 18) modified.
74LVC_ LVCH1T45 v.5 20111219 Product data sheet - 74LVC_LVCH1 T45 v.4
Modifications: •Legal pages updated.
74LVC_ LVCH1T45 v.4 20110927 Product data sheet - 74LVC_LVCH1T45 v.3
74LVC_ LVCH1T45 v.3 20100819 Product data sheet - 74LVC_LVCH1T45 v.2
74LVC_ LVCH1T45 v.2 20100119 Product data sheet - 74LVC_LVCH1T45 v.1
74LVC_ LVCH1T45 v.1 20090511 Product data sheet - -
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 31 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
18. Legal information
18.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsisten cy or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to off er functions and qualities beyon d those described in the
Product data sheet.
18.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an inf ormation
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in life support , life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with their
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data fro m the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
© Nexperia B.V. 2017. All rights reserved
74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 6 — 6 August 2012 32 of 33
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lified nor tested
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without Nexperia’s warranty of the
product for such automotive ap plications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond Nexperia’s
standard warranty and Nexperia’s product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
19. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Nexperia 74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
20. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Typical pro pagation delay characteristics . . 16
14 Application information. . . . . . . . . . . . . . . . . . 22
14.1 Unidirectional logic level - shifting application . 22
14.2 Bidirectional logic level-shifting application. . . 23
14.3 Power-up considerations . . . . . . . . . . . . . . . . 24
14.4 Enable times. . . . . . . . . . . . . . . . . . . . . . . . . . 24
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25
16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 30
17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 30
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 31
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31
18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 31
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
19 Contact information. . . . . . . . . . . . . . . . . . . . . 32
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
06 August 2012