Xtrinsic FXLC95000CL Intelligent,
Motion-Sensing Platform
The FXLC95000CL Intelligent, Motion-Sensing Platform is a
breakthrough device with the integration of a 3-axis MEMS
accelerometer and a 32-bit ColdFire MCU that enables
autonomous, high-precision sensing solutions with local
computing and sensors management capability in an open, easy
to use, architecture.
The FXLC95000CL hardware is user-programmable to create an
intelligent high-precision, flexible, motion-sensing platform. The
user's firmware, together with the hardware device, can make
system-level decisions required for sophisticated applications,
such as gesture recognition, pedometer, and e-compass tilt
compensation and calibration.
The FXLC95000 platform can act as an intelligent sensing hub
and a highly configurable decision engine. Using the Master I2C
or SPI module, the FXLC95000 platform can manage secondary
sensors such as pressure sensors, magnetometers, and
gyroscopes. The embedded microcontroller allows sensor
integration, initialization, calibration, data compensation, and
computation functions to be added to the platform, thereby off-
loading those functions from the host processor. Total system
power consumption is significantly reduced because the
application processor stays powered down for longer periods of
time.
The FXLC95000CL device is programmed and configured with
CodeWarrior Development Studio for Microcontroller (Eclipse
IDE). This standard, integrated development environment (IDE)
enables customers to quickly implement custom embedded
algorithms and features to exactly match their application needs.
Hardware Features
3-axis low noise accelerometer
±2 g, ±4 g, ±8 g configurable dynamic ranges available
Up to 16-bit resolution
32-bit MCU
Coldfire V1 CPU with MAC hardware unit
128K Flash, 16K RAM, 16K ROM
10-, 12-, 14-, and 16-bit, trimmed analog-to-digital converter (ADC) data formats available
Master and slave, I2C and SPI serial connectivity modules
Sleep and low power modes to enable local power
FXLC95000CL
24-LEAD LGA
3 mm by 5 mm by 1 mm
Case 2208-01
Top View
RGPIO14 / SCL1
RGPIO15 / SDA1
VSSIO
VDDIO
VDD
BKGD-MS / RGPIO9
RESETB
RGPIO11 / MOSI1
RGPIO10 / SCLK1
RGPIO7 / AN1+ / TPMCH1
RGPIO6 / AN0- / TPMCH0
RGPIO5 / PDB_A / INT_O
VSS
RGPIO4 / INT_I
VSSA
RGPIO8 / PDB_B
VDDA
RGPIO13 / SSB1
RGPIO12 / MISO1
SCL0 / RGPIO0 / SCLK
VSS
SDA0 / RGPIO1 / MOSI
RGPIO2 / SCL1 / MISO
RGPIO3 / SDA1 / SSB
Pin Connections
Freescale Semiconductor, Inc. FXLC95000CL
Data Sheet: Technical Data Rev 1.2, 8/2013
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2012–2013 Freescale
Semiconductor, Inc. All rights reserved.
Wide operating voltage and temperature range
1.71 to 3.6 V I/O supply voltage
–40ºC to +85ºC operating temperature range
Small package footprint
3 mm x 5 mm x 1 mm 24-pin LGA package
Ordering Information
Part number Temperature range Package description Shipping
FXLC95000CLR1 –40°C to +85°C LGA-24 Tape and reel
2Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
Table of Contents
1 Typical Applications..............................................................4
2Software Support..................................................................4
3Related Documentation.........................................................5
4 General Description..............................................................5
4.1 Functional overview.....................................................5
4.1.1 ROM content and usage..................................7
4.2 Pinout...........................................................................7
4.2.1 Pin function description....................................9
4.3 System connections.....................................................12
4.3.1 Power supply considerations...........................12
4.3.2 General connections and layout
recommendations............................................13
4.3.3 I2C reset considerations..................................14
4.3.4 FXLC95000CL as an intelligent slave..............14
4.3.5 FXLC95000CL as a sensor hub......................16
4.4 Sensing direction and output response.......................19
5 Mechanical and Electrical Specifications..............................20
5.1 Definitions....................................................................21
5.2 Absolute maximum ratings..........................................21
5.3 Operating conditions....................................................22
5.4 General DC characteristics..........................................23
5.5 Supply current characteristics......................................23
5.6 Accelerometer transducer mechanical characteristics 24
5.7 Temperature sensor characteristics............................25
5.8 ADC characteristics.....................................................25
5.9 AC electrical characteristics.........................................26
5.10 General timing control..................................................27
5.11 Interfaces.....................................................................28
5.12 Flash parameters.........................................................31
6 Package Information.............................................................32
6.1 Product Identification Markings....................................32
6.2 Footprint and pattern information.................................32
6.3 Tape and reel information............................................35
6.4 Package dimensions....................................................35
7 Revision History....................................................................37
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 3
Freescale Semiconductor, Inc.
1 Typical Applications
This low-power intelligent sensor platform is optimized for a variety of applications.
Mobile phones/PMP/PDA/Digital cameras
E-Compass applications with tilt compensation
Smartbooks/e-readers/netbooks/laptops
Pedometers
Gaming and toys
Virtual-reality, 3D position feedback
Personal navigation devices (PNDs)
Activity monitoring in medical and fitness applications
Security
Fleet monitoring and tracking
Power tools and small appliances
2 Software Support
The Xtrinsic Intelligent Sensing Framework (ISF) is a software framework built on top
of Freescale’s MQX real time operating system (RTOS). ISF offers an open
programming model with library support for FXLC95000CL devices. The flexibility of
this open programming model allows the FXLC95000CL to be delivered ready to
accept a customer’s choice of firmware images. A number of pre-built firmware images
are available for download from the Freescale website, or, using CodeWarrior and ISF,
a customer may create their own custom firmware image incorporating sensor
processing algorithms of their own design.
Sensor Adapter libraries for a number of additional Freescale sensors are also available
for download enabling the FXLC95000CL to become a sensor hub.
Typical Applications
4Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
3 Related Documentation
The FXLC95000CL device's features and operations are described in a variety of
reference manuals, user guides, and application notes.
To find the most-current versions of these documents:
1. Go to the Freescale homepage at freescale.com.
2. In the Keyword search box at the top of the page, enter the device number
FXLC95000CL.
3. In the Refine Your Result pane on the left, click on the Documentation link.
4 General Description
4.1 Functional overview
The FXLC95000CL platform consists of a three-axis, MEMS accelerometer and a
mixed-signal ASIC with an integrated, 32-bit CPU. The mixed-signal ASIC can be
utilized to measure and condition the outputs of the MEMS accelerometer, internal
temperature sensor, or a differential analog signal from an external device.
These measured values can be read at different sample rates through a subscription
mechanism in the Intelligent Sensing Framework (ISF) and/or utilized internally by
firmware for the FXLC95000CL device (Freescale supplied or user-written).
Related Documentation
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 5
Freescale Semiconductor, Inc.
External
clock
domain
Internal
clock
domain
Analog Front End
SDA1,SCL1
8
BKGD/MS
Temperature
sensor
Drive circuit
C2V
ADC Peripheral
bus interface
Trim
3-axis
accelerometer
transducer
System Integration
Module
Interrupt
controller
16 KB
RAM
ColdFire
V1
16 KB
ROM
128 KB
Flash
memory
RGPIO[15:0]
Flash
controller
I2C master
SPI master
2 x 8 Port
control
16-bit modulo
timer
Programmable
Delay Block
Two-channel
TPM
Clock module
(16 MHz)
Control and
mailbox
register set
SPI slave
I2C slave
16
16
8
16
8
8
16
8
8
16
8
/
/
/
SCLK2. SSB2
MOSI, MISO,
SP_SCR[PS]
SSB
SCLK
MISO
MOSI
SDA0
SCL0
RESETB
INT_I
CPU
/
/PDB_A,
PDB_B
TPMCH0,
TPMCH1
RGPIO0, ... ,
RGPIO15
Figure 1. Block diagram of the FXLC95000CL
A block level view of the FXLC95000CL platform is shown in Figure 1 and can be
summarized at a high level as an analog/mixed mode subsystem associated with a
digital engine.
The analog sub-system is composed of:
A 3-axis MEMS transducer
An Analog Front End (AFE) with:
A capacitance-to-voltage converter
An analog-to-digital converter
A temperature sensor
The digital sub-system is composed of:
A 32-bit, ColdFire V1 CPU with Background Debug Module (BDM)
Memory: RAM, ROM, and flash
Rapid General Purpose Input/Output (RGPIO) port control logic
Timer functions:
Modulo Timer Module (MTIM16)
Programmable Delay Timer (PDB)
General-Purpose Timer/Pulse-Width Modulation Module (TPM)
General Description
6Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
I2C master interface
Queued SPI master interface (This interface has both send and receive FIFOs of
size 16 bit wordlength and 4 words depth each. No DMA.)
I2C or SPI slave interface
System Integration Module (SIM)
Clock-generation module
The slave interfaces (either SPI or I2C) operate independently of the ColdFire CPU
subsystem. This allows the host processor to access the slave interface at any time,
including while the FXLC95000CL's CPU is in low-power, deep-sleep mode. Host
access can be set to trigger a FXLC95000CL CPU wakeup.
4.1.1 ROM content and usage
There are several classes of functions stored in ROM:
A Boot program, including ROM-based slave port command interpreter.
A collection of utilities which can be invoked via the ROM-based slave port
command interpreter.
ROM functions which are callable from user code using the call_trap() function.
For a detailed description of these items, refer to the FXLC95000CL Hardware
Reference Manual ROM chapter.
The FXLC95000CL device boots from a standard routine in ROM. This boot function
is responsible for a number of initialization steps (in particular the state of GPIO8 pin
is checked in order to select either I2C or SPI interface as serial communication Slave
port), before transferring control if desired to user code in flash memory (when the
Boot from Flash bit-field has been set).
The ROM contains a simple command interpreter capable of running a number of
ROM-based utility and test functions. These ROM-based functions support flash
memory programming and erasing, the protection of flash, the device Reset, and the
reading of device information. They also provide useful error codes.
The FXLC95000CL platform is supplied with a fully erased flash memory. Users can
take advantage of the ROM-based flash controller and slave port command-line
interpreter to communicate with a virgin device and program custom firmware into
the flash array.
General Description
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 7
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4.2 Pinout
RGPIO14 / SCL1
RGPIO15 / SDA1
VSSIO
VDDIO
VDD
BKGD-MS / RGPIO9
RESETB
RGPIO11 / MOSI1
RGPIO10 / SCLK1
RGPIO7 / AN1+ / TPMCH1
RGPIO6 / AN0- / TPMCH0
RGPIO5 / PDB_A / INT_O
VSS
RGPIO4 / INT_I
VSSA
RGPIO8 / PDB_B
VDDA
RGPIO13 / SSB1
RGPIO12 / MISO1
SCL0 / RGPIO0 / SCLK
VSS
SDA0 / RGPIO1 / MOSI
RGPIO2 / SCL1 / MISO
RGPIO3 / SDA1 / SSB
Figure 2. Device pinout (top view)
Table 1. Pin functions
Pin # Default Pin
Function1Pin Function
#2
Pin Function
#3
Description
1 SCL12RGPIO14 Master I2C Clock / RGPIO14
2 SDA13RGPIO15 Master I2C Data / RGPIO15
3 VSSIO I/O ground
4 VDDIO I/O power supply
5 VDD Digital power supply
6 BKGD/MS RGPIO9 Background debug - Mode select / RGPIO9
7 RESETB4Active low reset with internal, pullup resistor
8 SCL0 RGPIO0 SCLK Serial clock for slave I2C / RGPIO0 / Serial clock for slave
SPI
9 VSS Digital ground
10 SDA0 RGPIO1 MOSI Serial data for slave I2C / RGPIO1 / SPI Master Output Slave
Input
11 RGPIO2 SCL1 MISO RGPIO2 / Serial clock for master I2C / SPI Master Input
Slave Output
12 RGPIO3 SDA1 SSB RGPIO3 / Serial data for master I2C / SPI slave select
13 RGPIO4 INT_I RGPIO4 / Interrupt input
14 VSS Must be connected to GND externally
15 RGPIO5 PDB_A INT_O RGPIO5 / PDB_A / Interrupt output
Table continues on the next page...
General Description
8Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
Table 1. Pin functions (continued)
Pin # Default Pin
Function1Pin Function
#2
Pin Function
#3
Description
16 RGPIO6 AN0- TPMCH0 RGPIO6 / ADC Input 0 / TPM Channel 0
17 RGPIO7 AN1+ TPMCH1 RGPIO7 / ADC Input 1 / TPM Channel 1
18 SCLK1 RGPIO10 master queued SPI clock / RGPIO10
19 MOSI1 RGPIO11 master queued SPI Master Output Slave Input / RGPIO11
20 MISO1 RGPIO12 master queued SPI Master Input Slave Output / RGPIO12
21 SSB1 RGPIO13 master queued SPI slave select / RGPIO13
22 VDDA Analog power
235RGPIO8 PDB_B RGPIO8 / PDB_B
24 VSSA Analog ground
1. Default Pin Function 1 represents the reset state of the device. Pin functions may be changed via the SIM pin mux-
control registers. Drive strength and pullup controls are programmed by the port control registers.
2. SCL1 is available for use on pin (RGPIO14) only when SIM_PMCR1[A2] is not equal to "01". That setting would
enable it for pin 11 (RGPIO2).
3. SDA1 is available for use on pin (RGPIO15) only when SIM_PMCR1[A3] is not equal to "01". That setting would
enable it for pin 12 (RGPIO3).
4. RESETB defaults to input only, but can be configured as an open-drain, bidirectional pin.
5. GPIO8/PDB_B = LOW at startup indicates that SPI should be used as slave instead of the I2C module.
4.2.1 Pin function description
Descriptions of the pin functions available on this device are provided in this section.
Sixteen of the device pins are multiplexed with Rapid GPIO (RGPIO) functions. The
Default Pin Function column of Table 1 lists which function is active when the device
exits the reset state. User firmware can use the Pin Mux Control registers in the
System Integration Module (SIM) to change pin assignments for these pins after reset.
VDDIO and VSSIO
I/O power and ground. VDDIO ranges from 1.71V to 3.6V for this device. The device
will not load the I2C bus if VDDIO is not connected. Parasitic paths to supply this
power domain from other pins is not recommended.
VDD and VSS
Digital power and ground. VDD is nominally 1.8V for this device. Parasitic paths to
supply this power domain from other pins is not recommended.
VDDA and VSSA
General Description
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 9
Freescale Semiconductor, Inc.
Analog power and ground. VDDA is nominally 1.8V for this device. It is recommended
that this supply voltage be filtered to remove any digital noise that may be present on
the supply.
RESETB
The RESETB pin is an open-drain, bidirectional pin. At power up, it is configured
strictly as an input pin. Setting RCSR[DR] (Reset Control & Status Register “Drive
Reset” bit) to one will cause the RESET function to become bidirectional. Using this
feature, FXLC95000CL can reset external devices whenever it is reset for any purpose
other than power-on-reset.
Slave I2C: SDA0, SCL0
Slave I2C data and clock signals. FXLC95000CL may be controlled via this serial port
or via the slave SPI interface. At reset, SDA0 and SCL0 are open-drain, bidirectional in
input mode, with the pullup resistor disabled.
Master I2C: SDA1, SCL1
Master I2C data and clock signals. Because the FXLC95000CL contains a 32-bit
ColdFire V1 CPU, it is fully capable of mastering other devices in the system via this
serial port.
State at reset: active. SCL1 and SDA1 are configured on pins 1 and 2, respectively. The
alternate functionality on these pins is RGPIO14 and RGPIO15.
Analog-to-Digital Conversion: AN0, AN1
The on-chip ADC can be used to perform a differential analog-to-digital conversion
based upon the voltage present across pins AN0(-) and AN1(+). Conversions for these
pins are at the same Sample Data Rate (SDR) as the MEMS transducer signals.
State at reset: Inactive. AN[1:0] are secondary functions on RGPIO[7:6], which own the
pins at reset.
Rapid General Purpose I/O: RGPIO[15:0]
The ColdFire V1 CPU has a feature called “Rapid GPIO” or RGPIO. This is a 16-bit
input/output port with single-cycle write, set, clear, and toggle functions available to the
CPU. The FXLC95000CL brings out all 16 bits of that port as pins of the device.
State at reset:
RGPIO[15:14]: inactive. SDA1 and SCL1 own the pin at reset.
General Description
10 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
RGPIO[13:10, 8:2]: Pin mux registers for these bits are configured as RGPIO.
Pullups are disabled. RGPIO functionality can be enabled via
RGPIO_ENB[13:10, 8:2].
RGPIO[9]: Inactive. BKGD/MS owns the pin at reset
RGPIO[1:0]: inactive. SDA0 and SCL0 own the pin at reset.
Configuration details:
RGPIO[15:14] are configured as Master I2C port at reset when
RGPIO_ENB[15:14]=00 and PMCR[A3]=PMCR[A2]=00 or 10. They can only
be configured as RGPIO when PMCR[A3]=PMCR[A2]=01. RGPIO_ENB[15:14]
must also be set to 11 for them to assume RGPIO functionality.
RGPIO_ENB[13:10] are used to configure RGPIO[13:10].
Pin function selections are made via the SIM pin mux registers for RGPIO[9:0].
Interrupts: INT_I
This input pin may be used to wake the CPU from a deep-sleep mode. It can be
programmed to trigger on either rising or falling edge or high or low level. This pin
operates as a level 7 (high priority) interrupt.
Interrupts: INT_O
RGPIO5 (pin 11) can be configured to function as an interrupt output pin. This
interrupt can be asserted via software when a command response packet has been
stored on the slave port mailboxes and is ready for the host to read. The host will see
the interrupt and can read the data from the FXLC95000CL platform. The
FXLC95000CL will automatically clear the interrupt once it recognizes that the
response packet is being transmitted. This clearing action occurs while the packet is
being read and prevents the host from falsely recognizing the same interrupt after the
packet read is complete.
State at reset: Pin muxing is set to RGPIO5 mode.
Debug/Mode Control: BKGD/MS
At power-up, this pin operates as Mode Select. If low during power-up, the CPU will
boot into debug halt mode. If high, the CPU will boot normally and run code. After
power-on reset, this pin operates as a bidirectional, single-wire Background Debug
port. CodeWarrior uses the Background Debug port to download code into on-chip
RAM and flash, and for debugging that code using breakpoints and single stepping.
State at reset: Mode Select (MS).
MS = 1'b0, at exit from reset boot to debug halt mode.
General Description
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 11
Freescale Semiconductor, Inc.
MS = 1'b1, at exit from reset boot to run mode.
State after reset: BKGD. The BKGD pin is a bidirectional, pseudo-open-drain pin used
for communications with a debug environment.
Programmable Delay Block: PDB_A, PDB_B
These are the two outputs of the programmable delay block (PDB). Normally, the PDB
is used to schedule internal events at some fixed interval(s) relative to start of either the
analog or digital phase. By bringing the PDB outputs to these pins, it becomes possible
for the FXLC95000CL to initiate some external event, also relative to start of analog or
digital phase. For more information, refer to the FXLC95000CL Hardware Reference
Manual.
Timer: TPMCH0 and TPMCH1
These pins are the outputs for a general modulo 16 timer and general input/output
capture (TPM) and pulse width modulation (PWM) functions.
Slave SPI Interface: SCLK, MOSI, MISO, SSB
Slave SPI clock, master-output slave-input, master-input slave-output, and slave-select
signals. The FXLC95000CL may be controlled via this serial port or via the slave I2C
interface.
State at reset: In reset, these pins are configured according to I2C and RGPIO[3:2]
functions listed above. The pin may be reconfigured for SPI use as part of the boot
process.
Master SPI Interface: SCLK1, MOSI1, MISO1, SSB1
Master SPI clock, master-output slave-input, master-input slave-output, and slave-select
signals.
State at reset: In reset, these pins are configured as RGPIO[13:10] functions listed
above.
4.3 System connections
The FXLC95000CL platform offers the choice of connecting to a host processor
through either an I2C or SPI interface. It can also act as a master controller for I2C or
SPI peripherals and analog sensors.
General Description
12 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
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4.3.1 Power supply considerations
An internal circuit powered by VDDA provides the FXLC95000CL with a power-
on-reset signal. For this signal to be properly recognized, it is important that VDD
is powered up before or simultaneously with VDDA.
The voltage potential difference between VDD and VDDA must not exceed ±0.1 V.
The simplest way to accomplish this is to power both pins from the same voltage
source.
When using the same voltage source, some digital noise might reach the analog
section. To prevent this, connect a small inductor or ferrite bead in serial with
both the VDDA and VSSA traces. Additionally, two ceramic capacitors (of
approximately 1 µF, and 100 nF, respectively) can be used to efficiently bypass
the power and ground of both digital and analog supply rails.
VDDIO must rise up before or simultaneously with VDDA/VDD.
4.3.2 General connections and layout recommendations
Provide a low-impedance path from the board power supply to each power pin
(VDD, VDDA, and VDDIO) on the device and from the board ground to each
ground pin (VSS, VSSA, and VSSIO).
The minimum bypass requirement is to place 0.01 – 0.1 μF capacitors positioned
as close as possible to the package supply pins. The recommended bypass
configuration is to place one bypass capacitor on each of the VDD/VSS pairs,
including VDDA/ VSSA. Ceramic and tantalum capacitors tend to provide better
tolerances.
Ensure that capacitor leads, associated printed circuit traces, and vias that connect
to the chip VDD and VSS (GND) pins are as short as possible.
Bypass the power and ground. It is suggested that a high-frequency bypass
capacitor be placed close to and on each power pin. Bulk capacitance also is
suggested, with it evenly distributed around the power and ground planes of the
board.
Take special care to minimize noise levels on the VDDA and VSSA pins. An
isolation circuit consisting of a Ferrite Bead and capacitors is suggested, to ensure
that the voltage supplying the analog input is noise free.
Use separate power planes for VDD and VDDA and separate ground planes for
VSS and VSSA. Connect the separate analog and digital power and ground planes
as close as possible to power supply outputs. If both analog circuit and digital
circuit are powered by the same power supply, it is advisable to connect a small
inductor or ferrite bead in serial with both VDDA and VSSA traces.
General Description
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 13
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It is highly desirable to physically separate analog components from noisy digital
components by ground planes. Do not place an analog trace in parallel with digital
traces. It is also desirable to place an analog ground trace around an analog signal
trace to isolate it from digital traces.
If in-circuit debug capability is desired, provide an interface to the BKGD/MS pin.
Select resistors R2 and R3 in Figure 3 to match requirements stated in the I2C
standard. An example value of 4.7kΩ is appropriate for the configuration shown.
Use the PCB footprint, solder mask, and solder stencil shown in Footprint and
pattern information.
4.3.3 I2C reset considerations
If there is a reset during a slave I2C read transaction, then the slave device state machine
will hang the bus, because it is waiting for the master clock. The host-driven reset signal
provides an external way to reset the I2C state machine.
4.3.4 FXLC95000CL as an intelligent slave
I2C pullup resistors, a ferrite bead, and a few bypass capacitors are all that are required
to attach this device to a host platform. The basic configuration of the I2C interface is
shown in Figure 3.
The voltage level on pin 23 (RGPIO8) selects the slave-port format: I2C or SPI. The
RGPIO pins can also be programmed to generate interrupts to the host platform, in
response to the occurrence of application events. In this case, the pins should be routed
to the external interrupt pins of the host processor.
General Description
14 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
FB
12
R3
4.7 KΩ
R2
4.7 KΩ
R6
1 KΩ
I2C_CLK
I2C_DATA
INT_OUT
1.8V VDDIO
C4
1 µF
C3
0.1 µF
C5
0.1 µF
C6
1 µF
1.8 VVDDIO VDDIO
VDDIO
C1
1 µF
1.8 V
C2
0.1 µF
R1
Notes:
VDD = 1.8V Pn = RGPIOn
VDDA = 1.8V (n from 0 to 15)
VDDIO = 1.71V to 3.6V
Quiet VDDA for best performance.
VDDIO
Manual
reset
push button
C7
(Optional
EMC
filter )
Pin 1
BDM
header
10 KΩ
U1
FXLC95000
1
3
6
4
5
2
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
17
18
RGPIO14 / SCL1
RGPIO15 / SDA1
VSSIO
BKGD / MS / RGPIO9
VDDIO
VDD
RESETB
RGPIO11 / MOSI1
RGPIO10 / SCLK1
RGPIO7 / AN1+ / TPMCH1
RGPIO6 / AN0- / TPMCH0
RGPIO5 / PDB_A / INT_O
RGPIO10 / INT_I
VSS
SCL0 / RGPIO0 /
SCLK
VSS
SDA0 / RGPIO1 /
MOSI
RGPIO3 / SDA1 /
SSB
RGPIO2 / SCL1 /
MISO
VSSA
RGPIO8 / PDB_B
VDDA
RGPIO13 / SSB1
RGPIO12 / MISO1
VDDIO
R7
1 KΩ
Figure 3. FXLC95000CL as a slave (I2C interface)
The basic configuration of the SPI interface is shown in Figure 4. The RGPIO pins
can also be programmed to generate interrupts to the host platform, in response to the
occurrence of application events. In this case, the pins should be routed to the external
interrupt pins of the host processor.
General Description
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 15
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R6
1 KΩ
1.8 VVDDIO VDDIO
R1
10 KΩ
Notes:
VDD = 1.8V Slave interface select
VDDA = 1.8V 1 = I2C
VDDIO = 1.7V to 3.6V 2 = SPI
Quiet VDDA for best performance .
SPI_CLK
SPI_DI (MOSI)
Slave SPI interface
SPI_DO (MISO)
SPI_EN
RESET
U1
FXLC95000
1
3
6
4
5
2
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
17
18
1.8V VDDIO
C4
1 µF
C3
0.1 µF
C5
0.1 µF
C6
1 µF
FB
12
C1
1 µF
1.8 V
C2
0.1 µF
RGPIO14 / SCL1
RGPIO15 / SDA1
VSSIO
BKGD / MS / RGPIO9
VDDIO
VDD
RESETB
RGPIO11 / MOSI1
RGPIO10 / SCLK1
RGPIO7 / AN1+ / TPMCH1
RGPIO6 / AN0- / TPMCH0
RGPIO5 / PDB_A / INT_O
RGPIO10 / INT_I
VSS
SCL0 / RGPIO0 /
SCLK
VSS
SDA0 / RGPIO1 /
MOSI
RGPIO3 / SDA1 /
SSB
RGPIO2 / SCL1 /
MISO
VSSA
RGPIO8 / PDB_B
VDDA
RGPIO13 / SSB1
RGPIO12 / MISO1
VDDIO
R7
1 KΩ
Figure 4. FXLC95000CL as a slave (SPI interface)
4.3.5 FXLC95000CL as a sensor hub
The FXLC95000CL device includes a 32-bit ColdFire V1 CPU associated with an
ample amount of RAM and flash memory, a master I2C and SPI bus, and external
differential analog inputs. These are the key hardware components that transform
FXLC95000CL into an efficient and versatile sensor hub. The FXLC95000CL Xtrinsic
General Description
16 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
Intelligent Sensing Platform can interface and manage almost any type of sensor,
digital or analog, such as pressure sensors, magnetometers, gyroscopes, and humidity
sensors. The system supports external sensors interfacing to FXLC95000CL
concurrently, via a combination of master SPI and master I2C interfaces, and external
differential analog inputs.
Besides FXLC95000CL rich connectivity, the 32-bit core and hardware Multiply
Accumulator (MAC) provide the processing power to collect, manipulate and fuse all
sensors measurement locally and make appropriate decisions to optimize overall
system power consumption.
For example, FXLC95000CL can be programmed to operate effectively as a power
controller for handheld units by enabling the host platform to put itself to sleep, with
confidence that the FXLC95000CL will issue a wake-up request when an external
event requires the host's attention. Figure 5 shows the FXLC95000CL being used in
this sensor hub configuration. Note the simple connections. Only a few bypass
capacitors, a ferrite bead, and pullup resistors for the I2C buses are required.
Slave I2C interface is dedicated to communication with the host processor.
Interrupt output line INT_O can be involved as well.
Master SPI, Master I2C, AN0/AN1 and interrupt input line INT_I are available to
interface a variety of external sensors
General Description
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 17
Freescale Semiconductor, Inc.
Notes:
VDD = 1.8 V Slave interface select
VDDA = 1.8 V 1 = I2C
VDDIO = 1.7 V to 3.6 V 2 = SPI
Quiet VDDA for best performance.
12
R3
4.7 KΩ
R2
4.7 KΩ
R6
1 KΩ
U1
FXLC95000
1
3
6
4
5
2
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
17
1.8 V VDDIO
C4
1 µF
C3
0.1 µF C5
0.1 µF
C6
1 µF
1.8 VVDDIO VDDIO
VDDIO
C1
1 µF
18
C2
0.1 µF
R1
10 KΩ
VDDIO
VDDIO
RESET
Optional
R4
4.7 KΩ R5
4.7
KΩ
Optional
Optional
Optional
Slave I2C interface
Master SPI interface
Master I2C interface
Alternate I2C interface on pins 1 and 2
1.8V
FB
RGPIO14/SCL1
RGPIO15/SDA1
VSSIO
VDDIO
VDD
BKGD/MS/RGPIO9
RESETB
SCL0/RGPIO0/
SCLK
VSS
SDA0/RGPIO1/
MOSI
RGPIO2/SCL1/
MISO
RGPIO3/SDA1/
SSB
VSSA
RGPIO8/
PDB_B
VDDA
RGPIO13/
SSB1
RGPIO12/
MISO1
RGPIO11/MOSI1
RGPIO 10/SCLK1
RGPIO7/AN 1+/TPMCH1
RGPIO6/AN0-/TPMCH0
RGPIO5/PDB_A/INT_O
VSS
RGPIO 10/INT_I
I2C_CLK
I2C_DATA
R7
1 KΩ
VDDIO
Figure 5. FXLC95000CL as a sensor hub (I2C interface)
General Description
18 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
Notes:
VDD = 1.8V Slave interface select
VDDA = 1.8V 1 = I2C
VDDIO = 1.7V to 3.6V 2 = SPI
Quiet VDDA for best performance .
1 2
R6
1 KΩ
U1
FXLC95000
1
3
6
4
5
2
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
17
RGPIO14/SCL1
RGPIO15/SDA1
VSSIO
VDDIO
VDD
BKGD/MS/RGPIO9
RESETB
SCL0/RGPIO0/
SCLK
VSS
SDA0/RGPIO1/
MOSI
RGPIO2/SCL1/
MISO
RGPIO3/SDA1/
SSB
VSSA
RGPIO8/
PDB_B
VDDA
RGPIO13/
SSB1
RGPIO12/
MISO1
RGPIO11/MOSI1
RGPIO10/SCLK1
RGPIO7/AN1+/TPMCH1
RGPIO6/AN0-/TPMCH0
RGPIO5/PDB_A/INT_O
VSS
RGPIO10/INT _I
SPI_CLK
SPI_DI (MOSI)
1.8V VDDIO
C4
1 µF
C3
0.1 µF C5
0.1 µF C6
1 µF
1.8 VVDDIO VDDIO
C1
1 µF
18
1.8V
C2
0.1 µF
R1
10 KΩ
VDDIO
R4
4.7 KΩ
R5
4.7
KΩ
Slave SPI interface
Master SPI interface
Master I2C interface
Alternate I2C interface on pins
1 and 2
Analog input +
Analog input -
SPI_DO (MISO)
SPI_EN
INT_OUT
INT_IN
FB
SPI_CLK
SPI_DO (MOSI)
SPI_DI (MISO)
SPI_SS (Slave Select)
R7
1 KΩ
VDDIO
Figure 6. FXLC95000CL as a sensor hub (SPI interface)
General Description
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 19
Freescale Semiconductor, Inc.
4.4 Sensing direction and output response
Pin 1
Top view Side view
Landscape Right
Xout @ 0g
Yout@ -1g
Zout @ 0g
Gravity
Landscape Left
Xout @ 0g
Yout@ +1g
Zout @ 0g
Portrait Up
Xout @ -1g
Yout@ 0g
Zout @ 0g
Portrait Down
Xout @ +1g
Yout@ 0g
Zout @ 0g
Back
Xout @ 0g
Yout@ 0g
Zout @ -1g
Front
Xout @ 0g
Yout@ 0g
Zout @ +1g
(Top view)
Reference frame for acceleration measurement
XY
Z
Figure 7. Sensing direction and output response
Table 2. ± 1 g field-measured results
g range Full Scale1± 1g1
± 2 g± 32,767 ± 16,384
± 4 g± 32,767 ± 8192
± 8 g± 32,767 ± 4095
1. Measured data in counts (16-bit word) after trimming.
5 Mechanical and Electrical Specifications
This section contains electrical specification tables and reference timing diagrams for
the FXLC95000CL platform, including detailed information on power considerations,
DC/AC electrical characteristics, and AC timing specifications.
Mechanical and Electrical Specifications
20 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
5.1 Definitions
cross-axis sensitivity The proportionality constant that relates a variation of accelerometer output to cross
acceleration. This sensitivity varies with the direction of cross acceleration and is
primarily due to misalignment.
deep-sleep mode The device’s lowest power state, when the system clock is stopped and the device
performs no functions. In this mode, only a few exception events can wake the device.
full range The maximum level of acceleration supported by the accelerometer's output signal,
typically specified in ±g. For example, the output of an accelerometer program in ±2 g
mode will be linear when subjected to accelerations within ±2 g. If the acceleration is
larger than ±2 g, the output will not be linear and may rail.
hardware compensated Sensor modules on this device include hardware correction factors for gain and offset
errors which are calibrated during factory test using a least-squares fit of the raw sensor
data.
nonlinearity A measurement of deviation from perfect sensitivity. Ideally, the relationship between
input and output is linear and described by the sensitivity of the device.
pin group Device pins are clustered into a number of logical pin groupings in order to simplify and
standardize electrical data sheet parameters. Pin groups are defined in Table 6.
sensitivity Describes the gain of the sensor and can be determined by applying a 1 g acceleration
to it, such as the earth's gravitational field. The sensitivity of the sensor can be
determined by subtracting the -1 g acceleration value from the +1 g acceleration value
and dividing by two.
software compensated In addition to the first-order hardware gain and offset calibration features, Freescale
implements advanced, nonlinear calibration functions to improve sensor performance.
warm-up time The time—from the initial application of power—for a sensor to reach specified
performance under specified operating conditions.
zero-g offset Describes the deviation of an actual output signal from the ideal output signal, if no
acceleration is present. The expected ideal output signal, in this case, would be zero. A
deviation from ideal value is called zero-g offset. Offset is, to some extent, a result of
stress on the MEMS sensor and, therefore, the offset can slightly change after
mounting the sensor onto a printed circuit board or exposing it to extensive mechanical
stress.
5.2 Absolute maximum ratings
Absolute maximum ratings are stress ratings only and functional operation at the
maximum ratings is not guaranteed. Stress beyond the limits specified here may affect
device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
Mechanical and Electrical Specifications
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 21
Freescale Semiconductor, Inc.
This device contains circuitry protecting against damage due to high static voltage or
electrical fields. However, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate
logic voltage level (for instance, either VSS or VDD).
Table 3. Absolute maximum ratings
Rating Symbol Condition Minimum Maximum Unit
Digital supply voltage VDD –0.3 2.0 V
Analog supply voltage VDDA –0.3 2.0 V
I/O buffer supply voltage VDDIO –0.1 4.0 V
Voltage difference VDD to VDDA VDDA – VDD –0.1 0.1 V
Voltage difference VSS to VSSA VSSA – VSS –0.1 0.1 V
Input voltage VIn –0.3 VDDIO + 0.3 V
Input/Output pin clamp current IC –20 20 mA
Output voltage range VOUTOD Open-drain mode –0.3 VDDIO + 0.3 V
Storage temperature TSTG –40 +125 °C
Mechanical shock SH 5k g
Drop test DR Drop onto concrete slab 1.8 m
Table 4. ESD and latch-up protection characteristics
Rating Symbol Min Max Unit
Human body model (HBM) VHBM ±2000 V
Machine model (MM) VMM ±200 V
Charge device model (CDM) VCDM ±500 V
Latch-up current at T = 85 °C ILU ±100 mA
Caution
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
Caution
This is an ESD sensitive device, improper handling can cause permanent damage to the part.
Mechanical and Electrical Specifications
22 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
5.3 Operating conditions
Table 5. Nominal operating conditions
Rating Symbol Min Typ Max Unit
Digital supply voltage VDD 1.71 1.8 1.89 V
Analog supply voltage VDDA 1.71 1.8 1.89 V
I/O buffer supply voltage VDDIO 1.71 3.3 3.6 V
Input voltage high VIH 0.7 * VDDIO VDDIO + 0.1 V
Input voltage low VIL VSS – 0.3 0.3 * VDDIO V
Operating temperature TA–40 25 85 °C
5.4 General DC characteristics
Table 6. DC characteristics
Characteristic Symbol Condition(s)1Min Typ Max Unit
Output voltage high
Low drive strength
High drive strength
VOH Pin Groups 1 and 32, 3
ILOAD = –2 mA
ILOAD = –3 mA
VDD – 0.5 V
Output voltage low
Low drive strength
High drive strength
VOL Pin Groups 1 and 32, 3
ILOAD = 2 mA
ILOAD = 3 mA
0.5 V
Total package output low current
Max total IOL for all pins
IOHT 24 mA
Total package output high current
Max total IOH for all pins
IOHT 24 mA
Hi-Z (off state) leakage current |IOZ| Pin Group 3 input
resistors disabled3
VIN = VDD or VSS
0.1 1 μA
Pullup resistor
(Pins RESETB and BKGD/MS)
RPU When enabled 17.5 52.5
Power-on-reset voltage VPOR 1.50 V
Power-on-reset hysteresis VPOR-hys 100 mV
Input pin capacitance CIN 7 pF
Output pin capacitance COUT 7 pF
1. All conditions at nominal supply: VDD = VDDA = 1.8 V and VDDIO = 3.3 V.
2. Pin Group 1 = RESETB.
3. Pin Group 3 = RGPIO[15:0].
Mechanical and Electrical Specifications
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 23
Freescale Semiconductor, Inc.
5.5 Supply current characteristics
Table 7. Supply current characteristics
Characteristic Symbol Condition(s)1Min Typ Max Unit
Supply current in STOPNC mode2IDD-SNC Internal clocks disabled 2 μA
Supply current in STOPSC mode3IDD-SSC Intenal clock in slow
speed mode
15 μA
Supply current in RUN mode4IDD-R Internal clock in fast
mode
5.4 mA
1. All conditions at nominal supply: VDD = VDDA = 1.8 V and VDDIO = 3.3 V.
2. STOPNC: Stop mode, no clock.
3. STOPSC: Stop mode, slow clock.
4. RUN: Normal fast mode. Total current with the analog section active, 16 bits ADC resolution selected, MAC unit used,
and all peripheral clocks enabled.
5.6 Accelerometer transducer mechanical characteristics
Table 8. Accelerometer characteristics
Characteristic Symbol Condition(s)1Min Typ Max Unit
Full range
AFR ±2 g ±2
g±4 g ±4
±8 g ±8
Sensitivity/resolution
(16 bits ADC resolution)
(after trimming)
ASENS ±2 g 0.061 mg/LSB
±4 g 0.122
±8 g 0.244
Zero-g level offset accuracy
(pre-board mount)
OFFPBM ±2 g–100 +100 mg
±4 g
±8 g
Nonlinearity
Best fit straight line
ANL ±2 g ±0.25 % AFR
±4 g ±0.5
±8 g ±1
Sensitivity change versus
temperature
TCSA ±2 g ±0.17 %/°C
Zero-g level change versus
temperature2TCOff ±0.2 mg/°C
Zero-g level offset accuracy
(post-board mount)
OFFBM ±2 g–100 +100 mg
±4 g
±8 g
Output data bandwidth BW ODR/23 Hz
Noise density Noise ±2g, ODR=488Hz,
4xoversampling4 100 µg/sqrt(Hz)
3.12 mg (RMS)
Table continues on the next page...
Mechanical and Electrical Specifications
24 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
Table 8. Accelerometer characteristics (continued)
Characteristic Symbol Condition(s)1Min Typ Max Unit
±8g, ODR=488Hz,
4xoversampling4 120 µg/sqrt(Hz)
3.75 mg (RMS)
Cross-axis sensitivity –5 5 %
1. All conditions at nominal supply: VDD = VDDA = 1.8V and VDDIO = 3.3V.
2. Relative to 25°C.
3. ODR: Output Data Rate or the sampled data rate of the system.
4. Performance specification is with CPU being inactive during sensor data acquisition
5.7 Temperature sensor characteristics
Table 9. Temperature sensor characteristics
Characteristic Symbol Condition(s)1Min Typ Max Unit
Full scale range TFSR –40 +85 °C
Sensitivity TSENS 16 bit data word 0.0025 °C/LSB
Non-linearity TNL ±2.4 % FSR
1. All conditions at nominal supply: VDD = VDDA = 1.8 V and VDDIO = 3.3 V.
5.8 ADC characteristics
Table 10. ADC characteristics
Characteristic Symbol Condition(s)1Min Typ Max Unit
External input voltage VAI Voltage at AN0 or AN1 0.2 1.1 V
External differential input voltage2VADI AN1 – AN0 –0.9 0.9 V
Full-scale range VFS 1.8 V
Programmable resolution RES 10 14 16 bits
Conversion Time @ 14 bits
resolution (three-sample frame,
XYZ)
tc 207 μs
Integral nonlinearity INL Full scale ±15 LSB
Differential nonlinearity DNL ±2 LSB
Input leakage IIA ±2 μA
Total capacitance Cin 7 pF
Series resistance Rin 6
1. All conditions at nominal supply: VDD = VDDA = 1.8 V, VDDIO = 3.3 V, and RES = 14 unless otherwise noted.
2. The external ADC input pins go through a buffer line that is powered by VDDIO. Noise on the VDDIO line degrades the
external ADC signal.
Mechanical and Electrical Specifications
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 25
Freescale Semiconductor, Inc.
5.8.1 ADC Sample Rates
The system clock is 16 MHz with the first sample rate generated by dividing the system
clock by 4096 (16 MHz / 4096 = 3906.25 Hz). Subsequent sample rates are all a
sequence of divide-by-two.
The FXLC95000CL platform's internal frame timer supports the following sample rates
(frames per second (fps)):
3906.25 fps
1953.13 fps
976.56 fps
488.28 fps
244.14 fps
122.07 fps
61.04 fps
30.52 fps
15.26 fps
7.63 fps
3.81 fps
1.91 fps
0.95 fps
0.48 fps
0.24 fps
Notes
At the fastest sampling rate of 3906.25 Hz, there is not
enough time to complete the ADC conversions’ highest-
bit resolution, so only 10-,12-,and 14-bit resolutions are
available at that rate. All of the ADC resolutions (10-,12-,
14-, and 16-bit) are available at all other sample rates.
Freescale's Intelligent Sensor Framework (ISF) uses the
software-triggered sample mode, using the MTIM16
timer to set the sample period. This allows the
specification of sample periods to microsecond
resolution.
Mechanical and Electrical Specifications
26 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
5.9 AC electrical characteristics
Tests are conducted using the input levels specified in Table 5. Unless otherwise
specified, propagation delays are measured from one 50% point to the next 50% point,
and rise and fall times are measured between the 10% and 90% points, as shown in
Figure 8.
Figure 8. Input signal measurement references
Figure 9 shows the definitions of the following signal states:
Data Active state, when a bus or signal is driven, and enters a low impedance
state
Data Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
Data Invalid state, when a signal level is in transition between VOL and VOH
Figure 9. Signal states
5.10 General timing control
Table 11. General timing characteristics
Characteristic Symbol Condition(s)1Min Typ Max Unit
VDD rise time Trvdd 10% to 90% 1 ms
POR release delay2TPOR Power-up 0.35 1.5 ms
Table continues on the next page...
Mechanical and Electrical Specifications
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 27
Freescale Semiconductor, Inc.
Table 11. General timing characteristics (continued)
Characteristic Symbol Condition(s)1Min Typ Max Unit
Warm-up time TWU From STOP with No Clock 7 sample
periods
Frequency of operation FOPH Full-speed clock 16 MHz
FOPL Slow-speed clock 62.5 KHz
System clock period tCYCH Full-speed clock 62.5 ns
tCYCL Slow-speed clock 16 μs
Full/Slow clock ratio 256
Oscillator frequency absolute
accuracy @ 25°C
Full-speed clock –5 +5 %
Oscillator frequency variation over
temperature
(–40°C to 85°C vs. ambient)
Slow-speed clock –6 +6 %
Minimum RESET Assertion
Duration
tRA 4T3———
1. All conditions at nominal supply: VDD = VDDA = 1.8 V and VDDIO = 3.3 V.
2. Time measured from VDD = VPOR until the internal reset signal is released.
3. T = Period of one system clock cycle. In full-speed mode, T is nominally 62.5 ns. In slow-speed mode, T is
nominally 16 μs.
5.11 Interfaces
The FXLC95000CL may be controlled via its included slave I2C module that can be
active 100% of the time. The FXLC95000 also includes a master I2C that should be
used only when the system clock is running at full speed. The master interface is
intended to be used to communicate with other, external sensors.
Figure 10. I2C standard and fast-mode timing
Mechanical and Electrical Specifications
28 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.
5.11.1 Slave I2C
Table 12. I2C speed ranges
Mode Max Baud
Rate
(fSCL)
Minimum
Bit Time
Minimum SCL
Low
(tLOW)
Minimum SCL
High
(tHIGH)
Min Data Set-
up Time
(tSU; DAT)
Min/Max Data Hold
Time
(tHD; DAT)
Standard 100 KHz 10 μs 4.7 μs 4 μs 250 ns 0 μs/3.45 μs1
Fast 400 KHz 2.5 μs 1.3 μs 0.6 μs 100 ns 0 μs/0.9 μs1
Fast + 1 MHz 1 μs 500 ns 260 ns 50 ns 0 μs/0.45 μs1
High-speed
supported
2.0 MHz 0.5 μs 200 ns 200 ns 10 ns 0 ns/70 ns (100 pf)2
1. The maximum tHD;DAT must be at least a transmission time less than tVD;DAT or tVD;ACK. For details, see the I2C
standard.
2. Timing met with IFE = 0, DS = 1, and SE = 1. For more information, refer to Port Control Registers in the
FXLC95000CL Hardware Reference Manual.
5.11.2 Master I2C Timing
The master I2C should only be used when the system clock is running at full speed.
Do not attempt to use the master I2C across frames in which a portion of the time is
spent in low-speed mode.
Table 13. Master I2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Min Max Min Max
SCL clock frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition. After
this period, the first clock pulse is generated.
tHD; STA 4.0 0.6 μs
LOW period of the SCL clock tLOW 4.7 1.3 μs
HIGH period of the SCL clock tHIGH 4.0 0.6 μs
Set-up time for a repeated START condition tSU; STA 4.7 0.6 μs
Data Hold Time for I2C bus devices tHD; DAT 013.452010.92μs
Data set-up time tSU; DAT 250 1003, 4 ns
Set-up time for STOP condition tSU; STO 4.0 0.6 μs
Bus free time between STOP and START
condition
tBUF 4.7 1.3 μs
Pulse width of spikes that must be suppressed
by the input filter
tSP N/A N/A 0 50 μs
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
Mechanical and Electrical Specifications
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. 29
Freescale Semiconductor, Inc.