CY2XP304
Document #: 38-07589 Rev. *D Page 2 of 11
CY2XP304 Two-Wire Serial Interface
Introduction
The CY2XP304 has a two-wire serial interface designed for
data transfer operations, and is used for programming the P
and Q values for frequency generation. Sclk is the serial clock
line controlled by the master device. Sdata is a serial bidirec-
tional data line. The CY2XP304 is a slave device and can
either read or write information on the dataline upon request
from the master device.
Figure 1 shows the basic bus connections between master
and slave device. The buses are shared by a number of
devices and are pulled HIGH by a pull-up resistor.
Serial Interface Specifications
Figure 2 shows the basic transmission specification. To begin
and end a transmissio n, the master device generates a start
signal (S) and a stop signal (P). Start (S) is defined as
switching the Sdata from HIGH to LOW while the Sclk is at
HIGH. Similarly , stop (P) is defined as switching the Sdata from
LOW to HIGH while holding the Sclk HIGH. Between these two
signals, data on Sdata is synchronous with the clock on the Sclk.
Data is allowed to change only at LOW period of clock, and
must be stable at the HIGH period of clock. To acknowledge,
drive the Sdata LOW before the Sclk rising edge and hold it
LOW until the Sclk falling edge.
Serial Interface Format
Each slave carries an address. The data transfer is initiated by
a start signal (S). Each transfer segment is one byte in length.
The slave address and the read/write bit are first sent from the
master device after the start signal. The addressed slave
device must acknowledge (Ack) the master device. Depending
on the Read/Write bit, the master device will either write d ata
into (logic 0) or read data (logic 1) from the slave device. Each
time a byte of data is successfully transferred, the receiving
device must acknowledge. At the end of the transfer, the
master device will generate a stop si gnal (P).
Serial Interface Transfer Format
Figure 2 shows the serial interface transfer format used with
the CY2XP304. T wo dummy bytes must be transferred before
the first data byte. The CY2XP304 has only three bytes of
latches to store information, and the third byte of data is
reserved. Extra data will be ignored.
Pin Definitions
Pin # Pin Name Pin Description
A1,B1,G3,G4 VDDB 3.3V Power Supply for Crys tal Driver
A2 XIN Reference Crystal Input
A3 XOUT Reference Crystal Feedback
A4,B2,C1,C3,C4,F3,F4,G2,G5,B5 GND Ground
A5,H1,H2,H4,H5 VDDA 3.3V Power Supply
A6 CLK0 LVPECL Clock Output
B6 CLK0B LVPECL Clock Output (Complement)
C6 CLK1 LVPECL Clock Output
D6 CLK1B LVPECL Clock Output (Complement)
E6 CLK2 LVPECL Clock Output
F6 CLK2B LVPECL Clock Output (Complement)
G6 CLK3 LVPECL Clock Output
H6 CLK3B LVPECL Clock Output (Complement)
B3 SER_CLK Serial Interface Clock
B4 SER_DATA Serial Interface Data
D1 PLL_MULT PLL Multiplier Select Input, Inte rnal pull-up resistor, see Frequ ency Table
E1 CLK_SEL Clock Select Input, Internal Pull down. HIGH select INA/INAB, Internal PLL
is bypassed. LOW select internal PLL
F1,G1 INA,INAB Differential Clock Input pair, used in PLL-bypassed mode
H3 NC No Connect
Frequency Table
PLL_Mult M (PLL Multiplier) Example Input Crystal Frequency CLK[0:3],CLKB[0:3]
0 x16 25 MHz 400 MHz
31.25 MHz 500 MHz
1 x8 15.625 MHz 125 MHz