CY2XP304BVXC - Cypress Semiconductor Corp.

High-Frequency Programmable PECL

Clock Generation Module

CY2XP304

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-07589 Rev. *D Revised October 27, 2005

Features

• 40 ps typical peak-peak period jitter at 125 MHz

• 30 ps typical output-output skew at 400 MHz

• Four low-skew LVPECL outputs

• Phase-locked loop (PLL) multiplier select

• Serially-configurable multiply ratios

• Eight-bit feedback counter and six-bit reference

counter for high accuracy

• HSTL inputs—HSTL-to-LVPECL level translation

• 125- to 500-MHz output range for high-speed

applications

• High-speed PLL bypass mode to 1.5 GHz

• 36-VFBGA , 6 × 8 × 1 mm

• 3.3V oper ation

Block Diagram

Pin Configuration

INA

INAB

CLK0

CLK0B

CLK1

CLK1B

CLK2

CLK2B

CLK3

CLK3B

CLK_SEL

XTAL

OSCILLATOR PLL

XIN

XOUT

SER CLK

SER DATA

PLL_MULT

5TOP VIEW

ABCDE FGH

CY2X P304 36 V FBG A P IN CO NFIGURAT IO N TO P VIEW

CLK0

VDDA

GND

Xout

Xin

VDDB

CLK0B

GND

SER_D

ATA

SER_CL

GND

VDDB

CLK1

GND

CLK1B

PLL_MU

CLK2

CLK_SE

CLK2B

GND

INA

CLK3

GND

VDDB

GND

IN A B

CLK3B

VDDA

CY2XP304

Document #: 38-07589 Rev. *D Page 2 of 11

CY2XP304 Two-Wire Serial Interface

Introduction

The CY2XP304 has a two-wire serial interface designed for

data transfer operations, and is used for programming the P

and Q values for frequency generation. Sclk is the serial clock

line controlled by the master device. Sdata is a serial bidirec-

tional data line. The CY2XP304 is a slave device and can

either read or write information on the dataline upon request

from the master device.

Figure 1 shows the basic bus connections between master

and slave device. The buses are shared by a number of

devices and are pulled HIGH by a pull-up resistor.

Serial Interface Specifications

Figure 2 shows the basic transmission specification. To begin

and end a transmissio n, the master device generates a start

signal (S) and a stop signal (P). Start (S) is defined as

switching the Sdata from HIGH to LOW while the Sclk is at

HIGH. Similarly , stop (P) is defined as switching the Sdata from

LOW to HIGH while holding the Sclk HIGH. Between these two

signals, data on Sdata is synchronous with the clock on the Sclk.

Data is allowed to change only at LOW period of clock, and

must be stable at the HIGH period of clock. To acknowledge,

drive the Sdata LOW before the Sclk rising edge and hold it

LOW until the Sclk falling edge.

Serial Interface Format

Each slave carries an address. The data transfer is initiated by

a start signal (S). Each transfer segment is one byte in length.

The slave address and the read/write bit are first sent from the

master device after the start signal. The addressed slave

device must acknowledge (Ack) the master device. Depending

on the Read/Write bit, the master device will either write d ata

into (logic 0) or read data (logic 1) from the slave device. Each

time a byte of data is successfully transferred, the receiving

device must acknowledge. At the end of the transfer, the

master device will generate a stop si gnal (P).

Serial Interface Transfer Format

Figure 2 shows the serial interface transfer format used with

the CY2XP304. T wo dummy bytes must be transferred before

the first data byte. The CY2XP304 has only three bytes of

latches to store information, and the third byte of data is

reserved. Extra data will be ignored.

Pin Definitions

Pin # Pin Name Pin Description

A1,B1,G3,G4 VDDB 3.3V Power Supply for Crys tal Driver

A2 XIN Reference Crystal Input

A3 XOUT Reference Crystal Feedback

A4,B2,C1,C3,C4,F3,F4,G2,G5,B5 GND Ground

A5,H1,H2,H4,H5 VDDA 3.3V Power Supply

A6 CLK0 LVPECL Clock Output

B6 CLK0B LVPECL Clock Output (Complement)

C6 CLK1 LVPECL Clock Output

D6 CLK1B LVPECL Clock Output (Complement)

E6 CLK2 LVPECL Clock Output

F6 CLK2B LVPECL Clock Output (Complement)

G6 CLK3 LVPECL Clock Output

H6 CLK3B LVPECL Clock Output (Complement)

B3 SER_CLK Serial Interface Clock

B4 SER_DATA Serial Interface Data

D1 PLL_MULT PLL Multiplier Select Input, Inte rnal pull-up resistor, see Frequ ency Table

E1 CLK_SEL Clock Select Input, Internal Pull down. HIGH select INA/INAB, Internal PLL

is bypassed. LOW select internal PLL

F1,G1 INA,INAB Differential Clock Input pair, used in PLL-bypassed mode

H3 NC No Connect

Frequency Table

PLL_Mult M (PLL Multiplier) Example Input Crystal Frequency CLK[0:3],CLKB[0:3]

0 x16 25 MHz 400 MHz

31.25 MHz 500 MHz

1 x8 15.625 MHz 125 MHz

CY2XP304

Document #: 38-07589 Rev. *D Page 3 of 11

To program the CY2XP304 using the two-wire serial interface,

set the SELPQ bit HIGH. The default setting of this bit is LOW .

The P and Q values are determined by the following formulas:

Pfinal = (P7..0 + 3) * 2

Qfinal = Q5..0 + 2

If the QCNTBYP bit is set HIGH, then Qfinal defaults to a value

of 1. The default setting of this bit is LOW.

If the SELPQ bit is set LOW, the PLL multipliers will be set

using the values in the Select Function Table.

CyberClocks™ has been developed to generate P and Q

values for stable PLL operation. This software is downloadable

from www.cypress.com.

Figure 1. Device Connections

Figure 2. Serial Interface Specifications

Figure 3. CY2XP304 Tra nsfe r Format

Serial Interface Address for the CY2XP304

A6 A5 A4 A3 A2 A1 A0 R/W

11001010

Serial Interface Programming for the CY2XP304

b7 b6 b5 b4 b3 b2 b1 b0

Data0 QCNTBYP SELPQ Q<5> Q<4> Q<3> Q<2> Q<1> Q<0>

Data1P<7>P<6>P<5>P<4>P<3>P<2>P<1>P<0>

Data2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Sclk

Sdata

Sclk_C

Sclk_in

Sdata_C

Sdata_in

M aster D evice

Sclk_in

Sdata_C

Sdata_in

S lav e D evice

VDD

Start (S) Stop (P )

Sclk

Sdata

valid data Acknowledge

Ack

1 bit8 bits

Data 1 P

Slave Address AckSDummy Byte 0

R/W Dummy Byte 1 Ack

1 bit 1 bit

Ack

1 bit7 bits 8 bits1 bit

Data 0 Ack

1 bit8 bits1 bit8 b its

CY2XP304

Document #: 38-07589 Rev. *D Page 4 of 11

PLL Frequency = Reference x P/Q = Output

Functional Specifications

Crystal Input

The CY2XP304 receives its reference from an external crystal.

Pin XIN is the reference crystal input, and pin XOUT is the

reference crystal feedback. The parameters for the crystal are

given on page 5 of this data sheet. The oscillator circuit

requires external capacitors. Please refer to the application

note entitled Crystal Oscillator Topics for details.

Select Input

There are two select input pins, the PLL_MUL T and CLK_SEL.

PLL_MUL T pin selects the frequency multiplier in the PLL, and

is a standard LVCMOS input. The S pin has an internal pull-up

resistor . The multiplier selection is given on page 2 of this data

sheet (see Frequency Table).

State Transition Characteristics

Specifies the maximum settling time of the CLK and CLKB

outputs from device power-up. For VDD and VDDX any

sequences are allowed to power-up and power-down the

CY2XP304.

Reference

PLL

VCO

Output

Figure 4. PLL Block Diagram

State Transition Characteristics

From To Transition

Latency Description

VDD/VDDX

On CLK/CLK

B Normal 3 ms Time from VDD/VDDX is

applied and settled to

CLK/CLKB outputs

settled.

CY2XP304

Document #: 38-07589 Rev. *D Page 5 of 11

Crystal Requirements

Requirements to use parallel mode fundamental xtal. External

capacitors are required in the crystal oscillator circuit. Please

refer to the application note entitled Crystal Oscillator Topics

for details.

Note:

1. Where VCC is 3.3V±5%.

Absolute Maximum Conditions

Parameter Description Condition Min. Max. Unit

VCC Supply Voltage Non-functional –0.3 4.6 V

VCC Operating Voltage Functional 3.135 3.465 V

VTT Output Termination Voltage Relative to VCC[1] VCC – 2 V

VIN Input Voltage Relative to VCC[1] –0.3 VCC + 0.3 V

VOUT Output Voltage Relative to VCC[1] –0.3 VCC + 0.3 V

LUILatch Up Immunity Functional 100 mA

TSTemperature, Stor age Non-functional –65 +150 °C

TATemperature, Operating Ambient Functional –40 +85 °C

TJTemperature, Junction Non-functional – 150 °C

ØJc Dissipation, Junction to Case Functional 11.38 °C/W

ØJa Dissipation, Junction to Ambient Functional 85.83 °C/W

ESDhESD Protection (Human Body Model) 2000 V

MSL Moisture Sensitivity Level 3 N.A.

GATES Total Functional Gate Count Assembled die 50 Ea.

Crystal Requirements

Parameter Description Min. Max. Unit

XFFrequency 10 31.25 MHz

DC Electrical Specifications

Parameter Description Min. Max. Unit

VDD Supply voltage 3.135 3.465 V

VIL Input signal low voltage at pin PLL_MULT – 0.35 V

VIH Input signal high voltage at pin PLL_MULT 0.65 – V

RPUP Internal pull-up resistance 10 100 kΩ

tPU Power-up time for all VDDs to reach minimum specified voltage

(power ramps must be monotonic) 0.05 500 ms

Operating Conditions

Parameter Description Min. Max. Unit

TACommercial Temperature 0 70 °C

Industrial Temperature –40 85 °C

CY2XP304

Document #: 38-07589 Rev. *D Page 6 of 11

DC Specifications (VCC = 3.3 V ± 5%, Commercial and Industrial temp.)

Parameter Description Condition Min. Max. Unit

Clock Input Pair INA, INAB (HSTL differential signals)

VDIF HSTL Differential Input Voltage[2] 0.4 1.9 V

VXHSTL Differential Crosspoint

Voltage[3] 0.68 0.9 V

IIN Input Current VIN = VX ± 0.2V |150| µA

PECL Outputs CLK[0:3], CLK[0:3]B (PECL differential signals)

VOL Output Low Voltage

VCC = 3.3V ± 5% IOL = –5 mA[4] VCC – 1.995 VCC – 1.5 V

VOH Output High Voltage IOH = –30 mA[4] VCC – 1.25 VCC – 0.7 V

Supply Current and VBB

IEE Maximum Quiescent Supply Current

without Output Termination Current 150 mA

CIN Input Pin Capacitance INA, INAB 3 pF

LIN Pin Inductance 1nH

AC Electrical SpecificationsÐInput

Parameter Description Min. Max. Unit

fIN Input frequency with driven reference, crystal inputs 1 133 MHz

fXTAL,IN Input frequency with crystal input 10 31.25 MHz

fINA_IN Input Frequency with INA/INAB inputs 0 1500 MHz

CIN,CMOS Input capacitance at PLL_MULT pin[5] –10pF

AC SpecificationsÐPECL Clock Outpu ts CLK[0:3] , CL K[0:3]B

Parameter Description Conditions Min. Typ. Max. Unit

fOOutput Frequency CLK_SEL = 0 125 – 500 MHz

CLK_SEL = 1 0 – 1500 MHz

Vo(P-P) Differential output voltage

(peak-to-peak) fO < 1GHz 0.375 – – V

VCMRO Output Common V o ltage Range VCC – 1.425 V

tsk(O) Output-to-output skew 400-MHz 50% duty cycle Standard load

Differential Operation –3050ps

tsk(PP) Part-to-part output skew 400-MHz 50% duty cycle Standard load

Differential Operation ––150ps

TR,TFOutput Rise / Fall time 400-MHz 50% duty cycle Differential 20%

to 80% ––0.3ns

DC Long-term average output duty

cycle 45–55%

tDC,ERR Cycle-cycle duty cycle error at x8

with 15.625-MHz input ––70ps

Phase

Noise Phase Noise at 10 kHz (x8

mode) @ 125 MHz –107 – –92 dBc

BWLOOP PLL Loop Bandwidth 50 kHz

(–3dB)

Notes:

2. VDIF (DC) is the amplit ude of the differential HSTL input volt age swing required for device functionality.

3. VX (DC) is the crosspoint of the dif ferential HSTL input signal. Functional operations is obt ained when the crosspoint is within the VX (DC) range and the inp ut

swing lies within the VDIF (DC) specification.

4. Equivalent to a termination of 50Ω to VTT.

5. Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV.

CY2XP304

Document #: 38-07589 Rev. *D Page 7 of 11

tJCRMS Cycle-to-cycle RMS jitter At 125-MHz frequency – 12.1 15 ps

At 400-MHz frequency – 8.2 10 ps

At 500-MHz frequency – 9.7 12 ps

tJCPK Cycle-to-cycle jitter (pk-pk) At 125-MHz frequency – 72 95 ps

At 200-MHz frequency, XF = 25 MHz – 50 65 p s

At 400-MHz frequency – 40 55 ps

At 500-MHz frequency – 50 65 ps

tJPRMS Period jitter RMS At 125-MHz frequency – 5.7 6.8 ps

At 400-MHz frequency – 4.5 5.6 ps

At 500-MHz frequency – 5.6 6.8 ps

tJPPK Period jitter (pk-pk) At 125-MHz frequency – 4.0 55 ps

At 200-MHz frequency, XF = 25 MHz – 38 50 p s

At 400-MHz frequency – 34 45 ps

At 500-MHz frequency – 39 50 ps

tJLT Long term RMS Jitter (P < 20) At 125-MHz frequency – – 25 ps

At 400-MHz frequency – – 20 ps

At 500-MHz frequency – – 25 ps

tJLT Long term RMS Jitter (20 < P < 40) At 125-MHz frequency – – 55 p s

At 400-MHz frequency – – 65 ps

At 500-MHz frequency – – 55 ps

tJLT Long-term RMS Jitter (40 < P < 60) At 125-MHz frequency – – 70 p s

At 400-MHz frequency – – 90 ps

At 500-MHz frequency – – 65 ps

AC Electrical SpecificationsÐPECL Clock Outputs: PLL Bypass Mode

Parameter Description Conditions Min Max Unit

Vo(P-P) Differential output voltage (peak-to-peak) Differential PRBS

fo < 1.0 GHz 0.375 – V

JPPeriod Jitter 660 MHz 50% duty cycle

Standard load – 1.3 ps r.m.s.

TPD Propagation delay (INA/INAB to output) PECL, 660MHz 280 650 ps

HSTL, <1 GHz 280 750 ps

AC SpecificationsÐPECL Clock Outpu ts CLK[0:3] , CL K[0:3]B (continu ed )

Parameter Description Conditions Min. Typ. Max. Unit

tr, tf,

20-80% VO

Figure 5. ECL/LVPECL Output

CY2XP304

Document #: 38-07589 Rev. *D Page 8 of 11

Jitter

This section defines the specifications that relate to timing

uncertainty (or jitter) of the input and output waveforms.

Figure 6 shows the definition of period jitter with respect to the

falling edge of the CLK signal. Period jitter is the difference

between the minimum and maximum cycle times over many

cycles (typically 12800 cycles at 400 MHz). Equal require-

ments apply for rising edges of the CLK signal. t JP is defined

as the output period jitter.

Figure 7 shows the definition of cycle-to-cycle jitter with

respect to the falling edge of the CLK signal. Cycle-to-cycle

jitter is the difference between cycle times of adjacent cycles

over many cycles (typi cally 12800 cycles at 4 00 MHz). Equal

requirements apply for rising edges of the CLK signal. tJC is

defined as the clock output cycle-to-cycle jitter.

Figure 8 shows the definition of cycle-to-cycle duty cycle error .

Cycle-to-cycle duty cycle error is defined as the difference

between high-times of adjacent cycles over many cycles

(typically 12800 cycles at 400 MHz). Equal requirements apply

to the low-times. tDC,ERR is defined as the clock output

cycle-to-cycle duty cycle error.

Figure 9 shows the definition of long-term jitter error.

Long-term jitter is defined as the accumulated timing error over

many cycles (typically 12800 cycles at 400 MHz). It applies to

both rising and falling edge s. tJLT is define d as the long-term

jitter.

tCYCLE

tJP = tCYCLE,max – tCYCLE, min. over many cycles

CLK

CLKB

Figure 6. Period Jitter

tCYCLE,i

tJC = tCYLCE,i – tCYCLE,i+1 over many consecutive cycles

CLK

CLKB

tCYCLE, i+1

Figure 7. Cycle-to-cycle Jitter

tPW+,i

tDC,ERR = tPW+,i – tPW+,i+1 over many consecutive cycles

CLK

CLKB

tPW+,i+1

tCYCLE,i+1 tCYCLE, i+1

Cycle i Cycle i+1

Figure 8. Cycle-to-cycle Duty Cycle Error

tJLT = tmax – tmin over many cycles

CLK

CLKB

tmin

tmax

Figure 9. Long-term Jitter

CY2XP304

Document #: 38-07589 Rev. *D Page 9 of 11

Test Configurations

Standard test load using a differential pulse generator and

differential measurement instrument.

Applications Information

Termination Examples

OSC PLL

Pulse

Generator

Z = 50 ohm Zo = 50 ohm

VTT

Zo = 50 ohm

VTT

RT = 50 ohm

CLK_SEL

XTAL

DUT

Figure 10. CY2XP304 AC Test Reference

Clock

XTAL

1.3 V

Zo = 50 ohm

1.3 V

RT = 50 ohm

VC C = 3.3V

VEE = 0V

Figure 11. St andard LVPECL–PECL Output Termination

3.3 V

Zo = 50 ohm

3.3 V

120 ohm

VCC =3.3 V

VEE = 0V

LVDS

51 ohm

(2 places)

33 ohm

(2 places)

LVPECL to

LVDS

Clock

XTAL

Figure 12. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) to a Low-voltage Differential

Signaling (LVDS) Interface

CY2XP304

Document #: 38-07589 Rev. *D Page 10 of 11

© Cypress Semi con duct or Cor po rati on , 20 05 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no resp onsibility f or the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Package Drawing and Dimensions

CyberClocks is a trademark of Cypress Semiconductor . All product and company names mentioned in this document may be the

trademarks of their respective holders.

Ordering Information

Ordering Code Package Type Operating Range Operating Voltage

CY2XP304BVC 36-lead VFBGA Commercial, to 400 MHz 3.3V

CY2XP304BVCT 36-lead VFBGA – Tape and Reel Commercial, to 400 MHz 3.3V

CY2XP304BVI 36-lead VFBGA Industrial, to 400 MHz 3.3V

CY2XP304BVIT 36-lead VFBGA – Tape and Reel Industrial, to 400 MHz 3.3V

Lead-free

CY2XP304BVXC 36-lead VFBGA Commercial, to 400 MHz 3.3V

CY2XP304BVXCT 36-lead VFBGA – Tape and Reel Commercial, to 400 MHz 3.3V

CY2XP304BVXI 36-lead VFBGA Industrial, to 400 MHz 3.3V

CY2XP304BVXIT 36-lead VFBGA – Tape and Reel Industrial, to 400 MHz 3.3V

A1 CORNER

0.75

Ø0.30±0.05(36X)

Ø0.25 M C A B

Ø0.05 M C

0.15(4X)

0.21±0.05

1.00 MAX

SEATING PLANE

0.55 MAX.

0.25 C

0.10 C

A1 CORNER

TOP VIEW BOTTOM VIEW

234

3.75

5.25

465231

6.00±0.10

8.00±0.10

6.00±0.10

1.875

2.625

0.26 MAX.

36-Lead VFBGA (6 x 8 x 1 mm) BV36A

51-85149-*C

CY2XP304

Document #: 38-07589 Rev. *D Page 11 of 11

Document History Page

Document Title: CY2XP304 High-Frequency Programmable PECL Clock Generation Module

Document Number: 38-07589

REV. ECN NO. Issue Date Orig. of

Change Description of Cha ng e

** 129898 12/02/03 RGL New Data Sheet

*A 235868 See ECN RGL Updated Jitter spec based on the characterization report

*B 247601 See ECN RGL/GGK Changed VOH and VOL to match the Char Data

*C 300320 See ECN RGL Minor Change: Re-phrased the first bullet in the features

*D 413407 See ECN RGL Added Lead-free devices

Added typical Values