LTC6804-1/LTC6804-2 Multicell Battery Monitors Features Description Measures Up to 12 Battery Cells in Series nn Stackable Architecture Supports 100s of Cells nn Built-In isoSPITM Interface: 1Mbps Isolated Serial Communications Uses a Single Twisted Pair, Up to 100 Meters Low EMI Susceptibility and Emissions nn 1.2mV Maximum Total Measurement Error nn 290s to Measure All Cells in a System nn Synchronized Voltage and Current Measurement nn 16-Bit Delta-Sigma ADC with Frequency Programmable 3rd Order Noise Filter nn Engineered for ISO26262 Compliant Systems nn Passive Cell Balancing with Programmable Timer nn 5 General Purpose Digital I/O or Analog Inputs: Temperature or other Sensor Inputs Configurable as an I2C or SPI Master nn 4A Sleep Mode Supply Current nn 48-Lead SSOP Package The LTC(R)6804 is a 3rd generation multicell battery stack monitor that measures up to 12 series connected battery cells with a total measurement error of less than 1.2mV. The cell measurement range of 0V to 5V makes the LTC6804 suitable for most battery chemistries. All 12 cell voltages can be captured in 290s, and lower data acquisition rates can be selected for high noise reduction. nn Multiple LTC6804 devices can be connected in series, permitting simultaneous cell monitoring of long, high voltage battery strings. Each LTC6804 has an isoSPI interface for high speed, RF-immune, local area communications. Using the LTC6804-1, multiple devices are connected in a daisy-chain with one host processor connection for all devices. Using the LTC6804-2, multiple devices are connected in parallel to the host processor, with each device individually addressed. Additional features include passive balancing for each cell, an onboard 5V regulator, and 5 general purpose I/O lines. In sleep mode, current consumption is reduced to 4A. The LTC6804 can be powered directly from the battery, or from an isolated supply. Applications Electric and Hybrid Electric Vehicles Backup Battery Systems nn Grid Energy Storage nn High Power Portable Equipment nn nn L, LT, LTC, LTM, Linear Technology and the Linear logo are registered and isoSPI is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. patents, including 8908799, 9182428, 9270133. Typical Application + 2.0 1.5 IMA + + * * IPB LTC6804-1 IMB IPA IMA + IPB LTC6804-1 IMB IPA CELL VOLTAGE = 3.3V 5 TYPICAL UNITS 1.0 0.5 0 -0.5 -1.0 -1.5 * * MPU SPI * * + MEASUREMENT ERROR (mV) 12S1P Total Measurement Error vs Temperature of 5 Typical Units IPB LTC6804-1 IMB ILP IPA * * + -2.0 -50 -25 75 50 25 TEMPERATURE (C) 0 100 125 680412 TA01b IP LTC6820 IMA IM 680412 TA01a For more information www.linear.com/LTC6804-1 680412fc 1 LTC6804-1/LTC6804-2 Table of Contents Features...................................................... 1 Applications................................................. 1 Typical Application ......................................... 1 Description.................................................. 1 Absolute Maximum Ratings............................... 3 Pin Configuration........................................... 3 Order Information........................................... 4 Electrical Characteristics.................................. 4 Pin Functions............................................... 17 Block Diagram.............................................. 18 Operation................................................... 20 State Diagram..........................................................20 LTC6804 Core State Descriptions............................20 isoSPI State Descriptions........................................ 21 Power Consumption................................................ 21 ADC Operation......................................................... 21 Data Acquisition System Diagnostics......................26 Watchdog and Software Discharge Timer...............30 I2C/SPI Master on LTC6804 Using GPIOS............... 31 Serial Interface Overview.........................................35 4-Wire Serial Peripheral Interface (SPI) Physical Layer.........................................................36 2-Wire Isolated Interface (isoSPI) Physical Layer....36 2 Data Link Layer........................................................44 Network Layer.........................................................44 Programming Examples..........................................54 Simple Linear Regulator..........................................58 Improved Regulator Power Efficiency......................58 Fully Isolated Power................................................. 59 Reading External Temperature Probes..................... 59 Expanding the Number of Auxiliary Measurements.........................................................60 Internal Protection Features.....................................60 Filtering of Cell and GPIO Inputs..............................60 Cell Balancing with Internal Mosfets........................62 Cell Balancing with External MOSFETS................... 62 Discharge Control During Cell Measurements.........62 Power Dissipation and Thermal Shutdown..............63 Method to Verify Balancing Circuitry.......................63 Current Measurement with a Hall Effect Sensor......66 Current Measurement with a Shunt Resistor...........66 Using the LTC6804 with Less Than 12 Cells............ 67 Package Description...................................... 76 Revision History........................................... 77 Typical Application........................................ 78 Related Parts............................................... 78 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Absolute Maximum Ratings (Note 1) Total Supply Voltage V+ to V-.....................................75V Input Voltage (Relative to V-) C0.......................................................... -0.3V to 0.3V C12......................................................... -0.3V to 75V C(n)......................................-0.3V to MIN (8 * n, 75V) S(n)......................................-0.3V to MIN (8 * n, 75V) IPA, IMA, IPB, IMB .....................-0.3V to VREG + 0.3V DRIVE Pin................................................. -0.3V to 7V All Other Pins............................................ -0.3V to 6V Voltage Between Inputs V+ to C12.............................................................-5.5V C(n) to C(n - 1)......................................... -0.3V to 8V S(n) to C(n - 1)......................................... -0.3V to 8V C12 to C8................................................ -0.3V to 25V C8 to C4.................................................. -0.3V to 25V C4 to C0.................................................. -0.3V to 25V Current In/Out of Pins All Pins Except VREG, IPA, IMA, IPB, IMB, S(n)...10mA IPA, IMA, IPB, IMB..............................................30mA Operating Temperature Range LTC6804I..............................................-40C to 85C LTC6804H........................................... -40C to 125C Specified Temperature Range LTC6804I..............................................-40C to 85C LTC6804H........................................... -40C to 125C Junction Temperature............................................ 150C Storage Temperature.............................. -65C to 150C Lead Temperature (Soldering, 10sec).................... 300C Pin Configuration LTC6804-1 LTC6804-2 TOP VIEW V+ 1 C12 2 S12 TOP VIEW 48 IPB V+ 1 48 A3 47 IMB C12 2 47 A2 3 46 ICMP S12 3 46 A1 C11 4 45 IBIAS C11 4 45 A0 S11 5 44 SDO (NC)* S11 5 44 SDO (IBIAS)* C10 6 43 SDI (NC)* C10 6 43 SDI (ICMP)* S10 7 42 SCK (IPA)* S10 7 42 SCK (IPA)* C9 8 41 CSB (IMA)* C9 8 41 CSB (IMA)* S9 9 40 ISOMD S9 9 40 ISOMD C8 10 39 WDT C8 10 39 WDT S8 11 38 DRIVE S8 11 38 DRIVE C7 12 37 VREG C7 12 37 VREG S7 13 36 SWTEN S7 13 36 SWTEN C6 14 35 VREF1 C6 14 35 VREF1 S6 15 34 VREF2 S6 15 34 VREF2 C5 16 33 GPIO5 C5 16 33 GPIO5 S5 17 32 GPIO4 S5 17 32 GPIO4 C4 18 31 V- C4 18 31 V- S4 19 30 V-** 29 GPIO3 S4 19 30 V-** C3 20 29 GPIO3 C3 20 S3 21 28 GPIO2 S3 21 28 GPIO2 C2 22 27 GPIO1 C2 22 27 GPIO1 S2 23 26 C0 S2 23 26 C0 C1 24 25 S1 C1 24 25 S1 G PACKAGE 48-LEAD PLASTIC SSOP G PACKAGE 48-LEAD PLASTIC SSOP TJMAX = 150C, JA = 55C/W *THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD ISOMD TIED TO V-: CSB, SCK, SDI, SDO ISOMD TIED TO VREG: IMA, IPA, NC, NC **THIS PIN MUST BE CONNECTED TO V- TJMAX = 150C, JA = 55C/W *THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD ISOMD TIED TO V-: CSB, SCK, SDI, SDO ISOMD TIED TO VREG: IMA, IPA, ICMP, IBIAS **THIS PIN MUST BE CONNECTED TO V- 680412fc For more information www.linear.com/LTC6804-1 3 LTC6804-1/LTC6804-2 Order Information http://www.linear.com/product/LTC6804-1#orderinfo TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6804IG-1#PBF LTC6804IG-1#TRPBF LTC6804G-1 48-Lead Plastic SSOP -40C to 85C LTC6804HG-1#PBF LTC6804HG-1#TRPBF LTC6804G-1 48-Lead Plastic SSOP -40C to 125C LTC6804IG-2#PBF LTC6804IG-2#TRPBF LTC6804G-2 48-Lead Plastic SSOP -40C to 85C LTC6804HG-2#PBF LTC6804HG-2#TRPBF LTC6804G-2 48-Lead Plastic SSOP -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Parts ending with PBF are RoHS and WEEE compliant. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ADC DC Specifications Measurement Resolution ADC Offset Voltage (Note 2) ADC Gain Error (Note 2) Total Measurement Error (TME) in Normal Mode l 0.1 mV/bit l 0.1 mV l 0.01 0.02 % % C(n) to C(n - 1), GPIO(n) to V- = 0 0.2 C(n) to C(n - 1) = 2.0 0.1 C(n) to C(n - 1), GPIO(n) to V- = 2.0 l C(n) to C(n - 1) = 3.3 C(n) to C(n - 1), GPIO(n) to V- = 3.3 0.2 l C(n) to C(n - 1) = 4.2 C(n) to C(n - 1), GPIO(n) to V- = 4.2 0.3 l C(n) to C(n - 1), GPIO(n) to V- = 5.0 Sum of Cells, V(CO) = V- mV 1.4 mV 1.2 mV 2.2 mV 1.6 mV 2.8 mV 1 l Internal Temperature, T = Maximum Specified Temperature 4 mV 0.8 0.2 mV 0.75 5 % C VREG Pin l 0.1 0.25 % VREF2 Pin l 0.02 0.1 % Digital Supply Voltage VREGD l 0.1 1 % 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS Total Measurement Error (TME) in Filtered Mode C(n) to C(n - 1), GPIO(n) to V- = 0 MIN 0.1 l C(n) to C(n - 1) = 3.3 C(n) to C(n - 1), GPIO(n) to V- = 3.3 0.2 l C(n) to C(n - 1) = 4.2 C(n) to C(n - 1), GPIO(n) to V- = 4.2 0.3 l C(n) to C(n - 1), GPIO(n) to V- = 5.0 Sum of Cells, V(CO) = V- 0.2 l mV 1.4 mV 1.2 mV 2.2 mV 1.6 mV 2.8 mV mV 0.75 % C VREG Pin l 0.1 0.25 % VREF2 Pin l 0.02 0.1 % Digital Supply Voltage VREGD l 0.1 1 C(n) to C(n - 1), GPIO(n) to V- = 0 2 % mV C(n) to C(n - 1), GPIO(n) to V- = 2.0 l 4 mV C(n) to C(n - 1), GPIO(n) to V- = 3.3 l 4.7 mV C(n) to C(n - 1), GPIO(n) to V- = 4.2 l 8.3 mV Sum of Cells, V(CO) = V- 10 0.3 l Internal Temperature, T = Maximum Specified Temperature IL 0.8 5 C(n) to C(n - 1), GPIO(n) to V- = 5.0 Input Range UNITS mV 1 Internal Temperature, T = Maximum Specified Temperature Total Measurement Error (TME) in Fast Mode MAX 0.1 C(n) to C(n - 1) = 2.0 C(n) to C(n - 1), GPIO(n) to V- = 2.0 TYP mV 1 5 % C VREG Pin l 0.3 1 % VREF2 Pin l 0.1 0.25 % Digital Supply Voltage VREGD l 0.2 2 % C(n), n = 1 to 12 l C(n - 1) C(n - 1) + 5 V 5 V 0 C0 l GPIO(n), n = 1 to 5 l Input Leakage Current When Inputs C(n), n = 0 to 12 Are Not Being Measured GPIO(n), n = 1 to 5 l 10 250 nA l 10 250 nA Input Current When Inputs Are Being Measured 0 C(n), n = 0 to 12 2 GPIO(n), n = 1 to 5 Input Current During Open Wire Detection A 2 l 70 100 A 130 A 680412fc For more information www.linear.com/LTC6804-1 5 LTC6804-1/LTC6804-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX 3.1 3.2 3.3 UNITS Voltage Reference Specifications VREF1 VREF2 1st Reference Voltage VREF1 Pin, No Load 1st Reference Voltage TC VREF1 Pin, No Load 3 ppm/C 1st Reference Voltage Hysteresis VREF1 Pin, No Load 20 ppm 1st Reference Long Term Drift VREF1 Pin, No Load 2nd Reference Voltage VREF2 Pin, No Load VREF2 l 20 Pin, 5k Load to V- l 2.990 l 2.988 V ppm/kHr 3 3.010 3 3.012 V V 2nd Reference Voltage TC VREF2 Pin, No Load 10 ppm/C 2nd Reference Voltage Hysteresis VREF2 Pin, No Load 100 ppm 2nd Reference Long Term Drift VREF2 Pin, No Load 60 ppm/kHr General DC Specifications IVP V+ Supply Current (See Figure 1: LTC6804 Operation State Diagram) State: Core = SLEEP, isoSPI = IDLE VREG = 0V 3.8 6 A VREG = 0V l 3.8 10 A VREG = 5V 1.6 3 A VREG = 5V l 1.6 5 A 18 32 50 A l 10 32 60 A 0.4 0.55 0.7 mA l 0.375 0.55 0.725 mA VREG = 5V 2.2 4 A VREG = 5V l 2.2 6 A 35 60 A State: Core = STANDBY State: Core = REFUP or MEASURE IREG(CORE) VREG Supply Current (See Figure 1: LTC6804 Operation State diagram) State: Core = SLEEP, isoSPI = IDLE State: Core = STANDBY 10 6 35 65 A 0.2 0.45 0.7 mA 0.15 0.45 0.75 mA 10.8 11.5 12.2 mA l 10.7 11.5 12.3 mA l State: Core = REFUP l State: Core = MEASURE IREG(isoSPI) Additional VREG Supply Current if isoSPI in READY/ACTIVE States Note: ACTIVE State Current Assumes tCLK = 1s, (Note 3) LTC6804-2: ISOMD = 1, RB1 + RB2 = 2k LTC6804-1: ISOMD = 0, RB1 + RB2 = 2k LTC6804-1: ISOMD = 1, RB1 + RB2 = 2k LTC6804-2: ISOMD = 1, RB1 + RB2 = 20k 6 READY l 3.9 4.8 5.8 mA ACTIVE l 5.1 6.1 7.3 mA READY l 3.7 4.6 5.6 mA ACTIVE l 5.7 6.8 8.1 mA READY l 6.5 7.8 9.5 mA ACTIVE l 10.2 11.3 13.3 mA READY l 1.3 2.1 3 mA ACTIVE l 1.6 2.5 3.5 mA LTC6804-1: ISOMD = 0, RB1 + RB2 = 20k READY l 1.1 1.9 2.8 mA ACTIVE l 1.5 2.3 3.3 mA LTC6804-1: ISOMD = 1, RB1 + RB2 = 20k READY l 2.1 3.3 4.9 mA ACTIVE l 2.7 4.1 5.8 mA 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted. SYMBOL VREG PARAMETER CONDITIONS V+ Supply Voltage TME Specifications Met (Note 6) VREG Supply Voltage TME Supply Rejection < 1mV/V DRIVE output voltage Sourcing 1A Sourcing 500A VREGD Digital Supply Voltage Discharge Switch ON Resistance VCELL = 3.6V MIN TYP MAX l 11 40 55 V l 4.5 5 5.5 V l 5.4 5.2 5.6 5.6 5.8 6.0 V V l 5.1 5.6 6.1 V l 2.7 3.0 3.6 V 10 25 l Thermal Shutdown Temperature 150 UNITS C VOL(WDT) Watchdog Timer Pin Low WDT Pin Sinking 4mA l 0.4 V VOL(GPIO) General Purpose I/O Pin Low GPIO Pin Sinking 4mA (Used as Digital Output) l 0.4 V Measure 12 Cells l 2120 2335 2480 s Measure 2 Cells l 365 405 430 s Measure 12 Cells and 2 GPIO Inputs l 2845 3133 3325 s Measurement + Calibration Cycle Time When Starting from the REFUP State in Filtered Mode Measure 12 Cells l 183 201.3 213.5 ms Measure 2 Cells l 30.54 33.6 35.64 ms Measure 12 Cells and 2 GPIO Inputs l 244 268.4 284.7 ms Measurement + Calibration Cycle Time When Starting from the REFUP State in Fast Mode Measure 12 Cells l 1010 1113 1185 s Measure 2 Cells l 180 201 215 s Measure 12 Cells and 2 GPIO Inputs l 1420 1564 1660 s Skew Time. The Time Difference between C12 and GPIO2 Measurements, Command = ADCVAX Fast Mode l 189 208 221 s Normal Mode l 493 543 576 s Skew Time. The Time Difference between C12 and C0 Measurements, Command = ADCV Fast Mode l 211 233 248 s Normal Mode l 609 670 711 s 100 300 s ADC Timing Specifications tCYCLE (Figure 3) tSKEW1 (Figure 6) tSKEW2 (Figure 3) Measurement + Calibration Cycle Time When Starting from the REFUP State in Normal Mode tWAKE Regulator Start-Up Time VREG Generated from Drive Pin (Figure 28) l tSLEEP Watchdog or Software Discharge Timer SWTEN Pin = 0 or DCTO[3:0] = 0000 l tREFUP (Figure 1, Figures 3 to 7) Reference Wake-Up Time State: Core = STANDBY l State: Core = REFUP l fS ADC Clock Frequency SWTEN Pin = 1 and DCTO[3:0] 0000 1.8 2 0.5 2.7 l 3.0 2.3 3.5 3.3 2.2 sec 120 min 4.4 ms 0 ms 3.5 MHz 0.8 V SPI Interface DC Specifications VIH(SPI) SPI Pin Digital Input Voltage High Pins CSB, SCK, SDI l VIL(SPI) SPI Pin Digital Input Voltage Low Pins CSB, SCK, SDI l VIH(CFG) Configuration Pin Digital Input Voltage High Pins ISOMD, SWTEN, GPIO1 to GPIO5, A0 to A3 l VIL(CFG) Configuration Pin Digital Input Voltage Low Pins ISOMD, SWTEN, GPIO1 to GPIO5, A0 to A3 l V 2.7 V 1.2 V 680412fc For more information www.linear.com/LTC6804-1 7 LTC6804-1/LTC6804-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS ILEAK(DIG) Digital Input Current Pins CSB, SCK, SDI, ISOMD, SWTEN, A0 to A3 l MIN TYP MAX 1 UNITS A VOL(SDO) Digital Output Low Pin SDO Sinking 1mA l 0.3 V l 1.9 2.1 V V l 0.1 l l 18 18 isoSPI DC Specifications (See Figure 16) VBIAS Voltage on IBIAS Pin READY/ACTIVE State IDLE State IB Isolated Interface Bias Current RBIAS = 2k to 20k AIB Isolated Interface Current Gain VA 1.6V VA Transmitter Pulse Amplitude VA = |VIP - VIM| VICMP Threshold-Setting Voltage on ICMP VTCMP = ATCMP * VICMP Pin l ILEAK(ICMP) Input Leakage Current on ICMP Pin VICMP = 0V to VREG Leakage Current on IP and IM Pins IDLE State, VIP or VIM = 0V to VREG l ATCMP Receiver Comparator Threshold Voltage Gain VCM = VREG/2 to VREG - 0.2V, VICMP = 0.2V to 1.5V l VCM Receiver Common Mode Bias IP/IM Not Driving RIN Receiver Input Resistance Single-Ended to IPA, IMA, IPB, IMB l 27 ILEAK(IP/IM) IB = 1mA IB = 0.1mA 2.0 0 20 20 l 0.2 l 0.4 0.5 1.0 mA 22 24.5 mA/mA mA/mA 1.6 V 1.5 V 1 A 1 A 0.6 V/V (VREG - VICMP/3 - 167mV) 35 43 V k isoSPI Idle/Wakeup Specifications (See Figure 21) VWAKE Differential Wake-Up Voltage tDWELL = 240ns l 200 mV tDWELL Dwell Time at VWAKE Before Wake Detection VWAKE = 200mV l 240 ns tREADY Startup Time After Wake Detection l tIDLE Idle Timeout Duration l 4.3 10 s 5.5 6.7 ms 120 150 180 ns 200 ns 40 50 60 ns 70 ns isoSPI Pulse Timing Specifications (See Figure 19) t1/2PW(CS) Chip-Select Half-Pulse Width l tINV(CS) Chip-Select Pulse Inversion Delay l t1/2PW(D) Data Half-Pulse Width l tINV(D) Data Pulse Inversion Delay l SPI Timing Requirements (See Figure 15 and Figure 20) tCLK SCK Period t1 (Note 4) l 1 s SDI Setup Time before SCK Rising Edge l 25 ns t2 SDI Hold Time after SCK Rising Edge l 25 ns t3 SCK Low tCLK = t3 + t4 1s l 200 ns t4 SCK High tCLK = t3 + t4 1s l 200 ns t5 CSB Rising Edge to CSB Falling Edge l 0.65 s t6 SCK Rising Edge to CSB Rising Edge (Note 4) l 0.8 s t7 CSB Falling Edge to SCK Rising Edge (Note 4) l 1 s 8 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. The test conditions are V+ = 39.6V, VREG = 5.0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS isoSPI Timing Specifications (See Figure 19) t8 SCK Falling Edge to SDO Valid l 60 ns t9 SCK Rising Edge to Short 1 Transmit (Note 5) l 50 ns t10 CSB Transition to Long 1 Transmit l 60 ns t11 CSB Rising Edge to SDO Rising l 200 ns tRTN Data Return Delay l 430 525 ns tDSY(CS) Chip-Select Daisy-Chain Delay l 150 200 ns tDSY(D) Data Daisy-Chain Delay l 300 360 ns tLAG Data Daisy-Chain Lag (vs ChipSelect) l 0 35 70 ns t6(GOV) Data to Chip-Select Pulse Governor l 0.8 1.05 s (Note 5) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The ADC specifications are guaranteed by the Total Measurement Error specification. Note 3: The ACTIVE state current is calculated from DC measurements. The ACTIVE state current is the additional average supply current into VREG when there is continuous 1MHz communications on the isoSPI ports with 50% data 1's and 50% data 0's. Slower clock rates reduce the supply current. See Applications Information section for additional details. Note 4: These timing specifications are dependent on the delay through the cable, and include allowances for 50ns of delay each direction. 50ns corresponds to 10m of CAT-5 cable (which has a velocity of propagation of 66% the speed of light). Use of longer cables would require derating these specs by the amount of additional delay. Note 5: These specifications do not include rise or fall time of SDO. While fall time (typically 5ns due to the internal pull-down transistor) is not a concern, rising-edge transition time tRISE is dependent on the pull-up resistance and load capacitance on the SDO pin. The time constant must be chosen such that SDO meets the setup time requirements of the MCU. Note 6: V+ needs to be greater than or equal to the highest C(n) voltage for accurate measurements. See the graph Top Cell Measurement Error vs V+. 680412fc For more information www.linear.com/LTC6804-1 9 LTC6804-1/LTC6804-2 Typical Performance Characteristics Measurement Error vs Temperature 35 CELL VOLTAGE = 3.3V 5 TYPICAL UNITS 1.5 0.5 0 -0.5 -1.0 30 260C, 1 CYCLE 25 20 15 10 5 -1.5 -2.0 -50 -25 75 50 25 TEMPERATURE (C) 0 100 0 25 50 -125 -100 -75 -50 -25 0 CHANGE IN GAIN ERROR (ppm) 125 Measurement Error vs Input, Normal Mode MEASUREMENT ERROR (mV) MEASUREMENT ERROR (mV) 0 -0.5 -1.0 -1.5 3 INPUT (V) 4 1.0 0.5 0 -0.5 -1.0 -2.0 5 0 -2 -4 -6 0 1 2 3 INPUT (V) 4 -10 5 9 0.8 0.8 8 0.7 0.7 7 PEAK NOISE (mV) 10 0.6 0.5 0.4 0.3 0.1 1 0 0 10 0 1 3 2 INPUT (V) 4 5 3 2 680412 G07 4 4 0.1 5 3 2 INPUT (V) 5 0.2 4 1 6 0.2 3 2 INPUT (V) 0 Measurement Noise vs Input, Fast Mode 0.9 1 10 ADC MEASUREMENTS AVERAGED AT EACH INPUT 680412 G06 1.0 PEAK NOISE (mV) PEAK NOISE (mV) 2 0.9 0 3000 4 1.0 0.3 2500 6 Measurement Noise vs Input, Filtered Mode 0.4 1000 1500 2000 TIME (HOURS) 680412 G05 Measurement Noise vs Input, Normal Mode 0.5 500 -8 680412 G04 0.6 0 8 -1.5 2 5 10 1.5 0.5 1 10 Measurement Error vs Input, Fast Mode 2.0 1.0 0 15 Measurement Error vs Input, Filtered Mode 10 ADC MEASUREMENTS AVERAGED AT EACH INPUT 1.5 20 680412 G03 MEASUREMENT ERROR (mV) 2.0 25 0 75 CELL VOLTAGE = 3.3V 8 TYPICAL PARTS 680412 G02 680412 G01 -2.0 Measurement Error LongTerm Drift 30 1.0 NUMBER OF PARTS MEASUREMENT ERROR (mV) Measurement Error Due to IR Reflow MEASUREMENT ERROR (ppm) 2.0 TA = 25C, unless otherwise noted. 5 680412 G08 0 0 1 3 2 INPUT (V) 4 680412 G09 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Typical Performance Characteristics Measurement Gain Error Hysteresis, Hot 25 Measurement Gain Error Hysteresis, Cold 30 TA = 85C TO 25C TA = -45C TO 25C -10 15 10 5 NOISE REJECTION (dB) NUMBER OF PARTS 20 15 10 5 0 0 -50 -40 -30 -20 -10 10 20 CHANGE IN GAIN ERROR (ppm) 0 10 20 30 -40 -30 -20 -10 0 CHANGE IN GAIN ERROR (ppm) 30 -40 2.0 -50 1.0 -55 0 -0.5 -10 -65 -70 C=0 C = 10nF C = 100nF C = 1F -15 1 100 10 1000 INPUT RESISTOR, R () -40 1k 100k 10k FREQUENCY (Hz) 1M -70 100 10M 10 680412 G16 10k 100k 1M 68412 G15 Top Cell Measurement Error vs V+ 6 4 2 0 -2 -4 C=0 C = 100nF C = 1F C = 10F -6 -10 1 10M FREQUENCY (Hz) 1.0 TIME BETWEEN MEASUREMENTS > 3RC 8 -8 10000 1k 680412 G14 MEASUREMENT ERROR (mV) -5 -10 -30 GPIO Measurement Error vs Input RC Values 0 VREG(DC) = 5V VREG(AC) = 500mVP-P 1 BIT CHANGE < -70dB -60 -90 100 Cell Measurement Error vs Input RC Values 1M -50 680412 G13 5 1k 10k 100k INPUT FREQUENCY (Hz) -20 -60 -85 -2.0 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 VREG (V) CELL MEASUREMENT ERROR (mV) 0 -80 VIN = 2V VIN = 3.3V VIN = 4.2V 10 100 Measurement Error VREG PSRR vs Frequency -75 NORMAL MODE CONVERSIONS DIFFERENTIAL RC FILTER ON EVERY C PIN. EXPECT CELL-TO-CELL AND PART-TO-PART VARIATIONS IN ERROR IF R > 100 AND/OR C > 10nF 10 ADC MODE: NORMAL FILTERED 15kHz 2kHz FAST 680412 G12 3kHz PSRR (dB) 0.5 PSRR (dB) MEASUREMENT ERROR (mV) 1.5 15 -50 -70 40 V+DC = 39.6V V+AC = 5VP-P 1 BIT CHANGE < -90dB VREG GENERATED FROM DRIVE PIN, FIGURE 28 -45 20 -40 Measurement Error V+ PSRR vs Frequency Measurement Error vs VREG -1.5 -30 680412 G11 680412 G10 -1.0 -20 -60 CELL 12 MEASUREMENT ERROR (mV) NUMBER OF PARTS Noise Filter Response 0 25 20 -20 TA = 25C, unless otherwise noted. 10 1000 10000 100000 100 INPUT RESISTANCE, R () 680412 G17 C12-C11 = 3.3V C12 = 39.6V 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 36 38 40 V+ (V) 42 44 680412 G18 680412fc For more information www.linear.com/LTC6804-1 11 LTC6804-1/LTC6804-2 Typical Performance Characteristics Cell Measurement Error vs Common Mode Voltage Cell Measurement CMRR vs Frequency 0 C12-C11 = 3.3V V+ = 39.6V MEASUREMENT ERROR (mV) 0.2 0 -0.2 -0.4 -30 -40 -50 -60 -0.6 -70 -0.8 -80 10 0 20 C11 VOLTAGE (V) 1k 3 SLEEP SUPPLY CURRENT = V+ CURRENT + VREG CURRENT 15 25 45 35 V+ (V) 55 65 70 50 2440 2420 12.25 11.00 5 15 25 45 35 V+ (V) 55 65 75 680412 G25 12 MEASUREMENT TIME (s) MEASURE MODE SUPPLY CURRENT (mA) 12.50 11.25 30 35 STANDBY SUPPLY CURRENT = V+ CURRENT + VREG CURRENT 5 15 25 45 35 V+ (V) 55 65 125C 85C 25C -45C REFUP SUPPLY CURRENT = V+ CURRENT + VREG CURRENT 900 850 75 12 CELL NORMAL MODE TIME SHOWN. ALL ADC MEASURE TIMES SCALE PROPORTIONALLY 2400 2380 2360 2340 2320 VREG = 5V VREG = 4.5V VREG = 5.5V 2300 2280 -50 -25 75 50 25 TEMPERATURE (C) 0 40 950 5 15 25 45 35 V+ (V) 55 100 125 680412 G26 65 75 680412 G24 Internal Die Temperature Measurement Error vs Temperature Measurement Time vs Temperature 125C 85C 25C -45C MEASURE MODE SUPPLY CURRENT = + CURRENT + V V REG CURRENT 25 20 V+ (V) 680412 G23 Measure Mode Supply Current vs V+ 11.75 15 1000 60 40 75 12.00 10 5 REFUP Supply Current vs V+ 125C 85C 25C -45C 680412 G22 11.50 -1.0 680412 G21 REFUP SUPPLY CURRENT (A) 4 STANDBY SUPPLY CURRENT (A) SLEEP SUPPLY CURRENT (A) 80 125C 85C 25C -45C 5 -0.5 Standby Supply Current vs V+ 5 2 0 680412 G20 Sleep Supply Current vs V+ 6 0.5 -2.0 10M 1M 100k 10k FREQUENCY (Hz) 680412 G19 7 1.0 -1.5 -90 100 30 MEASUREMENT ERROR OF CELL 1 WITH 3.3V INPUT. VREG GENERATED FROM DRIVE PIN, FIGURE 28 1.5 -20 0.4 -1.0 VCM(IN) = 5VP-P NORMAL MODE CONVERSIONS -10 0.6 Measurement Error vs V+ 2.0 TEMPERATURE MEASUREMENT ERROR (DEG) 0.8 REJECTION (dB) CELL 12 MEASUREMENT ERROR (mV) 1.0 TA = 25C, unless otherwise noted. 10 8 5 TYPICAL UNITS 6 4 2 0 -2 -4 -6 -8 -10 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 680412 G27 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Typical Performance Characteristics VREF2 vs Temperature 3.003 VREG GENERATED FROM 150 DRIVE PIN, FIGURE 28 3.000 2.999 -400 -600 V+ = 39.6V -800 2.998 50 25 75 0 TEMPERATURE (C) 100 125 -1000 0.01 VREG = 5V 125C 85C 25C -45C 1 0.1 3.0 VREF2 (V) 100 50 0 -200 15 5 25 -50 5.25 65 2.5 2.0 VREF2 1.5 CSB 50 25 0 -25 -50 -75 0 -5 8 TYPICAL PARTS 75 5 5.5 1ms/DIV 680412 G32 -100 500 0 VREG (V) 1000 1500 2000 2500 680412 G33 VREF2 Hysteresis, Hot VREF2 Hysteresis, Cold 16 TA = 85C TO 25C VREF2 Change Due to IR Reflow 30 TA = -45C TO 25C 14 15 10 260C, 1 CYCLE 25 12 NUMBER OF PARTS NUMBER OF PARTS NUMBER OF PARTS 20 10 8 6 20 15 10 4 5 5 2 0 -125 3000 TIME (HOURS) 680412 G31 25 75 580412 G30 RL = 5k CL = 1F 0 125C 85C 25C -45C 55 45 35 V+ (V) VREF2 Long-Term Drift 0.5 5 125C 85C 25C -45C 100 1.0 CSB CHANGE IN VREF2 (ppm) 10 VREF2 Power-Up 3.5 4.75 -50 680412 G29 RL = 5k 4.5 0 IOUT (mA) VREF2 VREG Line Regulation -150 50 -150 680412 G28 -100 100 -100 CHANGE IN VREF2 (ppm) 2.997 -50 -25 CHANGE IN VREF2 (ppm) CHANGE IN VREF2 (ppm) VREF2 (V) 200 -200 3.001 150 VREF2 V+ Line Regulation VREF2 Load Regulation 0 V+ = 39.6V 5 TYPICAL PARTS 3.002 TA = 25C, unless otherwise noted. -75 25 75 125 -25 CHANGE IN REF2 (ppm) 175 680412 G34 0 0 50 -250 -200 -150 -100 -50 CHANGE IN REF2 (ppm) 100 680412 G35 0 -700 -500 -300 -100 100 CHANGE IN REF2 (ppm) 300 680412 G36 680412fc For more information www.linear.com/LTC6804-1 13 LTC6804-1/LTC6804-2 Typical Performance Characteristics Discharge Switch On-Resistance vs Cell Voltage Drive Pin Load Regulation 0 40 35 30 25 20 15 125C 85C 25C -45C 10 5 0 1 2 4 3 CELL VOLTAGE (V) V+ = 39.6V -20 -40 -60 125C 85C 25C -45C -80 -100 0.01 5 0.1 3.5 3.0 -5 125C 85C 25C -45C -10 -15 1 5 15 25 45 35 V+ (V) 55 3 VREF1 Power-Up 3.155 CL = 1F 75 VREF1 vs Temperature 5 TYPICAL 3.154 3.153 2.5 2.0 3.152 VREF1 1.5 1.0 2 65 680412 G39 VREF1 (V) VREF1 (V) VREG 0.5 3.151 3.150 3.149 3.148 1 VREG: CL = 1F VREG GENERATED FROM DRIVE PIN, FIGURE 28 0 -1 3.147 3.146 0 -5 680412 G40 100s/DIV CSB 5 CSB VDRIVE AND VREG (V) 5 VDRIVE 0 680412 G38 Drive and VREG Pin Power-Up 4 5 ILOAD (mA) 680412 G37 6 Drive Pin Line Regulation 10 CHANGE IN DRIVE PIN VOLTAGE (mV) ON-RESISTANCE OF INTERNAL DISCHARGE SWITCH MEASURED WITH 100. EXTERNAL DISCHARGE RESISTOR BETWEEN S(n) and C(n) 45 CHANGE IN DRIVE PIN VOLTAGE (mV) DISCHARGE SWITCH ON-RESISTANCE () 50 TA = 25C, unless otherwise noted. 1ms/DIV 680412 G41 3.145 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 680412 G42 Internal Die Temperature Increase vs Discharge Current isoSPI Current (READY) vs Temperature 45 40 35 30 25 12 CELLS DISCHARGING 20 15 10 5 1 CELL DISCHARGING 0 80 40 20 0 60 INTERNAL DISCHARGE CURRENT (mA PER CELL) 680412 G43 14 LT6804-1 ISOMD = VREG 8 6 CELLS DISCHARGING 14 IB = 1mA 7 6 LT6804-2 ISOMD = VREG 5 4 -50 50 0 75 25 TEMPERATURE (C) LTC6804-1 10 8 LTC6804-2 6 4 2 LT6804-1, ISOMD = 0 -25 ISOMD = VREG IB = 1mA 12 isoSPI CURRENT (mA) 9 isoSPI CURRENT (mA) INCREASE IN DIE TEMPERATURE (C) 50 isoSPI Current (READY/ACTIVE) vs isoSPI Clock Frequency 100 125 680412 G44 0 WRITE READ 0 200 400 600 800 isoSPI CLOCK FREQUENCY (kHz) 1000 680412 G45 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Typical Performance Characteristics IBIAS Voltage vs Temperature 2.010 2.01 2.00 1.99 -25 75 0 25 50 TEMPERATURE (C) 100 125 23 2.005 CURRENT GAIN (mA/mA) IB = 1mA 3 PARTS 1.98 -50 2.000 1.995 1.990 200 0 600 800 400 BIAS CURRENT (A) 680412 G46 20 19 50 0 75 25 TEMPERATURE (C) 100 IB = 100A 4.5 4.0 3.5 3.0 2.5 125 IB = 1mA 0 0.5 1.0 1.5 PULSE AMPLITUDE (V) WAKE-UP PULSE AMPLITUDE, VWAKE (mV) 0.52 0.50 0.48 0.46 0.4 600 800 400 BIAS CURRENT (A) 0.6 0.8 1.0 1.2 ICMP VOLTAGE (V) 1000 2.0 0.54 0.52 VICMP = 1V 0.50 VICMP = 0.2V 0.48 0.46 0.44 2.5 3.5 4.0 4.5 5.0 3.0 COMMON MODE VOLTAGE (V) 1.4 5.5 680412 G51 Typical Wake-Up Pulse Amplitude (Port A) vs Dwell Time 0.54 0.2 200 680412 G50 3 PARTS 0 0 isoSPI Comparator Threshold Gain (Port A/Port B) vs Common Mode 5.0 isoSPI Comparator Threshold Gain (Port A/Port B) vs ICMP Voltage 0.44 VA = 0.5V VA = 1.0V VA = 1.6V 0.56 680412 G49 0.56 19 680412 G48 COMPARATOR THRESHOLD GAIN (V/V) DRIVER COMMON MODE (V) IB = 1mA COMPARATOR THRESHOLD GAIN (V/V) CURRENT GAIN (mA/mA) IB = 100A -25 20 18 1000 5.5 21 21 isoSPI Driver Common Mode Voltage (Port A/Port B) vs Pulse Amplitude 23 22 22 408912 G47 isoSPI Driver Current Gain (Port A/PortB) vs Temperature 18 -50 isoSPI Driver Current Gain (Port A/PortB) vs Bias Current IBIAS Voltage Load Regulation IBIAS PIN VOLTAGE (V) IBIAS PIN VOLTAGE (V) 2.02 TA = 25C, unless otherwise noted. 1.6 300 GUARANTEED WAKE-UP REGION 250 200 150 100 50 0 680412 G52 300 150 450 WAKE-UP DWELL TIME, tDWELL (ns) 600 680412 G53 680412fc For more information www.linear.com/LTC6804-1 15 LTC6804-1/LTC6804-2 Typical Performance Characteristics TA = 25C, unless otherwise noted. Write Command to a Daisy-Chained Device (ISOMD = 0) CSB 5V/DIV SDI 5V/DIV PORT A IPA-IMA 1V/DIV (PORT A) SCK 5V/DIV SDO 5V/DIV IPB-IMB 2V/DIV (PORT B) Write Command to a Daisy-Chained Device (ISOMD = 1) IPB-IMB 1V/DIV (PORT B) 1s/DIV ISOMD = V- BEGINNING OF A COMMAND 680412 G54 1s/DIV ISOMD = VREG BEGINNING OF A COMMAND Data Read-Back from a Daisy-Chained Device (ISOMD = 0) CSB 5V/DIV SDI 5V/DIV PORT A SDO 5V/DIV 16 Data Read-Back from a Daisy-Chained Device (ISOMD = 1) IPA-IMA 1V/DIV (PORT A) SCK 5V/DIV IPB-IMB 2V/DIV (PORT B) 680412 G55 IPB-IMB 1V/DIV (PORT B) 1s/DIV ISOMD = V- END OF A READ COMMAND 680412 G56 1s/DIV ISOMD = VREG END OF A READ COMMAND 680412 G57 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Pin Functions C0 to C12: Cell Inputs. Serial Port Pins LTC6804-1 (DAISY-CHAINABLE) S1 to S12: Balance Inputs/Outputs. 12 N-MOSFETs are connected between S(n) and C(n - 1) for discharging cells. V+: Positive Supply Pin. V-: Negative Supply Pins. The together, external to the IC. V- pins must be shorted VREF2: Buffered 2nd reference voltage for driving multiple 10k thermistors. Bypass with an external 1F capacitor. VREF1: ADC Reference Voltage. Bypass with an external 1F capacitor. No DC loads allowed. GPIO[1:5]: General Purpose I/O. Can be used as digital inputs or digital outputs, or as analog inputs with a measurement range from V- to 5V. GPIO [3:5] can be used as an I2C or SPI port. SWTEN: Software Timer Enable. Connect this pin to VREG to enable the software timer. PORT B (Pins 45 to 48) PORT A (Pins 41 to 44) LTC6804-2 (ADDRESSABLE) ISOMD = VREG ISOMD = V- ISOMD = VREG ISOMD = V- IPB IPB A3 A3 IMB IMB A2 A2 ICMP ICMP A1 A1 IBIAS IBIAS A0 A0 (NC) SDO IBIAS SDO (NC) SDI ICMP SDI IPA SCK IPA SCK IMA CSB IMA CSB CSB, SCK, SDI, SDO: 4-Wire Serial Peripheral Interface (SPI). Active low chip select (CSB), serial clock (SCK), and serial data in (SDI) are digital inputs. Serial data out (SDO) is an open drain NMOS output pin. SDO requires a 5k pull-up resistor. DRIVE: Connect the base of an NPN to this pin. Connect the collector to V+ and the emitter to VREG. A0 to A3: Address Pins. These digital inputs are connected to VREG or V- to set the chip address for addressable serial commands. VREG: 5V Regulator Input. Bypass with an external 1F capacitor. IPA, IMA: Isolated 2-Wire Serial Interface Port A. IPA (plus) and IMA (minus) are a differential input/output pair. ISOMD: Serial Interface Mode. Connecting ISOMD to VREG configures Pins 41 to 44 of the LTC6804 for 2-wire isolated interface (isoSPI) mode. Connecting ISOMD to V- configures the LTC6804 for 4-wire SPI mode. IPB, IMB: Isolated 2-Wire Serial Interface Port B. IPB (plus) and IMB (minus) are a differential input/output pair. WDT: Watchdog Timer Output Pin. This is an open drain NMOS digital output. It can be left unconnected or connected with a 1M resistor to VREG. If the LTC6804 does not receive a wake-up signal (see Figure 21) within 2 seconds, the watchdog timer circuit will reset the LTC6804 and the WDT pin will go high impedance. IBIAS: Isolated Interface Current Bias. Tie IBIAS to V- through a resistor divider to set the interface output current level. When the isoSPI interface is enabled, the IBIAS pin voltage is 2V. The IPA/IMA or IPB/IMB output current drive is set to 20 times the current, IB, sourced from the IBIAS pin. ICMP: Isolated Interface Comparator Voltage Threshold Set. Tie this pin to the resistor divider between IBIAS and V- to set the voltage threshold of the isoSPI receiver comparators. The comparator thresholds are set to 1/2 the voltage on the ICMP pin. 680412fc For more information www.linear.com/LTC6804-1 17 LTC6804-1/LTC6804-2 Block Diagram LTC6804-1 V+ IPB C12 IMB 1 48 2 47 VREGD POR S12 VREG ICMP 3 46 C11 4 S11 5 C10 6 C12 C11 C10 C9 C8 C7 P 6-CELL MUX IBIAS + 45 ADC2 M DIGITAL FILTERS C6 S10 7 C9 8 S9 SERIAL I/O PORT B 16 - C5 C4 C3 C2 C1 C0 P 6-CELL MUX + M 43 SCK/(IPA) 16 - 44 SDI/(NC) LOGIC AND MEMORY SERIAL I/O PORT A ADC1 SDO/(NC) 42 CSB/(IMA) 41 ISOMD 9 40 C8 10 WDT S8 11 DRIVE C7 12 S7 13 39 38 12 BALANCE FETs S(n) VREGD SOC VREG C(n - 1) P C6 14 S6 15 C5 16 S5 17 C4 18 S4 19 C3 20 S3 21 AUX MUX M 37 SOFTWARE TIMER SWTEN 36 VREF1 35 VREF2 34 REGULATORS GPIO5 V+ 33 LDO2 GPIO4 DRIVE LDO1 VREG V+ VREGD POR DIE TEMPERATURE 2ND REFERENCE 32 V- 31 V-* 30 GPIO3 1ST REFERENCE 29 GPIO2 28 C2 22 GPIO1 S2 23 C0 C1 24 S1 27 26 25 680412 BD1 18 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Block Diagram LTC6804-2 V+ A4 C12 A3 1 48 2 47 VREGD POR S12 VREG A2 3 46 C11 4 S11 5 C10 6 C12 C11 C10 C9 C8 C7 P 6-CELL MUX A1 + 45 ADC2 M DIGITAL FILTERS C6 S10 7 C9 8 S9 SERIAL I/O ADDRESS 16 - C5 C4 C3 C2 C1 C0 P 6-CELL MUX + M 43 SCK/(IPA) 16 - 44 SDI/(ICMP) LOGIC AND MEMORY SERIAL I/O PORT A ADC1 SDO/(IBIAS) 42 CSB/(IMA) 41 ISOMD 9 40 C8 10 WDT S8 11 DRIVE C7 12 S7 13 39 38 12 BALANCE FETs S(n) VREGD SOC VREG C(n - 1) P C6 14 S6 15 C5 16 S5 17 C4 18 S4 19 C3 20 S3 21 AUX MUX M 37 SOFTWARE TIMER SWTEN 36 VREF1 35 VREF2 34 REGULATORS GPIO5 V+ 33 LDO2 GPIO4 DRIVE LDO1 VREG V+ VREGD POR DIE TEMPERATURE 2ND REFERENCE 32 V- 31 V-* 30 GPIO3 1ST REFERENCE 29 GPIO2 28 C2 22 GPIO1 S2 23 C0 C1 24 S1 27 26 25 680412 BD2 680412fc For more information www.linear.com/LTC6804-1 19 LTC6804-1/LTC6804-2 Operation State Diagram The operation of the LTC6804 is divided into two separate sections: the core circuit and the isoSPI circuit. Both sections have an independent set of operating states, as well as a shutdown timeout. LTC6804 Core State Descriptions SLEEP State The reference and ADCs are powered down. The watchdog timer (see Watchdog and Software Discharge Timer) has timed out. The software discharge timer is either disabled or timed out. The supply currents are reduced to minimum levels. The isoSPI ports will be in the IDLE state. If a WAKEUP signal is received (see Waking Up the Serial Interface), the LTC6804 will enter the STANDBY state. returns to the SLEEP state. If the software discharge timer is disabled, only the watchdog timer is relevant. REFUP State To reach this state the REFON bit in the Configuration Register Group must be set to 1 (using the WRCFG command, see Table 36). The ADCs are off. The reference is powered up so that the LTC6804 can initiate ADC conversions more quickly than from the STANDBY state. When a valid ADC command is received, the IC goes to the MEASURE state to begin the conversion. Otherwise, the LTC6804 will return to the STANDBY state when the REFON bit is set to 0, either manually (using WRCFG command) or automatically when the watchdog timer expires. (The LTC6804 will then move straight into the SLEEP state if both timers are expired). MEASURE State STANDBY State The reference and the ADCs are off. The watchdog timer and/or the software discharge timer is running. The DRIVE pin powers the VREG pin to 5V through an external transistor. (Alternatively, VREG can be powered by an external supply). When a valid ADC command is received or the REFON bit is set to 1 in the Configuration Register Group, the IC pauses for tREFUP to allow for the reference to power up and then enters either the REFUP or MEASURE state. If there is no WAKEUP signal for a duration tSLEEP (when both the watchdog and software discharge timer have expired) the LTC6804 The LTC6804 performs ADC conversions in this state. The reference and ADCs are powered up. After ADC conversions are complete the LTC6804 will transition to either the REFUP or STANDBY states, depending on the REFON bit. Additional ADC conversions can be initiated more quickly by setting REFON = 1 to take advantage of the REFUP state. Note: Non-ADC commands do not cause a Core state transition. Only an ADC conversion or diagnostic commands will place the Core in the MEASURE state. CORE LTC6804 isoSPI PORT SLEEP IDLE WD TIMEOUT OR SWT TIMEOUT (tSLEEP) WAKEUP SIGNAL (tWAKE) STANDBY REFON = 0 REFON = 1 (tREFUP) REFUP ADC COMMAND WAKEUP SIGNAL (CORE = SLEEP) (tWAKE) IDLE TIMEOUT (tIDLE) WAKEUP SIGNAL (CORE = STANDBY) (tREADY) READY ADC COMMAND (tREFUP) CONVERSION DONE (REFON = 0) NO ACTIVITY ON isoSPI PORT MEASURE TRANSMIT/RECEIVE ACTIVE CONVERSION DONE (REFON = 1) NOTE: STATE TRANSITION DELAYS DENOTED BY (tX) 680412 F01 Figure 1. LTC6804 Operation State Diagram 20 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation isoSPI State Descriptions Note: The LTC6804-1 has two isoSPI ports (A and B), for daisy-chain communication. The LTC6804-2 has only one isoSPI port (A), for parallel-addressable communication. IDLE State The isoSPI ports are powered down. When isoSPI port A receives a WAKEUP signal (see Waking Up the Serial Interface), the isoSPI enters the READY state. This transition happens quickly (within tREADY) if the Core is in the STANDBY state because the DRIVE and VREG pins are already biased up. If the Core is in the SLEEP state when the isoSPI receives a WAKEUP signal, then it transitions to the READY state within tWAKE. READY State The isoSPI port(s) are ready for communication. Port B is enabled only for LTC6804-1, and is not present on the LTC6804-2. The serial interface current in this state depends on if the part is LTC6804-1 or LTC6804-2, the status of the ISOMD pin, and RBIAS = RB1 + RB2 (the external resistors tied to the IBIAS pin). If there is no activity (i.e., no WAKEUP signal) on port A for greater than tIDLE = 5.5ms, the LTC6804 goes to the IDLE state. When the serial interface is transmitting or receiving data the LTC6804 goes to the ACTIVE state. ACTIVE State The LTC6804 is transmitting/receiving data using one or both of the isoSPI ports. The serial interface consumes maximum power in this state. The supply current increases with clock frequency as the density of isoSPI pulses increases. Power Consumption The LTC6804 is powered via two pins: V+ and VREG. The V+ input requires voltage greater than or equal to the top cell voltage, and it provides power to the high voltage elements of the core circuitry. The VREG input requires 5V and provides power to the remaining core circuitry and the isoSPI circuitry. The VREG input can be powered through an external transistor, driven by the regulated DRIVE output pin. Alternatively, VREG can be powered by an external supply. The power consumption varies according to the operational states. Table 1 and Table 2 provide equations to approximate the supply pin currents in each state. The V+ pin current depends only on the Core state and not on the isoSPI state. However, the VREG pin current depends on both the Core state and isoSPI state, and can therefore be divided into two components. The isoSPI interface draws current only from the VREG pin. IREG = IREG(CORE) + IREG(isoSPI) Table 1. Core Supply Current STATE SLEEP IV+ IREG(CORE) VREG = 0V 3.8A 0A VREG = 5V 1.6A 2.2A STANDBY 32A 35A REFUP 550A 450A MEASURE 550A 11.5mA In the SLEEP state the VREG pin will draw approximately 2.2A if powered by a external supply. Otherwise, the V+ pin will supply the necessary current. ADC Operation There are two ADCs inside the LTC6804. The two ADCs operate simultaneously when measuring twelve cells. Only one ADC is used to measure the general purpose inputs. The following discussion uses the term ADC to refer to one or both ADCs, depending on the operation being performed. The following discussion will refer to ADC1 and ADC2 when it is necessary to distinguish between the two circuits, in timing diagrams, for example. ADC Modes The ADCOPT bit (CFGR0[0]) in the configuration register group and the mode selection bits MD[1:0] in the conversion command together provide 6 modes of operation for the ADC which correspond to different over sampling ratios (OSR). The accuracy of these modes are summarized in Table 3. In each mode, the ADC first measures the inputs, and then performs a calibration of each channel. The names of the modes are based on the -3dB bandwidth of the ADC measurement. 680412fc For more information www.linear.com/LTC6804-1 21 LTC6804-1/LTC6804-2 Operation Table 2. isoSPI Supply Current Equations isoSPI STATE IDLE READY DEVICE LTC6804-1/LTC6804-2 LTC6804-1 LTC6804-2 ACTIVE LTC6804-1 ISOMD CONNECTION N/A VREG V- VREG V- VREG IREG(isoSPI) 0mA 2.8mA + 5 * IB Note: IB = VBIAS/(RB1 + RB2) 1.6mA + 3 * IB 1.8mA + 3 * IB 0mA V- LTC6804-2 Write: 2.8mA + 5 *IB + ( 2 *IB + 0.4mA ) * 1s tCLK Read: 2.8mA + 5 *IB + ( 3 *IB + 0.5mA ) * 1s tCLK 1.6mA+ 3 *IB + ( 2 *IB + 0.2mA ) * VREG Write: 1.8mA + 3 *IB + ( 0.3mA ) * 1s tCLK 1s tCLK Read: 1.8mA + 3 *IB + (IB + 0.3mA ) * V- 1s tCLK 0mA Table 3. ADC Filter Bandwidth and Accuracy MODE -3dB FILTER BW -40dB FILTER BW TME SPEC AT 3.3V, 25C TME SPEC AT 3.3V,-40C, 125C 27kHz (Fast Mode) 27kHz 84kHz 4.7mV 4.7mV 14kHz 13.5kHz 42kHz 4.7mV 4.7mV 7kHz (Normal Mode) 6.8kHz 21kHz 1.2mV 2.2mV 3kHz 3.4kHz 10.5kHz 1.2mV 2.2mV 2kHz 1.7kHz 5.3kHz 1.2mV 2.2mV 26Hz (Filtered Mode) 26Hz 82Hz 1.2mV 2.2mV Note: TME is the total measurement error. Mode 7kHz (Normal): Mode 26Hz (Filtered): In this mode, the ADC has high resolution and low TME (total measurement error). This is considered the normal operating mode because of the optimum combination of speed and accuracy. In this mode, the ADC digital filter -3dB frequency is lowered to 26Hz by increasing the OSR. This mode is also referred to as the filtered mode due to its low -3dB frequency. The accuracy is similar to the 7kHz (Normal) mode with lower noise. Mode 27kHz (Fast): In this mode, the ADC has maximum throughput but has some increase in TME (total measurement error). So this mode is also referred to as the fast mode. The increase in speed comes from a reduction in the oversampling ratio. This results in an increase in noise and average measurement error. 22 Modes 14kHz, 3kHz and 2kHz: Modes 14kHz, 3kHz and 2kHz provide additional options to set the ADC digital filter -3dB frequency at 13.5kHz, 3.4kHz and 1.7kHz respectively. The accuracy of the 14kHz mode is similar to the 27kHz (fast) mode. The accuracy of 3kHz and 2kHz modes is similar to the 7kHz (normal) mode. 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation The conversion times for these modes are provided in Table 5. If the core is in STANDBY state, an additional tREFUP time is required to power up the reference before beginning the ADC conversions. The reference can remain powered up between ADC conversions if the REFON bit in Configuration Register Group is set to 1 so the core is in REFUP state after a delay tREFUP. Then, the subsequent ADC commands will not have the tREFUP delay before beginning ADC conversions. 1.0 PEAK NOISE (mV) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ADC Range and Resolution The C inputs and GPIO inputs have the same range and resolution. The ADC inside the LTC6804 has an approximate range from -0.82V to 5.73V. Negative readings are rounded to 0V. The format of the data is a 16-bit unsigned integer where the LSB represents 100V. Therefore, a reading of 0x80E8 (33,000 decimal) indicates a measurement of 3.3V. Delta-Sigma ADCs have quantization noise which depends on the input voltage, especially at low over sampling ratios (OSR), such as in FAST mode. In some of the ADC modes, the quantization noise increases as the input voltage approaches the upper and lower limits of the ADC range. For example, the total measurement noise versus input voltage in normal and filtered modes is shown in Figure 2. The specified range of the ADC is 0V to 5V. In Table 4, the precision range of the ADC is arbitrarily defined as 0.5V to 4.5V. This is the range where the quantization noise is relatively constant even in the lower OSR modes (see Figure 2). Table 4 summarizes the total noise in this range for all six ADC operating modes. Also shown is the noise NORMAL MODE FILTERED MODE 0.9 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ADC INPUT VOLTAGE (V) 680412 F02 Figure 2. Measurement Noise vs Input Voltage free resolution. For example, 14-bit noise free resolution in normal mode implies that the top 14 bits will be noise free with a DC input, but that the 15th and 16th least significant bits (LSB) will flicker. ADC Range vs Voltage Reference Value: Typical Delta-Sigma ADC's have a range which is exactly twice the value of the voltage reference, and the ADC measurement error is directly proportional to the error in the voltage reference. The LTC6804 ADC is not typical. The absolute value of VREF1 is trimmed up or down to compensate for gain errors in the ADC. Therefore, the ADC total measurement error (TME) specifications are superior to the VREF1 specifications. For example, the 25C specification of the total measurement error when measuring 3.300V in 7kHz (normal) mode is 1.2mV and the 25C specification for VREF1 is 3.200V 100mV. Table 4. ADC Range and Resolution SPECIFIED RANGE PRECISION RANGE2 MAX NOISE NOISE FREE RESOLUTION3 27kHz (Fast) 4mVP-P 10 Bits 14kHz 1mVP-P 12 Bits 250VP-P 14 Bits 150VP-P 14 Bits 2kHz 100VP-P 15 Bits 26Hz (Filtered) 50VP-P 16 Bits MODE 7kHz (Normal) 3kHz FULL RANGE1 -0.8192V to 5.7344V 0V to 5V 0.5V to 4.5V LSB 100V FORMAT Unsigned 16 Bits 1. Negative readings are rounded to 0V. 2. PRECISION RANGE is the range over which the noise is less than MAX NOISE. 3. NOISE FREE RESOLUTION is a measure of the noise level within the PRECISION RANGE. 680412fc For more information www.linear.com/LTC6804-1 23 LTC6804-1/LTC6804-2 Operation Measuring Cell Voltages (ADCV Command) tREFUP The ADCV command initiates the measurement of the battery cell inputs, pins C0 through C12. This command has options to select the number of channels to measure and the ADC mode. See the section on Commands for the ADCV command format. Figure 3 illustrates the timing of ADCV command which measures all twelve cells. After the receipt of the ADCV command to measure all 12 cells, ADC1 sequentially measures the bottom 6 cells. ADC2 sequentially measures the top 6 cells. After the cell measurements are complete, each channel is calibrated to remove any offset errors. SERIAL INTERFACE MEASURE C10 TO C9 CALIBRATE C10 TO C9 ADC1 MEASURE C4 TO C3 CALIBRATE C4 TO C3 t1M t1C 680412 F04 Figure 4. Timing for ADCV Command Measuring 2 Cells Table 6. Conversion Times for ADCV Command Measuring Only 2 Cells in Different Modes CONVERSION TIMES (in s) Figure 4 illustrates the timing of the ADCV command that measures only two cells. Table 6 shows the conversion time for ADCV command measuring only 2 cells. t1C indicates the total conversion time for this command. SERIAL INTERFACE ADC2 t0 Table 5 shows the conversion times for the ADCV command measuring all 12 cells. The total conversion time is given by t6C which indicates the end of the calibration step. tREFUP ADCV + PEC MODE t0 t1M t1C 27kHz 0 57 201 14kHz 0 86 230 7kHz 0 144 405 3kHz 0 260 521 2kHz 0 493 754 26Hz 0 29,817 33,568 tCYCLE tSKEW2 ADCV + PEC ADC2 MEASURE C7 TO C6 MEASURE C8 TO C7 MEASURE C12 TO C11 CALIBRATE C7 TO C6 CALIBRATE C8 TO C7 CALIBRATE C12 TO C11 ADC1 MEASURE C1 TO C0 MEASURE C2 TO C1 MEASURE C6 TO C5 CALIBRATE C1 TO C0 CALIBRATE C2 TO C1 CALIBRATE C6 TO C5 t1M t0 t2M t5M t6M t1C t2C t5C t6C 680412 F03 Figure 3. Timing for ADCV Command Measuring All 12 Cells Table 5. Conversion Times for ADCV Command Measuring All 12 Cells in Different Modes CONVERSION TIMES (in s) MODE t0 t1M t2M t5M t6M t1C t2C t5C t6C 27kHz 0 57 103 243 290 432 568 975 1,113 14kHz 0 86 162 389 465 606 742 1,149 1,288 7kHz 0 144 278 680 814 1,072 1,324 2,080 2,335 3kHz 0 260 511 1,262 1,512 1,770 2,022 2,778 3,033 2kHz 0 493 976 2,425 2,908 3,166 3,418 4,175 4,430 26Hz 0 29,817 59,623 149,043 178,850 182,599 186,342 197,571 201,317 24 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation Under/Overvoltage Monitoring Whenever the C inputs are measured, the results are compared to undervoltage and overvoltage thresholds stored in memory. If the reading of a cell is above the overvoltage limit, a bit in memory is set as a flag. Similarly, measurement results below the undervoltage limit cause a flag to be set. The overvoltage and undervoltage thresholds are stored in the configuration register group. The flags are stored in the status register group B. Auxiliary (GPIO) Measurements (ADAX Command) The ADAX command initiates the measurement of the GPIO inputs. This command has options to select which GPIO input to measure (GPIO1-5) and which ADC mode. The ADAX command also measures the 2nd reference. There are options in the ADAX command to measure each GPIO and the 2nd reference separately or to measure all 5 GPIOs and the 2nd reference in a single command. See the section on commands for the ADAX command format. All auxiliary measurements are relative to the V- pin voltage. This command can be used to read external temperature tREFUP SERIAL INTERFACE by connecting the temperature sensors to the GPIOs. These sensors can be powered from the 2nd reference which is also measured by the ADAX command, resulting in precise ratiometric measurements. Figure 5 illustrates the timing of the ADAX command measuring all GPIOs and the 2nd reference. Since all the 6 measurements are carried out on ADC1 alone, the conversion time for the ADAX command is similar to the ADCV command. Measuring Cell Voltages and GPIOs (ADCVAX Command) The ADCVAX command combines twelve cell measurements with two GPIO measurements (GPIO1 and GPIO2). This command simplifies the synchronization of battery cell voltage and current measurements when current sensors are connected to GPIO1 or GPIO2 inputs. Figure 6 illustrates the timing of the ADCVAX command. See the section on commands for the ADCVAX command format. The synchronization of the current and voltage measurements, tSKEW1, in FAST MODE is within 208s. tCYCLE tSKEW ADAX + PEC ADC2 MEASURE GPIO1 ADC1 MEASURE GPIO2 t1M t0 MEASURE 2ND REF t2M t5M CALIBRATE GPIO1 t6M CALIBRATE GPIO2 t1C CALIBRATE 2ND REF t2C t5C t6C 680412 F05 Figure 5. Timing for ADAX Command Measuring All GPIOs and 2nd Reference Table 7. Conversion Times for ADAX Command Measuring All GPIOs and 2nd Reference in Different Modes CONVERSION TIMES (in s) MODE t0 t1M t2M t5M t6M t1C t2C t5C t6C 27kHz 0 57 103 243 290 432 568 975 1,113 14kHz 0 86 162 389 465 606 742 1,149 1,288 7kHz 0 144 278 680 814 1,072 1,324 2,080 2,335 3kHz 0 260 511 1,262 1,512 1,770 2,022 2,778 3,033 2kHz 0 493 976 2,425 2,908 3,166 3,418 4,175 4,430 26Hz 0 29,817 59,623 149,043 178,850 182,599 186,342 197,571 201,317 680412fc For more information www.linear.com/LTC6804-1 25 LTC6804-1/LTC6804-2 Operation tREFUP SERIAL INTERFACE tCYCLE tSKEW1 tSKEW1 ADCVAX + PEC ADC2 MEASURE C7 TO C6 MEASURE C8 TO C7 MEASURE C9 TO C8 ADC1 MEASURE C1 TO C0 MEASURE C2 TO C1 MEASURE C3 TO C2 t1M t0 t2M MEASURE GPIO1 t3M MEASURE GPIO2 t4M MEASURE C10 TO C9 MEASURE C11 TO C10 MEASURE C12 TO C11 CALIBRATE MEASURE C4 TO C3 MEASURE C5 TO C4 MEASURE C6 TO C5 CALIBRATE t5M t6M t7M t8M t8C 680412 F06 Figure 6. Timing of ADCVAX Command Table 8. Conversion and Synchronization Times for ADCVAX Command in Different Modes SYNCHRONIZATION TIME (s) CONVERSION TIMES (in s) MODE t0 t1M t2M t3M t4M t5M t6M t7M t8M t8C tSKEW1 27kHz 0 57 106 155 216 265 326 375 424 1,564 208 14kHz 0 86 161 237 320 396 479 555 630 1,736 310 7kHz 0 144 278 412 553 687 828 962 1,096 3,133 543 3kHz 0 260 511 761 1,018 1,269 1,526 1,777 2,027 4,064 1009 2kHz 0 493 976 1,459 1,949 2,432 2,923 3,406 3,888 5,925 1939 26Hz 0 29,817 59,623 89,430 119,244 149,051 178,864 208,671 238,478 268,442 119234 Table 8 shows the conversion and synchronization time for the ADCVAX command in different modes. The total conversion time for the command is given by t8C. Data Acquisition System Diagnostics The battery monitoring data acquisition system is comprised of the multiplexers, ADCs, 1st reference, digital filters, and memory. To ensure long term reliable performance there are several diagnostic commands which can be used to verify the proper operation of these circuits. tREFUP SERIAL INTERFACE Measuring Internal Device Parameters (ADSTAT Command) The ADSTAT command is a diagnostic command that measures the following internal device parameters: sum of all cells (SOC), internal die temperature (ITMP), analog power supply (VA) and the digital power supply (VD). These parameters are described in the section below. All 6 ADC modes are available for these conversions. See the section on commands for the ADSTAT command format. Figure 7 illustrates the timing of the ADSTAT command measuring all 4 internal device parameters. tCYCLE tSKEW ADSTAT + PEC ADC2 MEASURE SOC ADC1 t0 MEASURE ITMP t1M MEASURE VD t2M t3M CALIBRATE SOC t4M CALIBRATE ITMP t1C CALIBRATE VD t2C t3C t4C 680412 F07 Figure 7. Timing for ADSTAT Command Measuring SOC, ITMP, VA, VD 26 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation Table 9 shows the conversion time of the ADSTAT command measuring all 4 internal parameters. t4C indicates the total conversion time for the ADSTAT command. Sum of Cells Measurement: The sum of all cells measurement is the voltage between C12 and C0 with a 20:1 attenuation. The 16-bit ADC value of sum of cells measurement (SOC) is stored in status register group A. Any potential difference between the CO and V- pins results in an error in the SOC measurement equal to this difference. From the SOC value, the sum of all cell voltage measurements is given by: Sum of all Cells = SOC * 20 * 100V Internal Die Temperature: The ADSTAT command can measure the internal die temperature. The 16-bit ADC value of the die temperature measurement (ITMP) is stored in status register group A. From ITMP the actual die temperature is calculated using the expression: Internal Die Temperature (C) = (ITMP) * 100V/ (7.5mV)C - 273C Power Supply Measurements: The ADSTAT command is also used to measure the analog power supply (VREG) and digital power supply (VREGD). The 16-bit ADC value of the analog power supply measurement (VA) is stored in Status Register Group A. The 16-bit ADC value of the digital power supply measurement (VD) is stored in status register group B. From VA and VD, the power supply measurements are given by: Analog power supply measurement (VREG) = VA * 100V Digital power supply measurement (VREGD) = VD * 100V The nominal range of VREG is 4.5V to 5.5V. The nominal range of VREGD is 2.7V to 3.6V. Issuing an ADSTAT command with CHST = 100 runs an ADC measurement of just the digital supply (VREGD). This is not recommended following an ADCV command. With large cell voltages, running the ADSTAT command with CST = 100 following an ADCV command with CH = 000 (all cells) can cause the LTC6804 to perform a power on reset. If using the ADSTAT command with CHST = 100, it is necessary to run an ADCV command with CH = 001 prior to running the ADSTAT command with CHST = 100. This charges the high voltage multiplexer to a low potential before the VREGD measurement is executed. To save time, this sacrificial ADCV command run prior to running the VREGD measurement can be executed in FAST mode (MD = 01). Accuracy Check Measuring an independent voltage reference is the best means to verify the accuracy of a data acquisition system. The LTC6804 contains a 2nd reference for this purpose. The ADAX command will initiate the measurement of the 2nd reference. The results are placed in auxiliary register group B. The range of the result depends on the ADC measurement accuracy and the accuracy of the 2nd reference, including thermal hysteresis and long term drift. Readings outside the range 2.985 to 3.015 indicate the system is out of its specified tolerance. MUX Decoder Check The diagnostic command DIAGN ensures the proper operation of each multiplexer channel. The command cycles through all channels and sets the MUXFAIL bit to 1 in status register group B if any channel decoder fails. The MUXFAIL bit is set to 0 if the channel decoder passes the Table 9. Conversion Times for ADSTAT Command Measuring SOC, ITMP, VA, VD CONVERSION TIMES (in s) MODE t0 t1M t2M t3M t4M t1C t2C t3C t4C 27kHz 0 57 103 150 197 338 474 610 748 14kHz 0 86 162 237 313 455 591 726 865 7kHz 0 144 278 412 546 804 1,056 1,308 1,563 3kHz 0 260 511 761 1,011 1,269 1,522 1,774 2,028 2kHz 0 493 976 1,459 1,942 2,200 2,452 2,705 2,959 26Hz 0 29,817 59,623 89,430 119,237 122,986 126,729 130,472 134,218 680412fc For more information www.linear.com/LTC6804-1 27 LTC6804-1/LTC6804-2 Operation test. The MUXFAIL bit is also set to 1 on power-up (POR) or after a CLRSTAT command. test signal passes through the digital filter and is converted to a 16-bit value. The 1-bit test signal undergoes the same digital conversion as the regular 1-bit pulse from the modulator, so the conversion time for any self test command is exactly the same as the corresponding regular ADC conversion command. The 16-bit ADC value is stored in the same register groups as the regular ADC conversion command. The test signals are designed to place alternating one-zero patterns in the registers. Table 10 provides a list of the self test commands. If the digital filters and memory are working properly, then the registers will contain the values shown in Table 10. For more details see the section Commands. The DIAGN command takes about 400s to complete if the core is in REFUP state and about 4.5ms to complete if the core is in STANDBY state. The polling methods described in the section Polling Methods can be used to determine the completion of the DIAGN command. Digital Filter Check The delta-sigma ADC is composed of a 1-bit pulse density modulator followed by a digital filter. A pulse density modulated bit stream has a higher percentage of 1s for higher analog input voltages. The digital filter converts this high frequency 1-bit stream into a single 16-bit word. This is why a delta-sigma ADC is often referred to as an oversampling converter. ADC Clear Commands LTC6804 has 3 clear commands - CLRCELL, CLRAUX and CLRSTAT. These commands clear the registers that store all ADC conversion results. The self test commands verify the operation of the digital filters and memory. Figure 8 illustrates the operation of the ADC during self test. The output of the 1-bit pulse density modulator is replaced by a 1-bit test signal. The The CLRCELL command clears cell voltage register group A, B, C and D. All bytes in these registers are set to 0xFF by CLRCELL command. PULSE DENSITY MODULATED BIT STREAM MUX ANALOG INPUT 1-BIT MODULATOR DIGITAL FILTER 1 SELF TEST PATTERN GENERATOR 16 RESULTS REGISTER TEST SIGNAL 680412 F08 Figure 8. Operation of LTC6804 ADC Self Test Table 10. Self Test Command Summary COMMAND SELF TEST OPTION 27kHz 14kHz 7kHz 3kHz 2kHz 26Hz CVST ST[1:0]=01 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 ST[1:0]=10 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA AXST STATST 28 RESULTS REGISTER GROUPS OUTPUT PATTERN IN DIFFERENT ADC MODES ST[1:0]=01 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 ST[1:0]=10 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA ST[1:0]=01 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 ST[1:0]=10 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA C1V to C12V (CVA, CVB, CVC, CVD) G1V to G5V, REF (AUXA, AUXB) SOC, ITMP, VA, VD (STATA, STATB) 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation The CLRAUX command clears auxiliary register group A and B. All bytes in these registers are set to 0xFF by CLRAUX command. The CLRSTAT command clears status register group A and B except the REVCODE and RSVD bits in status register group B. A read back of REVCODE will return the revision code of the part. All OV flags, UV flags, MUXFAIL bit, and THSD bit in status register group B are set to 1 by CLRSTAT command. The THSD bit is set to 0 after RDSTATB command. The registers storing SOC, ITMP, VA and VD are all set to 0xFF by CLRSTAT command. time to create a large enough difference for the algorithm to detect an open connection. This can be accomplished by running more than two ADOW commands in steps 1 and 2, or by using filtered mode conversions instead of normal mode conversions. Use Table 11 to determine how many conversions are necessary: Table 11 Number of ADOW Commands Required in Steps 1 and 2 EXTERNAL C PIN CAPACITANCE Open-Wire Check (ADOW Command) The ADOW command is used to check for any open wires between the ADCs in the LTC6804 and the external cells. This command performs ADC conversions on the C pin inputs identically to the ADCV command, except two internal current sources sink or source current into the two C pins while they are being measured. The pull-up (PUP) bit of the ADOW command determines whether the current sources are sinking or sourcing 100A. The following simple algorithm can be used to check for an open wire on any of the 13 C pins (see Figure 9): 1) Run the 12-cell command ADOW with PUP = 1 at least twice. Read the cell voltages for cells 1 through 12 once at the end and store them in array CELLPU(n). 2) Run the 12-cell command ADOW with PUP = 0 at least twice. Read the cell voltages for cells 1 through 12 once at the end and store them in array CELLPD(n). 3) Take the difference between the pull-up and pull-down measurements made in above steps for cells 2-12: CELL(n) = CELLPU(n) - CELLPD(n). 4) For all values of n from 1 to 11: If CELL(n+1) < -400mV, then C(n) is open. If the CELLPU(1) = 0.0000, then C(0) is open. If the CELLPD(12) = 0.0000, then C(12) is open. The above algorithm detects open wires using normal mode conversions with as much as 10nF of capacitance remaining on the LTC6804 side of the open wire. However, if more external capacitance is on the open C pin, then the length of time that the open wire conversions are ran in steps 1 and 2 must be increased to give the 100A current sources NORMAL MODE FILTERED MODE 10nF 2 2 100nF 10 2 1F 100 2 C 1+ROUNDUP(C/10nF) 2 V+ 1 + 2 + 4 + 6 + 8 + 10 + 12 + 14 + 16 + 18 + 20 + 22 + V+ C12 100A C11 PUP = 1 C10 26 ADC2 6-CELL MUX C9 PUP = 0 C8 100A C7 C6 24 LTC6804 V+ C6 V- V- V+ V+ C5 100A C4 PUP = 1 C3 C2 ADC1 6-CELL MUX PUP = 0 C1 100A C0 V- 30 V- 31 V- 680412 F09 Figure 9. Open-Wire Detection Circuitry 680412fc For more information www.linear.com/LTC6804-1 29 LTC6804-1/LTC6804-2 Operation Thermal Shutdown Watchdog and Software Discharge Timer To protect the LTC6804 from overheating, there is a thermal shutdown circuit included inside the IC. If the temperature detected on the die goes above approximately 150C, the thermal shutdown circuit trips and resets the configuration register group to its default state. This turns off all discharge switches. When a thermal shutdown event has occurred, the THSD bit in status register group B will go high. This bit is cleared after a read operation has been performed on the status register group B (RDSTATB command). The CLRSTAT command sets the THSD bit high for diagnostic purposes, but does not reset the configuration register group. When there is no wake-up signal (see Figure 21) for more than 2 seconds, the watchdog timer expires. This resets configuration register bytes CFGR0-CFGR3 in all cases. CFGR4 and CFGR5 are reset by the watchdog timer when the software timer is disabled. The WDT pin is pulled high by the external pull-up when the watchdog time elapses. The watchdog timer is always enabled and is reset by a qualified wake-up signal. Revision Code and Reserved Bits To enable the software timer, SWTEN pin needs to be tied high to VREG (Figure 10). The discharge switches can now be kept ON for the programmed time duration that is determined by the DCTO value written to the configuration register. Table 12 shows the various time settings and the corresponding DCTO value. Table 13 summarizes the status of the configuration register group after a watchdog timer or software timer event. The status register group B contains a 4-bit revision code and 2 reserved bits. If software detection of device revision is necessary, then contact the factory for details. Otherwise, the code can be ignored. In all cases, however, the values of all bits must be used when calculating the packet error code (PEC) on data reads. The software discharge timer is used to keep the discharge switches turned ON for programmable time duration. If the software timer is being used, the discharge switches are not turned OFF when the watchdog timer is activated. LTC6804 DCTEN TIMEOUT EN SW TIMER CLK OSC 16Hz VREG 1 DCTO > 0 SWTEN RST 2 (POR OR WRCFG DONE OR TIMEOUT) RST1 (RESETS DCTO, DCC) WDTRST && ~DCTEN WDT RST2 (RESETS REFUP, VUV, VOV) WDTPD WATCHDOG TIMER CLK RST OSC 16Hz WDTRST (POR OR VALID COMMAND) 680412 F10 Figure 10. Watchdog and Software Discharge Timer Table 12. DCTO Settings DCTO 0 1 2 3 4 5 6 7 8 9 A B C D E F Time Min Disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90 120 30 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation Table 14 Table 13 SWTEN = 0, DCTO = XXXX WATCHDOG TIMER SOFTWARE TIMER Resets CFGR0-5 When It Activates Disabled DCTO (READ VALUE) TIME LEFT (MIN) 0 Disabled (or) Timer Has Timed Out 1 0 < Timer 0.5 2 0.5 < Timer 1 3 1 < Timer 2 4 2 < Timer 3 Unlike the watchdog timer, the software timer does not reset when there is a valid command. The software timer can only be reset after a valid WRCFG (write configuration register) command. There is a possibility that the software timer will expire in the middle of some commands. 5 3 < Timer 4 6 4 < Timer 5 7 5 < Timer 10 8 10 < Timer 15 9 15 < Timer 20 If software timer activates in the middle of WRCFG command, the configuration register resets as per Table 14. However, at the end of the valid WRCFG command, the new data is copied to the configuration register. The new data is not lost when the software timer is activated. A 20 < Timer 30 B 30 < Timer 40 SWTEN = 1, DCTO = 0000 SWTEN = 1, DCTO ! = 0000 Resets CFGR0-5 When It Activates Disabled Resets CFGR0-3 When It Activates Resets CFGR4-5 When It Fires If software timer activates in the middle of RDCFG command, the configuration register group resets as per Table 14. As a result, the read back data from bytes CRFG4 and CRFG5 could be corrupted. I2C/SPI Master on LTC6804 Using GPIOS The I/O ports GPIO3, GPIO4 and GPIO5 on LTC6804-1 and LTC6804-2 can be used as an I2C or SPI master port to communicate to an I2C or SPI slave. In the case of an I2C master, GPIO4 and GPIO5 form the SDA and SCL ports of the I2C interface respectively. In the case of a SPI master, GPIO3, GPIO5 and GPIO4 become the chip select (CSBM), clock (SCKM) and data (SDIOM) ports of the SPI interface respectively. The SPI master on LTC6804 supports only SPI mode 3 (CHPA = 1, CPOL = 1). C 40 < Timer 60 D 60 < Timer 75 E 75 < Timer 90 F 90 < Timer 120 The GPIOs are open drain outputs, so an external pull-up is required on these ports to operate as an I2C or SPI master. It is also important to write the GPIO bits to 1 in the CFG register group so these ports are not pulled low internally by the device. COMM Register LTC6804 has a 6-byte COMM register as shown in Table 15. This register stores all data and control bits required for I2C or SPI communication to a slave. The COMM register contains 3 bytes of data Dn[7:0] to be transmitted to or received from the slave device. ICOMn [3:0] specify control actions before transmitting/receiving the data byte. FCOMn [3:0] specify control actions after transmitting/ receiving the data byte. Table 15. COMM Register Memory Map REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COMM0 RD/WR ICOM0[3] ICOM0[2] ICOM0[1] ICOM0[0] D0[7] D0[6] D0[5] D0[4] COMM1 RD/WR D0[3] D0[2] D0[1] D0[0] FCOM0[3] FCOM0[2] FCOM0[1] FCOM0[0] COMM2 RD/WR ICOM1[3] ICOM1[2] ICOM1[1] ICOM1[0] D1[7] D1[6] D1[5] D1[4] COMM3 RD/WR D1[3] D1[2] D1[1] D1[0] FCOM1[3] FCOM1[2] FCOM1[1] FCOM1[0] COMM4 RD/WR ICOM2[3] ICOM2[2] ICOM2[1] ICOM2[0] D2[7] D2[6] D2[5] D2[4] COMM5 RD/WR D2[3] D2[2] D2[1] D2[0] FCOM2[3] FCOM2[2] FCOM2[1] FCOM2[0] 680412fc For more information www.linear.com/LTC6804-1 31 LTC6804-1/LTC6804-2 Operation Table 16. Write Codes for ICOMn[3:0] and FCOMn[3:0] on I2C Master CONTROL BITS ICOMn[3:0] FCOMn[3:0] CODE ACTION DESCRIPTION 0110 START Generate a START Signal on I2C Port Followed By Data Transmission 0001 STOP Generate a STOP Signal on I2C port 0000 BLANK Proceed Directly to Data Transmission on I2C Port 0111 No Transmit Release SDA and SCL and Ignore the Rest of the Data 0000 Master ACK Master Generates an ACK Signal on Ninth Clock Cycle 1000 Master NACK Master Generates a NACK Signal on Ninth Clock Cycle 1001 Master NACK + STOP Master Generates a NACK Signal Followed by STOP Signal Table 17. Write Codes for ICOMn[3:0] and FCOMn[3:0] on SPI Master CONTROL BITS ICOMn[3:0] FCOMn[3:0] CODE ACTION DESCRIPTION 1000 CSBM low Generates a CSBM Low Signal on SPI Port (GPIO3) 1001 CSBM high Generates a CSBM High Signal on SPI Port (GPIO3) 1111 No Transmit Releases the SPI Port and Ignores the Rest of the Data X000 CSBM low Holds CSBM Low at the End of Byte Transmission 1001 CSBM high Transitions CSBM High at the End of Byte Transmission If the bit ICOMn[3] in the COMM register is set to 1 the part becomes an I2C master and if the bit is set to 0 the part becomes a SPI master. Table 16 describes the valid write codes for ICOMn[3:0] and FCOMn[3:0] and their behavior when using the part as an I2C master. Table 17 describes the valid codes for ICOMn[3:0] and FCOMn[3:0] and their behavior when using the part as a SPI master. Note that only the codes listed in Tables 16 and 17 are valid for ICOMn[3:0] and FCOMn[3:0]. Writing any other code that is not listed in Tables 16 and 17 to ICOMn[3:0] and FCOMn[3:0] may result in unexpected behavior on the I2C and SPI ports. COMM Commands Three commands help accomplish I2C or SPI communication to the slave device: WRCOMM, STCOMM, RDCOMM WRCOMM Command: This command is used to write data to the COMM register. This command writes 6 bytes of data to the COMM register. The PEC needs to be written 32 at the end of the data. If the PEC does not match, all data in the COMM register is cleared to 1's when CSB goes high. See the section Bus Protocols for more details on a write command format. STCOMM Command: This command initiates I2C/SPI communication on the GPIO ports. The COMM register contains 3 bytes of data to be transmitted to the slave. During this command, the data bytes stored in the COMM register are transmitted to the slave I2C or SPI device and the data received from the I2C or SPI device is stored in the COMM register. This command uses GPIO4 (SDA) and GPIO5 (SCL) for I2C communication or GPIO3 (CSBM), GPIO4 (SDIOM) and GPIO5 (SCKM) for SPI communication. The STCOMM command is to be followed by 24 clock cycles for each byte of data to be transmitted to the slave device while holding CSB low. For example, to transmit 3 bytes of data to the slave, send STCOMM command and its PEC followed by 72 clock cycles. Pull CSB high at the end of the 72 clock cycles of STCOMM command. During I2C or SPI communication, the data received from the slave device is updated in the COMM register. 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation RDCOMM Command: The data received from the slave device can be read back from the COMM register using the RDCOMM command. The command reads back 6 bytes of data followed by the PEC. See the section Bus Protocols for more details on a read command format. Table 18 describes the possible read back codes for ICOMn[3:0] and FCOMn[3:0] when using the part as an I2C master. Dn[7:0] contains the data byte either transmitted by the I2C master or received from the I2C slave. In case of the SPI master, the read back codes for ICOMn[3:0] and FCOMn[3:0] are always 0111 and 1111 respectively. Dn[7:0] contains the data byte either transmitted by the SPI master or received from the SPI slave. Table 18. Read Codes for ICOMn[3:0] and FCOMn[3:0] on I2C Master CONTROL BITS ICOMn[3:0] FCOMn[3:0] CODE DESCRIPTION 0110 Master Generated a START Signal 0001 Master Generated a STOP Signal 0000 Blank, SDA Was Held Low Between Bytes 0111 Blank, SDA Was Held High Between Bytes 0000 Master Generated an ACK Signal 0111 Slave Generated an ACK Signal 1111 Slave Generated a NACK Signal 0001 Slave Generated an ACK Signal, Master Generated a STOP Signal 1001 Slave Generated a NACK Signal, Master Generated a STOP Signal Figure 11 illustrates the operation of LTC6804 as an I2C or SPI master using the GPIOs. LTC6804-1/LTC6804-2 I2C/SPI SLAVE STCOMM RDCOMM GPIO PORT COMM REGISTER PORT A WRCOMM Any number of bytes can be transmitted to the slave in groups of 3 bytes using these commands. The GPIO ports will not get reset between different STCOMM commands. However, if the wait time between the commands is greater than 2 seconds, the watchdog will timeout and reset the ports to their default values. To transmit several bytes of data using an I2C master, a START signal is only required at the beginning of the entire data stream. A STOP signal is only required at the end of the data stream. All intermediate data groups can use a BLANK code before the data byte and an ACK/NACK signal as appropriate after the data byte. SDA and SCL will not get reset between different STCOMM commands. To transmit several bytes of data using SPI master, a CSBM low signal is sent at the beginning of the 1st data byte. CSBM can be held low or taken high for intermediate data groups using the appropriate code on FCOMn[3:0]. A CSBM high signal is sent at the end of the last byte of data. CSBM, SDIOM and SCKM will not get reset between different STCOMM commands. Figure 12 shows the 24 clock cycles following STCOMM command for an I2C master in different cases. Note that if ICOMn[3:0] specified a STOP condition, after the STOP signal is sent, the SDA and SCL lines are held high and all data in the rest of the word is ignored. If ICOMn[3:0] is a NO TRANSMIT, both SDA and SCL lines are released, and rest of the data in the word is ignored. This is used when a particular device in the stack does not have to communicate to a slave. Figure 13 shows the 24 clock cycles following STCOMM command for a SPI master. Similar to the I2C master, if ICOMn[3:0] specified a CSBM HIGH or a NO TRANSMIT condition, the CSBM, SCKM and SDIOM lines of the SPI master are released and the rest of the data in the word is ignored. 680412 F11 Figure 11. LTC6804 I2C/SPI Master Using GPIOs 680412fc For more information www.linear.com/LTC6804-1 33 LTC6804-1/LTC6804-2 Operation tCLK t4 t3 (SCK) START NACK + STOP BLANK NACK START ACK SCL (GPIO5) SDA (GPIO4) SCL (GPIO5) SDA (GPIO4) SCL (GPIO5) SDA (GPIO4) STOP SCL (GPIO5) SDA (GPIO4) NO TRANSMIT SCL (GPIO5) SDA (GPIO4) 680412 F12 Figure 12. STCOMM Timing Diagram for an I2C Master tCLK t4 t3 (SCK) CSBM LOW CSBM HIGH LOW CSBM (GPIO3) SCKM (GPIO5) SDIOM (GPIO4) CSBM LOW HIGH CSBM LOW CSBM (GPIO3) SCKM (GPIO5) SDIOM (GPIO4) CSBM HIGH/NO TRANSMIT CSBM (GPIO3) SCKM (GPIO5) SDIOM (GPIO4) 680412 F13 Figure 13. STCOMM Timing Diagram for a SPI Master 34 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation Timing Specifications of I2C and SPI master The timing of the LTC6804 I2C or SPI master will be controlled by the timing of the communication at the LTC6804's primary SPI interface. Table 19 shows the I2C master timing relationship to the primary SPI clock. Table 20 shows the SPI master timing specifications. Table 19. I2C Master Timing TIMING RELATIONSHIP TIMING I2C MASTER TO PRIMARY SPI SPECIFICATIONS AT PARAMETER INTERFACE tCLK = 1s Max 500kHz SCL Clock Frequency 1/(2 * tCLK) t3 Min 200ns tHD; STA tCLK Min 1s tLOW tCLK Min 1s tHIGH tCLK + t4* Min 1.03s tSU; STA t 4* Min 30ns tHD; DAT t3 Min 1s tSU; DAT tCLK + t4* Min 1.03s tSU; STO 3 * tCLK Min 3s tBUF *Note: When using isoSPI, t4 is generated internally and is a minimum of 30ns. Also, t3 = tCLK - t4. When using SPI, t3 and t4 are the low and high times of the SCK input, each with a specified minimum of 200ns. Serial Interface Overview There are two types of serial ports on the LTC6804, a standard 4-wire serial peripheral interface (SPI) and a 2-wire isolated interface (isoSPI). Pins 41 through 44 are configurable as 2-wire or 4-wire serial port, based on the state of the ISOMD pin. There are two versions of the LTC6804: the LTC6804-1 and the LTC6804-2. The LTC6804-1 is used in a daisy chain configuration, and the LTC6804-2 is used in an addressable bus configuration. The LTC6804-1 provides a second isoSPI interface using pins 45 through 48. The LTC6804-2 uses pins 45 through 48 to set the address of the device, by tying these pins to V- or VREG. Table 20. SPI Master Timing TIMING RELATIONSHIP TIMING TO PRIMARY SPI SPECIFICATIONS SPI MASTER PARAMETER INTERFACE AT tCLK = 1s Min 200ns SDIOM Valid to SCKM t3 Rising Setup Min 1.03s SDIOM Valid from SCKM tCLK + t4* Rising Hold Min 1s SCKM Low tCLK Min 1s SCKM High tCLK Min 2s SCKM Period (SCKM_Low 2 * tCLK + SCKM_High) Min 3s CSBM Pulse Width 3 * tCLK Min 5.03s SCKM Rising to CSBM 5 * tCLK + t4* Rising Min 200ns CSBM Falling to SCKM t3 Falling Min 1.2s CSBM Falling to SCKM tCLK + t3 Rising SCKM Falling to SDIOM Master requires < tCLK Valid *Note: When using isoSPI, t4 is generated internally and is a minimum of 30ns. Also, t3 = tCLK - t4. When using SPI, t3 and t4 are the low and high times of the SCK input, each with a specified minimum of 200ns. 680412fc For more information www.linear.com/LTC6804-1 35 LTC6804-1/LTC6804-2 Operation 4-Wire Serial Peripheral Interface (SPI) Physical Layer 2-Wire Isolated Interface (isoSPI) Physical Layer External Connections The 2-wire interface provides a means to interconnect LTC6804 devices using simple twisted pair cabling. The interface is designed for low packet error rates when the cabling is subjected to high RF fields. Isolation is achieved through an external transformer. Connecting ISOMD to V- configures serial Port A for 4-wire SPI. The SDO pin is an open drain output which requires a pull-up resistor tied to the appropriate supply voltage (Figure 14). Timing The 4-wire serial port is configured to operate in a SPI system using CPHA = 1 and CPOL = 1. Consequently, data on SDI must be stable during the rising edge of SCK. The timing is depicted in Figure 15. The maximum data rate is 1Mbps. V+ C12 S12 LTC6804-1 Standard SPI signals are encoded into differential pulses. The strength of the transmission pulse and the threshold level of the receiver are set by two external resistors, RB1 and RB2. The values of the resistors allow the user to trade off power dissipation for noise immunity. V+ IPB IMB DAISY-CHAIN SUPPORT ICMP 5k C12 LTC6804-2 A3 A2 A1 S12 C11 IBIAS S11 SDO (NC) MISO C10 SDI (NC) S10 SCK (IPA) C9 CSB (IMA) CS S9 ISOMD C8 WDT C8 WDT S8 DRIVE S8 DRIVE C7 VREG C7 VREG S7 SWTEN S7 SWTEN C6 VREF1 C6 VREF1 S6 VREF2 S6 VREF2 C5 GPIO5 C5 GPIO5 S5 GPIO4 S5 GPIO4 C4 V- C4 V- S4 V- S4 V- C3 GPIO3 C3 GPIO3 S3 GPIO2 S3 GPIO2 C2 GPIO1 C2 GPIO1 S2 C0 S2 C0 C1 S1 C1 ADDRESS PINS 5k C11 A0 S11 SDO (IBIAS) MISO MOSI C10 SDI (ICMP) MOSI CLK S10 SCK (IPA) CLK C9 CSB (IMA) CS S9 ISOMD VDD MPU VDD MPU S1 680412 F14 Figure 14. 4-Wire SPI Configuration 36 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation t1 t4 t2 t3 t6 t7 SCK SDI D3 D2 D1 D0 D7...D4 D3 t5 CSB t8 SDO D4 D3 D2 D1 D0 D7...D4 PREVIOUS COMMAND D3 680412 F15 CURRENT COMMAND Figure 15. Timing Diagram of 4-Wire Serial Peripheral Interface LTC6804 VREG WAKEUP CIRCUIT (ON PORT A) 35k Tx = +1 LOGIC AND MEMORY SCK CSB IDLE VICMP/3 + 167mV IDLE Tx * 20 * IB IPA OR IPB Tx = 0 SDO SDI + - 35k Tx = -1 PULSE ENCODER/ DECODER IMA OR IMB Rx = +1 Rx = 0 Rx = -1 1 COMPARATOR THRESHOLD = * VICMP 2 RM * * + IB - + - IBIAS 2V ICMP RB1 0.5x RB2 Figure 16. isoSPI Interface Figure 16 illustrates how the isoSPI circuit operates. A 2V reference drives the IBIAS pin. External resistors RB1 and RB2 create the reference current IB. This current sets the drive strength of the transmitter. RB1 and RB2 also form a voltage divider of the 2V reference at the ICMP pin. This sets the threshold voltage of the receiver circuit. Transmitted current pulses are converted into voltage by termination resistor RM (in parallel with the characteristic impedance of the cable). 680412 F16 External Connections The LTC6804-1 has 2 serial ports which are called Port B and Port A. Port B is always configured as a 2-wire interface (master). The final device in the daisy chain does not use this port, and it should be terminated into RM. Port A is either a 2-wire or 4-wire interface (slave), depending on the connection of the ISOMD pin. 680412fc For more information www.linear.com/LTC6804-1 37 LTC6804-1/LTC6804-2 Operation Figure 17a is an example of a robust interconnection of multiple identical PCBs, each containing one LTC68041. Note the termination in the final device in the daisy chain. The microprocessor is located on a separate PCB. To achieve 2-wire isolation between the microprocessor PCB and the 1st LTC6804-1 PCB, use the LTC6820 support IC. The LTC6820 is functionally equivalent to the diagram in Figure 16. The LTC6804-2 has a single serial port (Port A) which can be 2-wire or 4-wire, depending on the state of the ISOMD pin. When configured for 2-wire communications, several devices can be connected in a multi-drop configuration, as shown in Figure 17b. The LTC6820 IC is used to interface the MPU (master) to the LTC6804-2's (slaves). Using a Single LTC6804 When only one LTC6804 is needed, the LTC6804-2 is recommended. It does not have isoSPI Port B, so it requires fewer external components and consumes less power, especially when Port A is configured as a 4-wire interface. However, the LTC6804-1 can be used as a single (non daisy-chained) device if the second isoSPI port (Port B) is properly biased and terminated, as shown in Figure 18c. ICMP should not be tied to GND, but can be tied directly to IBIAS. A bias resistance (2k to 20k) is required for IBIAS. Do not tie IBIAS directly to VREG or V-. Finally, IPB and IMB should be terminated into a 100 resistor (not tied to VREG or V-). Selecting Bias Resistors The adjustable signal amplitude allows the system to trade power consumption for communication robustness, and the adjustable comparator threshold allows the system to account for signal losses. The isoSPI transmitter drive current and comparator voltage threshold are set by a resistor divider (RBIAS = RB1 + RB2) between the IBIAS and V-. The divided voltage is connected to the ICMP pin which sets the comparator threshold to 1/2 of this voltage (VICMP). When either isoSPI interface is enabled (not IDLE) IBIAS is held at 2V, causing a current IB to flow out of the IBIAS pin. The IP and IM pin drive currents are 20 * IB. 38 As an example, if divider resistor RB1 is 2.8k and resistor RB2 is 1.21k (so that RBIAS = 4k), then: IB = 2V = 0.5mA RB1 +RB2 IDRV =IIP =IIM = 20 *IB = 10mA VICMP = 2V * RB2 =I *R = 603mV RB1 +RB2 B B2 VTCMP = 0.5 * VICMP = 302mV In this example, the pulse drive current IDRV will be 10mA, and the receiver comparators will detect pulses with IP-IM amplitudes greater than 302mV. If the isolation barrier uses 1:1 transformers connected by a twisted pair and terminated with 120 resistors on each end, then the transmitted differential signal amplitude () will be: VA =IDRV * RM = 0.6V 2 (This result ignores transformer and cable losses, which may reduce the amplitude). isoSPI Pulse Detail Two LTC6804 devices can communicate by transmitting and receiving differential pulses back and forth through an isolation barrier. The transmitter can output three voltage levels: +VA, 0V, and -VA. A positive output results from IP sourcing current and IM sinking current across load resistor RM. A negative voltage is developed by IP sinking and IM sourcing. When both outputs are off, the load resistance forces the differential output to 0V. To eliminate the DC signal component and enhance reliability, the isoSPI uses two different pulse lengths. This allows for four types of pulses to be transmitted, as shown in Table 21. A +1 pulse will be transmitted as a positive pulse followed by a negative pulse. A -1 pulse will be transmitted as a negative pulse followed by a positive pulse. The duration of each pulse is defined as t1/2PW, since each is half of the required symmetric pair. (The total isoSPI pulse duration is 2 * t1/2PW). 680412fc For more information www.linear.com/LTC6804-1 IPB GPIO5 GPIO4 V- V- GPIO3 GPIO2 GPIO1 C0 S1 A3 C5 S5 C4 S4 C3 S3 C2 S2 C1 V+ V- V- GPIO3 GPIO2 GPIO1 C0 S1 C4 S4 C3 S3 C2 S2 C1 GPIO4 V- V- GPIO3 GPIO2 GPIO1 C0 S1 S5 C4 S4 C3 S3 C2 S2 C1 * * * * * IPB VREF1 VREF2 GPIO5 GPIO4 V- V- GPIO3 GPIO2 GPIO1 C0 S1 C5 S5 C4 S4 C3 S3 C2 S2 C1 SWTEN S7 S6 VREG C7 C6 WDT DRIVE S9 S8 ISOMD C9 C8 SDI (NC) CSB (IMA) S10 SDO (NC) SCK (IPA) S11 C10 ICMP IBIAS IMB C11 LTC6804-1 S12 C12 V+ S12 C11 S11 A0 SDO (IBIAS) S11 For more information www.linear.com/LTC6804-1 C10 C6 S6 C5 S5 C4 GPIO5 GPIO4 V- C5 S5 C4 C3 S3 C2 S2 C1 V GPIO3 GPIO2 GPIO1 C0 S1 S4 C3 S3 C2 S2 C1 S4 S7 VREF1 VREF2 S6 S7 C6 C7 SWTEN VREG S8 C7 C8 WDT S9 ISOMD S9 DRIVE C9 S8 S10 SCK (IPA) CSB (IMA) C9 C8 C10 SDI (ICMP) S10 S1 C0 GPIO1 GPIO2 GPIO3 V - V- GPIO4 GPIO5 VREF2 VREF1 SWTEN VREG DRIVE WDT ISOMD CSB (IMA) SCK (IPA) SDI (ICMP) SDO (IBIAS) A0 A1 S1 C0 GPIO1 GPIO2 GPIO3 V - V- GPIO4 GPIO5 VREF2 VREF1 SWTEN VREG DRIVE WDT ISOMD CSB (IMA) SCK (IPA) SDI (ICMP) SDO (IBIAS) A0 A1 ADDRESS = 0x1 C1 S2 C2 S3 C3 S4 C4 S5 C5 S6 C6 S7 C7 S8 C8 S9 C9 S10 C10 S11 C11 S12 C12 V+ A0 A1 A2 A3 S1 C0 GPIO1 GPIO2 GPIO3 V - V- GPIO4 GPIO5 VREF2 VREF1 SWTEN VREG DRIVE WDT ISOMD CSB (IMA) SCK (IPA) SDI (ICMP) SDO (IBIAS) LTC6804-2 Figure 17b. Multi-Drop Configuration Using LTC6804-2 C1 S2 C2 S3 C3 S4 C4 S5 C5 S6 C6 S7 C7 S8 C8 S9 C9 S10 C10 S11 C11 S12 A2 A3 ADDRESS = 0x0 * A1 LTC6804-2 * C12 V+ * C11 ADDRESS = 0x2 * A2 A3 * S12 LTC6804-2 * - GPIO5 C5 * V+ GPIO4 S5 VREF1 VREF2 SWTEN S7 S6 VREG C7 C6 WDT S9 DRIVE ISOMD C9 S8 CSB (IMA) S10 C8 SDI (NC) SDO (NC) SCK (IPA) S11 C10 ICMP IBIAS C11 * * C12 ADDRESS = 0x3 GPIO5 C5 IPB IMB S12 LTC6804-1 * Figure 17a. Transformer-Isolated Daisy-Chain Configuration Using LTC6804-1 VREF1 VREF2 SWTEN S7 S6 VREG C7 C6 WDT S9 DRIVE ISOMD C9 S8 CSB (IMA) S10 C8 SDI (NC) SDO (NC) SCK (IPA) S11 C10 ICMP IBIAS C12 V+ * * C12 IPB IMB C11 LTC6804-1 S12 C12 V+ * A2 LTC6804-2 VREF1 VREF2 SWTEN S7 S6 VREG C7 C6 WDT S9 DRIVE ISOMD C9 S8 CSB (IMA) S10 C8 SDI (NC) SDO (NC) S11 SCK (IPA) C11 C10 ICMP IBIAS S12 * IMB * LTC6804-1 * C12 * V+ POL MISO IP GND CS IM IP SLOW IBIAS ICMP MSTR SCK MOSI MISO POL PHA VDD LTC6820 EN MPU VDD IM VDDS CS CLK MOSI GND CS SLOW ICMP IBIAS SCK MSTR MOSI MISO PHA VDD LTC6820 EN MPU VDD VDDS CS CLK MOSI MISO * * * * 680412 F18 680412 F17 LTC6804-1/LTC6804-2 Operation 680412fc 39 LTC6804-1/LTC6804-2 Operation TERMINATED UNUSED PORT RM * MISO MOSI CLK CS MPU LTC6820 VDD VDDS POL EN PHA MSTR ICMP IBIAS MISO GND MOSI SLOW SCK CS IP IM * * VDD MISO MOSI CLK CS MPU * ADDRESS = 0x0 LTC6804-2 V+ A3 C12 A2 S12 A1 C11 A0 S11 SDO(IBIAS) C10 SDI(ICMP) S10 SCK(IPA) C9 CSB(IMA) S9 ISOMD C8 WDT S8 DRIVE C7 VREG S7 SWTEN C6 VREF1 S6 VREF2 C5 GPIO5 S5 GPIO4 C4 V- S4 V- C3 GPIO3 S3 GPIO2 C2 GPIO1 S2 C0 C1 S1 VDD * * LTC6804-1 V+ IPB C12 IMB S12 ICMP C11 IBIAS S11 SDO(NC) C10 SDI(NC) S10 SCK(IPA) C9 CSB(IMA) S9 ISOMD C8 WDT S8 DRIVE C7 VREG S7 SWTEN C6 VREF1 S6 VREF2 C5 GPIO5 S5 GPIO4 C4 V- S4 V- C3 GPIO3 S3 GPIO2 C2 GPIO1 S2 C0 C1 S1 LTC6820 VDD VDDS POL EN PHA MSTR ICMP IBIAS MISO GND MOSI SLOW SCK CS IP IM 680412 F18a Figure 18a. Single-Device LTC6804-1 Using 2-Wire Port A * * 680412 F18b Figure 18b. Single-Device LTC6804-2 Using 2-Wire Port A TERMINATED UNUSED PORT LTC6804-1 V+ IPB C12 IMB S12 ICMP C11 IBIAS S11 SDO(NC) C10 SDI(NC) S10 SCK(IPA) C9 CSB(IMA) S9 ISOMD C8 WDT S8 DRIVE C7 VREG S7 SWTEN C6 VREF1 S6 VREF2 C5 GPIO5 S5 GPIO4 C4 V- S4 V- C3 GPIO3 S3 GPIO2 C2 GPIO1 S2 C0 C1 S1 100 20k ADDRESS = 0x0 LTC6804-2 V+ A3 C12 A2 S12 A1 C11 A0 S11 SDO(IBIAS) C10 SDI(ICMP) S10 SCK(IPA) C9 CSB(IMA) S9 ISOMD C8 WDT S8 DRIVE C7 VREG S7 SWTEN C6 VREF1 S6 VREF2 C5 GPIO5 S5 GPIO4 C4 V- S4 V- C3 GPIO3 S3 GPIO2 C2 GPIO1 S2 C0 C1 S1 REQUIRED BIAS 5k VDD MISO MOSI CLK CS MPU 680412 F18c Figure 18c. Single-Device LTC6804-1 Using 4-Wire Port A 40 5k VDD MISO MOSI CLK CS MPU 680412 F18d Figure 18d. Single-Device LTC6804-2 Using 4-Wire Port A 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation Table 21. isoSPI Pulse Types Table 22. LTC6804-1 Port B (Master) isoSPI Port Function COMMUNICATION EVENT (PORT A SPI) TRANSMITTED PULSE (PORT B isoSPI) 0V CSB Rising Long +1 +VA (150ns) 0V CSB Falling Long -1 +VA (50ns) -VA (50ns) 0V SCK Rising Edge, SDI = 1 Short +1 -VA (50ns) +VA (50ns) 0V SCK Rising Edge, SDI = 0 Short -1 PULSE TYPE FIRST LEVEL (t1/2PW) SECOND LEVEL (t1/2PW) ENDING LEVEL Long +1 +VA (150ns) -VA (150ns) Long -1 -VA (150ns) Short +1 Short -1 A host microcontroller does not have to generate isoSPI pulses to use this 2-wire interface. The first LTC6804 in the system can communicate to the microcontroller using the 4-wire SPI interface on its Port A, then daisy-chain to other LTC6804s using the 2-wire isoSPI interface on its Port B. Alternatively, an LTC6820 can be used to translate the SPI signals into isoSPI pulses. On the other side of the isolation barrier (i.e. at the other end of the cable), the 2nd LTC6804 will have ISOMD = VREG. Its Port A operates as a slave isoSPI interface. It receives each transmitted pulse and reconstructs the SPI signals internally, as shown in Table 23. In addition, during a READ command this port may transmit return data pulses. LTC6804-1 Operation with Port A Configured for SPI Table 23. LTC6804-1 Port A (Slave) isoSPI Port Function When the LTC6804-1 is operating with port A as an SPI (ISOMD = V-), the SPI detects one of four communication events: CSB falling, CSB rising, SCK rising with SDI = 0, and SCK rising with SDI = 1. Each event is converted into one of the four pulse types for transmission through the LTC6804-1 daisy chain. Long pulses are used to transmit CSB changes and short pulses are used to transmit data, as explained in Table 22. RECEIVED PULSE (PORT A isoSPI) INTERNAL SPI PORT ACTION RETURN PULSE Long +1 Drive CSB High None Long -1 Drive CSB Low Short +1 1. Set SDI = 1 2. Pulse SCK Short -1 Pulse if Reading a 0 bit Short -1 1. Set SDI = 0 2. Pulse SCK (No Return Pulse if Not in READ Mode or if Reading a 1 bit) +1 PULSE +VA +VTCMP t1/2PW VIP - VIM t1/2PW -VTCMP tINV -VA -1 PULSE +VA +VTCMP tINV t1/2PW VIP - VIM -VTCMP t1/2PW -VA 680412 F19 Figure 19. isoSPI Pulse Detail 680412fc For more information www.linear.com/LTC6804-1 41 LTC6804-1/LTC6804-2 Operation The lower isoSPI port (Port A) never transmits long (CSB) pulses. Furthermore, a slave isoSPI port will only transmit short -1 pulses, never a +1 pulse. The master port recognizes a null response as a logic 1. This allows for multiple slave devices on a single cable without risk of collisions (Multidrop). Bits Wn-W0 refers to the 16-bit command code and the 16-bit PEC of a READ command. At the end of bit W0 the 3 parts decode the READ command and begin shifting out data which is valid on the next rising edge of clock SCK. Bits Xn-X0 refer to the data shifted out by Part 1. Bits Yn-Y0 refer to the data shifted out by Part 2 and bits Zn-Z0 refer to the data shifted out by Part 3. All this data is read back from the SDO port on Part 1 in a daisy-chained fashion. Figure 20 shows the isoSPI timing diagram for a READ command to daisy-chained LTC6804-1 parts. The ISOMD pin is tied to V- on the bottom part so its Port A is configured as a SPI port (CSB, SCK, SDI and SDO). The isoSPI signals of three stacked devices are shown, labeled with the port (A or B) and part number. Note that ISO B1 and ISO A2 is actually the same signal, but shown on each end of the transmission cable that connects parts 1 and 2. Likewise, ISO B2 and ISO A3 is the same signal, but with the cable delay shown between parts 2 and 3. Waking Up the Serial Interface The serial ports (SPI or isoSPI) will enter the low power IDLE state if there is no activity on Port A for a time of tIDLE. The WAKEUP circuit monitors activity on pins 41 and 42. If ISOMD = V-, Port A is in SPI mode. Activity on the CSB or SCK pin will wake up the SPI interface. If ISOMD = VREG, COMMAND CSB READ DATA t7 t6 t1 SDI t5 t2 tCLK t4 SCK t3 t8 tRISE SDO t11 Xn t10 Xn-1 Z0 t9 t10 Wn ISO B1 W0 Wn ISO A2 Yn W0 Yn-1 Yn Yn-1 tRTN tDSY(CS) Wn ISO B2 tDSY(CS) tDSY(D) W0 Wn ISO A3 0 1000 W0 2000 Zn Zn 3000 Zn-1 Zn-1 4000 5000 6000 680412 F20 Figure 20. isoSPI Timing Diagram 42 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation Port A is in isoSPI mode. Differential activity on IPA-IMB wakes up the isoSPI interface. The LTC6804 will be ready to communicate when the isoSPI state changes to READY within tWAKE or tREADY, depending on the Core state (see Figure 1 and state descriptions for details.) Figure 21 illustrates the timing and the functionally equivalent circuit. Common mode signals will not wake up the serial interface. The interface is designed to wake up after receiving a large signal single-ended pulse, or a low-amplitude symmetric pulse. The differential signal |SCK(IPA) - CSB(IMA)|, must be at least VWAKE = 200mV for a minimum duration of tDWELL = 240ns to qualify as a wake up signal that powers up the serial interface. Waking a Daisy Chain -- Method 1 The LTC6804-1 sends a Long +1 pulse on Port B after it is ready to communicate. In a daisy-chained configuration, this pulse wakes up the next device in the stack which will, in turn, wake up the next device. If there are `N' devices in the stack, all the devices are powered up within the time N * tWAKE or N * tREADY, depending on the Core State. For large stacks, the time N * tWAKE may be equal to or larger than tIDLE. In this case, after waiting longer than the time of N * tWAKE, the host may send another dummy byte and wait for the time N * tREADY, in order to ensure that all devices are in the READY state. Method 1 can be used when all devices on the daisy chain are in the IDLE state. This guarantees that they propagate the wake-up signal up the daisy chain. However, this method will fail to wake up all devices when a device in the middle of the chain is in the READY state instead of IDLE. When this happens, the device in READY state will not propagate the wake-up pulse, so the devices above it will remain IDLE. This situation can occur when attempting to wake up the daisy chain after only tIDLE of idle time (some devices may be IDLE, some may not). Waking a Daisy Chain -- Method 2 A more robust wake-up method does not rely on the built-in wake-up pulse, but manually sends isoSPI traffic for enough time to wake the entire daisy chain. At minimum, a pair of long isoSPI pulses (-1 and +1) is needed for each device, separated by more than tREADY or tWAKE (if the core state is STANDBY or SLEEP, respectively), but less than tIDLE. This allows each device to wake up and propagate the next pulse to the following device. This method works even if some devices in the chain are not in the IDLE state. In practice, implementing method 2 requires toggling the CSB pin (of the LTC6820, or bottom LTC6804-1 with ISOMD = 0) to generate the long isoSPI pulses. Alternatively, dummy commands (such as RDCFG) can be executed to generate the long isoSPI pulses. REJECTS COMMON MODE NOISE CSB OR IMA SCK OR IPA VWAKE = 200mV |SCK(IPA) - CSB(IMA)| tDWELL= 240ns WAKE-UP STATE LOW POWER MODE tIDLE > 4.5ms tREADY < 10s CSB OR IMA SCK OR IPA LOW POWER MODE OK TO COMMUNICATE tDWELL = 240ns DELAY RETRIGGERABLE tIDLE = 5.5ms ONE-SHOT WAKE-UP 680412 F21 Figure 21. Wake-Up Detection and IDLE Timer 680412fc For more information www.linear.com/LTC6804-1 43 LTC6804-1/LTC6804-2 Operation Data Link Layer 3. Update the 15-bit PEC as follows All Data transfers on LTC6804 occur in byte groups. Every byte consists of 8 bits. Bytes are transferred with the most significant bit (MSB) first. CSB must remain low for the entire duration of a command sequence, including between a command byte and subsequent data. On a write command, data is latched in on the rising edge of CSB. PEC [14] = IN14, Network Layer PEC [9] = PEC [8], PEC [13] = PEC [12], PEC [12] = PEC [11], PEC [11] = PEC [10], PEC [10] = IN10, PEC [8] = IN8, Packet Error Code PEC [7] = IN7, The packet error code (PEC) is a 15-bit cyclic redundancy check (CRC) value calculated for all of the bits in a register group in the order they are passed, using the initial PEC seed value of 000000000010000 and the following characteristic polynomial: x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1. To calculate the 15-bit PEC value, a simple procedure can be established: PEC [6] = PEC [5], PEC [5] = PEC [4], PEC [4] = IN4, PEC [3] = IN3, PEC [2] = PEC [1], 1. Initialize the PEC to 000000000010000 (PEC is a 15-bit register group) 2. For each bit DIN coming into the PEC register group, set IN0 = DIN XOR PEC [14] IN3 = IN0 XOR PEC [2] PEC [1] = PEC [0], PEC [0] = IN0 4. Go back to step 2 until all the data is shifted. The final PEC (16 bits) is the 15-bit value in the PEC register with a 0 bit appended to its LSB Figure 22 illustrates the algorithm described above. An example to calculate the PEC for a 16-bit word (0x0001) is listed in Table 24. The PEC for 0x0001 is computed as 0x3D6E after stuffing a 0 bit at the LSB. For longer data streams, the PEC is valid at the end of the last bit of data sent to the PEC register. IN4 = IN0 XOR PEC [3] IN7 = IN0 XOR PEC [6] IN8 = IN0 XOR PEC [7] IN10 = IN0 XOR PEC [9] IN14 = IN0 XOR PEC [13] O/P I/P XOR GATE I/P X PEC REGISTER BIT X DIN 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 680412 F22 Figure 22. 15-Bit PEC Computation Circuit 44 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation LTC6804 calculates PEC for any command or data received and compares it with the PEC following the command or data. The command or data is regarded as valid only if the PEC matches. LTC6804 also attaches the calculated PEC at the end of the data it shifts out. Table 25 shows the format of PEC while writing to or reading from LTC6804. register group to two daisy-chained devices (primary device P, stacked device S), the data will be sent to the primary device on Port A in the following order: CFGR0(S), ... , CFGR5(S), PEC0(S), PEC1(S), CFGR0(P), ..., CFGR5(P), PEC0(P), PEC1(P) After a read command for daisy-chained devices, each device shifts out its data and the PEC that it computed for its data on Port A followed by the data received on Port B. For example, when reading status register group B from two daisy-chained devices (primary device P, stacked device S), the primary device sends out data on port A in the following order: While writing any command to LTC6804, the command bytes CMD0 and CMD1 (See Table 32 and Table 33) and the PEC bytes PEC0 and PEC1 are sent on Port A in the following order: CMD0, CMD1, PEC0, PEC1 After a broadcast write command to daisy-chained LTC6804-1 devices, data is sent to each device followed by the PEC. For example, when writing the configuration STBR0(P), ..., STBR5(P), PEC0(P), PEC1(P), STBR0(S), ... , STBR5(S), PEC0(S), PEC1(S) Table 24. PEC Calculation for 0x0001 PEC[14] 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 PEC[13] 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 PEC[12] 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 PEC[11] 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 PEC[10] 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 1 PEC[9] 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 PEC[8] PEC[7] PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[0] IN14 IN10 IN8 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 PEC Word IN7 IN4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 IN3 IN0 DIN Clock Cycle 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0 6 0 0 0 7 0 0 0 8 0 0 0 9 1 1 0 10 1 1 0 11 1 1 0 12 0 1 0 13 0 1 0 14 0 1 1 15 16 680412fc For more information www.linear.com/LTC6804-1 45 LTC6804-1/LTC6804-2 Operation Table 25. Write/Read PEC Format NAME RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PEC0 RD/WR PEC[14] PEC[13] PEC[12] PEC[11] PEC[10] PEC[9] PEC[8] PEC[7] PEC1 RD/WR PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[0] 0 Broadcast vs Address Commands CONFIGURATION TYPE OF COMMAND DEVICE INTERFACE READ WRITE POLL LTC6804-2 SPI AddressOnly Address or Broadcast Address or Broadcast (Address/Parallel) isoSPI LTC6804-1 (Daisy-Chain) SPI or isoSPI AddressOnly Broadcast-Only N/A The LTC6804-2 will not return data pulses when using broadcast commands in isoSPI mode. Therefore, ADC commands will execute, but polling will not work. Address Commands (LTC6804-2 Only) An address command is one in which only the addressed device on the bus responds. Address commands are used only with LTC6804-2 parts. All commands are compatible with addressing. See Bus Protocols for Address command format. Broadcast Commands (LTC6804-1 or LTC6804-2) A broadcast command is one to which all devices on the bus will respond, regardless of device address. This command format can be used with LTC6804-1 and LTC6804-2 parts. See Bus Protocols for Broadcast command format. With broadcast commands all devices can be sent commands simultaneously. In parallel (LTC6804-2) configurations, broadcast commands are useful for initiating ADC conversions or for sending write commands when all parts are being written with the same data. The polling function (automatic at the end of ADC commands, or manual using the PLADC command) can also be used with broadcast commands, but only with parallel SPI interfaces. Polling is not compatible with parallel isoSPI. Likewise, broadcast read commands should not be used in a parallel configuration (either SPI or isoSPI). 46 Daisy-chained (LTC6804-1) configurations support broadcast commands only, because they have no addressing. All devices in the chain receive the command bytes simultaneously. For example, to initiate ADC conversions in a stack of devices, a single ADCV command is sent, and all devices will start conversions at the same time. For read and write commands, a single command is sent, and then the stacked devices effectively turn into a cascaded shift register, in which data is shifted through each device to the next device in the stack. See the Serial Programming Examples section. Polling Methods The simplest method to determine ADC completion is for the controller to start an ADC conversion and wait for the specified conversion time to pass before reading the results. Polling is not supported with daisy-chain communication (LTC6804-1). In parallel configurations that communicate in SPI mode (ISOMD pin tied low), there are two methods of polling. The first method is to hold CSB low after an ADC conversion command is sent. After entering a conversion command, the SDO line is driven low when the device is busy performing conversions (Figure 23). SDO is pulled high when the device completes conversions. However, the SDO will also go back high when CSB goes high even if the device has not completed the conversion. An addressed device drives the SDO line based on its status alone. A problem with this method is that the controller is not free to do other serial communication while waiting for ADC conversions to complete. The next method overcomes this limitation. The controller can send an ADC start command, perform other tasks, and then send a poll ADC converter status (PLADC) command to determine the status of the ADC conversions (Figure 24). After entering the PLADC command, SDO will go low if the device is busy performing conversions. SDO is pulled high at the end of conversions. However, the SDO will also 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation go high when CSB goes high even if the device has not completed the conversion. See Programming Examples on how to use the PLADC command with devices in parallel configuration. In parallel configurations that communicate in isoSPI mode, the low side port transmits a data pulse only in response to a master isoSPI pulse received by it. So, after entering an address command in either method of polling described above, isoSPI data pulses are sent to the part to update the conversion status. These pulses can be sent using LTC6820 by simply clocking its SCK pin. In response to this pulse, the LTC6804-2 returns an isoSPI pulse if it is still busy performing conversions and does not return a pulse if it has completed conversions. If a CSB high isoSPI pulse is sent to the LTC6804-2, it exits the polling command. Note that broadcast poll commands are not compatible with parallel isoSPI. Bus Protocols Protocol Format: The protocol formats for both broadcast and address commands are depicted in Table 27 through Table 31. Table 26 is the key for reading the protocol diagrams. Table 26. Protocol Key CMD0 First Command Byte (See Tables 32 and 33) CMD1 Second Command Byte (See Tables 32 and 33) PEC0 First PEC Byte (See Table 25) PEC1 Second PEC Byte (See Table 25) n Number of Bytes ... Continuation of Protocol Master to Slave Slave to Master tCYCLE CSB SCK SDI MSB(CMD) BIT 14(CMD) LSB(PEC) SDO 680412 F23 Figure 23. SDO Polling After an ADC Conversion Command CSB SCK SDI MSB(CMD) BIT 14(CMD) LSB(PEC) SDO CONVERSION DONE 680412 F24 Figure 24. SDO Polling Using PLADC Command 680412fc For more information www.linear.com/LTC6804-1 47 LTC6804-1/LTC6804-2 Operation Command Format: The formats for the broadcast and address commands are shown in Table 32 and Table 33 respectively. The 11-bit command code CC[10:0] is the same for a broadcast or an address command. A list of all the command codes is shown in Table 34. A broadcast command has a value 0 for CMD0[7] through CMD0[3]. An address command has a value 1 for CMD0[7] followed by the 4-bit address of the device (a3, a2, a1, a0) in bits CMD0[6:3]. An addressed device will respond to an address command only if the physical address of the device on pins A3 to A0 match the address specified in the address command. The PEC for broadcast and address commands must be computed on the entire 16-bit command (CMD0 and CMD1). Commands Table 34 lists all the commands and its options for both LTC6804-1 and LTC6804-2 Table 27. Broadcast/Address Poll Command 8 8 8 8 CMD0 CMD1 PEC0 PEC1 Poll Data Table 28. Broadcast Write Command (LTC6804-1) 8 8 8 8 8 CMD0 CMD1 PEC0 PEC1 Data Byte Low 8 8 8 8 ... Data Byte High PEC0 PEC1 Shift Byte 1 8 8 8 ... Data Byte High PEC0 PEC1 8 8 8 8 ... Data Byte High PEC0 PEC1 Shift Byte 1 8 8 8 ... Data Byte High PEC0 PEC1 8 ... Shift Byte n Table 29.Broadcast/Address Write Command (LTC6804-2) 8 8 8 8 8 CMD0 CMD1 PEC0 PEC1 Data Byte Low Table 30. Broadcast Read Command (LTC6804-1) 8 8 8 8 8 CMD0 CMD1 PEC0 PEC1 Data Byte Low 8 ... Shift Byte n Table 31. Address Read Command (LTC6804-2) 8 8 8 8 8 CMD0 CMD1 PEC0 PEC1 Data Byte Low Table 32. Broadcast Command Format NAME RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CMD0 WR 0 0 0 0 0 CC[10] CC[9] CC[8] CMD1 WR CC[7] CC[6] CC[5] CC[4] CC[3] CC[2] CC[1] CC[0] Table 33. Address Command Format NAME RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CMD0 WR 1 a3* a2* a1* a0* CC[10] CC[9] CC[8] CMD1 WR CC[7] CC[6] CC[5] CC[4] CC[3] CC[2] CC[1] CC[0] *ax is Address Bit x 48 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation Table 34. Command Codes COMMAND DESCRIPTION NAME CC[10:0] - COMMAND CODE 10 9 8 7 6 5 4 3 2 1 0 Write Configuration Register Group WRCFG 0 0 0 0 0 0 0 0 0 0 1 Read Configuration Register Group RDCFG 0 0 0 0 0 0 0 0 0 1 0 Read Cell Voltage Register Group A RDCVA 0 0 0 0 0 0 0 0 1 0 0 Read Cell Voltage Register Group B RDCVB 0 0 0 0 0 0 0 0 1 1 0 Read Cell Voltage Register Group C RDCVC 0 0 0 0 0 0 0 1 0 0 0 Read Cell Voltage Register Group D RDCVD 0 0 0 0 0 0 0 1 0 1 0 Read Auxiliary Register Group A RDAUXA 0 0 0 0 0 0 0 1 1 0 0 Read Auxiliary Register Group B RDAUXB 0 0 0 0 0 0 0 1 1 1 0 Read Status Register Group A RDSTATA 0 0 0 0 0 0 1 0 0 0 0 Read Status Register Group B RDSTATB 0 0 0 0 0 0 1 0 0 1 0 Start Cell Voltage ADC Conversion and Poll Status ADCV 0 1 MD[1] MD[0] 1 1 DCP 0 CH[2] CH[1] CH[0] Start Open Wire ADC Conversion and Poll Status ADOW 0 1 MD[1] MD[0] PUP 1 DCP 1 CH[2] CH[1] CH[0] Start Self-Test Cell Voltage Conversion and Poll Status CVST 0 1 MD[1] MD[0] ST[1] ST[0] 0 0 1 1 1 Start GPIOs ADC Conversion and Poll Status ADAX 1 0 MD[1] MD[0] 1 1 0 0 CHG [2] CHG [1] CHG [0] Start Self-Test GPIOs Conversion and Poll Status AXST 1 0 MD[1] MD[0] ST[1] ST[0] 0 0 1 1 1 Start Status group ADC Conversion and Poll Status ADSTAT 1 0 MD[1] MD[0] 1 1 0 1 Start Self-Test Status group Conversion and Poll Status STATST 1 0 MD[1] MD[0] ST[1] ST[0] 0 1 1 1 1 Start Combined Cell Voltage and GPIO1, GPIO2 Conversion and Poll Status ADCVAX 1 0 MD[1] MD[0] 1 1 DCP 1 1 1 1 Clear Cell Voltage Register Group CLRCELL 1 1 1 0 0 0 1 0 0 0 1 Clear Auxiliary Register Group CLRAUX 1 1 1 0 0 0 1 0 0 1 0 Clear Status Register Group CLRSTAT 1 1 1 0 0 0 1 0 0 1 1 Poll ADC Conversion Status PLADC 1 1 1 0 0 0 1 0 1 0 0 Diagnose MUX and Poll Status DIAGN 1 1 1 0 0 0 1 0 1 0 1 Write COMM Register Group WRCOMM 1 1 1 0 0 1 0 0 0 0 1 Read COMM Register Group RDCOMM 1 1 1 0 0 1 0 0 0 1 0 Start I2C/SPI Communication STCOMM 1 1 1 0 0 1 0 0 0 1 1 CHST [2] CHST [1] CHST [0] 680412fc For more information www.linear.com/LTC6804-1 49 LTC6804-1/LTC6804-2 Operation Table 35. Command Bit Descriptions NAME MD[1:0] DESCRIPTION ADC Mode VALUES MD ADCOPT(CFGR0[0]) = 0 ADCOPT (CFGR0[0]) = 1 01 27kHz Mode (Fast) 14kHz Mode 10 7kHz Mode (Normal) 3kHz Mode 11 26Hz Mode (Filtered) 2kHz Mode DCP DCP Discharge Permitted 0 Discharge Not Permitted 1 Discharge Permitted Total Conversion Time in the 6 ADC Modes CH CH[2:0] PUP Cell Selection for ADC Conversion Pull-Up/Pull-Down Current for Open-Wire Conversions 000 All Cells 001 Cell 1 and Cell 7 010 Cell 2 and Cell 8 011 Cell 3 and Cell 9 100 Cell 4 and Cell 10 101 Cell 5 and Cell 11 110 Cell 6 and Cell 12 27kHz 14kHz 7kHz 3kHz 2kHz 26Hz 1.1ms 1.3ms 2.3ms 3.0ms 4.4ms 201ms 201s 230s 405s 501s 754s 34ms 27kHz 14kHz 2kHz 26Hz PUP 0 Pull-Down Current 1 Pull-Up Current Self-Test Conversion Result ST[1:0] Self-Test Mode Selection ST 7kHz 3kHz 01 Self Test 1 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 10 Self test 2 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA Total Conversion Time in the 6 ADC Modes CHG CHG[2:0] GPIO Selection for ADC Conversion 000 GPIO 1-5, 2nd Ref 001 GPIO 1 010 GPIO 2 011 GPIO 3 100 GPIO 4 101 GPIO 5 110 2nd Reference 27kHz 14kHz 7kHz 3kHz 2kHz 26Hz 1.1ms 1.3ms 2.3ms 3.0ms 4.4ms 201ms 201s 230s 405s 501s 754s 34ms Total Conversion Time in the 6 ADC Modes CHST CHST[2:0]* Status Group Selection 000 SOC, ITMP, VA, VD 001 SOC 010 ITMP 011 VA 100 VD** 27kHz 14kHz 7kHz 3kHz 2kHz 26Hz 748s 865s 1.6ms 2.0ms 3.0ms 134ms 201s 230s 405s 501s 754s 34ms *Note: Valid options for CHST in ADSTAT command are 0-4. If CHST is set to 5/6 in ADSTAT command, the LTC6804 treats it like ADAX command with CHG = 5/6. **The use of the ADSTAT command with CHST = 100 is not recommended unless special care is taken. See the Data Acquisition System Diagnostics section for more details. 50 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation Table 36. Configuration Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 CFGR0 RD/WR GPIO5 GPIO4 GPIO3 GPIO2 CFGR1 RD/WR VUV[7] VUV[6] VUV[5] VUV[4] CFGR2 RD/WR VOV[3] VOV[2] VOV[1] VOV[0] CFGR3 RD/WR VOV[11] VOV[10] VOV[9] CFGR4 RD/WR DCC8 DCC7 DCC6 CFGR5 RD/WR DCTO[3] DCTO[2] BIT 6 BIT 3 BIT 2 BIT 1 BIT 0 GPIO1 REFON SWTRD ADCOPT VUV[3] VUV[2] VUV[1] VUV[0] VUV[11] VUV[10] VUV[9] VUV[8] VOV[8] VOV[7] VOV[6] VOV[5] VOV[4] DCC5 DCC4 DCC3 DCC2 DCC1 DCTO[1] DCTO[0] DCC12 DCC11 DCC10 DCC9 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Table 37. Cell Voltage Register Group A REGISTER RD/WR BIT 7 CVAR0 RD C1V[7] C1V[6] C1V[5] C1V[4] C1V[3] C1V[2] C1V[1] C1V[0] CVAR1 RD C1V[15] C1V[14] C1V[13] C1V[12] C1V[11] C1V[10] C1V[9] C1V[8] CVAR2 RD C2V[7] C2V[6] C2V[5] C2V[4] C2V[3] C2V[2] C2V[1] C2V[0] CVAR3 RD C2V[15] C2V[14] C2V[13] C2V[12] C2V[11] C2V[10] C2V[9] C2V[8] CVAR4 RD C3V[7] C3V[6] C3V[5] C3V[4] C3V[3] C3V[2] C3V[1] C3V[0] CVAR5 RD C3V[15] C3V[14] C3V[13] C3V[12] C3V[11] C3V[10] C3V[9] C3V[8] BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Table 38. Cell Voltage Register Group B REGISTER RD/WR BIT 7 CVBR0 RD C4V[7] C4V[6] C4V[5] C4V[4] C4V[3] C4V[2] C4V[1] C4V[0] CVBR1 RD C4V[15] C4V[14] C4V[13] C4V[12] C4V[11] C4V[10] C4V[9] C4V[8] CVBR2 RD C5V[7] C5V[6] C5V[5] C5V[4] C5V[3] C5V[2] C5V[1] C5V[0] CVBR3 RD C5V[15] C5V[14] C5V[13] C5V[12] C5V[11] C5V[10] C5V[9] C5V[8] CVBR4 RD C6V[7] C6V[6] C6V[5] C6V[4] C6V[3] C6V[2] C6V[1] C6V[0] CVBR5 RD C6V[15] C6V[14] C6V[13] C6V[12] C6V[11] C6V[10] C6V[9] C6V[8] Table 39. Cell Voltage Register Group C REGISTER CVCR0 RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RD C7V[7] C7V[6] C7V[5] C7V[4] C7V[3] C7V[2] C7V[1] C7V[0] CVCR1 RD C7V[15] C7V[14] C7V[13] C7V[12] C7V[11] C7V[10] C7V[9] C7V[8] CVCR2 RD C8V[7] C8V[6] C8V[5] C8V[4] C8V[3] C8V[2] C8V[1] C8V[0] CVCR3 RD C8V[15] C8V[14] C8V[13] C8V[12] C8V[11] C8V[10] C8V[9] C8V[8] CVCR4 RD C9V[7] C9V[6] C9V[5] C9V[4] C9V[3] C9V[2] C9V[1] C9V[0] CVCR5 RD C9V[15] C9V[14] C9V[13] C9V[12] C9V[11] C9V[10] C9V[9] C9V[8] Table 40. Cell Voltage Register Group D REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CVDR0 RD C10V[7] C10V[6] C10V[5] C10V[4] C10V[3] C10V[2] C10V[1] C10V[0] CVDR1 RD C10V[15] C10V[14] C10V[13] C10V[12] C10V[11] C10V[10] C10V[9] C10V[8] CVDR2 RD C11V[7] C11V[6] C11V[5] C11V[4] C11V[3] C11V[2] C11V[1] C11V[0] CVDR3 RD C11V[15] C11V[14] C11V[13] C11V[12] C11V[11] C11V[10] C11V[9] C11V[8] CVDR4 RD C12V[7] C12V[6] C12V[5] C12V[4] C12V[3] C12V[2] C12V[1] C12V[0] CVDR5 RD C12V[15] C12V[14] C12V[13] C12V[12] C12V[11] C12V[10] C12V[9] C12V[8] 680412fc For more information www.linear.com/LTC6804-1 51 LTC6804-1/LTC6804-2 Operation Table 41. Auxiliary Register Group A REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 AVAR0 RD G1V[7] G1V[6] G1V[5] G1V[4] G1V[3] G1V[2] G1V[1] G1V[0] AVAR1 RD G1V[15] G1V[14] G1V[13] G1V[12] G1V[11] G1V[10] G1V[9] G1V[8] AVAR2 RD G2V[7] G2V[6] G2V[5] G2V[4] G2V[3] G2V[2] G2V[1] G2V[0] AVAR3 RD G2V[15] G2V[14] G2V[13] G2V[12] G2V[11] G2V[10] G2V[9] G2V[8] AVAR4 RD G3V[7] G3V[6] G3V[5] G3V[4] G3V[3] G3V[2] G3V[1] G3V[0] AVAR5 RD G3V[15] G3V[14] G3V[13] G3V[12] G3V[11] G3V[10] G3V[9] G3V[8] BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Table 42. Auxiliary Register Group B REGISTER RD/WR BIT 7 AVBR0 RD G4V[7] G4V[6] G4V[5] G4V[4] G4V[3] G4V[2] G4V[1] G4V[0] AVBR1 RD G4V[15] G4V[14] G4V[13] G4V[12] G4V[11] G4V[10] G4V[9] G4V[8] AVBR2 RD G5V[7] G5V[6] G5V[5] G5V[4] G5V[3] G5V[2] G5V[1] G5V[0] AVBR3 RD G5V[15] G5V[14] G5V[13] G5V[12] G5V[11] G5V[10] G5V[9] G5V[8] AVBR4 RD REF[7] REF[6] REF[5] REF[4] REF[3] REF[2] REF[1] REF[0] AVBR5 RD REF[15] REF[14] REF[13] REF[12] REF[11] REF[10] REF[9] REF[8] BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Table 43. Status Register Group A REGISTER RD/WR BIT 7 STAR0 RD SOC[7] SOC[6] SOC[5] SOC[4] SOC[3] SOC[2] SOC[1] SOC[0] STAR1 RD SOC[15] SOC[14] SOC[13] SOC[12] SOC[11] SOC[10] SOC[9] SOC[8] STAR2 RD ITMP[7] ITMP[6] ITMP[5] ITMP[4] ITMP[3] ITMP[2] ITMP[1] ITMP[0] STAR3 RD ITMP[15] ITMP[14] ITMP[13] ITMP[12] ITMP[11] ITMP[10] ITMP[9] ITMP[8] STAR4 RD VA[7] VA[6] VA[5] VA[4] VA[3] VA[2] VA[1] VA[0] STAR5 RD VA[15] VA[14] VA[13] VA[12] VA[11] VA[10] VA[9] VA[8] Table 44. Status Register Group B REGISTER STBR0 RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RD VD[7] VD[6] VD[5] VD[4] VD[3] VD[2] VD[1] VD[0] STBR1 RD VD[15] VD[14] VD[13] VD[12] VD[11] VD[10] VD[9] VD[8] STBR2 RD C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV STBR3 RD C8OV C8UV C7OV C7UV C6OV C6UV C5OV C5UV STBR4 RD C12OV C12UV C11OV C11UV C10OV C10UV C9OV C9UV STBR5 RD REV[3] REV[2] REV[1] REV[0] RSVD RSVD MUXFAIL THSD Table 45. COMM Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COMM0 RD/WR ICOM0[3] ICOM0[2] ICOM0[1] ICOM0[0] D0[7] D0[6] D0[5] D0[4] COMM1 RD/WR D0[3] D0[2] D0[1] D0[0] FCOM0[3] FCOM0[2] FCOM0[1] FCOM0[0] COMM2 RD/WR ICOM1[3] ICOM1[2] ICOM1[1] ICOM1[0] D1[7] D1[6] D1[5] D1[4] COMM3 RD/WR D1[3] D1[2] D1[1] D1[0] FCOM1[3] FCOM1[2] FCOM1[1] FCOM1[0] COMM4 RD/WR ICOM2[3] ICOM2[2] ICOM2[1] ICOM2[0] D2[7] D2[6] D2[5] D2[4] COMM5 RD/WR D2[3] D2[2] D2[1] D2[0] FCOM2[3] FCOM2[2] FCOM2[1] FCOM2[0] 52 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation Table 46. Memory Bit Descriptions NAME GPIOx REFON SWTRD ADCOPT VUV VOV DCC[x] DCTO CxV GxV REF SOC ITMP VA VD CxOV CxUV REV RSVD DESCRIPTION VALUES GPIOx Pin Control Write: 0 -> GPIOx Pin Pull-Down ON; 1-> GPIOx Pin Pull-Down OFF (Default) Read: 0 -> GPIOx Pin at Logic 0; 1 -> GPIOx Pin at Logic 1 Reference 1 -> Reference Remains Powered Up Until Watchdog Timeout 0 -> Reference Shuts Down after Conversions (Default) Powered Up SWTEN Pin Status 1 -> SWTEN Pin at Logic 1 (Read Only) 0 -> SWTEN Pin at Logic 0 ADC Mode Option ADCOPT: 0 -> Selects Modes 27kHz, 7kHz or 26Hz with MD[1:0] Bits in ADC Conversion Commands (Default). 1 -> Selects Modes 14kHz, 3kHz or 2kHz with MD[1:0] Bits in ADC Conversion Commands. Bit Undervoltage Comparison voltage = (VUV + 1) * 16 * 100V Comparison Default: VUV = 0x000 Voltage* Comparison voltage = VOV * 16 * 100V Overvoltage Default: VOV = 0x000 Comparison Voltage* Discharge Cell x x = 1 to 12 1 -> Turn ON Shorting Switch for Cell x 0 -> Turn OFF Shorting Switch for Cell x (Default) Discharge Time DCTO 0 1 2 3 4 5 6 7 8 9 A B C D Out Value (Write) Time Disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 (Min) DCTO 0 1 2 3 4 5 6 7 8 9 A B C D (Read) 0.5 1 2 3 4 5 10 15 20 30 40 60 Time Disabled 0 to to to to to to to to to to to to to Left or 1 2 3 4 5 10 15 20 30 40 60 75 (Min) Timeout 0.5 E F 90 120 E F 75 to 90 90 to 120 Cell x Voltage* x = 1 to 12 16-Bit ADC Measurement Value for Cell x Cell Voltage for Cell x = CxV * 100V CxV Is Reset to 0xFFFF on Power-Up and After Clear Command GPIO x Voltage* x = 1 to 5 16-Bit ADC Measurement Value for GPIOx Voltage for GPIOx = GxV * 100V GxV Is Reset to 0xFFFF on Power-Up and After Clear Command 2nd Reference 16-Bit ADC Measurement Value for 2nd Reference Voltage for 2nd Reference = REF * 100V Voltage* Normal Range Is within 2.985V to 3.015V Sum of Cells 16-Bit ADC Measurement Value of the Sum of All Cell Voltages Sum of All Cells Voltage = SOC * 100V * 20 Measurement* Internal Die 16-Bit ADC Measurement Value of Internal Die Temperature Temperature Measurement (C) = ITMP * 100V/7.5mV/C - 273C Temperature* Analog Power 16-Bit ADC Measurement Value of Analog Power Supply Voltage Analog Power Supply Voltage = VA * 100V Supply Voltage* Normal Range Is within 4.5V to 5.5V Digital Power 16-Bit ADC Measurement Value of Digital Power Supply Voltage Digital Power Supply Voltage = VA * 100V Supply Voltage* Normal Range Is within 2.7V to 3.6V Cell x Overvoltage x = 1 to 12 Cell Voltage Compared to VOV Comparison Voltage 0 -> Cell x Not Flagged for Overvoltage Condition. 1 -> Cell x Flagged Flag Cell x x = 1 to 12 Cell Voltage Compared to VUV Comparison Voltage 0 -> Cell x Not Flagged for Undervoltage Condition. 1 -> Cell x Flagged Undervoltage Flag Revision Code Device Revision Code. See Revision Code and Reserved Bits in Operation Section. Reserved Bits See Revision Code and Reserved Bits in Operation Section. 680412fc For more information www.linear.com/LTC6804-1 53 LTC6804-1/LTC6804-2 Operation Table 46. Memory Bit Descriptions NAME DESCRIPTION MUXFAIL Multiplexer SelfTest Result THSD Thermal Shutdown Status ICOMn Initial Communication Control Bits Dn FCOMn I2C/SPI Communication Data Byte Final Communication Control Bits VALUES Read: 0 -> Multiplexer Passed Self Test 1 -> Multiplexer Failed Self Test Read: 0 -> Thermal Shutdown Has Not Occurred 1 -> Thermal Shutdown Has Occurred THSD Bit Cleared to 0 on Read of Status RegIster Group B Write I2C 0110 0001 0000 0111 STOP BLANK NO TRANSMIT START SPI 1000 1001 1111 CSB Low CSB High NO TRANSMIT Read I2C 0110 0001 0000 0111 START from Master STOP from Master SDA Low Between Bytes SDA High Between Bytes SPI 0111 Data Transmitted (Received) to (From) I2C/SPI Slave Device Write I2C SPI Read I2C 0000 Master ACK 1000 Master NACK X000 CSB Low 0000 0111 ACK from Master ACK from Slave 1111 NACK from Slave 1001 Master NACK + STOP 1001 CSB High 0001 1001 ACK from Slave + NACK from Slave STOP from Master + STOP from Master SPI 1111 *Voltage equations use the decimal value of registers, 0 to 4095 for 12 bits and 0 to 65535 for 16 bits. Programming Examples 4. Wait for the amount of time 3 * tREADY The following examples use a configuration of 3 stacked LTC6804-1 devices: S1, S2, S3. Port A on device S1 is configured in SPI mode (ISOMD pin low). Port A on devices S2 and S3 is configured in isoSPI mode (ISOMD pin high). Port B on S1 is connected to Port A on S2. Port B on S2 is connected to Port A on S3. The microcontroller communicates to the stack through Port A on S1. 5. Send commands Write Configuration Registers 1. Pull CSB low 2. Send WRCFG command (0x00 0x01) and its PEC (0x3D 0x6E) Waking Up Serial Interface 3. Send CFGR0 byte of device S3, then CFGR1(S3), ... CFGR5(S3), PEC of CFGR0(S3) to CFGR5(S3) 1. Send a dummy byte. The activity on CSB and SCK will wake up the serial interface on device S1. 4. Send CFGR0 byte of device S2, then CFGR1(S2), ... CFGR5(S2), PEC of CFGR0(S2) to CFGR5(S2) 2. Wait for the amount of time 3 * tWAKE in order to power up all devices S1, S2 and S3. 5. Send CFGR0 byte of device S1, then CFGR1(S1), ... CFGR5(S1), PEC of CFGR0(S1) to CFGR5(S1) For large stacks where some devices may go to the IDLE state after waking, apply steps 3 and 4: 6. Pull CSB high, data latched into all devices on rising edge of CSB 3. Send a second dummy byte. 54 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation Calculation of serial interface time for sequence above: Clear Cell Voltage Registers Number of LTC6804-1s in daisy chain stack = n 1. Pull CSB low Number of bytes in sequence (B): 2. Send CLRCELL command (0x07 0x11) and its PEC (0xC9 0xC0) Command: 2 (command byte) + 2 (command PEC) = 4 Data: 6 (Data bytes) + 2 (Data PEC) per LTC6804 = 8 bytes per device B=4+8*n 3. Pull CSB high Poll ADC Status (Parallel configuration and ISOMD = 0) Serial port frequency per bit = F Time = (1/F) * B * 8 bits/byte = (1/F) * [4 + 8 * n] * 8 Time for 3 LTC6804 example above, with 1MHz serial port = (1/1e6) * (4 + 8 * 3) * 8 = 224s Note: This time will remain the same for all write and read commands. Read Cell Voltage Register Group A 1. Pull CSB low 2. Send RDCVA command (0x00 0x04) and its PEC (0x07 0xC2) 3. Read CVAR0 byte of device S1, then CVAR1(S1), ... CVAR5(S1), PEC of CVAR0(S1) to CVAR5(S1) 4. Read CVAR0 byte of device S2, then CVAR1(S2), ... CVAR5(S2), PEC of CVAR0(S2) to CVAR0(S2) 5. Read CVAR0 byte of device S3, then CVAR1(S3), ... CVAR5(S3), PEC of CVAR0(S3) to CVAR5(S3) 6. Pull CSB high This example uses an addressed LTC6804-2 with address A [3:0] = 0011 and ISOMD = 0 1. Pull CSB low 2. Send PLADC command (0x9F 0x14) and its PEC (0x1C 0x48 ) 3. SDO output is pulled low if the LTC6804-2 is busy. The host needs to send clocks on SCK in order for the polling status to be updated from the addressed device. 4. SDO output is high when the LTC6804-2 has completed conversions 5. Pull CSB high to exit polling Talk to an I2C Slave Connected to LTC6804 The LTC6804 supports I2C slave devices by connection to GPIO4(SDA) and GPIO5(SCL). One valuable use for this capability is to store production calibration constants or other information in a small serial EEPROM using a connection like shown in Figure 25. Start Cell Voltage ADC Conversion (All cells, normal mode with discharge permitted) and poll status 1. Pull CSB low 4.7k WP VCC 1F 10V VREG LTC6804 SCL GPIO5(SCL) 24AA01 VSS GPIO4(SDA) SDA V- 2. Send ADCV command with MD[1:0] = 10 and DCP = 1 i.e. 0x03 0x70 and its PEC (0xAF 0x42) 3. Pull CSB high 4.7k 680412 F25 Figure 25. Connecting I2C EEPROM to LTC6804 GPIO Pins 680412fc For more information www.linear.com/LTC6804-1 55 LTC6804-1/LTC6804-2 Operation This example uses a single LTC6804-1 to write a byte of data to an I2C EEPROM. The LTC6804 will send three bytes of data to the I2C slave device. The data sent will be B0 = 0xA0 (EEPROM address), B1 = 0x01 (write command), and B2 = 0xAA (data to be stored in EEPROM). The three bytes will be transmitted to the I2C slave device in the following format: START - B0 - NACK - B1 - NACK - B2 - NACK - STOP 1. Write data to COMM register using WRCOMM command 3. Data transmitted to slave during the STCOMM command is stored in the COMM register. Use the RDCOMM command to retrieve the data a. Pull CSB low b. Send RDCOMM command (0x07 0x22) and its PEC (0x32 0xD6) c. Read COMM0-COMM5 and the PEC for the 6 bytes of data. Assuming the slave acknowledged all 3 bytes of data, the read back data in this example would look like: a. Pull CSB low b. Send WRCOMM command (0x07 0x21) and its PEC (0x24 0xB2) c. Send COMM0 = 0x6A, COMM1 = 0x08 ([START] [B0] [NACK]), COMM2 = 0x00, COMM3 = 0x18 ([BLANK] [B1] [NACK]), COMM4 = 0x0A, COMM5 = 0xA9 ([BLANK] [B2] [NACK+STOP]) COMM0 = 0x6A, COMM1 = 0x07, COMM2 = 0x70, COMM3 = 0x17, COMM4 = 0x7A, COMM5 = 0xA1, PEC = 0xD0 0xDE d. Pull CSB high Note: If the slave returns data, this data will be placed in COMM0-COMM5. Figure 26 shows the activity on GPIO5 (SCL) and GPIO4 (SDA) ports of the I2C master for 72 clock cycles during the STCOMM command in the above example. and PEC = 0x6D 0xFB for the above data d. Pull CSB high 2. Send the 3 bytes of data to I2C slave device using STCOMM command a. Pull CSB low b. Send STCOMM command (0x07 0x23) and its PEC (0xB9 0xE4) c. Send 72 clock cycles on SCK d. Pull CSB high SCK SCL (GPIO5) SDA (GPIO4) START LAST CLOCK OF STCOMM COMMAND 0xA0 0x01 ACK FROM SLAVE 0xAA ACK FROM SLAVE STOP ACK FROM SLAVE 680412 F26 Figure 26. LTC6804 I2C Communication Example 56 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Operation Talk to a SPI Slave Connected to LTC6804 This example uses a single LTC6804-1 device which has a SPI device connected to it through GPIO3 (CSBM), GPIO4 (SDOM) and GPIO5 (SCKM). In this example, the LTC6804 device sends out 3 bytes of data B0 = 0x55, B1 = 0xAA and B2 = 0xCC to the SPI slave device in the following format: CSB low - B0 - B1 - B2 - CSB high 1. Write data to COMM register using WRCOMM command a. Pull CSBM low b. Send WRCOMM command (0x07 0x21) and its PEC (0x24 0xB2) c. Send COMM0 = 0x85, COMM1 = 0x50 ([CSBM low] [B0] [CSBM low]), COMM2 = 0x8A, COMM3 = 0xA0 ([CSBM low] [B1] [CSBM low]), COMM4 = 0x8C, COMM5 = 0xC9 ([CSBM low] [B2] [CSBM high]) 3. Data transmitted to slave during the STCOMM command is stored in the COMM register. Use the RDCOMM command to retrieve the data. a. Pull CSB low b. Send RDCOMM command (0x07 0x22) and its PEC (0x32 0xD6) c. Read COMM0-COMM5 and the PEC for the 6 bytes of data. The read back data in this example would look like: COMM0 = 0x755F, COMM1 = 0x7AAF, COMM2 = 7CCF, PEC = 0xF2BA d. Pull CSB high Note: If the slave returns data, this data will be placed in COMM0-COMM5. Figure 27 shows the activity on GPIO3 (CSBM), GPIO5 (SCKM) and GPIO4 (SDOM) ports of SPI master for 72 clock cycles during the STCOMM command in the above example. and PEC = 0x89 0xA4 for the above data. d. Pull CSB high 2. Send the 3 bytes of data to SPI slave device using STCOMM command a. Pull CSB low b. Send STCOMM command (0x07 0x23) and its PEC (0xB9 0xE4) c. Send 72 clock cycles on SCK d. Pull CSB high SCK CSBM (GPIO3) SCKM (GPIO5) SDOM (GPIO4) CSBM LOW 0x55 0xAA LAST CLOCK OF STCOMM COMMAND 0xCC CSBM HIGH 680412 F27 Figure 27. LTC6804 SPI Communication Example 680412fc For more information www.linear.com/LTC6804-1 57 LTC6804-1/LTC6804-2 Applications Information Simple Linear Regulator Improved Regulator Power Efficiency The LTC6804 draws most of its power from the VREG input pin. 5V 0.5V should be applied to VREG. A regulated DC/ DC converter can power VREG directly, or the DRIVE pin may be used to form a discrete regulator with the addition of a few external components. When active, the DRIVE output pin provides a low current 5.6V output that can be buffered using a discrete NPN transistor, as shown in Figure 28. The collector power for the NPN can come from any potential of 6V or more above V-, including the cells being monitored or an unregulated converter supply. A 100/100nF RC decoupling network is recommended for the collector power connection to protect the NPN from transients. The emitter of the NPN should be bypassed with a 1F capacitor. Larger capacitor values should be avoided because they increase the wake-up time of the LTC6804. Some attention to the thermal characteristic of the NPN is needed, as there can be significant heating with a high collector voltage. To minimize power consumption within the LTC6804, the current drawn on the V+ pin has been designed to be very small (500A). The voltage on the V+ pin must be at least as high as the top cell to provide accurate measurement. The V+ and VREG pins can be unpowered to provide an exceptionally low battery drain shutdown mode. In many applications, the V+ will be permanently connected to the top cell potential through a decoupling RC to protect against transients (100/100nF is recommended). 100 LTC6804 WDT DRIVE VREG SWTEN VREF1 VREF2 GPIO5 GPIO4 V- V- GPIO3 NSV1C201MZ4 0.1F For better running efficiency when powering from the cell stack, the VREG may be powered from a buck converter rather than the NPN pass transistor. An ideal circuit for this is based on the LT3990 as shown in Figure 29. A 1k resistor should be used in series with the input to prevent inrush current when connecting to the stack and to reduce conducted EMI. The EN/UVLO pin should be connected to DRIVE so that the converter sleeps along with the LTC6804. The LTC6804 watchdog timer requires VREG power to timeout. Therefore, if the EN/UVLO pin is not connected to DRIVE, care must be taken to allow the LTC6804 to timeout first before removing VREG power; otherwise the LTC6804 will not enter sleep mode. VIN 28V TO 62V 1F 1k VIN 1F BOOST LT3990 1F OFF ON EN/UVLO PG 33H BD 22pF RT 374k Figure 28. Simple VREG Power Source Using NPN Pass Transistor f = 400kHz GND VREG 5V 40mA SW 2.2F 680412 F28 0.22F 1M FB 22F 316k 680412 F29 Figure 29. VREG Powered from Cell Stack with High Efficiency 58 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Applications Information Fully Isolated Power current from conducting through internal parasitic paths inside the IC when the isolated power is removed. A simple DC/DC flyback converter can provide isolated power for an LTC6804 from a remote 12V power source as shown in Figure 30. This circuit, along with the isoSPI transformer isolation, results in LTC6804 circuitry that is completely floating and uses almost no power from the batteries. Aside from reducing the amount of circuitry that operates at battery potential, such an arrangement prevents battery load imbalance. The LTC6804 watchdog timer requires VREG power to timeout. Therefore, care must be taken to allow the LTC6804 to timeout first before removing VREG power; otherwise the LTC6804 will not enter sleep mode. A diode should be added between the V+ and the top cell being monitored. This will prevent any Reading External Temperature Probes Figure 31 shows the typical biasing circuit for a negativetemperature-coefficient (NTC) thermistor. The 10k at 25C is the most popular sensor value and the VREF2 output stage is designed to provide the current required to directly bias several of these probes. The biasing resistor is selected to correspond to the NTC value so the circuit will provide 1.5V at 25C (VREF2 is 3V nominal). The overall circuit response is approximately -1%/C in the range of typical cell temperatures, as shown in the chart of Figure 31 . CONNECT TO TOP CELL CMHD459A 130k 12VRETURN 8 22.1k RFB GND EN/UVLO SW VIN 5 *1 4* CMMSH1-40 52V 13V 4.7F 25V 7 *2 V+ CMHZ5265B 62V 1F 100V NSV1C201MZ4 1F 10V PA0648NL 12V 100nF 100V LTC6804 DRIVE VREG V- 680412 F30 Figure 30. Powering LTC6804 from a Remote 12V Source 100 90 80 VREF2 10k VTEMP NTC 10k AT 25C V- VTEMPx (% VREF2) 100k 4.7F 25V LT8300 100 70 60 50 40 30 20 10 0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 680412 F31 Figure 31. Typical Temperature Probe Circuit and Relative Output 680412fc For more information www.linear.com/LTC6804-1 59 LTC6804-1/LTC6804-2 Applications Information Expanding the Number of Auxiliary Measurements Filtering of Cell and GPIO Inputs The LTC6804 uses a delta-sigma ADC, which has deltasigma modulator followed by a SINC3 finite impulse response (FIR) digital filter. This greatly reduces input filtering requirements. Furthermore, the programmable oversampling ratio allows the user to determine the best trade-off between measurement speed and filter cutoff frequency. Even with this high order lowpass filter, fast transient noise can still induce some residual noise in measurements, especially in the faster conversion modes. This can be minimized by adding an RC lowpass decoupling to each ADC input, which also helps reject potentially damaging high energy transients. Adding more than about 100 to the ADC inputs begins to introduce a systematic error in the measurement, which can be improved by raising the filter capacitance or mathematically compensating in software with a calibration procedure. For situations that demand the highest level of battery voltage ripple rejection, grounded capacitor filtering is recommended. This configuration has a series resistance and capacitors that decouple HF noise to V-. In systems where noise is less The LTC6804 provides five GPIO pins, each of which is capable of performing as an ADC input. In some applications there is need to measure more signals than this, so one means of supporting higher signal count is to add a MUX circuit such as shown in Figure 32. This circuit digitizes up to sixteen source signals using the GPIO1 ADC input and MUX control is provided by two other GPIO lines configured as an I2C port. The buffer amplifier provides for fast settling of the selected signal to increase the usable conversion rate. Internal Protection Features The LTC6804 incorporates various ESD safeguards to ensure a robust performance. An equivalent circuit showing the specific protection structures is shown in Figure 33. While pins 43 to 48 have different functionality for the -1 and -2 variants, the protection structure is the same. Zener-like suppressors are shown with their nominal clamp voltage, other diodes exhibit standard PN junction behavior. ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOG9 ANALOG10 ANALOG11 ANALOG12 ANALOG13 ANALOG14 ANALOG15 ANALOG16 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 16 S0 VCC 15 SCL S1 14 SDA S2 13 A0 S3 LTC1380 12 A1 S4 11 GND S5 10 VEE S6 9 DO S7 16 S0 VCC 15 SCL S1 14 SDA S2 13 A0 S3 LTC1380 12 A1 S4 11 GND S5 10 VEE S6 9 DO S7 4.7k 4.7k 1F 37 LTC6804 VREG 33 GPIO5(SCL) 32 GPIO4(SDA) 31 - V 3 4 + 5 LTC6255 - 1 100 2 27 GPIO1 10nF 680412 F32 ANALOG INPUTS: 0.04V TO 4.5V Figure 32. MUX Circuit Supports Sixteen Additional Analog Measurements 60 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Applications Information 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 31 30 C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 S1 C0 12V 1 30V 10k 30V 12V 30V 12V 10k 12V 12V 30V 10k 12V 12V 12V 12V 12V 10k 12V 12V 12V 12V 10k 12V 12V 12V 10k 12V 12V 12V 30V 10k 12V 12V 12V 12V 12V 10k 12V 12V 12V 12V 10k 12V 12V 12V 10k 12V 12V 12V 12V 30V 10k 12V 12V 12V 12V 10k 12V 12V 12V 12V V- V- V+ LTC6804 IPB/A3 IMB/A2 ICMP/A1 IBIAS/A0 SDO SDI SCK CSB ISOMD WDT DRIVE VREG SWTEN VREF1 VREF2 GPIO5 48 47 46 45 44 43 periodic or higher oversample rates are in use, a differential capacitor filter structure is adequate. In this configuration there are series resistors to each input, but the capacitors connect between the adjacent C pins. However, the differential capacitor sections interact. As a result, the filter response is less consistent and results in less attenuation than predicted by the RC, by approximately a decade. Note that the capacitors only see one cell of applied voltage (thus smaller and lower cost) and tend to distribute transient energy uniformly across the IC (reducing stress events on the internal protection structure). Figure 34 shows the two methods schematically. Basic ADC accuracy varies with R, C as shown in the Typical Performance curves, but error is minimized if R = 100 and C = 10nF. The GPIO pins will always use a grounded capacitor configuration because the measurements are all with respect to V-. 42 41 100 CELL2 33 40 39 GPIO2 GPIO1 3.3k 33 37 C0 10nF BATTERY V- 36 S1 10nF 100 V- Differential Capacitor Filter 35 34 100 CELL2 C2 3.3k BSS308PE 33 33 3.3k C 100 29 S1 * C0 C 28 LTC6804 C1 BSS308PE 32 S2 C * 100 33 GPIO3 LTC6804 C1 BSS308PE 38 S2 10nF 100 CELL1 CELL1 GPIO4 C2 3.3k BSS308PE BATTERY V- * V- *6.8V ZENERS RECOMMENDED IF C > 100nF 27 25 680412 F34 Grounded Capacitor Filter 680412 F33 NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 31 Figure 34. Input Filter Structure Configurations Figure 33. Internal ESD Protection Structure of LTC6804 680412fc For more information www.linear.com/LTC6804-1 61 LTC6804-1/LTC6804-2 Applications Information Cell Balancing with Internal Mosfets LTC6804 C(n) RFILTER The S1 through S12 pins are used to balance battery cells. If one cell in a series becomes overcharged, an S output can be used to discharge the cell. Each S output has an internal N-channel MOSFET for discharging. The NMOS has a maximum on resistance of 20. An external resistor should be connected in series with the NMOS to dissipate heat outside of the LTC6804 package as illustrated in Figure 35. It is still possible to use an RC to add additional filtering to cell voltage measurements but the filter R must remain small, typically around 10 to reduce the effect on the programmed balance current. When using the internal MOSFETs to discharge cells, the die temperature should be monitored. See Power Dissipation and Thermal Shutdown section. RDISCHARGE + S(n) RFILTER C(n - 1) 680412 F35 Figure 35. Internal Discharge Circuit LTC6804 C(n) + BSS308PE R S(n) 3.3k C(n - 1) 680412 F36 Figure 36. External Discharge Circuit Cell Balancing with External MOSFETS The S outputs include an internal pull-up PMOS transistor. The S pins can act as digital outputs suitable for driving the gate of an external MOSFET. For applications requiring high battery discharge currents, connect a discrete PMOS switch device and suitable discharge resistor to the cell, and the gate terminal to the S output pin, as illustrated in Figure 36. Figure 34 shows external MOSFET circuits that include RC filtering. Discharge Control During Cell Measurements If the discharge permited (DCP) command bit is high in a cell measurement command, then the S pin discharge states are not altered during the cell measurements. However, if the DCP bit is low, any discharge that is turned on will be turned off when the corresponding cell or adjacent cells are being measured. Table 47 illustrates this during an Table 47. Discharge Control During an ADCV Command with DCP = 0 CELL MEASUREMENT PERIODS DISCHARGE PIN CELL CALIBRATION PERIODS CELL1/7 CELL2/8 CELL3/9 CELL4/10 CELL5/11 CELL6/12 CELL1/7 t0 to t1M t1M to t2M t2M to t3M t3M to t4M t4M to t5M t5M to t6M OFF ON ON ON OFF t6M to t1C CELL2/8 CELL3/9 CELL4/10 CELL5/11 CELL6/12 t1C to t2C t2C to t3C t3C to t4C t4C to t5C t5C to t6C S1 OFF OFF OFF ON ON ON OFF S2 OFF OFF OFF ON ON ON OFF OFF OFF ON ON ON S3 ON OFF OFF OFF ON ON ON OFF OFF OFF ON ON S4 ON ON OFF OFF OFF ON ON ON OFF OFF OFF ON S5 ON ON ON OFF OFF OFF ON ON ON OFF OFF OFF S6 OFF ON ON ON OFF OFF OFF ON ON ON OFF OFF S7 OFF OFF ON ON ON OFF OFF OFF ON ON ON OFF S8 OFF OFF OFF ON ON ON OFF OFF OFF ON ON ON S9 ON OFF OFF OFF ON ON ON OFF OFF OFF ON ON S10 ON ON OFF OFF OFF ON ON ON OFF OFF OFF ON S11 ON ON ON OFF OFF OFF ON ON ON OFF OFF OFF S12 OFF ON ON ON OFF OFF OFF ON ON ON OFF OFF 62 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Applications Information ADCV command with DCP = 0. In this table, OFF implies that a discharge is forced off during that period even if the corresponding DCC[x] bit is high in the configuration register. ON implies that if the discharge is turned on, it will stay on during that period. Refer to Figure 3 for the timing of the ADCV command. Power Dissipation and Thermal Shutdown The internal MOSFETs connected to the pins S1 through S12 pins can be used to discharge battery cells. An external resistor should be used to limit the power dissipated by the MOSFETs. The maximum power dissipation in the MOSFETs is limited by the amount of heat that can be tolerated by the LTC6804. Excessive heat results in elevated die temperatures. Little or no degradation will be observed in the measurement accuracy for die temperatures up to 125C. Damage may occur above 150C, therefore the recommended maximum die temperature is 125C. To protect the LTC6804 from damage due to overheating a thermal shutdown circuit is included. Overheating of the device can occur when dissipating significant power in the cell discharge switches. The thermal shutdown circuit is enabled whenever the device is not in sleep mode (see LTC6804 Core State Descriptions). If the temperature detected on the device goes above approximately 150C the configuration registers will be reset to default states turning off all discharge switches. When a thermal shutdown has occurred, the THSD bit in the status register group B will go high. The bit is cleared after a read operation of the status register group B. The bit can also be set using the CLRSTAT command. Since thermal shutdown interrupts normal operation, the internal temperature monitor should be used to determine when the device temperature is approaching unacceptable levels. Method to Verify Balancing Circuitry The functionality of the discharge circuitry is best verified by cell measurements. Figure 37 shows an example using the LTC6804 battery monitor IC. The resistor between the battery and the source of the discharge MOSFET causes cell voltage measurements to decrease. The amount of measurement change depends on the resistor values and the MOSFET on resistance. The following algorithm could be used in conjunction with Figure 37: 1. Measure all cells with no discharging (all S outputs off) and read and store the results. 2. Turn on S1 and S7 3. 4. 5. 6. Measure C1-C0, C7-C6 Turn off S1 and S7 Turn on S2 and S8 Measure C2-C1, C8-C7 7. Turn off S2 and S8 ... 14. Turn on S6 and S12 15. Measure C6-C5, C12-C11 16. Turn off S6 and S12 17. Read the voltage register group to get the results of steps 2 thru 16. 18. Compare new readings with old readings. Each cell voltage reading should have decreased by a fixed percentage set by RB1 and RB2 (Figure 37). The exact amount of decrease depends on the resistor values and MOSFET characteristics. Improved PEC Calculation The PEC allows the user to have confidence that the serial data read from the LTC6804 is valid and has not been corrupted by any external noise source. This is a critical feature for reliable communication and the LTC6804 requires that a PEC be calculated for all data being read from and written to the LTC6804. For this reason it is important to have an efficient method for calculating the PEC. The code below demonstrates a simple implementation of a lookup table derived PEC calculation method. There are two functions, the first function init_PEC15_Table() should only be called once when the microcontroller starts and will initialize a PEC15 table array called pec15Table[]. This table will be used in all future PEC calculations. The pec15 table can also be hard coded into the microcontroller rather than running the init_PEC15_Table() function at startup. The pec15() function calculates the PEC and will return the correct 15 bit PEC for byte arrays of any given length. 680412fc For more information www.linear.com/LTC6804-1 63 LTC6804-1/LTC6804-2 Applications Information RB1 RB2 RB1 RB2 RB1 V+ C12 RB2 LTC6804 S12 C11 RB1 S11 C10 RB2 S10 C9 RB1 S9 RB2 C8 S8 C7 RB1 S7 RB2 C6 S6 C5 RB1 S5 RB2 C4 S4 RB1 C3 S3 RB2 RB1 C2 V- S2 C0 C1 S1 RB2 RB1 RB2 RB1 RB2 RB1 RB2 680412 F37 Figure 37. Balancing Self Test Circuit 64 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Applications Information /************************************ Copyright 2012 Linear Technology Corp. (LTC) Permission to freely use, copy, modify, and distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies: THIS SOFTWARE IS PROVIDED "AS IS" AND LTC DISCLAIMS ALL WARRANTIES INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL LTC BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM ANY USE OF SAME, INCLUDING ANY LOSS OF USE OR DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTUOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ***********************************************************/ int16 pec15Table[256]; int16 CRC15_POLY = 0x4599; void init_PEC15_Table() { for (int i = 0; i < 256; i++) { remainder = i << 7; for (int bit = 8; bit > 0; --bit) { if (remainder & 0x4000) { remainder = ((remainder << 1)); remainder = (remainder ^ CRC15poly) } else { remainder = ((remainder << 1)); } } pec15Table[i] = remainder&0xFFFF; } } unsigned int16 pec15 (char *data , int len) { int16 remainder,address; remainder = 16;//PEC seed for (int i = 0; i < len; i++) { address = ((remainder >> 7) ^ data[i]) & 0xff;//calculate PEC table address remainder = (remainder << 8 ) ^ pec15Table[address]; } return (remainder*2);//The CRC15 has a 0 in the LSB so the final value must be multiplied by 2 } 680412fc For more information www.linear.com/LTC6804-1 65 LTC6804-1/LTC6804-2 Applications Information and produces analog outputs that are connected to GPIO pins or inputs of the MUX application shown in Figure 32. The use of GPIO1 and GPIO2 as the ADC inputs has the possibility of being digitized within the same conversion sequence as the cell inputs (using the ADCVAX command), thus synchronizing cell voltage and cell current measurements. Current Measurement with a Hall Effect Sensor The LTC6804 auxiliary ADC inputs (GPIO pins) may be used for any analog signal, including those from various active sensors that generate a compatible voltage. One such example that may be useful in a battery management setting is the capture of battery current. Hall-effect sensors are popular for measuring large battery currents since the technology provides a non-contact, low power dissipation solution. Figure 38 shows schematically a typical Hall sensor that produces two outputs that proportion to the VCC provided. The sensor is powered from a 5V source Current Measurement with a Shunt Resistor It is possible to measure the battery current on the LTC6804 GPIO pins with a high performance current sense amplifier and a shunt. Figure 39 shows 2 LTC6102s being used to measure the discharge and charge currents on a 12-cell battery stack. To achieve a large dynamic range while maintaining a high level of accuracy the LTC6102 is required. The circuit shown is able to accurately measure 200Amps to 0.1Amps. The offset of the LTC6102 will only contribute a 20mA error. To maintain a very low sleep current the VDRIVE is used to disable the LTC6102 circuits so that they draw no current when the LTC6804 goes to sleep. LEM DHAB CH2 VCC GND CH1 A ANALOG GPIO2 B 5V C ANALOG_COM V- D ANALOG0 GPIO1 680412 F38 Figure 38. Interfacing a Typical Hall-Effect Battery Current Sensor to Auxiliary ADC Inputs RSENSE 0.5m ICHARGE LTC6804 V+ IDISCHARGE CHARGER RIN(C) 100 +IN VBATTSTACK V- + - -INF V+ V+ 0.1F GPIO 2 + ROUT(C) 4.02k 0.1F + VOUT(D) - - + OUT GPIO 1 VOUT(C) +IN V- VREG VDRIVE OUT 1F -INS -INF VREG LTC6102 RIN(D) 100 RIN(C) 100 -INS RIN(D) 100 - ROUT(D) 4.02k L O A D LTC6102 1F 680412 F39 LTC6804 V- VDRIVE LTC6804 V- DISCHARGING: VOUT D = IDISCHARGE * RSENSE ( ( ) ROUT(D) WHEN IDISCHARGE 0 RIN(D) ) ROUT(C) CHARGING: VOUT C = ICHARGE * RSENSE WHEN ICHARGE 0 RIN(C) Figure 39. Monitoring Charge and Discharge Currents with a LTC6102 66 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Applications Information Using the LTC6804 with Less Than 12 Cells If the LTC6804 is powered by the battery stack, the minimum number of cells that can be monitored by the LTC6804 is governed by the supply voltage requirements of the LTC6804. V+ must be at least 11V to properly bias the LTC6804. Figure 40 shows an example of the LTC6804 when used to monitor eight cells with best cell measurement synchronization. The 12 cells monitored by the LTC6804 are split into two groups of 6 cells and are measured using two internal multiplexers and two ADCs. To optimize measurement synchronization in applications with less than 12 Cells the unused C pins should be equally distributed between the top of the second mux (C12) and the top of the first mux (C6). If there are an odd number of cells being used, the top mux should have fewer cells connected. The unused cell channels should be tied to the other unused channels on the same mux and then connected to the battery stack through a 100 resistor. The unused inputs will result in a reading of 0V for those cells channels. It is also acceptable to connect in the conventional sequence with all unused cell inputs at the top. NEXT HIGHER GROUP OF 8 CELLS V+ C12 S12 C11 S11 + + + + C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 + + + isoSPI IBIAS and ICMP Setup The LTC6804 allows the isoSPI links of each application to be optimized for power consumption or for noise immunity. The power and noise immunity of an isoSPI system is determined by the programmed IB current, which controls the isoSPI signaling currents. Bias current IB can range from 100A to 1mA. Internal circuitry scales up this bias current to create the isoSPI signal currents equal to 20 * IB. A low IB reduces the isoSPI power consumption in the READY and ACTIVE states, while a high IB increases the amplitude of the differential signal voltage VA across the matching termination resistor, RM. The IB current is programmed by the sum of the RB1 and RB2 resistors connected between the 2V IBIAS pin and GND as shown in LTC6804 + C4 S4 C3 S3 C2 S2 C1 S1 C0 V- NEXT LOWER GROUP OF 8 CELLS 680412 F40 Figure 40. 8 Cell Connection Scheme Figure 41. The receiver input threshold is set by the ICMP voltage that is programmed with the resistor divider created by the RB1 and RB2 resistors. The receiver threshold will be half of the voltage present on the ICMP pin. 680412fc For more information www.linear.com/LTC6804-1 67 LTC6804-1/LTC6804-2 Applications Information ISOLATION BARRIER (MAY USE ONE OR TWO TRANFORMERS) ISOMD MASTER SDO SDI SCK CS IPB + VA MOSI IMB - 2V MISO IBIAS SCK CS ICMP LTC6804 RM RB1 * * * + IPA ISOMD RM VA LTC6804 - IMA 2V IBIAS RB1 * TWISTED-PAIR CABLE WITH CHARACTERISTIC IMPEDANCE RM VREG ICMP RB2 RB2 680412 F41 Figure 41. isoSPI Circuit The following guidelines should be used when setting the bias current (100A to 1mA) IB and the receiver comparator threshold voltage VICMP/2: RM = Transmission Line Characteristic Impedance Z0 Signal Amplitude VA = (20 * IB) * (RM/2) VTCMP (Receiver Comparator Threshold) = K * VA VICMP (voltage on ICMP pin) = 2 * VTCMP RB2 = VICMP/IB RB1 = (2/IB) - RB2 Select IB and K (Signal Amplitude VA to Receiver Comparator Threshold ratio) according to the application: For lower power links: IB = 0.5mA and K = 0.5 For full power links: IB = 1mA and K = 0.5 The maximum clock rate of an isoSPI link is determined by the length of the isoSPI cable. For cables 10 meters or less, the maximum 1MHz SPI clock frequency is possible. As the length of the cable increases, the maximum possible SPI clock rate decreases. This dependence is a result of the increased propagation delays that can create possible timing violations. Figure 42 shows how the maximum data rate reduces as the cable length increases when using a CAT5 twisted pair. Cable delay affects three timing specifications: tCLK, t6 and t7. In the Electrical Characteristics table, each of these specifications is de-rated by 100ns to allow for 50ns of cable delay. For longer cables, the minimum timing parameters may be calculated as shown below: tCLK, t6 and t7 > 0.9s + 2 * tCABLE(0.2m per ns) For long links (>50m): IB = 1mA and K = 0.25 1.2 For addressable multi-drop: IB = 1mA and K = 0.4 68 1.0 DATA RATE (Mbps) For applications with little system noise, setting IB to 0.5mA is a good compromise between power consumption and noise immunity. Using this IB setting with a 1:1 transformer and RM = 100, RB1 should be set to 3.01k and RB2 set to 1k. With typical CAT5 twisted pair, these settings will allow for communication up to 50m. For applications in very noisy environments or that require cables longer than 50m it is recommended to increase IB to 1mA. Higher drive current compensates for the increased insertion loss in the cable and provides high noise immunity. When using cables over 50m and a transformer with a 1:1 turns ratio and RM = 100, RB1 would be 1.5k and RB2 would be 499. CAT5 ASSUMED 0.8 0.6 0.4 0.2 0 1 10 CABLE LENGTH (METERS) 100 680412 F42 Figure 42. Data Rate vs Cable Length 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Applications Information The use of cables between battery modules, particularly in automotive applications, can lead to increased noise susceptibility in the communication lines. For high levels of electromagnetic interference (EMC), additional filtering is recommended. The circuit example in Figure 43 shows the use of common mode chokes (CMC)to add common mode noise rejection from transients on the battery lines. The use of a center tapped transformer will also provide additional noise performance. A bypass capacitor connected to the center tap creates a low impedance for common mode noise (Figure 43b). Since transformers without a center tap can be less expensive, they may be preferred. In this case, the addition of a split termination resistor and a bypass capacitor (Figure 43a) can enhance the isoSPI performance. Large center tap capacitors greater than 10nF should be avoided as they may prevent the isoSPI common mode voltage from settling. Common mode chokes similar to those used in Ethernet or CANbus applications are recommended. Specific examples are provided in Table 49. 100H CMC 300 62 * 300 * 62 LTC6804-1 10nF IM V- XFMR * * isoSPI LINK 10nF a) IP 51 100H CMC * The hardware design of a daisy-chain isoSPI bus is identical for each device in the network due to the daisy-chain point-to-point architecture. The simple design as shown in Figure 41 is functional, but inadequate for most designs. The termination resistor RM should be split and bypassed with a capacitor as shown in Figure 43. This change provides both a differential and a common mode termination, and as such, increases the system noise immunity. IP LTC6804-1 10nF IM V- 51 CT XFMR * * isoSPI LINK * Implementing a Modular isoSPI Daisy Chain 10nF 680412 F43 b) Figure 43. Daisy Chain Interface Components An important daisy chain design consideration is the number of devices in the isoSPI network. The length of the chain determines the serial timing and affects data latency and throughput. The maximum number of devices in an isoSPI daisy chain is strictly dictated by the serial timing requirements. However, it is important to note that the serial read back time, and the increased current consumption, might dictate a practical limitation. For a daisy chain, two timing considerations for proper operation dominate (see Figure 20): 1. t6, the time between the last clock and the rising chip select, must be long enough. 2. t5, the time from a rising chip select to the next falling chip select (between commands), must be long enough. Both t5 and t6 must be lengthened as the number of LTC6804 devices in the daisy chain increases. The equations for these times are below: t5 > (#devices * 70ns) + 900ns t6 > (#devices * 70ns) + 950ns 680412fc For more information www.linear.com/LTC6804-1 69 LTC6804-1/LTC6804-2 IPB LTC6804-1 49.9 10nF 49.9 GNDD IMB IBIAS ICMP 1k 1k GNDD IPA 49.9 10nF 49.9 V- GNDD GNDD 10nF* * IMA * GNDD 10nF* GNDC IPB LTC6804-1 49.9 10nF 49.9 GNDC IMB IBIAS ICMP 1k 1k GNDC IPA 49.9 49.9 V- IMA 10nF GNDC GNDC 10nF* * GNDC * 10nF* GNDB IPB LTC6804-1 49.9 49.9 IMB IBIAS ICMP 1k 10nF GNDB 1k GNDB IPA 49.9 49.9 V - IMA 10nF* 10nF GNDB GNDB * * IP LTC6820 49.9 10nF* GNDA 49.9 IBIAS ICMP 10nF GNDA IM 1k 1k GNDA V- GNDA GNDB * IF TRANSFORMER BEING USED HAS A CENTER TAP, IT SHOULD BE BYPASSED WITH A 10nF CAP 680412 F44 Figure 44. Daisy Chain Interface Components on Single Board 70 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Applications Information Connecting Multiple LTC6804-1s on the Same PCB On single board designs with low noise requirements, it is possible for a simplified capacitor-isolated coupling as shown in Figure 45 to replace the transformer. Dual Zener diodes are used at each IC to clamp the common mode voltage to stay within the receiver's input range. The optional common mode choke (CMC) provides noise rejection with symmetrically tapped termination. The 590 resistor creates a resistor divider with the termination resistors and attenuates common mode noise. The 590 value is chosen to provide the most noise attenuation while maintaining sufficient differential signal. The circuit is designed such that IB and VICMP are the same as would be used for a transformer based system with cables over 50m. When connecting multiple LTC6804-1 devices on the same PCB, only a single transformer is required between the LTC68041 isoSPI ports. The absence of the cable also reduces the noise levels on the communication lines and often only a split termination is required. Figure 44 shows an example application that has multiple LTC6804-1s on the same PCB, communicating to the bottom MCU through an LTC6820 isoSPI driver. If a transformer with a center tap is used, a capacitor can be added for better noise rejection. Additional noise filtering can be provided with discrete common mode chokes (not shown) placed to both sides of the single transformer. VREG 590 100 3.3V 10nF 100 3.3V V- IPB LTC6804-1 3.3V 10nF 100 3.3V IPA V- GNDA IMA CMC * 100 GNDB VREG 590 100 3.3V 10nF 100 3.3V 1.5k 590 GNDA IMB IBIAS ICMP 1nF GNDB VREG IMA GNDB 1nF 499 * IPA 1.5k 499 GNDA VREG 100 3.3V 10nF 100 3.3V CMC * IBIAS ICMP 1nF 590 GNDB IMB 1nF * IPB LTC6804-1 GNDA 1nF 1nF 680412 F45 Figure 45. Capacitive Isolation Coupling for LTC6804-1s on the Same PCB 680412fc For more information www.linear.com/LTC6804-1 71 LTC6804-1/LTC6804-2 Applications Information When an LTC6804-2 is not addressed, it will not transmit data pulses. This scheme eliminates the possibility for collisions since only the addressed device returns data to the master. Generally, multi-drop systems are best confined to compact assemblies where they can avoid excessive isoSPI pulse-distortion and EMC pickup. Connecting an MCU to an LTC6804-1 with an isoSPI Data Link The LTC6820 will convert standard 4-wire SPI into a 2-wire isoSPI link that can communicate directly with the LTC6804. An example is shown in Figure 46. The LTC6820 can be used in applications to provide isolation between the microcontroller and the stack of LTC6804s. The LTC6820 also enables system configurations that have the BMS controller at a remote location relative to the LTC6804 devices and the battery pack. Basic Connection of the LTC6804-2 in a Multi-Drop Configuration In a multi-drop isoSPI bus, placing the termination at the ends of the transmission line provides the best performance (with 100 typically). Each of the LTC6804 isoSPI ports should couple to the bus with a resistor network, as shown in Figure 48a. Here again, a center-tapped transformer offers the best performance and a common mode choke (CMC) increases the noise rejection further, as shown in Figure 48b. Figure 48b also shows the use of an RC snubber at the IC connections as a means to suppress resonances (the IC capacitance provides sufficient out-of-band rejection). When using a non-center-tapped transformer, a virtual CT can be generated by connecting a CMC as a voltage-splitter. Series resistors are recommended to decouple the LTC6804 and board parasitic capacitance from the transmission line. Reducing these parasitics on the transmission line will minimize reflections. Configuring the LTC6804-2 in a Multi-Drop isoSPI Link The addressing feature of the LTC6804-2 allows multiple devices to be connected to a single isoSPI master by distributing them along one twisted pair, essentially creating a large parallel SPI network. A basic multi-drop system is shown in Figure 47; the twisted pair is terminated only at the beginning (master) and the end of the cable. In between, the additional LTC6804-2s are connected to short stubs on the twisted pair. These stubs should be kept short, with as little capacitance as possible, to avoid degrading the termination along the isoSPI wiring. IPB LTC6804-1 49.9 * * * * 10nF* 10nF 49.9 IMB IBIAS ICMP 1k GNDB GNDB 1k IPA 49.9 10nF GNDB IMA GNDB GNDB LTC6820 49.9 10nF* 49.9 V- IP 10nF* GNDA IBIAS ICMP 10nF 1k 1k GNDA 49.9 GNDA IM * IF TRANSFORMER BEING USED HAS A CENTER TAP, IT SHOULD BE BYPASSED WITH A 10nF CAP V- GNDA 680412 F46 Figure 46. Interfacing an LTC6804-1 with a C Using an LTC6820 for Isolated SPI Control 72 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Applications Information LTC6804-2 * * IPA VREGC ISOMD IBIAS 100 1.21k ICMP IMA 806 V- GNDC LTC6804-2 * * IPA GNDC VREGB ISOMD IBIAS 1.21k ICMP IMA GNDB LTC6804-2 5V * * * * IPA GNDB VREGA ISOMD IBIAS 5V 100 1.21k 100nF ICMP IMA 806 V- GNDA GNDA 680412 F47 Figure 47. Connecting the LTC6804-2 in a Multi-Drop Configuration IPA LTC6804-2 15pF IMA V- 100H CMC HV XFMR 22 100H CMC * * 402 * isoSPI BUS 22 * POL PHA IBIAS ICMP GND SLOW MSTR IP IM VDD 806 V- 806 * 5V VDDS EN MOSI MISO SCK CS 1.21k * 5k LTC6820 10nF a) IPA LTC6804-2 402 15pF IMA V- 100H CMC CT HV XFMR 22 * C SDO SDI SCK CS 5V * * isoSPI BUS 22 * 100nF 10nF 680412 F48 b) Figure 48. Preferred isoSPI Bus Couplings For Use With LTC6804-2 680412fc For more information www.linear.com/LTC6804-1 73 LTC6804-1/LTC6804-2 Applications Information Table 48. Recommended Transformers TEMPERATURE MANUFACTURER PART NUMBER RANGE VWORKING VHIPOT/60s CT CMC H Dual Transformers l 6.0mm Pulse HX1188FNL -40C to 85C 60V (est) 1.5kVrms l l 2.1mm Pulse HX0068ANL -40C to 85C 60V (est) 1.5kVrms l l 3.4mm Pulse HM2100NL -40C to 105C 1000V 4.3kVdc - l l Pulse HM2102NL -40C to 125C 1000V 4.3kVdc 4.9mm l Sumida CLP178-C20114 -40C to 125C 1000V (est) 3.75kVrms l 9mm - 5.7mm Sumida CLP0612-C20115 600Vrms 3.75kVrms l l l 10.9mm Wurth Elektronik 7490140110 -40C to 85C 250Vrms 4kVrms - 8.4mm Wurth Elektronik 7490140111 0C to 70C 1000V (est) 4.5kVrms l l l 8.4mm Wurth Elektronik 749014018 0C to 70C 250Vrms 4kVrms l 6.4mm Halo TG110-AE050N5LF -40C to 85/125C 60V (est) 1.5kVrms l Single Transformers Pulse PE-68386NL -40C to 130C 60V (est) 1.5kVdc - - 2.5mm l 5.7mm Pulse HM2101NL -40C to 105C 1000V 4.3kVdc - Wurth Elektronik 750340848 -40C to 105C 250V 3kVrms - - 2.2mm l - 10mm Halo TGR04-6506V6LF -40C to 125C 300V 3kVrms l - 9.4mm Halo TGR04-A6506NA6NL -40C to 125C 300V 3kVrms l TDK ALT4532V-201-T001 -40C to 105C 60V (est) ~1kV - 2.9mm l Halo TDR04-A550ALLF -40C to 105C 1000V 5kVrms - 6.4mm Sumida CEEH96BNP-LTC6804/11 -40C to 125C 600V 2.5kVrms - - 7mm - 10mm Sumida CEP99NP-LTC6804 -40C to 125C 600V 2.5kVrms l Sumida ESMIT-4180/A -40C to 105C 250Vrms 3kVrms - - 3.5mm TDK VGT10/9EE-204S2P4 -40C to 125C 250V (est) 2.8kVrms l - 10.6mm Transformer Selection Guide As shown in Figure 41, a transformer or pair of transformers isolates the isoSPI signals between two isoSPI ports. The isoSPI signals have programmable pulse amplitudes up to 1.6VP-P and pulse widths of 50ns and 150ns. To be able to transmit these pulses with the necessary fidelity the system requires that the transformers have primary inductances above 60H and a 1:1 turns ratio. It is also necessary to use a transformer with less than 2.5H of leakage inductance. In terms of pulse shape the primary inductance will mostly effect the pulse droop of the 50ns and 150ns pulses. If the primary inductance is too low, the pulse amplitude will begin to droop and decay over the pulse period. When the pulse droop is severe enough, the effective pulse width seen by the receiver will drop substantially, reducing noise margin. Some droop is acceptable as long as it is a relatively small percentage of 74 L W (W/LEADS) PINS 12.7mm 12.7mm 14.7mm 14.8mm 17.5mm 12.7mm 24.6mm 17.1mm 17.1mm 12.7mm 9.7mm 9.7mm 14.9mm 14.7mm 15.1mm 9.4mm 17.0mm 15.2mm 15.2mm 9.5mm 16SMT 16SMT 10SMT 12SMT 12SMT 16SMT 16SMT 12SMT 12SMT 16SMT 6.7mm 7.6mm 4.4mm 9.5mm 8.9mm 3.2mm 8.9mm 9.2mm 9.2mm 5.2mm 10.4mm 8.6mm 9.3mm 9.1mm 12.1mm 12.1mm 4.5mm 16.6mm 12.0mm 12.0mm 9.1mm 12.7mm 6SMT 6SMT 4SMT 6SMT 6SMT 6SMT 6TH 4SMT 8SMT 4SMT 8SMT AEC- Q200 - - l l - - - - - l - l - - l l l - - l - the total pulse amplitude. The leakage inductance primarily affects the rise and fall times of the pulses. Slower rise and fall times will effectively reduce the pulse width. Pulse width is determined by the receiver as the time the signal is above the threshold set at the ICMP pin. Slow rise and fall times cut into the timing margins. Generally it is best to keep pulse edges as fast as possible. When evaluating transformers, it is also worth noting the parallel winding capacitance. While transformers have very good CMRR at low frequency, this rejection will degrade at higher frequencies, largely due to the winding to winding capacitance. When choosing a transformer, it is best to pick one with less parallel winding capacitance when possible. When choosing a transformer, it is equally important to pick a part that has an adequate isolation rating for the application. The working voltage rating of a transformer is a key spec when selecting a part for an application. 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Interconnecting daisy-chain links between LTC6804-1 devices see <60V stress in typical applications; ordinary pulse and LAN type transformers will suffice. Multi-drop connections and connections to the LTC6820, in general, may need much higher working voltage ratings for good long-term reliability. Usually, matching the working voltage to the voltage of the entire battery stack is conservative. Unfortunately, transformer vendors will often only specify one-second HV testing, and this is not equal to the long-term ("permanent") rating of the part. For example, according to most safety standards a 1.5kV rated transformer is expected to handle 230V continuously, and a 3kV device is capable of 1100V long-term, though manufacturers may not always certify to those levels (refer to actual vendor data for specifics). Usually, the higher voltage transformers are called "high-isolation" or "reinforced insulation" types by the suppliers. Table 48 shows a list of transformers that have been evaluated in isoSPI links. In most applications a common mode choke is also necessary for noise rejection. Table 49 includes a list of suitable CMCs if the CMC is not already integrated into the transformer being used. Table 49. Recommended Common Mode Chokes MANUFACTURER PART NUMBER TDK ACT45B-101-2P Murata DLW43SH101XK2 isoSPI Layout Guidelines Layout of the isoSPI signal lines also plays a significant role in maximizing the noise immunity of a data link. The following layout guidelines are recommended: 1. The transformer should be placed as close to the isoSPI cable connector as possible. The distance should be kept less than 2cm. The LTC6804 should be placed close to but at least 1cm to 2cm away from the transformer to help isolate the IC from magnetic field coupling. 2. A V- ground plane should not extend under the transformer, the isoSPI connector or in between the transformer and the connector. 3. The isoSPI signal traces should be as direct as possible while isolated from adjacent circuitry by ground metal or space. No traces should cross the isoSPI signal lines, unless separated by a ground plane on an inner layer. 680412fc For more information www.linear.com/LTC6804-1 75 LTC6804-1/LTC6804-2 Package Description Please refer to http://www.linear.com/product/LTC6804-1#packaging for the most recent package drawings. G Package 48-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1887 Rev O) 12.50 - 13.10* (.492 - .516) 1.25 0.12 7.8 - 8.2 5.3 - 5.7 0.25 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 - 5.60* (.197 - .221) PARTING LINE 0.10 - 0.25 (.004 - .010) 3. DIMENSIONS ARE IN 0.50 BSC 7.40 - 8.20 (.291 - .323) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2.0 (.079) MAX 1.65 - 1.85 (.065 - .073) 0 - 8 0.50 (.01968) BSC 0.55 - 0.95** (.022 - .037) 1.25 (.0492) REF NOTE: 1.DRAWING IS NOT A JEDEC OUTLINE 2. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS (INCHES) 4. DRAWING NOT TO SCALE 5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE 76 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEATING PLANE 0.20 - 0.30 (.008 - .012) TYP 0.05 (.002) MIN G48 (SSOP) 0910 REV 0 *DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE **LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE 680412fc For more information www.linear.com/LTC6804-1 LTC6804-1/LTC6804-2 Revision History REV DATE DESCRIPTION A 10/13 TJMAX corrected from 125C to 150C PAGE NUMBER WDT pin description updated B 6/14 68 Correction to TME Test Conditions, V(CO) = V- 4, 5 Description of TSLEEP added to STANDBY State Discussion 20 Correction to Temperature Range for TMS Spec, 125C instead of 85C 22 Correction to Measurement Range for Accuracy Check, 2.985V to 3.015V Clarification of CLRSTAT command, which also clears RSVD bits Description of Reserved Bits Added 27 27, 51 28 30, 51 Clarification: Watchdog timer is reset by Qualfied Wake-up Signal 30 Clarification: SPI master supports only SPI mode 3 31 Correction to data register, Dn[3:0] changed to Dn[7:0] 32 Discussion of Address, Broadcast and Polling Commands edited for Clarity 10/16 17, 30, 56, 57 Information added to Recommended Transformers table Note regarding potential differences between CO and V- added C 3 Absolute maximum voltage between V+ to C12 Added Note added in table to define IB Explanation added for issuing ADSTAT command with CHST = 100 43-46 2 22 27, 50 Table 18 (read codes for I2C master operation) added 33 Explanation of setting SPI strength using RB1 and RB2 36 Explanation of the SPI terminating resistor, RM 37 Explanation of SPI termination and use of a single LTC6804 38 Figure 18 added to single LTC6804 SPI termination 40 Explanation of waking up the LTC6804 daisy chain 43 Note added to Fully Isolated Power section to include a diode from V+ to top of cell 59 Section added for isoSPI IBIAS and ICMP setup 67, 68 Section added for modular isoSPI daisy chain 69 Section added for multiple LTC6804s on the same PCB 71 Section added for connecting an MCU to an LTC6804-1 72 Section added for configuring an LTC6804-2 multidrop 72 Section added for basic connection of an LTC6804-2 multidrop 72 Figure 47, 48 added to show isoSPI connections 73 Section added for Transformer Selection Guide 74 Section added for isoSPI Layout Guidelines 75 680412fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. For more www.linear.com/LTC6804-1 77 LTC6804-1/LTC6804-2 Typical Application Basic 12-Cell Monitor with isoSPI Daisy Chain 100 100 100nF V+ 100 CELL12 3.6V CELL11 3.6V + 33 BSS308PE 100 C12 3.3k 10nF + CELL3 TO CELL11 CIRCUITS CELL3 3.6V + 100 CELL2 + 3.6V CELL1 3.6V 33 BSS308PE 100 + 33 BSS308PE 3.3k 10nF 100nF IPB LTC6804-1 IMB S12 ICMP C11 IBIAS S11 SDO (NC) C10 SDI (NC) S10 SCK (IPA) C9 CSB (IMA) S9 ISOMD C8 WDT S8 DRIVE C7 VREG S7 SWTEN C6 VREF1 S6 VREF2 C5 GPIO5 S5 GPIO4 C4 V- S4 V- C3 GPIO3 S3 GPIO2 C2 GPIO1 S2 C0 C1 S1 TG110-AE050N5* 1 16 isoSPIB+ 1 806 120 1.2k 2 10nF NSV1C201MZ4 * 3 6 120 * 7 15 14 * * 8 isoSPIB- 2 11 isoSPIA+ 1 10 isoSPIA- 2 9 isoSPI PORT B isoSPI PORT A 10nF *THE PART SHOWN IS A DUAL TRANSFORMER WITH BUILT-IN COMMON MODE CHOKES 1F 1F 1F 680412 TA02 3.3k 10nF Related Parts PART NUMBER DESCRIPTION COMMENTS LTC6801 Independent Multicell Battery Stack Fault Monitor Monitors Up to 12 Series-Connected Battery Cells for Undervoltage or Overvoltage. Companion to LTC6802, LTC6803 and LTC6804 LTC6802 Precision Multicell Battery Stack Monitor 1st Generation: Superseded by the LTC6804 and LTC6803 for New Designs LTC6803 Precision Multicell Battery Stack Monitor 2nd Generation: Functionally Enhanced and Pin Compatible to the LTC6802 LTC6820 Isolated Bidirectional Communications Interface for SPI Provides an Isolated Interface for SPI Communication Up to 100 Meters, Using a Twisted Pair. Companion to the LTC6804 LTC3300 High Efficiency Bidirectional Multicell Battery Balancer Bidirectional Synchronous Flyback Balancing of Up to 6 Li-Ion or LiFeP04 Cells in Series. Up to 10A Balancing Current (Set by External Components). Bidirectional Architecture Minimizes Balancing Time and Power Dissipation. Up to 92% Charge Transfer Efficiency. 48-Lead Exposed Pad QFN and LQFP Packages 78 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC6804-1 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC6804-1 680412fc LT 1016 REV C * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013