JWS50-24/A - TDK - Datasheet.Live

16-Bit 1 MSPS PulSARTM

Unipolar ADC with Reference

AD7653

Rev. A

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Tel: 781.329.4700 www.analog.com

FEATURES

Throughput:

1 MSPS (Warp mode)

800 kSPS (Normal mode)

666 kSPS (Impulse mode)

16-bit resolution

Analog input voltage range: 0 V to 2.5 V

No pipeline delay

Parallel and serial 5 V/3 V interface

SPI®/QSPITM/MICROWIRETM/DSP compatible

Single 5 V supply operation

Power dissipation

92 mW typ @ 666 kSPS, 138 μW @ 1 kSPS without REF

128 mW typ @ 1 MSPS with REF

48-lead LQFP and 48-lead LFCSP packages

Pin-to-pin compatible with PulSAR ADCs

APPLICATIONS

Data acquisition

Instrumentation

Digital signal processing

Spectrum analysis

Medical instruments

Battery-powered systems

Process control

GENERAL DESCRIPTION

The AD7653 is a 16-bit, 1 MSPS, charge redistribution SAR

analog-to-digital converter that operates from a single 5 V

power supply. The part contains a high speed 16-bit sampling

ADC, internal conversion clock, internal reference, error

correction circuits, and both serial and parallel system interface

ports. It features a very high sampling rate mode (Warp), a fast

mode (Normal) for asynchronous conversion rate applications,

and a reduced power mode (Impulse) for low power applica-

tions where power is scaled with the throughput. The AD7653 is

fabricated using Analog Devices’ high performance, 0.6 micron

CMOS process, with correspondingly low cost. It is available in

a 48-lead LQFP and a tiny 48-lead LFCSP with operation

specified from –40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

02966-0-001

SWITCHED

CAP DAC

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

CLOCK

AD7653

DATA[15:0]

BUSY

SER/PAR

OB/2C

OGND

OVDD

DGNDDVDD

AVDD

AGND

REF REFGND

INGND

RESET

SERIAL

PORT

PARALLEL

INTERFACE

CNVSTWARP IMPULSE

REF

REFBUFIN

PDBUF

PDREF

BYTESWAP

Figure 1.

Table 1. PulSAR Selection

Type/kSPS 100–250 500–570

800–

1000

Pseudo-

Differential

AD7651

AD7660/AD7661

AD7650/AD7652

AD7664/AD7666

AD7653

AD7667

True Bipolar AD7663 AD7665 AD7671

True

Differential

AD7675 AD7676 AD7677

18-Bit AD7678 AD7679 AD7674

Multichannel/

Simultaneous

AD7654

AD7655

PRODUCT HIGHLIGHTS

1. Fast Throughput.

The AD7653 is a 1 MSPS, charge redistribution, 16-bit SAR

ADC with internal error correction circuitry.

2. Internal Reference.

The AD7653 has an internal reference with a typical

temperature drift of 7 ppm/°C.

3. Single-Supply Operation.

The AD7653 operates from a single 5 V supply. In Impulse

mode, its power dissipation decreases with the throughput.

4. Serial or Parallel Interface.

Versatile parallel or 2-wire serial interface arrangement is

compatible with both 3 V and 5 V logic.

AD7653

Rev. A | Page 2 of 28

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 7

Pin Configuration and Function Descriptions............................. 8

Definitions of Specifications ......................................................... 11

Typical Performance Characteristics ........................................... 12

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

Typical Connection Diagram.................................................... 17

Power Dissipation vs. Throughput........................................... 19

Conversion Control.................................................................... 19

Digital Interface .......................................................................... 20

Parallel Interface......................................................................... 20

Serial Interface ............................................................................ 20

Master Serial Interface............................................................... 21

Slave Serial Interface .................................................................. 22

Microprocessor Interfacing....................................................... 24

Application Hints............................................................................ 25

Bipolar and Wider Input Ranges.............................................. 25

Layout .......................................................................................... 25

Evaluating the AD7653’s Performance .................................... 25

Outline Dimensions ....................................................................... 26

Ordering Guide........................................................................... 26

REVISION HISTORY

Location Page

9/03—Data Sheet Changed from Rev. 0 to Rev. A

Change to Product Highlights .................................................... 1

Changes to Specifications............................................................ 3

Changes to Absolute Maximum Ratings ................................... 7

Changes to Figure 15.................................................................. 13

Changes to Figure 22.................................................................. 16

Changes to Voltage Reference Input section........................... 18

Changes to Figure 31.................................................................. 20

AD7653

SPECIFICATIONS

Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits

ANALOG INPUT

Voltage Range VIN – VINGND 0 VREF V

Operating Input Voltage VIN –0.1 +3 V

INGND –0.1 +0.5 V

Analog Input CMRR fIN = 10 kHz 65 dB

Input Current 1 MSPS Throughput 12 µA

Input Impedance1

THROUGHPUT SPEED

Complete Cycle In Warp Mode 1 µs

Throughput Rate In Warp Mode 1 1000 kSPS

Time between Conversions In Warp Mode 1 ms

Complete Cycle In Normal Mode 1.25 µs

Throughput Rate In Normal Mode 0 800 kSPS

Complete Cycle In Impulse Mode 1.5 µs

Throughput Rate In Impulse Mode 0 666 kSPS

DC ACCURACY

Integral Linearity Error –6 +6 LSB2

No Missing Codes 15 Bits

Differential Linearity Error –2 +3 LSB

Transition Noise 0.7 LSB

Unipolar Zero Error, TMIN to TMAX3 ±25 LSB

Unipolar Zero Error Temperature Drift ±0.2 ppm/°C

Full-Scale Error, TMIN to TMAX3 REF = 2.5 V ±0.12 % of FSR

Full-Scale Error Temperature Drift ±0.4 ppm/°C

Power Supply Sensitivity AVDD = 5 V ± 5%, with REF ±2 LSB

AC ACCURACY

Signal-to-Noise fIN = 100 kHz 86 dB4

Spurious Free Dynamic Range fIN = 100 kHz 98 dB

Total Harmonic Distortion fIN = 45 kHz –98 dB

IN = 100 kHz –96 dB

Signal-to-(Noise + Distortion) fIN = 100 kHz 86 dB

–60 dB Input, fIN = 100 kHz 30 dB

–3 dB Input Bandwidth 12 MHz

SAMPLING DYNAMICS

Aperture Delay 2 ns

Aperture Jitter 5 ps rms

Transient Response Full-Scale Step 250 ns

REFERENCE

Internal Reference Voltage VREF @ 25°C 2.48 2.50 2.52 V

Internal Reference Temperature Drift –40°C to +85°C ±7 ppm/°C

Line Regulation AVDD = 5 V ± 5% ±24 ppm/V

Turn-On Settling Time CREF = 10 µF 5 ms

Temperature Pin

Voltage Output @ 25°C 300 mV

Temperature Sensitivity 1 mV/°C

Output Resistance 4.3 kΩ

External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V

External Reference Current Drain 1 MSPS Throughput 300 µA

Rev. A | Page 3 of 28

AD7653

Parameter Conditions Min Typ Max Unit

DIGITAL INPUTS

Logic Levels

VIL –0.3 +0.8 V

VIH 2.0 DVDD + 0.3 V

IIL –1 +1 µA

IIH –1 +1 µA

DIGITAL OUTPUTS

Data Format5

Pipeline Delay6

VOL I

SINK = 1.6 mA 0.4 V

VOH I

SOURCE = –500 µA OVDD – 0.6 V

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V

DVDD 4.75 5 5.25 V

OVDD 2.7 5.257 V

Operating Current8 1 MSPS Throughput

AVDD9 With Reference and Buffer 18.7 mA

AVDD10 Reference and Buffer Alone 3 mA

DVDD11 6.7 mA

OVDD11 200 µA

Power Dissipation without REF 666 kSPS Throughput11 92 115 mW

1 kSPS Throughput11 138 µW

Power Dissipation with REF 1 MSPS Throughput8 128 145 mW

TEMPERATURE RANGE12

Specified Performance TMIN to TMAX –40 +85 °C

1See Analog Input section.

2LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV.

3See Definitions of Specifications section. These specifications do not include the error contribution from the external reference.

4All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

5Parallel or serial 16-bit.

6Conversion results are available immediately after completed conversion.

7The max should be the minimum of 5.25 V and DVDD + 0.3 V.

8In Warp mode.

9With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.

10With PDREF, PDBUF LOW and PD HIGH.

11Impulse Mode. Tested in Parallel Reading mode.

12Consult factory for extended temperature range.

Rev. A | Page 4 of 28

AD7653

TIMING SPECIFICATIONS

Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted

Parameter Symbol Min Typ Max Unit

Refer to Figure 26 and Figure 27

Convert Pulse Width t1 10 ns

Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)1 t2 1/1.25/1.5 µs

CNVST LOW to BUSY HIGH Delay t3 35 ns

BUSY HIGH All Modes Except Master Serial Read after Convert

(Warp Mode/Normal Mode/Impulse Mode) t4 0.75/1/1.25 µs

Aperture Delay t5 2 ns

End of Conversion to BUSY LOW Delay t6 10 ns

Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t7 0.75/1/1.25 µs

Acquisition Time t8 250 ns

RESET Pulse Width t9 10 ns

Refer to Figure 28, Figure 29, and (Parallel Interface Modes)

CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) t10 0.75/1/1.25 µs

DATA Valid to BUSY LOW Delay t11 12 ns

Bus Access Request to DATA Valid t12 45 ns

Bus Relinquish Time t13 5 15 ns

Refer to Figure 32 and Figure 33 (Master Serial Interface Modes)2

CS LOW to SYNC Valid Delay t14 10 ns

CS LOW to Internal SCLK Valid Delay2 t15 10 ns

CS LOW to SDOUT Delay t16 10 ns

CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) t17 25/275/525 ns

SYNC Asserted to SCLK First Edge Delay t18 3 ns

Internal SCLK Period3 t19 25 40 ns

Internal SCLK HIGH3 t20 12 ns

Internal SCLK LOW3 t21 7 ns

SDOUT Valid Setup Time3 t22 4 ns

SDOUT Valid Hold Time3 t23 2 ns

SCLK Last Edge to SYNC Delay3 t24 3 ns

CS HIGH to SYNC HI-Z t25 10 ns

CS HIGH to Internal SCLK HI-Z t26 10 ns

CS HIGH to SDOUT HI-Z t27 10 ns

BUSY HIGH in Master Serial Read after Convert3

(Warp Mode/Normal Mode/Impulse Mode) t28 See Table 4

CNVST LOW to SYNC Asserted Delay

(Warp Mode/Normal Mode/Impulse Mode) t29 0.75/1/1.25 µs

SYNC Deasserted to BUSY LOW Delay t30 25 ns

Refer to and (Slave Serial Interface Modes) 2

External SCLK Setup Time t31 5 ns

External SCLK Active Edge to SDOUT Delay t32 3 18 ns

SDIN Setup Time t33 5 ns

SDIN Hold Time t34 5 ns

External SCLK Period t35 25 ns

External SCLK HIGH t36 10 ns

External SCLK LOW t37 10 ns

Figure 30

Figure 34 Figure 35

1In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.

2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

3In Serial Master Read during Convert Mode. See for Serial Master Read after Convert mode. Table 4

Rev. A | Page 5 of 28

AD7653

Table 4. Serial Clock Timings in Master Read after Convert

DIVSCLK[1] 0 0 1 1

DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns

Internal SCLK Period Minimum t19 25 50 100 200 ns

Internal SCLK Period Maximum t19 40 70 140 280 ns

Internal SCLK HIGH Minimum t20 12 22 50 100 ns

Internal SCLK LOW Minimum t21 7 21 49 99 ns

SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns

SDOUT Valid Hold Time Minimum t23 2 4 30 80 ns

SCLK Last Edge to SYNC Delay Minimum t24 3 55 130 290 ns

BUSY HIGH Width Maximum (Warp) t28 1.5 2 3 5.25 µs

BUSY HIGH Width Maximum (Normal) t28 1.75 2.25 3.25 5.55 µs

BUSY HIGH Width Maximum (Impulse) t28 2 2.5 3.5 5.75 µs

Rev. A | Page 6 of 28

AD7653

ABSOLUTE MAXIMUM RATINGS

Table 5. AD7653 Absolute Maximum Ratings1

Parameter Rating

IN2, TEMP2,REF, REFBUFIN,

INGND, REFGND to AGND

AVDD + 0.3 V to

AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD –0.3 V to +7 V

AVDD to DVDD, AVDD to OVDD ±7 V

DVDD to OVDD –0.3 V to +7 V

Digital Inputs –0.3 V to DVDD + 0.3 V

PDREF, PDBUF3 ±20 mA

Internal Power Dissipation4 700 mW

Internal Power Dissipation5 2.5 W

Junction Temperature 150°C

Storage Temperature Range –65°C to +150°C

Lead Temperature Range

(Soldering 10 sec)

300°C

1Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions above those listed

in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect

device reliability.

2See section.

3See Voltage Reference Input section.

4Specification is for the device in free air:

48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W

5Specification is for the device in free air:

48-Lead LFCSP; θJA = 26°C/W.

Analog Input

500µA

1.6mA I

TO OUTPUT

PIN 1.4V

60pF*

* IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND

SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD

OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.

02966-0-006

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, SCLK Outputs CL = 10 pF

0.8V

tDELAY tDELAY

02966-0-007

Figure 3. Voltage Reference Levels for Timing

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page 7 of 28

AD7653

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 39 38 3743 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AGND

CNVST

RESET

DGND

AGND

AVDD

BYTESWAP

OB/2C

WARP

IMPULSE

NC = NO CONNECT

SER/PAR

BUSY

D15

D14

D13

AD7653

D3/DIVSCLK1 D12

D4/EXT/INT

D5/INVSYNC

D6/INVSCLK

D7/RDC/SDIN

OGND

OVDD

DVDD

DGND

D8/SDOUT

D9/SCLK

D10/SYNC

D11/RDERROR

PDBUF

PDREF

REFBUFIN

TEMP

AVDD

AGND

INGND

REFGND

REF

02966-0-002

D2/DIVSCLK0

Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1, 36,

41, 42

AGND P Analog Power Ground Pin.

2, 44 AVDD P Input Analog Power Pin. Nominally 5 V.

3, 40 NC No Connect.

4 BYTESWAP DI Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on

D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].

5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;

when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift

6 WARP DI Mode Selection. When this pin is HIGH and the IMPULSE pin is LOW, this input selects the fastest

mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in

order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of

the minimum conversion rate.

7 IMPULSE DI Mode Selection. When IMPULSE is HIGH and WARP is LOW, this input selects a reduced power

mode. In this mode, the power dissipation is approximately proportional to the sampling rate.

8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial

interface mode is selected and some bits of the DATA bus are used as a serial port.

9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high

impedance.

11, 12 D[2:3]or

DIVSCLK[0:1]

DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.

When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert),

these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that

clocks the data output. In other serial modes, these pins are not used.

13 D4 or

EXT/INT

DI/O When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.

When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choos-

ing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is

selected on the SCLK output. With EXT/INT set to logic HIGH, output data is synchronized to an

external clock signal connected to the SCLK input.

14 D5 or

INVSYNC

DI/O When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus.

When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the

SYNC signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When

HIGH, SYNC is active LOW.

Rev. A | Page 8 of 28

AD7653

Pin No. Mnemonic Type1 Description

15 D6 or

INVSCLK

DI/O When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.

When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active

in both master and slave modes.

16 D7 or

RDC/SDIN

DI/O When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus.

When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a

read mode selection input depending on the state of EXT/INT.

When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion

results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on

DATA with a delay of 16 SCLK periods after the initiation of the read sequence.

When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data

is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT

only when the conversion is complete.

17 OGND P Input/Output Interface Digital Power Ground.

18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface

(5 V or 3 V).

19 DVDD P Digital Power. Nominally at 5 V.

20 DGND P Digital Power Ground.

21 D8 or

SDOUT

DO When SER/PAR is LOW, this output is used as Bit 8 of the parallel port data output bus.

When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchro-

nized to SCLK. Conversion results are stored in an on-chip register. The AD7653 provides the

conversion result, MSB first, from its internal shift register. The DATA format is determined by the

logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In

serial mode when EXT/INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge

and valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge

and valid on the next rising edge.

22 D9 or

SCLK

DI/O When SER/PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus.

When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,

depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is

updated depends upon the logic state of the INVSCLK pin.

23 D10 or

SYNC

DO When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus.

When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame

synchronization for use with the internal data clock (EXT/INT = logic LOW). When a read sequence is

initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is

valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains

LOW while the SDOUT output is valid.

24 D11 or

RDERROR

DO When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When

SER/PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read

error flag. In slave mode, when a data read is started and not complete when the following

conversion is complete, the current data is lost and RDERROR is pulsed HIGH.

25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the

state of SER/PAR.

29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion

is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be

used as a data ready clock signal.

30 DGND P Must Be Tied to Digital Ground.

31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.

32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS

is also used to gate the external clock.

33 RESET DI Reset Input. When set to a logic HIGH, this pin resets the AD7653 and the current conversion, if any,

is aborted. If not used, this pin could be tied to DGND.

34 PD DI Power-Down Input. When set to logic HIGH, power consumption is reduced and conversions are

inhibited after the current one is completed.

35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and

initiates a conversion. In Impulse mode (IMPULSE HIGH, WARP LOW), if CNVST is held LOW when

the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a

conversion is immediately started.

Rev. A | Page 9 of 28

AD7653

Pin No. Mnemonic Type1 Description

37 REF AI/O Reference Input Voltage. On-chip reference output voltage.

38 REFGND AI Reference Input Analog Ground.

39 INGND AI Analog Input Ground.

43 IN AI Primary Analog Input with a Range of 0 V to 2.5 V.

45 TEMP AO Temperature Sensor Voltage Output.

46 REFBUFIN AI/O Reference Input Voltage. The reference output and the reference buffer input.

47 PDREF DI This pin allows the choice of internal or external voltage references. When LOW, the on-chip

reference is turned on. When HIGH, the internal reference is switched off and an external reference

must be used.

48 PDBUF DI This pin allows the choice of buffering an internal or external reference with the internal buffer.

When LOW, the buffer is selected. When HIGH, the buffer is switched off.

1AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.

Rev. A | Page 10 of 28

AD7653

DEFINITIONS OF SPECIFICATIONS

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code

from a line drawn from negative full scale through positive full

scale. The point used as negative full scale occurs ½ LSB before

the first code transition. Positive full scale is defined as a level

1½ LSB beyond the last code transition. The deviation is

measured from the middle of each code to the true straight line.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential

nonlinearity is the maximum deviation from this ideal value. It

is often specified in terms of resolution for which no missing

codes are guaranteed.

Full-Scale Error

The last transition (from 011…10 to 011…11 in twos

complement coding) should occur for an analog voltage 1½ LSB

below the nominal full scale (2.49994278 V for the 0 V to 2.5 V

range). The full-scale error is the deviation of the actual level of

the last transition from the ideal level.

Unipolar Zero Error

The first transition should occur at a level ½ LSB above analog

ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero

error is the deviation of the actual transition from that point.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms

amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave

input. It is related to S/(N+D) by the following formula:

ENOB = (S/[N+D]dB – 1.76)/6.02

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic

components to the rms value of a full-scale input signal, and is

expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the

rms sum of all other spectral components below the Nyquist

frequency, excluding harmonics and dc. The value for SNR is

expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (S/[N+D])

S/(N+D) is the ratio of the rms value of the actual input signal

to the rms sum of all other spectral components below the

Nyquist frequency, including harmonics but excluding dc. The

value for S/(N+D) is expressed in decibels.

Aperture Delay

Aperture delay is a measure of the acquisition performance and

is measured from the falling edge of the CNVST input to when

the input signal is held for a conversion.

Transient Response

Transient response is the time required for the AD7653 to

achieve its rated accuracy after a full-scale step function is

applied to its input.

Overvoltage Recovery

Overvoltage recovery is the time required for the ADC to

recover to full accuracy after an analog input signal 150% of the

full-scale value is reduced to 50% of the full-scale value.

Reference Voltage Temperature Coefficient

Reference voltage temperature coefficient is the change of

internal reference voltage output voltage V over the operating

temperature range and normalized by the output voltage at

25°C, expressed in ppm/°C. The equation follows:

12 10

)–()C25(

)(–)(

)/( ×

×°

=° TTV

TVTV

CppmTCV

where:

V(25°C) = V at +25°C

V(T2) = V at Temperature 2 (+85°C)

V(T1) = V at Temperature 1 (–40°C)

Rev. A | Page 11 of 28

AD7653

TYPICAL PERFORMANCE CHARACTERISTICS

CODE

INL (LSB)

–4

–3

–1

–2

16384 32768 65536

49152

02966-0-023

Figure 5. Integral Nonlinearity vs. Code

CODE IN HEX

COUNTS

7FFB

20000

60000

40000

80000

140000

120000

8000 8001 80038002

02966-0-027

80047FFC 7FFD 7FFE 7FFF

100000

17001

00 00

377

679

15906

114641

112516

Figure 6. Histogram of 261,120 Conversions of a

DC Input at the Code Transition

FREQUENCY (kHz)

AMPLITUDE (dB of Full Scale)

–180

–160

–120

–140

–100

–60

–80

200 300 500400

02966-0-029

100

–40

–20

= 1000kSPS

= 101kHz

SNR = 86.0dB

THD = 90.3dB

SFDR = 91.5dB

S/[N+D] = 84.8dB

Figure 7. FFT Plot

CODE

DNL (LSB)

–1.0

–0.5

0.5

1.0

2.0

1.5

16384 32768 65536

49152

02966-0-026

Figure 8. Differential Nonlinearity vs. Code

CODE IN HEX

COUNTS

20000

80000

40000

100000

160000

120000

8000 8001 80038002

02966-0-028

80047FFC 7FFD 7FFE 7FFF

053 2856 3099 90

60000

146148

54473

54482

140000

Figure 9. Histogram of 261,120 Conversions of a

DC Input at the Code Center

FREQUENCY (kHz)

SNR, S/[N+D] (dB)

100

02966-0-030

1000

ENOB (Bits)

15.0

12.0

14.5

12.5

13.0

13.5

14.0

ENOB

SNR

S/[N+D]

Figure 10. SNR, S/(N+D), and ENOB vs. Frequency

Rev. A | Page 12 of 28

AD7653

FREQUENCY (kHz)

THD, HARMONICS (dB)

–120

–100

–80

–90

–70

–50

100

02966-0-031

1000

–60

SFDR (dB)

120

100

SECOND

HARMONIC

SFDR

THIRD

HARMONIC

–110

THD

Figure 11. THD, Harmonics, and SFDR vs. Frequency

INPUT LEVEL (dB)

SNR, S/[N+D] REFERRED TO FULL SCALE (dB)

–60

02966-A-032

0–50 –40 –30 –20 –10

SNR

S/[N+D]

Figure 12. SNR and S/(N+D) vs. Input Level (Referred to Full Scale)

TEMPERATURE (°C)

SNR, S/[N+D] (dB)

–55

02966-0-033

125–35 –15 25 45 65

88 SNR

ENOB

S[N+D]

585

105

13.75

14.75

14.00

14.25

14.50

ENOB (Bits)

Figure 13. SNR, S/(N+D), and ENOB vs. Temperature

TEMPERATURE (°C)

THD, HARMONICS (dB)

–55

–125

–95

02966-0-034

125–35 –15 25 45 65

–115

–105

SECOND

HARMONIC

585

105

THIRD

HARMONIC

THD

Figure 14. THD and Harmonics vs. Temperature

SAMPLE RATE (SPS)

02966-0-036

1000000100 10000 100000

100

1000

100000

0.001

0.1

0.01

OPERATING CURRENT (µA)

AVDD, WARP/NORMAL

DVDD, IMPULSE

OVDD, ALL MODES

DVDD, WARP/NORMAL

AVDD, IMPULSE

PDREF = PDBUF = HIGH

10000

Figure 15. Operating Current vs. Sample Rate

TEMPERATURE (°C)

ZERO ERROR, FULL SCALE (LSB)

–55

02966-0-040

125–35 5 25 45 65

–15 85 105

–1

–3

–2

–5

–4

–6

ZERO ERROR

FULL SCALE

Figure 16. Zero Error, Full Scale with Reference vs. Temperature

Rev. A | Page 13 of 28

AD7653

TEMPERATURE (°C)

VREF (V)

–40

2.5008

2.5020

02966-0-038

–20 0 20 40 60

2.5010

2.5012

2.5013

2.5014

2.5015

2.5016

2.5017

2.5018

2.5019

80 100 120

2.5009

2.5011

Figure 17. Typical Reference Output Voltage vs. Temperature

REFERENCE DRIFT (ppm/°C)

NUMBER OF UNITS

–30

02966-0-039

–26 –22 –18 –14

–10 –6 –2 2 3026221814106

Figure 18. Reference Voltage Temperature Coefficient Distribution (335 Units)

(pF)

DELAY (ns)

02966-0-035

20050 100 150

20 OVDD = 5V @ 25°C

OVDD = 5V @ 85°C

OVDD = 2.7V @ 25°C

OVDD = 2.7V @ 85°C

Figure 19. Typical Delay vs. Load Capacitance CL

Rev. A | Page 14 of 28

AD7653

CIRCUIT INFORMATION

COMP

REF

REFGND

LSB

MSB

32,768C

INGND

16,384C 4C 2C C C

65,536C

CONTROL

LOGIC

SWITCHES

CONTROL

BUSY

OUTPUT

CODE

02966-0-005

CNVST

Figure 20. ADC Simplified Schematic

igure 20

The AD7653 is a very fast, low power, single supply, precise

16-bit analog-to-digital converter (ADC). The AD7653 features

different modes to optimize performance according to the

application. In Warp mode, the part can convert 1 million

samples per second.

from the inputs and connected to REFGND. Therefore, the

differential voltage between IN and INGND captured at the end

of the acquisition phase is applied to the comparator inputs,

causing the comparator to become unbalanced. By switching

each element of the capacitor array between REFGND and REF,

the comparator input varies by binary weighted voltage steps

(VREF/2, VREF/4, …VREF/65536). The control logic toggles

these switches, starting with the MSB, to bring the comparator

back into a balanced condition.

The AD7653 provides the user with an on-chip track/hold,

successive approximation ADC that does not exhibit any

pipeline or latency, making it ideal for multiple multiplexed

channel applications.

After this process is completed, the control logic generates the

ADC output code and brings the BUSY output LOW.

The AD7653 can be operated from a single 5 V supply and can

be interfaced to either 5 V or 3 V digital logic. It is housed in

either a 48-lead LQFP or a 48-lead LFCSP that saves space and

allows flexible configurations as either a serial or a parallel

interface. The AD7653 is a pin-to-pin compatible upgrade of the

AD7651/AD7652.

Modes of Operation

The AD7653 features three modes of operations: Warp, Normal,

and Impulse. Each mode is best suited for specific applications.

Warp mode allows the fastest conversion rate up to 1 MSPS.

However in this mode and this mode only, the full specified

accuracy is guaranteed only when the time between conversions

does not exceed 1 ms. If the time between two consecutive

conversions is longer than 1 ms (e.g., after power-up), the first

conversion result should be ignored. This mode makes the

AD7653 ideal for applications where both high accuracy and

fast sample rate are required.

CONVERTER OPERATION

The AD7653 is a successive approximation ADC based on a

charge redistribution DAC. F shows a simplified

schematic of the ADC. The capacitive DAC consists of an array

of 16 binary weighted capacitors and an additional LSB

capacitor. The comparator’s negative input is connected to a

dummy capacitor of the same value as the capacitive DAC array.

Normal mode is the fastest mode (800 kSPS) without any

limitations on the time between conversions. This mode makes

the AD7653 ideal for asynchronous applications such as data

acquisition systems, where both high accuracy and fast sample

rate are required.

During the acquisition phase, the common terminal of the array

tied to the comparator’s positive input is connected to AGND

via SWA. All independent switches are connected to the analog

input IN. Thus, the capacitor array is used as a sampling

capacitor and acquires the analog signal on IN. Similarly, the

dummy capacitor acquires the analog signal on INGND. Impulse mode, the lowest power dissipation mode, allows power

saving between conversions. When operating at 1 kSPS, for

example, it typically consumes only 138 µW. This feature makes

the AD7653 ideal for battery-powered applications.

When CNVST goes LOW, a conversion phase is initiated. When

the conversion phase begins, SWA and SWB are opened. The

capacitor array and dummy capacitor are then disconnected

Rev. A | Page 15 of 28

AD7653

Transfer Functions

Using the OB/2C digital input, the AD7653 offers two output

codings: straight binary and twos complement. The LSB size is

VREF/65536, which is about 38.15 µV. The AD7653’s ideal

transfer characteristic is shown in and . Table 7

Table 7. Output Codes and Ideal Input Voltages

Digital Output Code (Hex)

Description

Analog

Input

Straight

Binary

Twos

Complement

FSR – 1 LSB 2.499962 V FFFF1 7FFF1

FSR – 2 LSB 2.499923 V FFFE 7FFE

Midscale + 1 LSB 1.250038 V 8001 0001

Midscale 1.25 V 8000 0000

Midscale – 1 LSB 1.249962 V 7FFF FFFF

–FSR + 1 LSB 38 µV 0001 8001

–FSR 0 V 00002 80002

Figure 21

Figure 21. ADC Ideal Transfer Function

000...000

000...001

000...010

111...101

111...110

111...111

ADC CODE (Straight Binary)

ANALOG INPUT

REF

– 1.5 LSB

REF

– 1 LSB

1LSB0V

0.5 LSB

1 LSB = V

REF

/65536

02966-0-003

1This is also the code for overrange analog input (VIN – VINGND above

VREF – VREFGND).

2This is also the code for underrange analog input (VIN below VINGND).

NOTES

THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER.

THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.

OPTIONAL LOW JITTER.

A 10

F CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M).

SEE VOLTAGE REFERENCE INPUT SECTION.

AD7653

CLOCK

µC/µP/DSP

SERIAL

PORT

DIGITAL SUPPLY

(3.3V OR 5V)

DVDD

100nF +

100nF

Ω

100nF

ANALOG

SUPPLY

(5V)

2.7nF

15Ω

ANALOG INPUT

(0V TO 2.5V)

PD RESET

IMPULSE

WARP

SER/PAR

OB/2C

BUSY

SDOUT

SCLK

INGND

REFGND

REF

GND

AVDD DGND DVDD OVDD OGND

02966-A-004

PDREF PDBUF RDCS

BYTESWAP

CNVST

REFBUFIN

100nF

Figure 22. Typical Connection Diagram

Rev. A | Page 16 of 28

AD7653

TYPICAL CONNECTION DIAGRAM when the switches are opened, the input impedance is limited to

C1. R1 and C2 make a 1-pole low-pass filter that reduces

undesirable aliasing effects and limits the noise.

Figure 22 shows a typical connection diagram for the AD7653.

Analog Input

When the source impedance of the driving circuit is low, the

AD7653 can be driven directly. Large source impedances will

significantly affect the ac performance, especially total

harmonic distortion.

Figure 23

Figure 23. Equivalent Analog Input Circuit

shows an equivalent circuit of the input structure of

the AD7653.

The two diodes, D1 and D2, provide ESD protection for the

analog inputs IN and INGND. Care must be taken to ensure

that the analog input signal never exceeds the supply rails by

more than 0.3 V. This will cause these diodes to become

forward-biased and start conducting current. These diodes can

handle a forward-biased current of 100 mA maximum. For

instance, these conditions could eventually occur when the

input buffer’s (U1) supplies are different from AVDD. In such a

case, an input buffer with a short-circuit current limitation can

be used to protect the part.

Driver Amplifier Choice

Although the AD7653 is easy to drive, the driver amplifier needs

to meet the following requirements:

• The driver amplifier and the AD7653 analog input circuit

must be able to settle for a full-scale step of the capacitor

array at a 16-bit level (0.0015%). In the amplifier’s data

sheet, settling at 0.1% to 0.01% is more commonly

specified. This could differ significantly from the settling

time at a 16-bit level and should be verified prior to driver

selection. The tiny op amp AD8021, which combines

ultralow noise and high gain-bandwidth, meets this settling

time requirement even when used with gains up to 13.

R INGND

AGND

AV D D

02966-0-008

• The noise generated by the driver amplifier needs to be

kept as low as possible in order to preserve the SNR and

transition noise performance of the AD7653. The noise

coming from the driver is filtered by the AD7653 analog

input circuit 1-pole low-pass filter made by R1 and C2 or

by the external filter, if one is used.

This analog input structure allows the sampling of the different-

tial signal between IN and INGND. Unlike other converters,

INGND is sampled at the same time as IN. By using this differ-

ential input, small signals common to both inputs are rejected.

For instance, by using INGND to sense a remote signal ground,

ground potential differences between the sensor and the local

ADC ground are eliminated.

• The driver needs to have a THD performance suitable to

that of the AD7653.

The AD8021 meets these requirements and is appropriate for

almost all applications. The AD8021 needs a 10 pF external

compensation capacitor that should have good linearity as an

NPO ceramic or mica type.

During the acquisition phase, the impedance of the analog input

IN can be modeled as a parallel combination of capacitor C1

and the network formed by the series connection of R1 and C2.

C1 is primarily the pin capacitance. R1 is typically 168 Ω and is

a lumped component made up of some serial resistors and the

on resistance of the switches. C2 is typically 60 pF and is mainly

the ADC sampling capacitor. During the conversion phase,

The AD8022 could also be used if a dual version is needed and

gain of 1 is present. The AD829 is an alternative in applications

where high frequency (above 100 kHz) performance is not

required. In gain of 1 applications, it requires an 82 pF

compensation capacitor. The AD8610 is an option when low

bias current is needed in low frequency applications.

Rev. A | Page 17 of 28

AD7653

Voltage Reference Input

The AD7653 allows the choice of either a very low temperature

drift internal voltage reference or an external 2.5 V reference.

For applications that use multiple AD7653s, it is more effective

to use the internal buffer to buffer the reference voltage.

Unlike many ADCs with internal references, the internal

reference of the AD7653 provides excellent performance and

can be used in almost all applications.

Care should be taken with the voltage reference’s temperature

coefficient, which directly affects the full-scale accuracy, if this

parameter matters. For instance, a ±15 ppm/°C temperature

coefficient of the reference changes full scale by ±1 LSB/°C.

To use the internal reference along with the internal buffer,

PDREF and PDBUF should both be LOW. This will produce a

1.207 V voltage on REFBUFIN which, amplified by the buffer,

will result in a 2.5 V reference on the REF pin.

Note that VREF can be increased to AVDD – 1.85 V. Since the

input range is defined in terms of VREF, this would essentially

increase the range to 0 V to 3 V with an AVDD above 4.85 V.

The AD780 can be selected with a 3 V reference voltage.

The output impedance of REFBUFIN is 11 kΩ (minimum) when

the reference is enabled. It is useful to decouple REFBUFIN with

a 100 nF ceramic capacitor. Thus, the 100 nF capacitor provides

an RC filter for noise reduction.

The TEMP pin, which measures the temperature of the AD7653,

can be used as shown in . The output of the TEMP pin

is applied to one of the inputs of the analog switch (e.g.,

ADG779), and the ADC itself is used to measure its own

temperature. This configuration is very useful for improving the

calibration accuracy over the temperature range.

Figure 24

Figure 24. Temperature Sensor Connection Diagram

To use an external reference along with the internal buffer,

PDREF should be HIGH and PDBUF should be LOW. This

powers down the internal reference and allows the 2.5 V

reference to be applied to REFBUFIN.

ADG779

AD8021 C

02966-0-024

NALOG INPU

(UNIPOLAR)

AD7653

TEMPERATURE

SENSOR

TEMP

To use an external reference directly on the REF pin, PDREF

and PDBUF should both be HIGH.

PDREF and PDBUF, respectively, power down the internal

reference and the internal reference. Note that the PDREF and

PDBUF input current should never exceed 20 mA. This could

eventually occur when input voltage is above AVDD (for

instance at power-up). In this case, a 100 Ω series resistor is

recommended.

Power Supply

The AD7653 uses three power supply pins: an analog 5 V supply

AVDD, a digital 5 V core supply DVDD, and a digital

input/output interface supply OVDD. OVDD allows direct

interface with any logic between 2.7 V and DVDD + 0.3 V. To

reduce the supplies needed, the digital core (DVDD) can be

supplied through a simple RC filter from the analog supply, as

shown in . The AD7653 is independent of power

supply sequencing once OVDD does not exceed DVDD by

more than 0.3 V, and is thus free of supply voltage induced

latch-up.

The internal reference is temperature compensated to 2.5 V ±

20 mV. The reference is trimmed to provide a typical drift of 7

. This typical drift characteristic is shown in .

For improved drift performance, an external reference such as

the AD780 can be used.

ppm/°C Figure 17

Figure 22

The AD7653 voltage reference input REF has a dynamic input

impedance; it should, therefore, be driven by a low impedance

source with efficient decoupling between the REF and REFGND

inputs. This decoupling depends on the choice of the voltage

reference, but usually consists of a low ESR capacitor connected

to REF and REFGND with minimum parasitic inductance. A

10 µF (X5R, 1206 size) ceramic chip capacitor (or 47 µF

tantalum capacitor) is appropriate when using either the

internal reference or one of these recommended reference

voltages:

• The low noise, low temperature drift ADR421 and AD780

• The low power ADR291

• The low cost AD1582

Rev. A | Page 18 of 28

AD7653

The CNVST trace should be shielded with ground and a low

value serial resistor (i.e., 50 Ω) termination should be added

close to the output of the component that drives this line.

POWER DISSIPATION VS. THROUGHPUT

Operating currents are very low during the acquisition phase,

allowing significant power savings when the conversion rate is

reduced (see F ). This power savings depends on the

mode used. In Impulse mode, the AD7653 automatically

reduces power consumption at the end of each conversion

phase. This makes the part ideal for very low power battery

applications. The digital interface and the reference remain

active even during the acquisition phase. To reduce operating

digital supply currents even further, digital inputs need to be

driven close to the power supply rails (i.e., DVDD or DGND),

and OVDD should not exceed DVDD by more than 0.3 V.

igure 25

Figure 25. Power Dissipation vs. Sampling Rate

For applications where SNR is critical, the CNVST signal should

have very low jitter. This may be achieved by using a dedicated

oscillator for CNVST generation, or to clock CNVST with a

high frequency, low jitter clock, as shown in . Figure 22

BUSY

MODE

t7t8

ACQUIRE CONVERT ACQUIRE CONVERT

02966-0-011

CNVST

SAMPLE RATE (SPS)

02966-0-041

1000000100 10000 100000

1000

10000

100

1000

1000000

WARP MODE POWER

IMPULSE MODE POWER

100000

POWER DISSIPATION (µW)

PDREF = PDBUF = HIGH

CONVERSION CONTROL

Figure 26

Figure 26. Basic Conversion Timing

RESET

DATA

BUSY

02966-0-011

CNVST

shows the detailed timing diagrams of the conversion

process. The AD7653 is controlled by the CNVST signal, which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the conversion

is complete. CNVST operates independently of CS and RD.

Figure 27. RESET Timing

BUSY

DATA

BUS

CS = RD = 0

PREVIOUS CONVERSION DATA NEW DATA

02966-0-012

CNVST

In Impulse mode, conversions can be automatically initiated. If

CNVST is held LOW when BUSY is LOW, the AD7653 controls

the acquisition phase and automatically initiates a new con-

version. By keeping CNVST LOW, the AD7653 keeps the

conversion process running by itself. It should be noted that the

analog input must be settled when BUSY goes low. Also, at

power-up, CNVST should be brought LOW once to initiate the

conversion process. In this mode, the AD7653 can run slightly

faster than the guaranteed 666 kSPS limits in Impulse mode.

This feature does not exist in Warp and Normal modes. Figure 28. Master Parallel Data Timing for Reading (Continuous Read)

Although CNVST is a digital signal, it should be designed with

special care with fast, clean edges, and levels with minimum

overshoot and undershoot or ringing.

Rev. A | Page 19 of 28

AD7653

CURRENT

CONVERSION

BUSY

DATA

BUS

02966-0-013

DIGITAL INTERFACE

The AD7653 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or a parallel inter-

face. The serial interface is multiplexed on the parallel data bus.

The AD7653 digital interface also accommodates both 3 V and

5 V logic by simply connecting the OVDD supply pin of the

AD7653 to the host system interface digital supply. Finally, by

using the OB/2C input pin, both twos complement and straight

binary coding can be used.

The two signals, CS and RD, control the interface. CS and RD

have a similar effect because they are OR’d together internally.

When at least one of these signals is HIGH, the interface

outputs are in high impedance. Usually CS allows the selection

of each AD7653 in multicircuit applications and is held LOW in

a single AD7653 design. RD is generally used to enable the

conversion result on the data bus.

PARALLEL INTERFACE

The AD7653 is configured to use the parallel interface when

SER/PAR is held LOW. The data can be read either after each

conversion, which is during the next acquisition phase, or

during the following conversion, as shown in F and

, respectively. When the data is read during the

conversion, however, it is recommended that it is read only

during the first half of the conversion phase. This avoids any

potential feedthrough between voltage transients on the digital

interface and the most critical analog conversion circuitry.

igure 29

Figure 29. Slave Parallel Data Timing for Reading

(Read after Convert Mode)

Figure 30

Figure 30. Slave Parallel Data Timing for Reading

(Read during Convert Mode)

CONVERSION

BUSY

DATA

BUS

02966-0-014

CNVST,

CS = 0

The BYTESWAP pin allows a glueless interface to an 8-bit bus.

As shown in , the LSB byte is output on D[7:0] and the

MSB is output on D[15:8] when BYTESWAP is LOW. When

BYTESWAP is HIGH, the LSB and MSB bytes are swapped and

the LSB is output on D[15:8] and the MSB is output on D[7:0].

By connecting BYTESWAP to an address line, the 16-bit data

can be read in two bytes on either D[15:8] or D[7:0].

Figure 31

Figure 31. 8-Bit Parallel Interface

BYTESWAP

PINS D[15:8]

PINS D[7:0] HI-Z

HI-Z HIGH BYTE LOW BYTE

LOW BYTE HIGH BYTE HI-Z

HI-Z

02966-A-025

SERIAL INTERFACE

The AD7653 is configured to use the serial interface when

SER/PAR is held HIGH. The AD7653 outputs 16 bits of data,

MSB first, on the SDOUT pin. This data is synchronized with

the 16 clock pulses provided on the SCLK pin. The output data

is valid on both the rising and falling edges of the data clock.

Rev. A | Page 20 of 28

AD7653

Usually, because the AD7653 is used with a fast throughput, the

Master Read During Conversion mode is the most

recommended serial mode. In this mode, the serial clock and

data toggle at appropriate instants, minimizing potential

feedthrough between digital activity and critical conversion

decisions.

MASTER SERIAL INTERFACE

Internal Clock

The AD7653 is configured to generate and provide the serial

data clock SCLK when the EXT/INT pin is held LOW. The

AD7653 also generates a SYNC signal to indicate to the host

when the serial data is valid. The serial clock SCLK and the

SYNC signal can be inverted, if desired. Depending on the

RDC/SDIN input, the data can be read after each conversion or

during the following conversion. F and show

the detailed timing diagrams of these two modes.

igure 32

Figure 32. Master Serial Data Timing for Reading (Read after Convert)

Figure 33

Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

In Read After Conversion mode, it should be noted that unlike

in other modes, the BUSY signal returns LOW after the 16 data

bits are pulsed out and not at the end of the conversion phase,

which results in a longer BUSY width.

BUSY

SYNC

SCLK

SDOUT

123 141516

D15 D14 D2 D1 D0

RDC/SDIN = 0 INVSCLK = INVSYNC = 0

02966-0-015

CNVST

CS, RD

EXT/INT = 0

EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0

D15 D14 D2 D1 D0X

12 3 141516

BUSY

SYNC

SCLK

SDOUT

02966-0-016

CNVST

CS, RD

Rev. A | Page 21 of 28

AD7653

SLAVE SERIAL INTERFACE

External Clock

The AD7653 is configured to accept an externally supplied

serial data clock on the SCLK pin when the EXT/INT pin is held

HIGH. In this mode, several methods can be used to read the

data. The external serial clock is gated by CS. When CS and RD

are both LOW, the data can be read after each conversion or

during the following conversion. The external clock can be

either a continuous or a discontinuous clock. A discontinuous

clock can be either normally HIGH or normally LOW when

inactive. F and F show the detailed timing

diagrams of these methods.

igure 34

Figure 34. Slave Serial Data Timing for Reading (Read after Convert)

igure 35

Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

While the AD7653 is performing a bit decision, it is important

that voltage transients be avoided on digital input/output pins,

or degradation of the conversion result could occur. This is

particularly important during the second half of the conversion

phase because the AD7653 provides error correction circuitry

that can correct for an improper bit decision made during the

first half of the conversion phase. For this reason, it is recom-

mended that when an external clock is being provided, it is a

discontinuous clock that is toggling only when BUSY is LOW,

or, more importantly, that it does not transition during the latter

half of BUSY HIGH.

SCLK

SDOUT D15 D14 D1 D0

D13

X15 X14 X13 X1 X0 Y15 Y14

BUSY

SDIN

INVSCLK = 0

t35

t36 t37

t31 t32

t16

t33

X15 X14

1 2 3 14151617 18

t34

02966-0-017

EXT/INT = 1

RD RD = 0

DOUT

SCLK

D1 D0

XD15 D14 D13

123 141516

BUSY

EXT/INT = 1 INVSCLK = 0

02966-0-018

CNVST

CS RD = 0

Rev. A | Page 22 of 28

AD7653

External Discontinuous Clock Data Read After

Conversion

External Clock Data Read During Conversion

Figure 35 shows the detailed timing diagrams of this method.

During a conversion, while both CS and RD are both LOW, the

result of the previous conversion can be read. The data is shifted

out MSB first with 16 clock pulses, and is valid on both the

rising and falling edges of the clock. The 16 bits must be read

before the current conversion is complete; otherwise,

RDERROR is pulsed HIGH and can be used to interrupt the

host interface to prevent incomplete data reading. There is no

daisy-chain feature in this mode, and the RDC/SDIN input

should always be tied either HIGH or LOW.

Though the maximum throughput cannot be achieved using

this mode, it is the most recommended of the serial slave modes.

shows the detailed timing diagrams of this method.

After a conversion is complete, indicated by BUSY returning

LOW, the conversion’s result can be read while both CS and RD

are LOW. Data is shifted out MSB first with 16 clock pulses and

is valid on the rising and falling edges of the clock.

Figure 34

Among the advantages of this method is the fact that conversion

performance is not degraded because there are no voltage

transients on the digital interface during the conversion process.

Another advantage is the ability to read the data at any speed up

to 40 MHz, which accommodates both the slow digital host

interface and the fastest serial reading.

To reduce performance degradation due to digital activity, a fast

discontinuous clock (at least 18 MHz when Impulse mode is

used, 25 MHz when Normal mode is used, or 40 MHz when

Warp mode is used) is recommended to ensure that all the bits

are read during the first half of the conversion phase. It is also

possible to begin to read data after conversion and continue to

read the last bits after a new conversion has been initiated. This

allows the use of a slower clock speed like 14 MHz in Impulse

mode, 18 MHz in Normal mode, and 25 MHz in Warp mode.

Finally, in this mode only, the AD7653 provides a daisy-chain

feature using the RDC/SDIN pin for cascading multiple

converters together. This feature is useful for reducing compo-

nent count and wiring connections when desired, as, for

instance, in isolated multiconverter applications.

The concatenation of two devices is shown in .

Simultaneous sampling is possible by using a common CNVST

signal. It should be noted that the RDC/SDIN input is latched

on the edge of SCLK opposite the one used to shift out the data

on SDOUT. Thus, the MSB of the upstream converter follows

the LSB of the downstream converter on the next SCLK cycle.

Figure 36

Figure 36. Two AD7653s in a Daisy-Chain Configuration

SCLK

SDOUTRDC/SDIN

BUSYBUSY

DATA

OUT

AD7653

(DOWNSTREAM)

BUSY

OUT

SCLK

AD7653

(UPSTREAM)

RDC/SDIN SDOUT

SCLK IN

CNVST IN

02966-0-019

CNVST

CS IN

Rev. A | Page 23 of 28

AD7653

MICROPROCESSOR INTERFACING

The AD7653 is ideally suited for traditional dc measurement

applications supporting a microprocessor, and for ac signal

processing applications interfacing to a digital signal processor.

The AD7653 is designed to interface either with a parallel 8-bit

or 16-bit wide interface, or with a general-purpose serial port or

I/O ports on a microcontroller. A variety of external buffers can

be used with the AD7653 to prevent digital noise from coupling

into the ADC. The following section discusses the use of an

AD7653 with an ADSP-219x SPI equipped DSP.

SPI Interface (ADSP-219x)

Figure 37

Figure 37. Interfacing the AD7653 to an SPI Interface

shows an interface diagram between the AD7653 and

the SPI equipped ADSP-219x. To accommodate the slower

speed of the DSP, the AD7653 acts as a slave device and data

must be read after conversion. This mode also allows the daisy-

chain feature. The convert command can be initiated in

response to an internal timer interrupt. The reading process can

be initiated in response to the end-of-conversion signal (BUSY

going LOW) using an interrupt line of the DSP. The serial inter-

face (SPI) on the ADSP-219x is configured for master mode—

(MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit

(CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by

writing to the SPI control register (SPICLTx). To meet all timing

requirements, the SPI clock should be limited to 17 Mbps, which

allows it to read an ADC result in less than 1 µs. When a higher

sampling rate is desired, use of one of the parallel interface

modes is recommended.

AD7653*

ADSP-219x*

SER/PAR

PFx

MISOx

SCKx

PFx or TFSx

BUSY

SDOUT

SCLK

CNVST

EXT/INT

INVSCLK

DVDD

* ADDITIONAL PINS OMITTED FOR CLARITY

SPIxSEL (PFx)

02966-0-021

Rev. A | Page 24 of 28

AD7653

APPLICATION HINTS

BIPOLAR AND WIDER INPUT RANGES

In some applications, it is desirable to use a bipolar or wider

analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although

the AD7653 has only one unipolar range, simple modifications

of input driver circuitry allow bipolar and wider input ranges to

be used without any performance degradation. shows

a connection diagram that allows this. Component values

required and resulting full-scale ranges are shown in .

Figure 38

Figure 38. Using the AD7653 in 16-Bit Bipolar and/or Wider Input Ranges

Table 8

Table 8. Component Values and Input Ranges

When desired, accurate gain and offset can be calibrated by

acquiring a ground and voltage reference using an analog

multiplexer (U2) as shown in .

ANALOG

INPUT

R3 R4 100nF

REF

INGND

REF

REFGND

AD7653

02966-0-022

15Ω

2.7nF

Input Range R1 (Ω) R2 (kΩ) R3 (kΩ) R4 (kΩ)

±10 V 500 4 2.5 2

±5 V 500 2 2.5 1.67

0 V to –5 V 500 1 None 0

LAYOUT

The AD7653 has very good immunity to noise on the power

supplies. However, care should still be taken with regard to

grounding layout.

The printed circuit board that houses the AD7653 should be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes that can be separated easily. Digital and

analog ground planes should be joined in only one place,

preferably underneath the AD7653, or as close as possible to the

AD7653. If the AD7653 is in a system where multiple devices

require analog-to-digital ground connections, the connection

should still be made at one point only, a star ground point that

should be established as close as possible to the AD7653.

Running digital lines under the device should be avoided since

these will couple noise onto the die. The analog ground plane

should be allowed to run under the AD7653 to avoid noise

coupling. Fast switching signals like CNVST or clocks should be

shielded with digital ground to avoid radiating noise to other

sections of the board, and should never run near analog signal

paths. Crossover of digital and analog signals should be avoided.

Traces on different but close layers of the board should run at

right angles to each other to will reduce the effect of crosstalk

through the board.

The power supply lines to the AD7653 should use as large a

trace as possible to provide low impedance paths and to reduce

the effect of glitches on the power supply lines. Good

decoupling is also important to lower the supply’s impedance

presented to the AD7653, and to reduce the magnitude of the

supply spikes. Decoupling ceramic capacitors, typically 100 nF,

should be placed on each power supply pin—AVDD, DVDD,

and OVDD—close to, and ideally right up against these pins

and their corresponding ground pins. Additionally, low ESR

10 µF capacitors should be located near the ADC to further

reduce low frequency ripple.

The DVDD supply of the AD7653 can be a separate supply or

can come from the analog supply AVDD or the digital interface

supply OVDD. When the system digital supply is noisy or when

fast switching digital signals are present, if no separate supply is

available, the user should connect DVDD to AVDD through an

RC filter (see F ), and the system supply to OVDD and

the remaining digital circuitry. When DVDD is powered from

the system supply, it is useful to insert a bead to further reduce

high frequency spikes.

igure 22

The AD7653 has five different ground pins: INGND, REFGND,

AGND, DGND, and OGND. INGND is used to sense the analog

input signal. REFGND senses the reference voltage and, because

it carries pulsed currents, should be a low impedance return to

the reference. AGND is the ground to which most internal ADC

analog signals are referenced; it must be connected with the

least resistance to the analog ground plane. DGND must be tied

to the analog or digital ground plane depending on the config-

uration. OGND is connected to the digital system ground.

EVALUATING THE AD7653’S PERFORMANCE

A recommended layout for the AD7653 is outlined in the

EVAL-AD7653 evaluation board for the AD7653. The

evaluation board package includes a fully assembled and tested

evaluation board, documentation, and software for controlling

the board from a PC via the EVAL-CONTROL BRD2.

Rev. A | Page 25 of 28

AD7653

Rev. A | Page 26 of 28

OUTLINE DIMENSIONS

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

0.50

BSC

7.00

BSC SQ

SEATING

PLANE

1.60

MAX

0.75

0.60

0.45

VIEW A

9.00 BSC

PIN 1

0.20

0.09

1.45

1.40

1.35

0.08 MAX

COPLANARITY

VIEW A

ROTATED 90

CCW

SEATING

PLANE

10°

6°

2°

7°

3.5°

0°

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MS-026BBC

Figure 39. 48-Lead Quad Flatpack (LQFP)(ST-48)

Dimensions shown in millimeters

PIN 1

INDICATOR

TOP

VIEW

6.75

BSC SQ

7.00

BSC SQ

BOTTOM

VIEW

5.25

5.10 SQ

4.95

0.50

0.40

0.30

0.23

0.18

0.50 BSC

12° MAX 0.80 MAX

0.65 TYP

1.00

0.85

0.80

5.50

REF

0.05 MAX

0.02 NOM

0.60 MAX

0.60 MAX PIN 1

INDICATOR

COPLANARITY

0.08

SEATING

PLANE

PADDLE CONNECTED TO AGND.

THIS CONNECTION IS NOT

REQUIRED TO MEET THE

ELECTRICAL PERFORMANCES

0.25 MIN

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

Figure 40. 48-Lead Frame Chip Scale Package (LFCSP) (CP-48)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7653AST –40°C to +85°C Quad Flatpack (LQFP) ST-48

AD7653ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48

AD7653ACP –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48

AD7653ACPRL –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48

EVAL-AD7653CB1 Evaluation Board

EVAL-CONTROL BRD22 Controller Board

1This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

2This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

AD7653

NOTES

Rev. A | Page 27 of 28

AD7653

NOTES

registered trademarks are the property of their respective owners.

C02966–0–9/03(A)

Rev. A | Page 28 of 28