Clock Generator for Intel£Alviso Chipset
CY28411
Rev 1.0, November 22, 2006 Page 1 of 18
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com
Features
• Compliant to Intel£ CK410M
• Supports Intel Pentium-M CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
• 33 MHz PCI clock
• Low-voltage frequency select input
•I
2C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
CPU SRC PCI REF DOT96 USB_48
x2 / x3 x7 / x8 x 6 x 1 x 1 x 1
Block Diagram Pin Configuration
VDD_PCI
VSS_PCI
PCI4
PCI5
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
PCIF1
VTT_PWRGD#/PD
VDD_48
USB_48/FS_A
VSS_48
DOT96T
DOT96C
FS_B/TEST_MODE
SRCT0
SRCC0
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
PCI2
PCI_STP#
SRCC5
CPUT2_ITP/SRCT7
VSSA
VDDA
IREF
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS_CPU
SDATA
SCLK
VDD_REF
XIN
VSS_REF
FS_C/TEST_SEL
REF
CPU_STP#
CPUC2_ITP/SRCC7
SRC4_SATAT
SRC4_SATAC
VDD_SRC
VDD_SRC
SRCT6
SRCT5
VSS_SRC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
31
30
29
VDD_REF
XTAL
PLL Ref Freq
XOUT
XIN
OSC
SCLK
PLL1
I2C
Logic
VDD_48 MHz
SDATA
VDD_PCI
Divider
Network
VDD_CPU
FS_[C:A]
REF
VTT_PWRGD#
IREF
PCI[2:5]
PLL2
CPUT[0:1], CPUC[0:1],
VDD_SRC
SRCT[0:6], SRCC[0:6]
USB_48
CPU_STP#
PCI_STP#
PCI3
SRCC6
XOUT
CY28411
56 SSOP/TSSOP
DOT96T
DOT96C
VDD_PCIF
PCIF[0:1]
CPU(T/C)2_ITP]
PD
CY28411
Rev 1.0, November 22, 2006 Page 2 of 18
Pin Definitions
Pin No. Name Type Description
54 CPU_STP# I, PU 3.3V LVTTL input for CPU_STP# active low.
44,43,41,40 CPUT/C O, DIF Differential CPU clock outputs.
36,35 CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
O, DIF Selectable differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
14,15 DOT96T, DOT96C O, DIF Fixed 96 MHz clock output.
12 FS_A/USB_48 I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48 MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
16 FS_B/TEST_MODE I 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
53 FS_C/TEST_SEL I 3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled
to VIMFS_C when VTT_PWRGD# is asserted low.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi-
cations.
39 IREF I A precision resistor is attached to this pin, which is connected to the internal
current reference.
56,3,4,5 PCI O, SE 33 MHz clocks.
55 PCI_STP# I, PU 3.3V LVTTL input for PCI_STP# active low.
8 PCIF0/ITP_EN I/O, SE 33 MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
9 PCIF1 O, SE 33 MHz clocks.
52 REF O, SE Reference clock. 3.3V 14.318-MHz clock output.
46 SCLK I SMBus-compatible SCLOCK.
47 SDATA I/O SMBus-compatible SDATA.
26,27 SRC4_SATAT,
SRC4_SATAC
O, DIF Differential serial reference clock. Recommended output for SATA.
24,25,22,23,
19,20,17,18,
33,32,31,30
SRCT/C O, DIF Differential serial reference clocks.
11 VDD_48 PWR 3.3V power supply for outputs.
42 VDD_CPU PWR 3.3V power supply for outputs.
1,7 VDD_PCI PWR 3.3V power supply for outputs.
48 VDD_REF PWR 3.3V power supply for outputs.
21,28,34 VDD_SRC PWR 3.3V power supply for outputs.
37 VDDA PWR 3.3V power supply for PLL.
13 VSS_48 GND Ground for outputs.
45 VSS_CPU GND Ground for outputs.
2,6 VSS_PCI GND Ground for outputs.
51 VSS_REF GND Ground for outputs.
29 VSS_SRC GND Ground for outputs.
38 VSSA GND Ground for PLL.
10 VTT_PWRGD#/PD I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#
(active low) assertion, this pin becomes a real-time input for asserting power
down (active high).
50 XIN I 14.318 MHz crystal input.
49 XOUT O, SE 14.318 MHz crystal output.
CY28411
Rev 1.0, November 22, 2006 Page 3 of 18
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B and FS_C input values. For all logic
levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B and FS_C transitions will be ignored, except in
test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 1. Frequency Select Table FS_A, FS_B and FS_C
FS_C FS_B FS_A CPU SRC PCIF/PCI REF0 DOT96 USB
MID 0 1 100 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz
0 0 1 133 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz
011
RESERVED
010
000
MID 0 0
MID 1 0
MID 1 1
1 0 x Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
1 1 0 REF/2 REF/8 REF/24 REF REF REF
1 1 1 REF/2 REF/8 REF/24 REF REF REF
Table 2. Command Code Definition
Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address – 7 bits 8:2 Slave address – 7 bits
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code – 8 bits 18:11 Command Code – 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Byte Count – 8 bits
(Skip this step if I2C_EN bit set)
20 Repeat start
CY28411
Rev 1.0, November 22, 2006 Page 4 of 18
Control Registers
28 Acknowledge from slave 27:21 Slave address – 7 bits
36:29 Data byte 1 – 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
45:38 Data byte 2 – 8 bits 37:30 Byte Count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge
.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave – 8 bits
.... Data Byte N –8 bits 47 Acknowledge
.... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave / Acknowledge
.... Data Byte N from slave – 8 bits
.... NOT Acknowledge
.... Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address – 7 bits 8:2 Slave address – 7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code – 8 bits 18:11 Command Code – 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte – 8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address – 7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave – 8 bits
38 NOT Acknowledge
39 Stop
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol Block Read Protocol
Bit Description Bit Description
Byte 0:Control Register 0
Bit @Pup Name Description
7 1 CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
CPU[T/C]2_ITP/SRC[T/C]7 Output Enable
0 = Disable (Hi-Z), 1 = Enable
6 1 SRC[T/C]6 SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
5 1 SRC[T/C]5 SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
4 1 SRC[T/C]4 SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
3 1 SRC[T/C]3 SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
CY28411
Rev 1.0, November 22, 2006 Page 5 of 18
2 1 SRC[T/C]2 SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1 1 SRC[T/C]1 SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0 1 SRC[T/C]0 SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit @Pup Name Description
7 1 PCIF0 PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6 1 DOT_96T/C DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
5 1 USB_48 USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
4 1 REF REF Output Enable
0 = Disabled, 1 = Enabled
3 0 Reserved Reserved
2 1 CPU[T/C]1 CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
1 1 CPU[T/C]0 CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
00 CPUT/C
SRCT/C
PCIF
PCI
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit @Pup Name Description
7 1 PCI5 PCI5 Output Enable
0 = Disabled, 1 = Enabled
6 1 PCI4 PCI4 Output Enable
0 = Disabled, 1 = Enabled
5 1 PCI3 PCI3 Output Enable
0 = Disabled, 1 = Enabled
4 1 PCI2 PCI2 Output Enable
0 = Disabled, 1 = Enabled
3 1 Reserved Reserved, Set = 1
2 1 Reserved Reserved, Set = 1
1 1 Reserved Reserved, Set = 1
0 1 PCIF1 PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit @Pup Name Description
7 0 SRC7 Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6 0 SRC6 Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
5 0 SRC5 Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 0:Control Register 0 (continued)
Bit @Pup Name Description
CY28411
Rev 1.0, November 22, 2006 Page 6 of 18
4 0 SRC4 Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3 0 SRC3 Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2 0 SRC2 Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1 0 SRC1 Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
0 0 SRC0 Allow control of SRC[T/C]0 with assertion of PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 4: Control Register 4
Bit @Pup Name Description
7 0 Reserved Reserved, Set = 0
6 0 DOT96T/C DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
5 0 Reserved Reserved, Set = 0
4 0 PCIF1 Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3 0 PCIF0 Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2 1 CPU[T/C]2 Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
1 1 CPU[T/C]1 Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
0 1 CPU[T/C]0 Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 SRC[T/C][7:0] SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted,1 = Hi-Z when PCI_STP# asserted
6 0 CPU[T/C]2 CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
5 0 CPU[T/C]1 CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
4 0 CPU[T/C]0 CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
3 0 SRC[T/C][7:0] SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
Byte 3: Control Register 3 (continued)
Bit @Pup Name Description
CY28411
Rev 1.0, November 22, 2006 Page 7 of 18
Crystal Recommendations
The CY28411 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal will cause the CY28411 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Byte 6: Control Register 6
Bit @Pup Name Description
7 0 REF/N or Hi-Z Select
0 = Hi-Z, 1 = REF/N Clock
6 0 Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Hi-Z mode,
5 0 Reserved Reserved, Set = 0
4 1 REF REF Output Drive Strength
0 = Low, 1 = High
3 1 PCIF, SRC, PCI SW PCI_STP Function
0=SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2 Externally
selected
CPUT/C FS_C Reflects the value of the FS_C pin sampled on power up
0 = FS_C was low during VTT_PWRGD# assertion
1 Externally
selected
CPUT/C FS_B Reflects the value of the FS_B pin sampled on power up
0 = FS_B was low during VTT_PWRGD# assertion
0 Externally
selected
CPUT/C FS_A Reflects the value of the FS_A pin sampled on power up
0 = FS_A was low during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit @Pup Name Description
7 0 Revision Code Bit 3 Revision Code Bit 3
6 0 Revision Code Bit 2 Revision Code Bit 2
5 0 Revision Code Bit 1 Revision Code Bit 1
4 1 Revision Code Bit 0 Revision Code Bit 0
3 1 Vendor ID Bit 3 Vendor ID Bit 3
2 0 Vendor ID Bit 2 Vendor ID Bit 2
1 0 Vendor ID Bit 1 Vendor ID Bit 1
0 0 Vendor ID Bit 0 Vendor ID Bit 0
Table 5. Crystal Recommendations
Frequency
(Fund) Cut Loading Load Cap Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz AT Parallel 20 pF 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm
CY28411
Rev 1.0, November 22, 2006 Page 8 of 18
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
Figure 1. Crystal Capacitive Clarification
XTAL
Ce2
Ce1
Cs1 Cs2
X1 X2
Ci1 Ci2
Clock Chip
Trace
2.8pF
Trim
33pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1+Ce2 + Cs2 + Ci2
1
()
1
=
CLe
CY28411
Rev 1.0, November 22, 2006 Page 9 of 18
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual function pin. During initial
power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active high input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted high, all clocks need to be driven
to a low value and held prior to turning off the VCOs and the
crystal oscillator.
PD (Power-down) – Assertion
When PD is sampled high by two consecutive rising edges of
CPUC, all single-ended outputs will be held low on their next
high to low transition and differential clocks must held high or
Hi-Zd (depending on the state of the control register drive
mode bit) on the next diff clock# high to low transition within
four clock periods. When the SMBus PD drive mode bit corre-
sponding to the differential (CPU, SRC, and DOT) clock output
of interest is programmed to ‘0’, the clock output are held with
“Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tri-state.
If the control register PD drive mode bit corresponding to the
output of interest is programmed to “1”, then both the “Diff
clock” and the “Diff clock#” are tristate. Note the example
below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all
differential outputs. This diagram and description is applicable
to valid CPU frequencies 100,133,166,200,266,333 and
400MHz. In the event that PD mode is desired as the initial
power-on state, PD must be asserted high in less than 10 uS
after asserting Vtt_PwrGd#.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 Ps of PD deassertion to a voltage greater than 200
mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
Figure 3. Power-down Assertion Timing Waveform
PD
USB, 48MHz
DOT96T
DOT96C
SRCT 100MHz
SRCC 100MHz
CPUT, 133MHz
PCI, 33 MHz
REF
CPUC, 133MHz
Figure 4. Power-down Deassertion Timing Waveform
DOT96C
PD
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
USB, 48MHz
DOT96T
SRCT 100MHz
Tstable
<1.8nS
PCI, 33MHz
REF
Tdrive_PWRDN#
<300PS, >200mV
CY28411
Rev 1.0, November 22, 2006 Page 10 of 18
CPU_STP# Assertion
The CPU_STP# signal is an active low input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final states of the stopped CPU signals are
CPUT = HIGH and CPUC = LOW. There is no change to the
output drive current values during the stopped state. The
CPUT is driven HIGH with a current value equal to 6 x (Iref),
and the CPUC signal will be Hi-Z.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CPU_STP#
CPUT
CPUC
Figure 5. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
Tdrive_CPU_STP#,10nS>200mV
CPUC Internal
Figure 6. CPU_STP# Deassertion Waveform
DOT96C
DOT96T
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Free Running
CPUT(Free Running
PD
1.8mS
CPU_STOP#
Figure 7. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
CY28411
Rev 1.0, November 22, 2006 Page 11 of 18
PCI_STP# Assertion[1]
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 9.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
Note:
1. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically
OR’ed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus
Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device’s stoppable PCI clocks are not running.
DOT96C
DOT96T
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Free Running)
CPUT(Free Running)
PD
1.8mS
CPU_STOP#
Figure 8. CPU_STP# = Hi-Z, CPU_PD = Hi-Z, DOT_PD = tHi-Z
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 9. PCI_STP# Assertion Waveform
PCI_STP#
PCI_F
PCI
SRC 100MHz
Tsu Tdrive_SRC
Figure 10. PCI_STP# Deassertion Waveform
CY28411
Rev 1.0, November 22, 2006 Page 12 of 18
FS_A, FS_B,FS_C
VTT_PWRGD#
PWRGD_VRM
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0 State 2 State 3
Wait for
VTT_PWRGD# Sample Sels
Off
Off
On
On
State 1
Device is not affected,
VTT_PWRGD# is ignored
Figure 11. VTT_PWRGD# Timing Diagram
VTT_PWRGD# = Low
Delay
>0.25mS
S1
Power Off
S0
VDD_A = 2.0V
Sample
Inputs straps
S2
Normal
Operation
Wait for <1.8ms
Enable Outputs
S3
VTT_PWRGD# = toggle
VDD_A = off
Figure 12. Clock Generator Power-up/Run State Diagram
CY28411
Rev 1.0, November 22, 2006 Page 13 of 18
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
VDD Core Supply Voltage –0.5 4.6 V
VDD_A Analog Supply Voltage –0.5 4.6 V
VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC
TSTemperature, Storage Non-functional –65 150 °C
TATemperature, Operating Ambient Functional 0 85 °C
TJTemperature, Junction Functional – 150 °C
ØJC Dissipation, Junction to Case
(Mil-Spec 883E Method 1012.1)
SSOP 39.56 °C/W
TSSOP 20.62
ØJA Dissipation, Junction to Ambient
JEDEC (JESD 51)
SSOP 45.29 °C/W
TSSOP 62.26
ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V
UL-94 Flammability Rating At 1/8 in. V–0
MSL Moisture Sensitivity Level 1
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing
is NOT required.
DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VDD_A,
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48,
VDD_CPU
3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
VILI2C Input Low Voltage SDATA, SCLK – 1.0 V
VIHI2C Input High Voltage SDATA, SCLK 2.2 – V
VIL_FS FS_A/FS_B Input Low Voltage VSS – 0.3 0.35 V
VIH_FS FS_A/FS_B Input High Voltage 0.7 VDD + 0.5 V
VILFS_C FS_C Low Range 0 0.35 V
VIMFS_C FS_C Mid Range 0.7 1.7 V
VIH FS_C FS_C High Range 2.1 VDD V
VIL 3.3V Input Low Voltage VSS – 0.5 0.8 V
VIH 3.3V Input High Voltage 2.0 VDD + 0.5 V
IIL Input Low Leakage Current except internal pull-up resistors, 0 < VIN < VDD –5 – PA
IIH Input High Leakage Current except internal pull-down resistors, 0 < VIN < VDD –5PA
VOL 3.3V Output Low Voltage IOL = 1 mA – 0.4 V
VOH 3.3V Output High Voltage IOH = –1 mA 2.4 – V
IOZ High-impedance Output Current –10 10 PA
CIN Input Pin Capacitance 2 5 pF
COUT Output Pin Capacitance 3 6 pF
LIN Pin Inductance –7nH
VXIH Xin High Voltage 0.7VDD VDD V
VXIL Xin Low Voltage 00.3V
DD V
IDD3.3V Dynamic Supply Current At max. load and freq. per Figure 14 –380mA
IPD3.3V Power-down Supply Current PD asserted, Outputs driven – 70 mA
IPD3.3V Power-down Supply Current PD asserted, Outputs Hi-Z – 12 mA
CY28411
Rev 1.0, November 22, 2006 Page 14 of 18
AC Electrical Specifications
Parameter Description Condition Min. Max. Unit
Crystal
TDC XIN Duty Cycle The device will operate reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
47.5 52.5 %
TPERIOD XIN Period When XIN is driven from an external
clock source 69.841 71.0 ns
TR / TFXIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD –10.0ns
TCCJ XIN Cycle to Cycle Jitter As an average over 1-Ps duration – 500 ps
LACC Long-term Accuracy Over 150 ms – 300 ppm
CPU at 0.7V
TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX 45 55 %
TPERIOD 100-MHz CPUT and CPUC Period Measured at crossing point VOX 9.997001 10.00300 ns
TPERIOD 133-MHz CPUT and CPUC Period Measured at crossing point VOX 7.497751 7.502251 ns
TPERIODSS 100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns
TPERIODSS 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 7.497751 7.539950 ns
TPERIODAbs 100-MHz CPUT and CPUC Absolute
period
Measured at crossing point VOX 9.912001 10.08800 ns
TPERIODAbs 133-MHz CPUT and CPUC Absolute
period
Measured at crossing point VOX 7.412751 7.587251 ns
TPERIODSSAbs 100-MHz CPUT and CPUC Absolute
period, SSC
Measured at crossing point VOX 9.912001 10.13827 ns
TPERIODSSAbs 133-MHz CPUT and CPUC Absolute
period, SSC
Measured at crossing point VOX 7.412751 7.624950 ns
TCCJ CPUT/C Cycle to Cycle Jitter Measured at crossing point VOX –125ps
TCCJ2 CPU2_ITP Cycle to Cycle Jitter Measured at crossing point VOX –125ps
TSKEW2 CPU2_ITP to CPU0 Clock Skew Measured at crossing point VOX –150ps
TR / TFCPUT and CPUC Rise and Fall Times Measured from VOL = 0.175 to VOH =
0.525V 175 700 ps
TRFM Rise/Fall Matching Determined as a fraction of 2*(TR –
TF)/(TR+ TF)–20%
'TRRise Time Variation – 125 ps
'TFFall Time Variation – 125 ps
VHIGH Voltage High Math averages Figure 14 660 850 mV
VLOW Voltage Low Math averages Figure 14 –150 – mV
VOX Crossing Point Voltage at 0.7V Swing 250 550 mV
VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V
VUDS Minimum Undershoot Voltage –0.3 – V
VRB Ring Back Voltage See Figure 14. Measure SE – 0.2 V
SRC
TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX 45 55 %
TPERIOD 100-MHz SRCT and SRCC Period Measured at crossing point VOX 9.997001 10.00300 ns
TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns
TPERIODAbs 100-MHz SRCT and SRCC Absolute
Period
Measured at crossing point VOX 10.12800 9.872001 ns
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute
Period, SSC
Measured at crossing point VOX 9.872001 10.17827 ns
TSKEW Any SRCT/C to SRCT/C Clock Skew Measured at crossing point VOX –100ps
CY28411
Rev 1.0, November 22, 2006 Page 15 of 18
TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX –125ps
LACC SRCT/C Long Term Accuracy Measured at crossing point VOX – 300 ppm
TR / TFSRCT and SRCC Rise and Fall Times Measured from VOL = 0.175 to VOH =
0.525V 175 700 ps
TRFM Rise/Fall Matching Determined as a fraction of 2*(TR –
TF)/(TR+ TF)–20%
'TRRise TimeVariation – 125 ps
'TFFall Time Variation – 125 ps
VHIGH Voltage High Math averages Figure 14 660 850 mV
VLOW Voltage Low Math averages Figure 14 –150 – mV
VOX Crossing Point Voltage at 0.7V Swing 250 550 mV
VOVS Maximum Overshoot Voltage –VHIGH +
0.3 V
VUDS Minimum Undershoot Voltage –0.3 – V
VRB Ring Back Voltage See Figure 14. Measure SE – 0.2 V
PCI/PCIF
TDC PCI Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.99100 30.00900 ns
TPERIODSS Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.9910 30.15980 ns
TPERIODAbs Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.49100 30.50900 ns
TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.49100 30.65980 ns
THIGH PCIF and PCI high time Measurement at 2.4V 12.0 – ns
TLOW PCIF and PCI low time Measurement at 0.4V 12.0 – ns
TR / TFPCIF and PCI rise and fall times Measured between 0.8V and 2.0V 0.5 2.0 ns
TSKEW Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 500 ps
TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 500 ps
DOT
TDC DOT96T and DOT96C Duty Cycle Measured at crossing point VOX 45 55 %
TPERIOD DOT96T and DOT96C Period Measured at crossing point VOX 10.41354 10.41979 ns
TPERIODAbs DOT96T and DOT96C Absolute Period Measured at crossing point VOX 10.16354 10.66979 ns
TCCJ DOT96T/C Cycle to Cycle Jitter Measured at crossing point VOX –250ps
LACC DOT96T/C Long Term Accuracy Measured at crossing point VOX – 100 ppm
TR / TFDOT96T and DOT96C Rise and Fall
Times
Measured from VOL = 0.175 to VOH =
0.525V 175 700 ps
TRFM Rise/Fall Matching Determined as a fraction of 2*(TR –
TF)/(TR+ TF)–20%
'TRRise Time Variation – 125 ps
'TFFall Time Variation – 125 ps
VHIGH Voltage High Math averages Figure 14 660 850 mV
VLOW Voltage Low Math averages Figure 14 –150 – mV
VOX Crossing Point Voltage at 0.7V Swing 250 550 mV
VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V
VUDS Minimum Undershoot Voltage –0.3 – V
VRB Ring Back Voltage See Figure 14. Measure SE – 0.2 V
USB
TDC Duty Cycle Measurement at 1.5V 45 55 %
AC Electrical Specifications (continued)
Parameter Description Condition Min. Max. Unit
CY28411
Rev 1.0, November 22, 2006 Page 16 of 18
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the test load configurations for
the single-ended PCI, USB, and REF output signals.
TPERIOD Period Measurement at 1.5V 20.83125 20.83542 ns
TPERIODAbs Absolute Period Measurement at 1.5V 20.48125 21.18542 ns
THIGH USB high time Measurement at 2.4V 8.094 10.036 ns
TLOW USB low time Measurement at 0.4V 7.694 9.836 ns
TR / TFRise and Fall Times Measured between 0.8V and 2.0V 1.0 2.0 ns
TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps
REF
TDC REF Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD REF Period Measurement at 1.5V 69.8203 69.8622 ns
TPERIODAbs REF Absolute Period Measurement at 1.5V 68.82033 70.86224 ns
TR / TFREF Rise and Fall Times Measured between 0.8V and 2.0V 0.5 2.0 V/ns
TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up – 1.8 ms
TSS Stopclock Set-up Time 10.0 – ns
TSH Stopclock Hold Time 0 – ns
AC Electrical Specifications (continued)
Parameter Description Condition Min. Max. Unit
Figure 13. Single-ended Load Configuration
PCI/
USB
REF
: Measurement
Point
5pF
:
: Measurement
Point
5pF
:
: Measurement
Point
5pF
:
CY28411
Rev 1.0, November 22, 2006 Page 17 of 18
For Differential CPU, SRC and DOT96 Output Signals
The following diagram shows the test load configuration for the
differential CPU and SRC outputs.
CPUT
CPUC
:
:
:
:
Measurement
Point
2pF
:
IR E F
Measurement
Point
2pF
SRCT
SRCC
:D iffere ntial
DOT96T
DOT96C
Figure 14. 0.7V Single-ended Load Configuration
2.4V
0.4V
3.3V
0V
TRTF
1.5V
3.3V si
g
nals
TDC
--
Figure 15. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number Package Type Product Flow
Standard
CY28411OC 56-pin SSOP Commercial, 0q to 85qC
CY28411OCT 56-pin SSOP – Tape and Reel Commercial, 0q to 85qC
CY28411ZC 56-pin TSSOP Commercial, 0q to 85qC
CY28411ZCT 56-pin TSSOP – Tape and Reel Commercial, 0q to 85qC
Lead-free
CY28411OXC 56-pin SSOP Commercial, 0q to 85qC
CY28411OXCT 56-pin SSOP – Tape and Reel Commercial, 0q to 85qC
CY28411ZXC 56-pin TSSOP Commercial, 0q to 85qC
CY28411ZXCT 56-pin TSSOP – Tape and Reel Commercial, 0q to 85qC
Rev 1.0, November 22, 2006 Page 18 of 18
CY28411
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Package Drawing and Dimensions
0.095
0.025
0.008
SEATING PLANE
0.420
0.088
.020
0.292
0.299
0.395
0.092
BSC
0.110
0.016
0.720
0.008
0.0135
0.730
DIMENSIONS IN INCHES MIN.
MAX.
0.040
0.024
0°-8°
GAUGE PLANE
.010
1
28
56
29
0.110
0.005
0.010
56-Lead Shrunk Small Outline Package O56
SEATING
PLANE
1
BSC
0°-8°
MAX.
GAUGE PLANE
28
29 56
1.100[0.043]
0.051[0.002]
0.851[0.033]
0.508[0.020]
0.249[0.009]
7.950[0.313]
0.25[0.010]
6.198[0.244]
13.894[0.547]
8.255[0.325]
5.994[0.236]
0.950[0.037]
0.500[0.020]
14.097[0.555]
0.152[0.006]
0.762[0.030]
DIMENSIONS IN MM[INCHES] MIN.
MAX.
0.170[0.006]
0.279[0.011]
0.20[0.008]
0.100[0.003]
0.200[0.008]
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.42gms
PART #
Z5624 STANDARD PKG.
ZZ5624 LEAD FREE PKG.
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
