NATL SEMICOND {MEMORY} 1OE D B usouzes 0062389 90 i __ National Semiconductor 1 76-45-05 DS78LS120/DS88LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe) General Description The DS78LS120 and DS88LS120 are high performance, dual differential, TTL compatible line receivers for both bal- anced and unbalanced digital data transmission. The inputs are compatible with EIA, Federal and MIL standards. The line receiver will discriminate a +200 mV input signal over & common-mode range of +10V and a +300 mV sig- nal over a range of + 15V. Circuit features include hysteresis and response control for applications where controlled rise and fall times and/or high frequency noise rejection are desirable. Threshold offset control is provided for fail-safe detection, should the input be open or short. Each receiver includes an optional 1800, terminating resistor and the output gate contains a logic strobe for time discrimination. The DS78L8120 is specified over a 55C to +125C temperature range and the DS88LS120 from 0C to +70C. Input specifications meet or exceed those of the popular DS7820/DS8820 line receiver. Features @ Meets EIA standards RS232-C, RS422 and RAS423, Federal Standards 1020, 1030 and MIL-188-114 m Input voltage range of +15V (differential or common- mode) @ Separate strobe input for each receiver m 5k typical input impedance @ Optional 1802 termination resistor m@ 50 mV input hysteresis m 200 mV input threshold m Separate fail-safe mode Connection Diagram Dual-In-Line Package FAIL-SAFE TEAMI- Voc OFFSET -INPUT NATION +INPUT STROBE 16 16 14 13 RESPONSE TIME OUTPUT 12 11 10 | 9 1 2 3 4 FAIL-SAFE-INPUT TERMI- OFFSET NATION +INPUT STROBE RESPONSE OUTPUT 6 7 GND TIME TL/F/7499~1 Top View Order Number DS78LS120J, DS88L$120J or DS88LS120N See NS Package Number J16A or N16A 1-195 02LS188S0/021S18ZSaNATL SENICOND IMEMORY} LOE D B soz. O0be390 ? i DS78LS120/DS88LS120 Absolute Maximum Ratings (note 1) Operating Conditions 1-75-45-05 If Milltary/Aerospace specified devices are required, Min Max = Units contact the National Semiconductor Sales Office/ Supply Voltage (Vcc) 45 5.5 v Distributors for avallability and specifications. Temperature (Ta) Supply Voltage Iv DS78LS120 55 +125 C input Voltage +OBY DS88LS120 0 +70 C Strobe Voltage 7V Common-Mode Voltage (Vom) -15 +15 Vv Output Sink Current 50 mA Storage Temperature Range 65C to + 150C Maximum Power Dissipation* at 25C Cavity Package 1433 mV Molded Package 1362 mW Lead Temperature (Soldering, 4 sec) 260C *Derate cavity package 9.6 mW/*C above 25C; derate molded package 10.9 mW/C above 25C. Electrical Characteristics (notes 2 and 3) Symbol Parameter Conditions Min | Typ | Max j Units VTH Differential Threshold Voltage lout = 400 pA, Vout = 2.5V | -7V < Vom Ss 7V 0.06 | 0.2 Vv 15 < Vou <15V 0.06 | 03 Vv VIL Differential Threshold Voltage lout = 4mA, Vout = 0.5V 7V < Vom s7V 0.08! -0.2} V 15V < Vow < 15V 0.08] 0.3] V VTH Differential Threshold Voltage lout = 400 pA, Vout 2 2.5V | -7V < Vom < 7V 0.47 | 0.7 v Vrt__| with Fail-Safe Offset = 5V lout = 4mA, Vout < 0.5V V<Vomse 7. | -0.2| -0.42 V Rin Input Resistance 15V < Vom < 15V, OV < Voc < 7V 4 5 kn Rr Line Termination Resistance Ta = 25C 100 | 180 | 300 2 Ro Offset Control Resistance Ta = 26C 42 56 70 kan lind Data Input Current (Unterminated) | Vom = 10V 2 3.1 | mA Vom = OV OV < Voc < 7V 0 ~0.5 | mA Vom = 10V -2 | -3.1] mA VTIHB Input Balance lout = 400 pA, Vout = 2.5V, | -7V < Vom 7V 0.1 0.4 Vv (Note 5) As = 5002 ; (our. soon Vout < 0.5V, 7V < Vom s 7V -o1!-04! v Vou Logical 1 Output Voltage lout = 400 pA, Voice = 1V, Voc = 4.5V 25 3 v Vor Logical 0 Output Voltage lout = 4mA, Vpoirr = 1V, Voc = 4.5V 0.35 | 0.5 Vv Ico Power Supply Current Voc = 5.5V Vom = 15V 10 16 mA VpirF = ~0.5V, (Both Receivers) Vom = 15V 10 16 | mA TIN (1) Logical 1" Strobe Input Current | VstRope = 5.5V, Voire = 3V 1 100 | pA lin (0) | Logical 0 Strobe Input Current | Vstnope = OV, VpirF = 3V 290|-400] pA Vin Logical 1 Strobe Input Voltage | VoL < 9.5, lout = 4mA 2.0 | 1.12 v Vit Logical 0 Strobe Input Voltage | VoH 2 2.5V, lout, = 400 pA 1.12 | 08 Vv los Output Short-Circuit Current Vout = OV, Voc = 5.5V, Vstrose = OV, (Note 4} 30] 100 | 170] mA Note 1: Absolute Maximum Ratings are those values beyond which the safely of the device cannot be guaranteed. Except for Operating Temperature Range they are not meant to imply that the devices should be operated at these limits. The table of "Etectrical Characteristics provides conditions for actual device operation. Note 2: Unless otherwise spacified min/max limits apply across the 55C to + 125C temperature range for the DS78L$120 and across the 0C to +70C for the DS86LS120. All typical values are for Ta = 25C, Vog = 5V and Vom = OV. Note 2: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground untess otherwise noted. All values shown as max or min on absolute value basis. Note 4: Only one output at a time should be shorted. Note 5: Refer to EIA-RS422 for exact conditions. 1-196NATL SEMICOND {MEMORY} LOE D B eso.aen Oobe391 9 fs Switching Characteristics Vc = sv, T, = 26C T-75-45-05 Symbol! Parameter Conditions Min Typ Max Units tpdo(D) Differential Input to O" Output 38 60 ns tpat(D) Differential Input to "i" Output Response Pin Open, G, = 15 pF, R, = 2k 38 60 ns tpao(s) Strobe Input to 0 Output 16 25 ns tod1(S) Strobe Input to 1" Output 12 25 ns AC Test Circuit and Switching Time Waveforms Differential and Strobe Input Signal ouTPUT Vee STROBE INPUT = TL/F/7499-3 *includes probe and test fixture capacitance 269, DiFF / \ INPUT w 600 -25V Yee STAQRE ox \ INPUT j K 500 es av ns ouTeuT 4.59 15V ts hened hele ya010)-] tyattDy] pants) ao) i Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection). TL/F/7499-4 Application Hints Balanced Data Transmission BsrgstAlosas E DRIVER 2 1/2 OS7815120 LINE RECEIVER, TWISTED PAIR STROBE TL/F/7499-5 1-197 01-S188S0/021S18ZSdDS78LS120/DS88LS120 NATL SEMICOND MEMORY? 10e p Mf e5o1z2_ oonza92 0 ff Application Hints (continued) T-75-45-05 Unbalanced Data Transmission 1/4 051488 OR TADSI69TA/DS3691 142 OS7BLS120 LINE RECEIVER TL/F/7499-6 Logic Level Translator You Qa 3 42 BS78LS120 ECL GATE LINE RECEIVER s 3 nm ECL THRESHOLD OJ Vo OUTPUT oe Vin Vt Vin TL/F/74 INPUT VOLTAGE. TL/F/7499-7 ms The DS78LS120/DS88LS120 may be used as a level trans- affecting the termination impedance of the transmission lator to interface between +12V MOS, ECL, TTL and line. Noise pulse width rejection vs the value of the re- CMOS. To configure, bias either input to a voltage equal to sponse control capacitor is shown in Figures 7 and 2. This Y the voltage of the input signal, and the other input to the combination of filters followed by hysteresis will optimize driving gate. performance in a worse case noise environment. 10k LINE DRIVERS Line drivers which will interface with the DS78LS120/ DS88LS120 are listed below. Balanced Drivers 10k NOISE PULSE WIDTH (ns) (FIGURE 2) DS26LS31 Quad RS-422 Line Driver tk Dual CMOS DS7830, DS8830 Dual TTL DS7831, DS8831 Dual TRISTATE TTL mo 9 * it DS7832, DS8832 Dual TRI-STATE TTL RESPONSE CONTROL CAPACITOR (pF) DS1691A, DS3691 Quad RS-423/Dual RS-422 TTL TL/F/7499-9 DS1692, DS3692 Quad RS-423/Dual TRI-STATE FIGURE 1. Noise Pulse Width vs RS-422 TIL Response Control Capacitor DS3487 Quad TRI-STATE RS-422 Unbalanced Drivers INPUT DS1488 Quad RS-232 ouTPUT DS75150 Dual RS-232 RESPONSE CONTROL AND HYSTERESIS in unbalanced (RS-232/RS-423) applications it is recom- CAPACITOR mended that the rise time and fall time of the line driver be Lr controlled to reduce cross-talk, Elimination of switching noise is accomplished in the DS78LS120/DS88LS120 by nev the 50 mV of hysteresis incorporated in the output gate. 0 This eliminates the oscillations which may appear in a line ett rise receiver due to the input signal slowly varying about the -2v threshold level for extended periods of time. [-+} NOISE PULSE WIDTH High frequency noise which is superimposed on the input wv signal which may exceed 50 mV can be reduced in ampli- POSITIVE INPUT tude by filtering the device input. On the DS78LS120/ NOISE PULSE DS88LS120, a high impedance response control pin in the input amplifier is available to filter the input signal without TL/F/7499-10 FIGURE 2 RESPONSE CONTROL a -OS 1-198NATL SEMICOND {MEMORY} 10E D ff LsoLLe6 OoLaaq3 2 i Application Hints (continue) TRANSMISSION LINE TERMINATION On a transmission line which is electrically long, it is advisa- ble to terminate the line in its characteristic impedance to prevent signal reflection and its associated noise/cross- talk. A 1809 termination resistor is provided in the DS78LS120/DS88LS120 line receiver. To use the termina- tion resistor, connect pins 2 and 3 together and pins 13 and 14 together. The 1802 resistor provides a good compro- mise between line reflections, power dissipation in the driv- er, and IR drop in the transmission line. If power dissipation and IR drop are still a concern, a capacitor may be connect- ed in series with the resistor to minimize power loss. The value of the capacitor is recommended to be the line length (time) divided by 3 times the resistor value. Example: if the transmission line is 1,000 feet long, (approximately 1000 ns), and the termination resistor value is 1800, the capacitor value should be 1852 pF. For additional applica- tion details, refer to application notes AN-22 and AN-108. FAIL-SAFE OPERATION Communication. systems require elements of a system to detect the presence of signals in the transmission lines, and it is desirable to have the system shut-down in a fail-safe mode if the transmission line is open or shorted. To facilitate the detection of input opens or shorts, the DS78LS120/ DS88LS120 incorporates an input threshold voltage offset. This feature will force the line receiver to a specific logic state if presence of either fault is a condition. Given that the receiver input threshold is +200 mV, an input signal greater than +200 mV insures the receiver will be in a specific logic state. When the offset contro! input (pins 1 and 15) is connected to Voc = 5V, the input thresholds T-75-45-05 are offset from 200 mV to 700 mV, referred to tne non-in- verting input, or -200 mV to 700 mV, referred to the inverting input. Therefore, if the input is open or shorted, the input will be greater than the input threshold and the receiv- er will remain in a specified logic state. The input circuit of the receiver consists of a 5k resistor terminated to ground through 1202 on both inputs. This net- work acts as an attenuator, and permits operation with com- mon-mode input voltages greater than +15V. The offset control input is actually another input to the attenuator, but its resistor value is 56k. The offset control input is connect- ed to the inverting input side of the attenuator, and the input voltage to the amplifier is the sum of the inverting input plus 0.09 times the voltage on the offset control input. When the offset control input is connected to 5V the input amplifier will see Vin(INVERTING) + 0.45V or VINUNVERTING) +0.9V when the control input is connected to 10V. The offset control input will not significantly affect the differential performance of the receiver over its common-mode operating range, and will not change the input impedance balance of the receiver. It is recommended that the receiver be terminated (5000 or less) to insure it will detect an open circuit in the presence of noise. The offset contro! can be used to insure fail-safe operation for unbalanced interface (RS-423) or for balanced interface (RS-422) operation. For unbalanced operation, the receiver would be in an inde- terminate logic state if the offset control input was open. Connecting the fail-safe offset pin to 5V, offsets the receiver threshold to 0.45V. The output is forced to a logic zero state if the input is open or shorted. Unbalanced RS-423 and RS-232 Fail-Safe LINE RECEIVER 1/2 DS78LS120 LINE DRIVER = 5v0O TL/F/7499-11 Ww iu 2 2 5 5 $ (OFFSET CONTROL $ (OFFSET CONTADL 5 INPUT OPEN) 5 INPUT = 5V) E E = = So 6 INPUT VOLTAGE Q 0.45V INPUT VOLTAGE TL/F/7499-12 1-199 021S188S0/02LS18ZSdDS78LS120/DS88LS120 NATL SEMICOND {MEMORY} LOE D B sone. OObe394 4 i Application Hints (continued) T-75-45-05 Balanced RS-422 Fail-Safe BALANCED LINE DRIVER 11/2 DS78LS120 LINE RECEIVERS 8vO a > A/B OUTPUT VOLTAGE INPUT VOLTAGE For balanced operation with inputs open or shorted, receiv- er GC will be In an indeterminate logic state. Receivers A and B will be in a logic zero state allowing the NOR gate to detect the open or short condition. The strobe will disable receivers A and B and may therefore be used to sample the fail-safe detector. Another method of fail-safe detection consists of filtering the output of NOR gate D so it would not indicate a fault condition when receiver inputs pass through the threshold region, generating an output transient. Truth Table (For Balanced Fail-Safe) INPUT VOLTAGE STROBE TL/F/7499-43 D OUTPUT VOLTAGE C GUTPUT VOLTAGE INPUT VOLTAGE TL/F/7499~14 In a communications system, only the control signals are required to detect input fault conditions. Advantages of a balanced data transmission system over an unbalanced transmission system are: 1. High nolse immunity 2. High data ratio 3. Long line lengths Input Strobe A-Out B-Out c-Out D-Out 0 1 0 1 0 0 1 1 1 0 1 0 x 1 0 0 X 1 0 0 1 1 0 0 1 0 1 1 0 0 X 0 1 1 0 0 ertyFD daha adc at eat MRA ENA AMG A ANE ae UMAR ENON a NMA Oak Mam da i ak eam aa te comes tae tte DS78LS120/DS88LS120 - w/ ah } "| v v f oy . + 29, 10H1NO3 3SNOdS3Y , | 0 wn oo Loy 2-66r2/sL m 9 = = mu a= So wOLSISaH oz < ozt mB td NOLLWNIWHAL > ! ) INdNt 3A oat 4 ONILUSANI rd rl Anan 138340 a ONLLUAANT-NON , WW 0 syst o 4G 495 uy T ang = > = = = 3 y t A Ny A = Lu [me | | fk >| Ot . oa q oS } 20 = Lndino O q 5 til = . i) z A oS 1) H = ud W -_t e < = | Schematic Diagram 1-201