ispLSI® 2064E
In-System Programmable
SuperFAST™ High Density PLD
2064e_04 1
Description
The ispLSI 2064E is a High Density Programmable Logic
Device. The device contains 64 Registers, 64 Universal
I/O pins, four Dedicated Input Pins, three Dedicated
Clock Input Pins, two dedicated Global OE input pins and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2064E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2064E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2064E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8037; http://www.latticesemi.com April 2000
Features
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functionally and JEDEC Upward Compatible
with ispLSI 2064 Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—fmax = 200 MHz Maximum Operating Frequency
—tpd = 4.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O Supports Mixed
Voltage Systems
— PCI Compatible Outputs
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
B3
B2
B1
B0
Input Bus
Output Routing Pool (ORP)
A2 GLB Logic
Array
DQ
DQ
DQ
DQ
A4 A5 A6 A7
Input Bus
Output Routing Pool (ORP)
B7 B6 B5 B4
Input Bus
Output Routing Pool (ORP)
0139/2064E
B7 B6 B5 B4
2
Specifications ispLSI 2064E
Functional Block Diagram
Figure 1. ispLSI 2064E Functional Block Diagram
TDO/IN 2
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
B3
B2
B1
B0
Input Bus
Output Routing Pool (ORP)
A2
CLK 0
CLK 1
CLK 2
GOE 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
TDI/IN 0
TMS/IN 1
I/O 4
I/O 5
BSCAN
RESET
0139B(1)isp/2064E
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
Input Bus
Output Routing Pool (ORP)
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
Y0
Y1
Y2
I/O 31
Output Routing Pool (ORP)
Megablock
Input Bus
A4 A5 A6 A7
B7 B6 B5 B4
GOE 1
TCK/IN 3
Generic Logic
Blocks (GLBs)
The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro-
grammed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat-
ible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by two ORPs. Each
ispLSI 2064E device contains two Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2064E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
3
Specifications ispLSI 2064E
Absolute Maximum Ratings 1
Supply Voltage Vcc................................................... -0.5 to +7.0V
Input Voltage Applied..............................-2.5 to VCC +1.0V
Off-State Output Voltage Applied ...........-2.5 to VCC +1.0V
Storage Temperature..................................... -65 to 150 °C
Case Temp. with Power Applied .................... -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ............ 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
Erase/Reprogram Specification
Capacitance (TA=25°C, f=1.0 MHz)
C
SYMBOL
Table 2-0006/2064e
C
PARAMETER
I/O Capacitance 8
UNITSTYPICAL TEST CONDITIONS
1
2
8Dedicated Input Capacitance pf
pf V = 5.0V, V = 2.0V
V = 5.0V, V = 2.0V
CC
CC I/O
IN
C
Clock Capacitance 10
3
pf V = 5.0V, V = 2.0V
CC Y
TA = 0°C to +70°C
SYMBOL
Table 2-0005/2096E
VCC
VIH
VIL
PARAMETER
Supply Voltage: Logic Core, Input Buffers
Input High Voltage
Input Low Voltage
MIN. MAX. UNITS
4.75
2.0
0
5.25
Vcc+1
0.8
V
VCCIO Supply Voltage: Output Drivers 4.75 5.25 V
3.3V
5V 3.0 3.6 V
V
V
Table 2-0008/2064e
PARAMETER MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles 10,000 –Cycles
4
Specifications ispLSI 2064E
Output Load Conditions (see Figure 2)
Figure 2. Test Load
+ 5V
R1
R2CL*
Device
Output Test
Point
*CL includes Test Fixture and Probe Capacitance.
DC Electrical Characteristics
Over Recommended Operating Conditions
Input Pulse Levels
Table 2-0003/2064E
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
1.5 ns
TEST CONDITION R1 R2 CL
A 470Ω390Ω35pF
B∞390Ω35pF
470Ω390Ω35pF
Active High
Active Low
C470Ω390Ω5pF
∞390Ω5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2-0004/2064
Switching Test Conditions
V
OL
SYMBOL
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25°C.
4. Unused inputs held at 0.0V.
5. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum I
CC
.
Table 2-0007/2064E
V
OH
I
IH
I
IL
PARAMETER
I
IL-PU
I
OS
1
I
CC
2,4,5
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Operating Power Supply Current
I
OL
= 8 mA
I
OH
= -4 mA
0V ≤ V
IN
≤ V
IL
(Max.)
V
IL
= 0.0V, V
IH
= 3.0V
CONDITION MIN. TYP.
3
MAX. UNITS
–
2.4
–
–
–
–
–
–
–
–
0.4
–
10
-10
10
V
V
µA
Input or I/O High Leakage Current V
CCIO
≤ V
IN
≤ 5.25V
(V
CCIO
- 0.2)V ≤ V
IN
≤ V
CCIO
µA
µA
I/O Active Pull-Up Current 0V ≤ V
IN
≤ 2.0V -10 –-250 µA
Output Short Circuit Current V
CCIO
= 5.0V or 3.3V, V
OUT
= 0.5V ––-240 mA
–100 mA–
f
TOGGLE
= 1 MHz
5
Specifications ispLSI 2064E
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
-200
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/2064E
1
1
tsu2 + tco1
( )
-135
MIN.MAX. MAX.
DESCRIPTION#
2
4
PARAMETER
A 1 Data Prop Delay, 4PT Bypass, ORP Bypass –4.5 –7.5 ns
t
pd2 A 2 Data Prop Delay –– ns
f
max A 3 Clk Freq with Internal Feedback
3
200 –135 –MHz
f
max (Ext.) –4 Clk Freq with External Feedback –– MHz
f
max (Tog.) –5 Clk Frequency, Max. Toggle –– MHz
t
su1 –6 GLB Reg Setup Time before Clk, 4 PT Bypass –– ns
t
co1 A 7 GLB Reg Clk to Output Delay, ORP Bypass –– ns
t
h1 –8 GLB Reg Hold Time after Clk, 4 PT Bypass 0.0 –ns
t
su2 –9 GLB Reg Setup Time before Clk 4.5 –ns
t
co2 –10 GLB Reg Clk to Output Delay –– ns
t
h2 –11 GLB Reg Hold Time after Clk 0.0 –ns
t
r1 A 12 External Reset Pin to Output Delay –– ns
t
rw1 –13 External Reset Pulse Duration 3.5 –ns
t
ptoeen B 14 Input to Output Enable –– ns
t
ptoedis C 15 Input to Output Disable –– ns
t
goeen B 16 Global OE Output Enable –– ns
t
goedis C 17 Global OE Output Disable –– ns
t
wh –18 External Synch Clk Pulse Duration, High 2.5 –– ns
t
wl –19 External Synch Clk Pulse Duration, Low 2.5 –– ns
133
200
3.5 3.0
–
–
3.5
–
6.0
–
8.0
8.0
4.0
4.0
7.0
100
143
5.0
0.0
6.0
0.0
5.0
3.5
3.5
10.0
4.0
4.5
10.0
12.0
12.0
7.0
7.0
-100
MIN. MAX.
–10.0
–
100 –
–
–
–
–
0.0
8.0
–
0.0
–
6.5
–
–
–
–
5.0 –
5.0 –
77
100
6.5 5.0
–
–
6.0
–
13.5
–
15.0
15.0
9.0
9.0
13.0
6
Specifications ispLSI 2064E
Internal Timing Parameters1
Over Recommended Operating Conditions
t
io
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2064E
Inputs
UNITS
-135
MIN. MAX.
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay –0.5 ns
t
din 21 Dedicated Input Delay –1.7 ns
t
grp 22 GRP Delay –1.2 ns
GLB
t
1ptxor 25 1 Product Term/XOR Path Delay –5.2 ns
t
20ptxor 26 20 Product Term/XOR Path Delay –5.2 ns
t
xoradj 27 XOR Adjacent Path Delay –5.2 ns
t
gbp 28 GLB Register Bypass Delay –0.5 ns
t
gsu 29 GLB Register Setup Time before Clock 0.7 –ns
t
gh 30 GLB Register Hold Time after Clock 4.3 –ns
t
gco 31 GLB Register Clock to Output Delay –0.3 ns
3
t
gro 32 GLB Register Reset to Output Delay –1.1 ns
t
ptre 33 GLB Product Term Reset to Register Delay –6.0 ns
t
ptoe 34 GLB Product Term Output Enable to I/O Cell Delay –6.9 ns
t
ptck 35 GLB Product Term Clock Delay 2.5 5.5 ns
ORP
t
ob 38 Output Buffer Delay –1.6 ns
t
sl 39 Output Slew Limited Delay Adder –1.5 ns
GRP
t
4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) –3.7 ns
t
4ptbpr 24 4 Product Term Bypass Path Delay (Registered) –4.2 ns
t
orp 36 ORP Delay –1.0 ns
t
orpbp 37 ORP Bypass Delay –0.5 ns
Outputs
t
oen 40 I/O Cell OE to Output Enabled –3.4 ns
t
odis 41 I/O Cell OE to Output Disabled –3.4 ns
t
goe 42 Global Output Enable –3.6 ns
t
gy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.6 1.6 ns
t
gy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.8 1.8 ns
Clocks
t
gr 45 Global Reset to GLB –6.3
–0.5
–1.1
–0.6
–2.9
–2.9
–2.9
–0.5
1.2 –
2.3 –
–0.3
–0.6
–4.3
–4.9
1.0 4.0
–1.6
–1.5
–1.4
–1.9
–0.9
–0.4
–2.0
–2.0
–2.0
0.7 0.7
0.9 0.9
–3.4 ns
Global Reset
-200
MIN. MAX.
-100
MIN. MAX.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.5
2.2
1.7
–
–
6.8
7.3
8.0
0.5
5.8
5.8
1.2
4.0
0.3
1.3
6.1
8.6
4.1 7.1
–
–1.4
0.4
1.6
1.0
–
–4.2
4.2
–4.8
2.7
2.7 2.7
2.7
–9.2
7
Specifications ispLSI 2064E
ispLSI 2064E Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
I/O Pin
(Input)
Y0,1,2
GRP GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Delay
I/O CellORPGLBGRPI/O Cell
#24
#25, 26, 27
#33, 34,
35
#43, 44
#36
Reset
Ded. In #21
#20 #28
#29, 30,
31, 32
#38,
39
GOE 0,1 #42
#40, 41
0491/2064
#22
Comb 4 PT Bypass #23
#37
#45
Derivations of tsu, th and tco from the Product Term Clock
=
=
=
=
t
su Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.5 + 0.6 + 2.9) + (1.2) - (0.5 + 0.6 + 1.0) 3.1ns
=
=
=
=
t
h Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.6 + 4.0) + (2.3) - (0.5 + 0.6 + 2.9) 3.4ns
=
=
=
=
t
co Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 1.6) 7.9ns
Table 2- 0042A-2064e
Note: Calculations are based upon timing specifications for the ispLSI 2064E-200L.
8
Specifications ispLSI 2064E
Power Consumption
Power consumption in the ispLSI 2064E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3 shows the relationship between power and
operating speed.
Figure 3. Typical Device Power Consumption vs fmax
0127A/2064E
ICC can be estimated for the ispLSI 2064E using the following equation:
ICC(mA) = 7 + (# of PTs * 0.75) + (# of nets * Max freq * 0.004)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
80
100
120
1 20 40 60 80 100 120 140 160 180 200
f
max (MHz)
I
CC (mA)
Notes: Configuration of Four 16-bit Counters
Typical Current at 5V, 25° C
ispLSI 2064E
110
90
70
130
140
150
160
9
Specifications ispLSI 2064E
Pin Description
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
GND 2, 13, 25, 38,
51, 63, 74, 88
1, 24, 52, 75
VCC 12, 64
Ground (GND)
VCC
No Connect.
BSCAN 14
TDI/IN 02 16
TMS/IN 12 37
TDO/IN 22 39
TCK/IN 32 60
NC110, 26, 27, 49,
50, 61, 76, 77,
89, 99, 100
DESCRIPTION
TQFP PIN NUMBERS
NAME
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 3 17, 18, 19, 20,
I/O 4 - I/O 7 21, 22, 23, 28,
I/O 8 - I/O 11 29, 30, 31, 32,
I/O 12 - I/O 15 33, 34, 35, 36,
I/O 16 - I/O 19 40, 41, 42, 43,
I/O 20 - I/O 23 44, 45, 46, 47,
I/O 24 - I/O 27 48, 53, 54, 55,
I/O 28 - I/O 31 56, 57, 58, 59,
I/O 32 - I/O 35 67, 68, 69, 70,
I/O 36 - I/O 39 71, 72, 73, 78,
I/O 40 - I/O 43 79, 80, 81, 82,
I/O 44 - I/O 47 83, 84, 85, 86,
I/O 48 - I/O 51 90, 91, 92, 93,
I/O 52 - I/O 55 94, 95, 96, 97,
I/O 56 - I/O 59 98, 3, 4, 5,
I/O 60 - I/O 63 6, 7, 8, 9
GOE 0, GOE 1 66, 87
Global Output Enable input pins.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Active Low (0) Reset pin which resets all of the registers in the device.
Y0, Y1, Y2 11, 65, 62
RESET 15
Table 2-0002-2064E.eps
VCCIO Supply voltage for output drivers, 5V or 3.3V. All VCCIO pins must
be connected to the same voltage level.
Input - This pin performs two functions. When BSCAN is logic low, it
functions as a pin to control the operation of the JTAG state machine.
When BSCAN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When BSCAN is logic low, it
functions as an input pin to load programming data into the device.
TDI/IN0 also is used as one of the two control pins for the JTAG state
machine. When BSCAN is high, it functions as a dedicated input pin.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The TMS, TDI, TDO
and TCK options become active.
Output/Input - This pin performs two functions. When BSCAN is logic
low, it functions as an output pin to read serial shift register data.
When BSCAN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When BSCAN is logic low, it
functions as a clock pin for the Serial Shift Register. When BSCAN is
high, it functions as a dedicated input pin.
10
Specifications ispLSI 2064E
Pin Configuration
ispLSI 2064E 100-Pin TQFP Pinout Diagram
VCCIO
GND
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
1NC
Y0
VCC
GND
BSCAN
RESET
2TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
VCCIO
GND
VCCIO
GND
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
GOE 0
Y1
VCC
GND
Y2
NC1
TCK/IN 32
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
VCCIO
GND
NC1
NC1
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
NC1
GND
GOE 1
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
NC1
NC1
1NC
1NC
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
2TMS/IN 1
GND
2TDO/IN 2
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
1NC
1NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
58
ispLSI 2064E
Top View
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capabilit
y
.
0766A-2064E
11
Specifications ispLSI 2064E
Part Number Description
100 10 100-Pin TQFPispLSI 2064E-100LT
Table 2-0041A/2064E
FAMILY fmax (MHz)
200 ORDERING NUMBER PACKAGE
100-Pin TQFP
tpd (ns)
4.5
ispLSI ispLSI 2064E-200LT
135 100-Pin TQFP7.5 ispLSI 2064E-135LT
COMMERCIAL
Device Number
ispLSI 2064E XXX X X
Grade
Blank = Commercial
X
Speed
200 = 200 MHz fmax
135 = 135 MHz fmax
100 = 100 MHz fmax Power
L = Low
Package
T = TQFP
–
Device Family
0212/2064E
ispLSI 2064E Ordering Information
