10-/12-/14-Bit, 1200 MSPS DACS
AD9734/AD9735/AD9736
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Pin-compatible family
Excellent dynamic performance
AD9736: SFDR = 82 dBc at fOUT = 30 MHz
AD9736: SFDR = 69 dBc at fOUT = 130 MHz
AD9736: IMD = 87 dBc at fOUT = 30 MHz
AD9736: IMD = 82 dBc at fOUT = 130 MHz
LVDS data interface with on-chip 100 Ω terminations
Built-in self test
LVDS sampling integrity
LVDS-to-DAC data transfer integrity
Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz)
1.8/3.3 V dual-supply operation
Adjustable analog output
8.66 mA to 31.66 mA (RL = 25 Ω to 50 Ω)
On-chip 1.2 V reference
160-lead chip scale ball grid array (CSP_BGA) package
APPLICATIONS
Broadband communications systems
Cellular infrastructure (digital predistortion)
Point-to-point wireless
CMTS/VOD
Instrumentation, automatic test equipment
Radar, avionics
GENERAL DESCRIPTION
The AD9736, AD9735, and AD9734 are high performance, high
frequency DACs that provide sample rates of up to 1200 MSPS,
permitting multicarrier generation up to their Nyquist
frequency. The AD9736 is the 14-bit member of the family,
while the AD9735 and the AD9734 are the 12-bit and 10-bit
members, respectively. They include a serial peripheral interface
(SPI) port that provides for programming of many internal
parameters and enables readback of status registers.
A reduced-specification LVDS interface is utilized to achieve
the high sample rate. The output current can be programmed
over a range of 8.66 mA to 31.66 mA. The AD973x family is
manufactured on a 0.18 µm CMOS process and operates from
1.8 V and 3.3 V supplies for a total power consumption of
380 mW in bypass mode. It is supplied in a 160-lead chip scale
ball grid array for reduced package parasitics.
FUNCTIONAL BLOCK DIAGRAM
LVDS
RECEIVER
SYNCHRONIZER
BAND GAP
DATACLK_IN+
DATACLK_IN–
DB[13:0]–
DB[13:0]+
SPI
14-, 12-,
10-BIT DAC
CORE
IOUTA
IOUTB
SDO
SDIO
SCLK
CSB
LVDS
DRIVER
CONTROLLER
REFERENCE
CURRENT
DACCLK–
IRQ DACCLK+
I120VREF
RESET
DATACLK_OUT+
DATACLK_OUT–
S1 S2 S3
C1
C2
C3
C2
C1S1
S3
S2
C3
04862-001
2×
CLOCK
DISTRIBUTION
Figure 1.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) features
enable high quality synthesis of wideband signals at inter-
mediate frequencies up to 600 MHz.
2. Double data rate (DDR) LVDS data receivers support the
maximum conversion rate of 1200 MSPS.
3. Direct pin programmability of basic functions or SPI port
access offers complete control of all AD973x family
functions.
4. Manufactured on a CMOS process, the AD973x family
uses a proprietary switching technique that enhances
dynamic performance.
5. The current output(s) of the AD9736 family are easily con-
figured for single-ended or differential circuit topologies.
AD9734/AD9735/AD9736
Rev. A | Page 2 of 72
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 6
AC Specifications.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Location of Supply and Control Pins....................................... 16
Terminology .................................................................................... 17
Typical Performance Characteristics ........................................... 18
AD9736 Static Linearity, 10 mA Full Scale ............................. 18
AD9736 Static Linearity, 20 mA Full Scale ............................. 19
AD9736 Static Linearity, 30 mA Full Scale ............................. 20
AD9735 Static Linearity, 10 mA, 20 mA, 30 mA
Full Scale...................................................................................... 21
AD9734 Static Linearity, 10 mA, 20 mA, 30 mA
Full Scale...................................................................................... 22
AD9736 Power Consumption, 20 mA Full Scale....................... 23
AD9736 Dynamic Performance, 20 mA Full Scale................ 24
AD9735, AD9734 Dynamic Performance, 20 mA
Full Scale...................................................................................... 27
AD973x WCDMA ACLR, 20 mA Full Scale .......................... 28
SPI Register Map............................................................................. 29
SPI Register Details ........................................................................ 30
Mode Register (Reg. 0) .............................................................. 30
Interrupt Request Register (IRQ) (Reg. 1) .............................. 30
Full Scale Current (FSC) Registers (Reg. 2, Reg. 3)............... 31
LVDS Controller (LVDS_CNT) Registers
(Reg. 4, Reg. 5, Reg. 6) ............................................................... 31
SYNC Controller (SYNC_CNT) Registers
(Reg. 7, Reg. 8)............................................................................ 32
Cross Controller (CROS_CNT) Registers
(Reg. 10, Reg. 11)........................................................................ 32
Analog Control (ANA_CNT) Registers
(Reg. 14, Reg. 15)........................................................................ 33
Built-In Self Test Control (BIST_CNT) Registers
(Reg. 17, Reg. 18, Reg. 19, Reg. 20, Reg. 21)........................... 33
Controller Clock Predivider (CCLK_DIV) Reading
Register (Reg. 22) ....................................................................... 34
Theory of Operation ...................................................................... 35
Serial Peripheral Interface ............................................................. 36
General Operation of the Serial Interface............................... 36
Short Instruction Mode (8-Bit Instruction) ........................... 36
Long Instruction Mode (16-Bit Instruction).......................... 36
Serial Interface Port Pin Descriptions ..................................... 36
SCLK—Serial Clock............................................................... 36
CSB—Chip Select................................................................... 37
SDIO—Serial Data I/O.......................................................... 37
SDO—Serial Data Out .......................................................... 37
MSB/LSB Transfers .................................................................... 37
Notes on Serial Port Operation ................................................ 37
Pin Mode Operation .................................................................. 38
RESET Operation....................................................................... 38
Programming Sequence ............................................................ 38
Interpolation Filter..................................................................... 39
Data Interface Controllers......................................................... 39
LVDS Sample Logic.................................................................... 40
LVDS Sample Logic Calibration............................................... 40
Operating the LVDS Controller in Manual Mode via the
SPI Port........................................................................................ 41
AD9734/AD9735/AD9736
Rev. A | Page 3 of 72
Operating the LVDS Controller in Surveillance and
Auto Mode ...................................................................................41
SYNC Logic and Controller...........................................................42
SYNC Logic and Controller Operation....................................42
Operation in Manual Mode.......................................................42
Operation in Surveillance and Auto Modes............................42
FIFO Bypass.................................................................................42
Digital Built-In Self Test (BIST) ....................................................44
Overview ......................................................................................44
AD973x BIST Procedure............................................................45
AD973x Expected BIST Signatures ..........................................45
Generating Expected Signatures...............................................46
Cross Controller Registers .............................................................47
Analog Control Registers ...............................................................48
Band Gap Temperature Characteristic Trim Bits ...................48
Mirror Roll-Off Frequency Control .........................................48
Headroom Bits.............................................................................48
Voltage Reference........................................................................48
Applications Information...............................................................50
Driving the DACCLK Input......................................................50
DAC Output Distortion Sources...................................................51
DC-Coupled DAC Output.............................................................52
DAC Data Sources ..........................................................................53
Input Data Timing ..........................................................................54
Synchronization Timing.................................................................55
Power Supply Sequencing ..............................................................56
AD973X Evaluation Board Schematics ........................................57
AD973X Evaluation Board PCB Layout.......................................62
Outline Dimensions........................................................................69
Ordering Guide ...........................................................................69
REVISION HISTORY
9/06—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Table 1 ............................................................................5
Changes to Table 2 ............................................................................6
Changes to Table 3 ............................................................................8
Inserted Table 5..................................................................................9
Replaced Pin Configuration and Function Descriptions
Section ..............................................................................................10
Changes to Figure 27 to Figure 38 ................................................21
Changes to Figure 40 ......................................................................23
Changes to Table 9 ..........................................................................29
Changes to Figure 103 ....................................................................56
Changes to Figure 105 ....................................................................58
Changes to Figure 107 ....................................................................60
Changes to Figure 108 ....................................................................61
Changes to Figure 115 ....................................................................68
Updated Outline Dimensions........................................................69
Changes to Ordering Guide...........................................................69
4/05—Revision 0: Initial Version
AD9734/AD9735/AD9736
Rev. A | Page 4 of 72
SPECIFICATIONS
DC SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load,
unless otherwise noted.
Table 1.
AD9736 AD9735 AD9734
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 14 12 10 Bits
ACCURACY
Integral Nonlinearity (INL) −5.6 ±1.0 +5.6 −1.5 ±0.50 +1.5 −0.5 ±0.12 +0.5 LSB
Differential Nonlinearity (DNL) −2.1 ±0.6 +2.1 −0.5 ±0.25 +0.5 −0.1 ±0.06 +0.1 LSB
ANALOG OUTPUTS
Offset Error −0.01 ±0.005 +0.01 −0.01 ±0.005 +0.01 −0.01 ±0.005 +0.01 % FSR
Gain Error (With Internal
Reference)
±1.0 ±1.0 ±1.0 % FSR
Gain Error (Without Internal
Reference)
±1.0 ±1.0 ±1.0 % FSR
Full-Scale Output Current 8.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 mA
Output Compliance Range −1.0 +1.0 −1.0 1.0 −1.0 +1.0 V
Output Resistance 10 10 10 MΩ
Output Capacitance 1 1 1 pF
TEMPERATURE DRIFT
Offset 0 0 0 ppm/°C
Gain 80 80 80 ppm/°C
Reference Voltage1 40 40 40 ppm/°C
REFERENCE
Internal Reference Voltage1 1.14 1.2 1.26 1.14 1.2 1.26 1.14 1.2 1.26 V
Output Resistance2 5 5 5 kΩ
ANALOG SUPPLY VOLTAGES
AVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
CVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V
DIGITAL SUPPLY VOLTAGES
DVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
DVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V
SUPPLY CURRENTS
1× Mode, 1.2 GSPS
IAVDD33 25 25 25 mA
ICVDD18 47 47 47 mA
IDVDD33 10 10 10 mA
IDVDD18 122 122 122 mA
FIR Bypass (1×) Mode 380 380 380 mW
2× Mode, 1.2 GSPS
IAVDD33 25 25 25 mA
ICVDD18 47 47 47 mA
IDVDD33 10 10 10 mA
IDVDD18 234 234 234 mA
FIR 2× Interpolation Filter
Enabled
550 550 550 mW
AD9734/AD9735/AD9736
Rev. A | Page 5 of 72
AD9736 AD9735 AD9734
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
Static, No Clock
IAVDD33 25 25 25 mA
ICVDD18 8 8 8 mA
IDVDD33 10 10 10 mA
IDVDD18 2 2 2 mA
FIR Bypass (1×) Mode 133 133 133 mW
Sleep Mode, No Clock
IAVDD33 2.5 3.15 2.5 3.15 2.5 3.15 mA
FIR Bypass (1×) Mode 59 65 59 65 59 65 mW
Power-Down Mode3
IAVDD33 0.01 0.13 0.01 0.13 0.01 0.13 mA
ICVDD18 0.02 0.12 0.02 0.12 0.02 0.12 mA
IDVDD33 0.01 0.12 0.01 0.12 0.01 0.12 mA
IDVDD18 0.01 0.11 0.01 0.11 0.01 0.11 mA
FIR Bypass (1×) Mode 0.12 1.24 0.12 1.24 0.12 1.24 mW
1 Default band gap adjustment (Reg. 0x0E <2:0> = 0x0).
2 Use an external amplifier to drive any external load.
3 Typical wake-up time is 8 μs with recommended 1 nF capacitor on VREF pin.
AD9734/AD9735/AD9736
Rev. A | Page 6 of 72
DIGITAL SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load,
unless otherwise noted. LVDS drivers and receivers are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
LVDS DATA INPUT
(DB[13:0]+, DB[13:0]−) DB+ = VIA, DB− = VIB
Input Voltage Range, VIA or VIB 825 1575 mV
Input Differential Threshold, VIDTH −100 +100 mV
Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV
Receiver Differential Input Impedance, RIN 80 120 Ω
LVDS Input Rate 1200 MSPS
LVDS Minimum Data Valid Period (tMDE) 344 ps
LVDS CLOCK INPUT
(DATACLK_IN+, DATACLK_IN−) DATACLK_IN+ = VIA, DATACLK_IN− = VIB
Input Voltage Range, VIA or VIB 825 1575 mV
Input Differential Threshold,1 VIDTH −100 +100 mV
Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV
Receiver Differential Input Impedance, RIN 80 120 Ω
Maximum Clock Rate 600 MHz
LVDS CLOCK OUTPUT
(DATACLK_OUT+, DATACLK_ OUT−) DATACLK_OUT+ = Voa, DATACLK_OUT− = Vob 100 Ω Termination
Output Voltage High, VOA or VOB 1375 mV
Output Voltage Low, VOA or VOB 1025 mV
Output Differential Voltage, |VOD| 150 200 250 mV
Output Offset Voltage, VOS 1150 1250 mV
Output Impedance, Single-Ended, RO 80 100 120 Ω
RO Mismatch Between A and B, ∆RO 10 %
Change in |VOD| Between 0 and 1, |∆VOD| 25 mV
Change in VOS Between 0 and 1, ∆VOS 25 mV
Output Current—Driver Shorted to Ground, ISA, ISB 20 mA
Output Current—Drivers Shorted Together, ISAB 4 mA
Power-Off Output Leakage, |IXA|, |IXB| 10 mA
Maximum Clock Rate 600 MHz
DAC CLOCK INPUT (CLK+, CLK−)
Input Voltage Range, CLK− or CLK+ 0 800
Differential Peak-to-Peak Voltage 400 800 1600 mV
Common-Mode Voltage 300 400 500 mV
Maximum Clock Rate 1200 MHz
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (fSCLK, 1/tSCLK) 20 MHz
Minimum Pulse Width High, tPWH 20 ns
Minimum Pulse Width Low, tPWL 20 ns
Minimum SDIO and CSB to SCLK Setup, tDS 10 ns
Minimum SCLK to SDIO Hold, tDH 5 ns
Maximum SCLK to Valid SDIO and SDO, tDV 20 ns
Minimum SCLK to Invalid SDIO and SDO, tDNV 5 ns
AD9734/AD9735/AD9736
Rev. A | Page 7 of 72
Parameter Min Typ Max Unit
INPUT (SDI, SDIO, SCLK, CSB)
Voltage in High, VIH 2.0 3.3 V
Voltage in Low, VIL 0 0.8 V
Current in High, IIH −10 +10 μA
Current in Low, IIL −10 +10 μA
SDIO OUTPUT
Voltage out High, VOH 2.4 3.6 V
Voltage out Low, VOL 0 0.4 V
Current out High, IOH 4 mA
Current out Low, IOL 4 mA
1Refer to the Input Data Timing section for recommended LVDS differential drive levels.
AD9734/AD9735/AD9736
Rev. A | Page 8 of 72
AC SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load,
unless otherwise noted.
Table 3.
AD9736 AD9735 AD9734
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Update Rate 1200 1200 1200 MSPS
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 800 MSPS
fOUT = 20 MHz 75 75 75 dBc
fDAC = 1200 MSPS
fOUT = 50 MHz 80 76 76 dBc
fOUT = 100 MHz 77 74 71 dBc
fOUT = 316 MHz 63 63 60 dBc
fOUT = 550 MHz 55 54 53 dBc
TWO-TONE INTERMODULATION
DISTORTION (IMD)
fDAC = 1200 MSPS
fOUT2 = fOUT + 1.25 MHz
fOUT = 40 MHz 88 84 83 dBc
fOUT = 50 MHz 85 84 83 dBc
fOUT = 100 MHz 84 81 79 dBc
fOUT = 316 MHz 70.5 67 66 dBc
fOUT = 550 MHz 65 60 60 dBc
NOISE SPECTRAL DENSITY (NSD)
Single Tone
fDAC = 1200 MSPS
fOUT = 50 MHz −165 −162 −154 dBm/Hz
fOUT = 100 MHz −164 −161 −154 dBm/Hz
fOUT = 241MHz −158.5 −160.5 −159.5 −155 dBm/Hz
fOUT = 316 MHz −158 −157 −152 dBm/Hz
fOUT = 550 MHz −155 −155 −149 dBm/Hz
Eight-Tone
fDAC = 1200 MSPS, 500 kHz Tone Spacing
fOUT = 50 MHz −166.5 −163 −154 dBm/Hz
fOUT = 100 MHz −166 −163 −152 dBm/Hz
fOUT = 241MHz −163.3 −165 −161.5 −150.5 dBm/Hz
fOUT = 316 MHz −164 −162 −151 dBm/Hz
fOUT = 550 MHz −162 −160 −150 dBm/Hz
AD9734/AD9735/AD9736
Rev. A | Page 9 of 72
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
With
Respect to Min Max
AVDD33 AVSS −0.3 V +3.6 V
DVDD33 DVSS −0.3 V +3.6 V
DVDD18 DVSS −0.3 V +1.98 V
CVDD18 CVSS −0.3 V +1.98 V
AVSS DVSS −0.3 V +0.3 V
AVSS CVSS −0.3 V +0.3 V
DVSS CVSS −0.3 V +0.3 V
CLK+, CLK− CVSS −0.3 V CVDD18 + 0.18 V
PIN_MODE DVSS −0.3 V DVDD33 + 0.3 V
DATACLK_IN,
DATACLK_OUT
DVSS −0.3 V DVDD33 + 0.3 V
LVDS Data Inputs DVSS −0.3 V DVDD33 + 0.3 V
IOUTA, IOUTB AVSS −1.0 V AVDD33 + 0.3 V
I120, VREF, IPTAT AVSS −0.3 V AVDD33 + 0.3 V
IRQ, CSB, SCLK, SDO,
SDIO, RESET
DVSS −0.3 V DVDD33 + 0.3 V
Junction Temperature 150°C
Storage Temperature −65°C +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may effect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type θJA1 Unit
160-Lead Ball, CSP_BGA 31.2 °C/W
1θJA measurement in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Note that this device in its current form does not meet Analog Devices’ standard requirements for ESD as measured against the charged
device model (CDM). As such, special care should be used when handling this product, especially in a manufacturing environment. Analog
Devices will provide a more ESD-hardy product in the near future at which time this warning will be removed from this data sheet.
AD9734/AD9735/AD9736
Rev. A | Page 10 of 72
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A
B
C
D
E
F
DACCLK–
DACCLK+
G
H
J
K
L
MDB0 (LSB)
N
P
1413121110876321954
04862-005
DB1
DB10
DB11
DB12
DB13 (MSB)
DB9
DB8
DB7
DB6
DATACLK_IN
DATACLK_OUT
DB5
DB4
DB3
DB2
Figure 2. AD9736 Digital LVDS Input, Clock I/O (Top View)
Table 6. AD9736 Pin Function Descriptions
Pin No. Mnemonic Description
A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3 CVDD18 1.8 V Clock Supply.
A4, A5, A6, A9, A10, A11, B4, B5, B6, B9,
B10, B11, C4, C5, C6, C9, C10, C11, D4, D5,
D6, D9, D10, D11
AVSS Analog Supply Ground.
A7, B7, C7, D7 IOUTB DAC Negative Output. 10 mA to 30 mA full-scale output current.
A8, B8, C8, D8 IOUTA DAC Positive Output. 10 mA to 30 mA full-scale output current.
A12, A13, B12, B13, C12, C13, D12, D13 AVDD33 3.3 V Analog Supply.
A14 DNC Do Not Connect.
B14 I120 Nominal 1.2 V Reference. Tie to analog ground via 10 kΩ resistor to
generate a 120 μA reference current.
C14 VREF Band Gap Voltage Reference I/O. Tie to analog ground via 1 nF
capacitor; output impedance is approximately 5 kΩ.
D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4 CVSS Clock Supply Ground.
D14 IPTAT Factory Test Pin. Output current, proportional to absolute
temperature, is approximately 10 μA at 25°C with a slope of
approximately 20 nA/°C.
E1, F1 DACCLK−/DACCLK+ Negative/Positive DAC Clock Input (DACCLK).
E11, E12, F11, F12, G11, G12 AVSS Analog Supply Ground Shield. Tie to AVSS at the DAC.
E13 IRQ/UNSIGNED If PIN_MODE = 0, IRQ: Active low open-drain interrupt request
output, pull up to DVDD33 with 10 kΩ resistor.
If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = twos
complement input data format, 1 = unsigned.
E14 RESET/PD If PIN_MODE = 0, RESET: 1 resets the AD9736.
If PIN_MODE = 1, PD: 1 puts the AD9736 in the power-down state.
F13 CSB/2× See the Serial Peripheral Interface section and the Pin Mode
Operation section for pin description.
F14 SDIO/FIFO See the Pin Mode Operation section for pin description.
G13 SCLK/FSC0 See the Pin Mode Operation section for pin description.
G14 SDO/FSC1 See the Pin Mode Operation section for pin description.
H1, H2, H3, H4, H11, H12, H13, H14, J1, J2,
J3, J4, J11, J12, J13, J14
DVDD18 1.8 V Digital Supply.
AD9734/AD9735/AD9736
Rev. A | Page 11 of 72
Pin No. Mnemonic Description
K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6,
L9, L10, L11, L12, M3, M4, M5, M6, M9,
M10, M11, M12
DVSS Digital Supply Ground.
K13, K14 DB<13>−/DB<13>+ Negative/Positive Data Input Bit 13 (MSB). Conforms to IEEE-1596
reduced range link.
L1 PIN_MODE 0 = SPI Mode. SPI is enabled.
1 = PIN Mode. SPI is disabled; direct pin control.
L7, L8, M7, M8, N7, N8, P7, P8 DVDD33 3.3 V Digital Supply.
L13, L14 DB<12>−/DB<12>+ Negative/Positive Data Input Bit 12. Conforms to IEEE-1596 reduced
range link.
M2, M1 DB<0>−/DB<0>+ Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596
reduced range link.
M13, M14 DB<11>−/DB<11>+ Negative/Positive Data Input Bit 11. Conforms to IEEE-1596 reduced
range link.
N1, P1 DB<1>−/DB<1>+ Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced
range link.
N2, P2 DB<2>−/DB<2>+ Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced
range link.
N3, P3 DB<3>−/DB<3>+ Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced
range link.
N4, P4 DB<4>−/DB<4>+ Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced
range link.
N5, P5 DB<5>−/DB<5>+ Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced
range link.
N6, P6 DATACLK_OUT−/
DATACLK_OUT+
Negative/Positive Data Output Clock. Conforms to IEEE-1596
reduced range link.
N9, P9 DATACLK_IN−/
DATACLK_IN+
Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced
range link.
N10, P10 DB<6>−/DB<6>+ Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced
range link.
N11, P11 DB<7>−/DB<7>+ Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced
range link.
N12, P12 DB<8>−/DB<8>+ Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced
range link.
N13, P13 DB<9>−/DB<9>+ Negative/Positive Data Input Bit 9. Conforms to IEEE-1596 reduced
range link.
N14, P14 DB<10>−/DB<10>+ Negative/Positive Data Input Bit 10. Conforms to IEEE-1596 reduced
range link.
AD9734/AD9735/AD9736
Rev. A | Page 12 of 72
04862-115
A
B
C
D
E
F
DACCLK–
DACCLK+
G
H
J
K
L
MNC
N
P
1413121110876321954
NC
DB8
DB9
DB10
DB11 (MSB)
DB7
DB6
DB5
DB4
DATACLK_IN
DB3
DATACLK_OUT
DB2
DB1
DB0 (LSB)
Figure 3. AD9735 Digital LVDS Input, Clock I/O (Top View)
Table 7. AD9735 Pin Function Descriptions
Pin No. Mnemonic Description
A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3 CVDD18 1.8 V Clock Supply.
A4, A5, A6, A9, A10, A11, B4, B5, B6, B9,
B10, B11, C4, C5, C6, C9, C10, C11, D4, D5,
D6, D9, D10, D11
AVSS Analog Supply Ground.
A7, B7, C7, D7 IOUTB DAC Negative Output. 10 mA to 30 mA full-scale output current.
A8, B8, C8, D8 IOUTA DAC Positive Output. 10 mA to 30 mA full-scale output current.
A12, A13, B12, B13, C12, C13, D12, D13 AVDD33 3.3 V Analog Supply.
A14 DNC Do Not Connect.
B14 I120 Nominal 1.2 V Reference. Tie to analog ground via 10 kΩ resistor to
generate a 120 μA reference current.
C14 VREF Band Gap Voltage Reference I/O. Tie to analog ground via 1 nF
capacitor; output impedance approximately 5 kΩ.
D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4 CVSS Clock Supply Ground.
D14 IPTAT Factory Test Pin; Output current, proportional to absolute
temperature, is approximately 10 μA at 25°C with a slope of
approximately 20 nA/°C.
E1, F1 DACCLK−/DACCLK+ Negative/Positive DAC Clock Input (DACCLK).
E11, E12, F11, F12, G11, G12 AVSS Analog Supply Ground Shield. Tie to AVSS at the DAC.
E13 IRQ/UNSIGNED If PIN_MODE = 0, IRQ: Active low open-drain interrupt request
output, pull up to DVDD33 with 10 kΩ resistor.
If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = twos
complement input data format, 1 = unsigned.
E14 RESET/PD If PIN_MODE = 0, RESET: 1 resets the AD9735.
If PIN_MODE = 1, PD: 1 puts the AD9735 in the power-down state.
F13 CSB/2× See the Serial Peripheral Interface section and the Pin Mode
Operation section for pin description.
F14 SDIO/FIFO See the Pin Mode Operation section for pin description.
G13 SCLK/FSC0 See the Pin Mode Operation section for pin description.
G14 SDO/FSC1 See the Pin Mode Operation section for pin description.
H1, H2, H3, H4, H11, H12, H13, H14, J1, J2,
J3, J4, J11, J12, J13, J14
DVDD18 1.8 V Digital Supply.
K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6,
L9, L10, L11, L12, M3, M4, M5, M6, M9,
M10, M11, M12
DVSS Digital Supply Ground.
AD9734/AD9735/AD9736
Rev. A | Page 13 of 72
Pin No. Mnemonic Description
K13, K14 DB<11>−/DB<11>+ Negative/Positive Data Input Bit 11 (MSB). Conforms to IEEE-1596
reduced range link.
L1 PIN_MODE 0 = SPI Mode. SPI is enabled.
1 = PIN Mode. SPI disabled; direct pin control.
L7, L8, M7, M8, N7, N8, P7, P8 DVDD33 3.3 V Digital Supply.
L13, L14 DB<10>−/DB<10>+ Negative/Positive Data Input Bit 10. Conforms to IEEE-1596 reduced
range link.
M1, M2 NC No Connect.
M13, M14 DB<9>−/DB<9>+ Negative/Positive Data Input Bit 9. Conforms to IEEE-1596 reduced
range link.
N1, P1 NC No Connect.
N2, P2 DB<0>−/DB<0>+ Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596
reduced range link.
N3, P3 DB<1>−/DB<1>+ Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced
range link.
N4, P4 DB<2>−/DB<2>+ Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced
range link.
N5, P5 DB<3>−/DB<3>+ Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced
range link.
N6, P6 DATACLK_OUT−/
DATACLK_OUT+
Negative/Positive Data Output Clock. Conforms to IEEE-1596
reduced range link.
N9, P9 DATACLK_IN−/
DATACLK_IN+
Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced
range link.
N10, P10 DB<4>−/DB<4>+ Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced
range link.
N11, P11 DB<5>−/DB<5>+ Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced
range link.
N12, P12 DB<6>−/DB<6>+ Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced
range link.
N13, P13 DB<7>−/DB<7>+ Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced
range link.
N14, P14 DB<8>−/DB<8>+ Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced
range link.
AD9734/AD9735/AD9736
Rev. A | Page 14 of 72
04862-114
A
B
C
D
E
F
DACCLK–
DACCLK
+
G
H
J
K
L
MNC
N
P
1413121110876321954
NC
DB6
DB7
DB8
DB9 (MSB)
DB5
DB4
DB3
DB2
DB1
DATACLK_OUT
DATACLK_IN
DB0 (LSB)
NC
NC
Figure 4. AD9734 Digital LVDS Input, Clock I/O (Top View)
Table 8. AD9734 Pin Function Descriptions
Pin No. Mnemonic Description
A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3 CVDD18 1.8 V Clock Supply.
A4, A5, A6, A9, A10, A11, B4, B5, B6, B9,
B10, B11, C4, C5, C6, C9, C10, C11, D4, D5,
D6, D9, D10, D11
AVSS Analog Supply Ground.
A7, B7, C7, D7 IOUTB DAC Negative Output. 10 mA to 30 mA full-scale output current.
A8, B8, C8, D8 IOUTA DAC Positive Output. 10 mA to 30 mA full-scale output current.
A12, A13, B12, B13, C12, C13, D12, D13 AVDD33 3.3 V Analog Supply.
A14 DNC Do Not Connect.
B14 I120 Nominal 1.2 V Reference. Tie to analog ground via 10 kΩ resistor to
generate a 120 μA reference current.
C14 VREF Band Gap Voltage Reference I/O. Tie to analog ground via 1 nF
capacitor; output impedance approximately 5 kΩ.
D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4 CVSS Clock Supply Ground.
D14 IPTAT Factory Test Pin. Output current, proportional to absolute
temperature, is approximately 10 μA at 25°C with a slope of
approximately 20 nA/°C.
E1, F1 DACCLK−/DACCLK+ Negative/Positive DAC Clock Input (DACCLK).
E11, E12, F11, F12, G11, G12 AVSS Analog Supply Ground Shield. Tie to AVSS at the DAC.
E13 IRQ/UNSIGNED If PIN_MODE = 0, IRQ: Active low open-drain interrupt request
output, pull up to DVDD33 with 10 kΩ resistor.
If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = twos
complement input data format, 1 = unsigned.
E14 RESET/PD If PIN_MODE = 0, RESET: 1 resets the AD9734.
If PIN_MODE = 1, PD: 1 puts the AD9734 in the power-down state.
F13 CSB/2× See the Serial Peripheral Interface section and the Pin Mode
Operation section for pin description.
F14 SDIO/FIFO See the Pin Mode Operation section for pin description.
G13 SCLK/FSC0 See the Pin Mode Operation section for pin description.
G14 SDO/FSC1 See the Pin Mode Operation section for pin description.
H1, H2, H3, H4, H11, H12, H13, H14, J1, J2,
J3, J4, J11, J12, J13, J14
DVDD18 1.8 V Digital Supply.
K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6,
L9, L10, L11, L12, M3, M4, M5, M6, M9,
M10, M11, M12
DVSS Digital Supply Ground.
AD9734/AD9735/AD9736
Rev. A | Page 15 of 72
Pin No. Mnemonic Description
K13, K14 DB<9>−/DB<9>+ Negative/Positive Data Input Bit 9 (MSB). Conforms to IEEE-1596
reduced range link.
L1 PIN_MODE 0 = SPI Mode. SPI is enabled.
1 = PIN Mode. SPI is disabled; direct pin control.
L7, L8, M7, M8, N7, N8, P7, P8 DVDD33 3.3 V Digital Supply.
L13, L14 DB<8>−/DB<8>+ Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced
range link.
M1, M2 NC No Connect.
M13, M14 DB<7>−/DB<7>+ Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced
range link.
N1, P1 NC No Connect.
N2, P2 NC No Connect.
N3, P3 NC No Connect.
N4, P4 DB<0>−/DB<0>+ Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596
reduced range link.
N5, P5 DB<1>−/DB<1>+ Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced
range link.
N6, P6 DATACLK_OUT−/
DATACLK_OUT+
Negative/Positive Data Output Clock. Conforms to IEEE-1596
reduced range link.
N9, P9 DATACLK_IN−/
DATACLK_IN+
Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced
range link.
N10, P10 DB<2>−/DB<2>+ Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced
range link.
N11, P11 DB<3>−/DB<3>+ Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced
range link.
N12, P12 DB<4>−/DB<4>+ Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced
range link.
N13, P13 DB<5>−/DB<5>+ Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced
range link.
N14, P14 DB<6>−/DB<6>+ Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced
range link.
AD9734/AD9735/AD9736
Rev. A | Page 16 of 72
LOCATION OF SUPPLY AND CONTROL PINS
04862-002
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1413121110876321954
AVSS, ANALOG SUPPLY GROUND
AVSS, ANALOG SUPPLY GROUND SHIELD
AVDD33, 3.3V, ANALOG SUPPLY
Figure 5. Analog Supply Pins (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1413121110876321954
CVDD18, 1.8V CLOCK SUPPLY
CVSS, CLOCK SUPPLY GROUND
04862-003
Figure 6. Clock Supply Pins (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1413121110876321954
04862-004
DVDD33, 3.3V DIGITAL SUPPLY
DVSS DIGITAL SUPPLY GROUND
DVDD18, 1.8V DIGITAL SUPPLY
Figure 7. Digital Supply Pins (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1413121110876321954
04862-006
I120
VREF
IPTAT PIN_MODE = 0,
SPI ENABLED
PIN_MODE = 1,
SPI DISABLED
PIN_MODE UNSIGNED
2×
FSC0
PD
FIFO
FSC1
IRQ
CSB
SCLK
RESET
SDIO
SDO
IOUTB
IOUTA
Figure 8. Analog I/O and SPI Control Pins (Top View)
AD9734/AD9735/AD9736
Rev. A | Page 17 of 72
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
The maximum deviation of the actual analog output from the
ideal output, determined by a straight line drawn from zero to
full scale.
Differential Nonlinearity (DNL)
The measure of the variation in analog value, normalized to full
scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero. For
IOUTA, 0 mA output is expected when the inputs are all 0s. For
IOUTB, 0 mA output is expected when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature D ri ft
Specified as the maximum change from the ambient (25°C)
value to the value at either TMIN or TMAX. For offset and gain
drift, the drift is reported in ppm of full-scale range (FSR) per
°C. For reference drift, the drift is reported in ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal. It is expressed as
a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak
spurious signal in the region of a removed tone.
AD9734/AD9735/AD9736
Rev. A | Page 18 of 72
TYPICAL PERFORMANCE CHARACTERISTICS
AD9736 STATIC LINEARITY, 10 mA FULL SCALE
04862-008
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
–2.00
Figure 9. AD9736 INL, −40°C, 10 mA FS
04862-008
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
–2.00
Figure 10. AD9736 INL, 25°C, 10 mA FS
04862-009
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
–2.00
Figure 11. AD9736 INL, 85°C, 10 mA FS
04862-010
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
Figure 12. AD9736 DNL, −40°C, 10 mA FS
04862-011
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
Figure 13. AD9736 DNL, 25°C, 10 mA FS
04862-012
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
Figure 14. AD9736 DNL, 85°C, 10 mA FS
AD9734/AD9735/AD9736
Rev. A | Page 19 of 72
AD9736 STATIC LINEARITY, 20 mA FULL SCALE
04862-013
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
Figure 15. AD9736 INL, −40°C, 20 mA FS
04862-014
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
Figure 16. AD9736 INL, 25°C, 20 mA FS
04862-015
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
Figure 17. AD9736 INL, 85°C, 20 mA FS
04862-016
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
Figure 18. AD9736 DNL, −40°C, 20 mA FS
04862-017
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
Figure 19. AD9736 DNL, 25°C, 20 mA FS
04862-018
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
Figure 20. AD9736 DNL, 85°C, 20 mA FS
AD9734/AD9735/AD9736
Rev. A | Page 20 of 72
AD9736 STATIC LINEARITY, 30 mA FULL SCALE
04862-019
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Figure 21. AD9736 INL, −40°C, 30 mA FS
04862-020
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Figure 22. AD9736 INL, 25°C, 30 mA FS
04862-021
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
2.0
1.5
1.0
0.5
0
0
0
0
–0.5
–0.5
–1.0
–1.0
–1.5
–1.5
–2.0
Figure 23. AD9736 INL, 85°C, 30 mA FS
04862-022
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
0.6
0.3
0.4
0.5
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
Figure 24. AD9736 DNL, −40°C, 30 mA FS
04862-023
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
0.6
0.3
0.4
0.5
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
Figure 25. AD9736 DNL, 25°C, 30 mA FS
04862-024
CODE
163840 2048 4096 6144 8192 10240 12288 14336
ERROR (LSB)
1.0
0
0.5
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
Figure 26. AD9736 DNL, 85°C, 30 mA FS
AD9734/AD9735/AD9736
Rev. A | Page 21 of 72
AD9735 STATIC LINEARITY, 10 mA, 20 mA, 30 mA FULL SCALE
04862-025
0.4
0.2
0.3
0.1
–0.1
0
–0.2
40963584307225602048153610240 512
CODE
ERROR (LSB)
Figure 27. AD9735 INL, 25°C, 10 mA FS
04862-026
0.15
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
40963584307225602048153610240 512
CODE
ERROR (LSB)
Figure 28. AD9735 INL, 25°C, 20 mA FS
04862-027
0.2
0
0.1
–0.2
–0.1
–0.4
–0.5
–0.3
–0.6
40963584307225602048153610240 512
CODE
ERROR (LSB)
Figure 29. AD9735 INL, 25°C, 30 mA FS
04862-028
40963584307225602048153610240 512
0.100
0.050
0
–0.050
–0.100
–0.150
–0.200
–0.250
CODE
ERROR (LSB)
Figure 30. AD9735 DNL, 25°C, 10 mA FS
04862-029
0.100
0.075
0.025
0.050
0
–0.025
–0.075
–0.050
–0.100
–0.125
40963584307225602048153610240 512
CODE
ERROR (LSB)
Figure 31. AD9735 DNL, 25°C, 20 mA FS
04862-030
40963584307225602048153610240 512
CODE
ERROR (LSB)
0.050
0
–1.000
–0.050
–1.150
–0.200
–0.300
–0.250
–0.350
–0.400
Figure 32. AD9735 DNL, 25°C, 30 mA FS
AD9734/AD9735/AD9736
Rev. A | Page 22 of 72
AD9734 STATIC LINEARITY, 10 mA, 20 mA, 30 mA FULL SCALE
04862-031
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
10248967686405123842560 128
CODE
ERROR (LSB)
Figure 33. AD9734 INL, 25°C, 10 mA FS
04862-032
ERROR (LSB)
0.03
0.02
0.01
0
–0.01
–0.03
–0.02
–0.04
–0.05
–0.06
10248967686405123842560 128
CODE
Figure 34. AD9734 INL, 25°C, 20 mA FS
04862-033
ERROR (LSB)
10248967686405123842560 128
CODE
0.06
0.04
0.02
0
–0.02
–0.06
–0.04
–0.08
–0.10
–0.12
Figure 35. AD9734 INL, 25°C, 30 mA FS
04862-034
ERROR (LSB)
10248967686405123842560 128
CODE
0.04
0.03
0.02
0.01
0
–0.01
–0.02
Figure 36. AD9734 DNL, 25°C, 10 mA FS
04862-035
ERROR (LSB)
10248967686405123842560 128
CODE
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
Figure 37. AD9734 DNL, 25°C, 20 mA FS
04862-036
ERROR (LSB)
10248967686405123842560 128
CODE
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
Figure 38. AD9734 DNL, 25°C, 30 mA FS
AD9734/AD9735/AD9736
Rev. A | Page 23 of 72
AD9736 POWER CONSUMPTION, 20 mA FULL SCALE
04862-037
DVDD18
DVDD33
CVDD18
AVDD33
TOTAL
f
DAC
(MHz)
15000 250 500 750 1000 1250
POWER (W)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
Figure 39. AD9736 1× Mode Power vs. fDAC at 25°C
04862-038
f
DAC
(MHz)
15000 250 500 750 1000 1250
POWER (W)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
DVDD18
DVDD33
CVDD18
AVDD33
TOTAL
Figure 40. AD9736, 2× Interpolation Mode Power vs. fDAC at 25°C
AD9734/AD9735/AD9736
Rev. A | Page 24 of 72
AD9736 DYNAMIC PERFORMANCE, 20 mA FULL SCALE
04862-039
800MSPS
1GSPS
1.2GSPS
f
OUT
(MHz)
6000 50 100 150 200 250 300 350 400 450 500 550
SFDR (dBc)
80
75
70
65
60
55
50
Figure 41. AD9736 SFDR vs. fOUT over fDAC at 25°C
04862-040
f
OUT
(MHz)
6000 50 100 150 200 250 300 350 400 450 500 550
SFDR (dBc)
80
75
70
65
60
55
50
+85°C
+25°C
–40°C
Figure 42. AD9736 SFDR vs. fOUT over Temperature
04862-041
5500 50 100 150 200 250 300 350 400 450 500
76
78
72
74
70
68
66
64
62
60
56
54
58
52
f
OUT
(MHz)
SFDR (dBc)
Figure 43. AD9736 SFDR vs. fOUT over 50 Parts, 25°C, 1.2 GSPS
04862-042
5500 50 100 150 200 250 300 350 400 450 500
92
86
88
90
82
80
84
78
76
74
70
72
66
68
62
60
64
58
f
OUT
(MHz)
IMD (dBc)
Figure 44. AD9736 IMD vs. fOUT over 50 Parts, 25°C,1.2 GSPS
04862-043
f
OUT
(MHz)
6000 100 200 300 400 500
IMD (dBc)
90
85
80
75
70
65
60
55
50
800MSPS
1GSPS
1.2GSPS
Figure 45. AD9736 IMD vs. fOUT over fDAC at 25°C
04862-044
f
OUT
(MHz)
6000 100 200 300 400 500
IMD (dBc)
90
85
80
75
70
65
60
55
50
+85°C +25°C
–40°C
Figure 46. AD9736 IMD vs. fOUT over Temperature, 1.2 GSPS
AD9734/AD9735/AD9736
Rev. A | Page 25 of 72
04862-045
f
OUT
(MHz)
100010
IMD AND SFDR (dBc)
95
90
85
80
75
70
65
60
55
IMD
SFDR
Figure 47. AD9736 Low Frequency IMD and SFDR vs. fOUT, 25°C, 1.2 GSPS
04862-046
f
OUT
(MHz)
3500 50 100 150 200 250 300
SFDR, IMID (dBc)
90
85
80
75
70
65
60
55
50
THIRD-ORDER IMD
SFDR
Figure 48. AD9736 IMD and SFDR vs. fOUT, 25°C, 1.2 GSPS, 2× Interpolation
04862-047
f
OUT
(MHz)
6000 100 200 300 400 500
SFDR (dBc)
80
75
70
65
60
55
50
45
40
0dBFS
–6dBFS
–12dBFS
Figure 49. AD9736 SFDR vs. fOUT over AOUT, 25°C, 1.2 GSPS
04862-048
f
OUT
(MHz)
6000 100 200 300 400 500
IMD (dBc)
90
85
80
75
70
65
60
55
50
0dBFS
–6dBFS –12dBFS
Figure 50. AD9736 IMD vs. fOUT over AOUT, 25°C, 1.2 GSPS
04862-049
f
OUT
(MHz)
3500 50 100 150 200 250 300
SFDR, IMD (dBc)
90
85
80
75
70
65
60
55
50
SFDR_1×
SFDR_2×
Figure 51. AD9736 SFDR vs. fOUT, 25°C, 1.2 GSPS, 1× and 2× Interpolation
04862-050
f
OUT
(MHz)
3500 50 100 150 200 250 300
SFDR, IMD (dBc)
90
85
80
75
70
65
60
55
50
THIRD-ORDER IMD_1×
THIRD-ORDER IMD_2×
Figure 52. AD9736 IMD vs. fOUT, 25°C, 1.2 GSPS, 1× and 2× Interpolation
AD9734/AD9735/AD9736
Rev. A | Page 26 of 72
04862-051
f
OUT
(MHz)
6000 100 200 300 400 500
NSD (dBm/Hz)
–150
–154
–156
–152
–158
–160
–162
–164
–166
–168
–170
1GSPS
1.2GSPS
Figure 53. AD9736 1-Tone NSD vs. fOUT over fDAC, 25°C
04862-052
f
OUT
(MHz)
6000 100 200 300 400 500
NSD (dBm/Hz)
–150
–154
–156
–152
–158
–160
–162
–164
–166
–168
–170
+85°C
+25°C
–40°C
Figure 54. AD9736 1-Tone NSD vs. fOUT over Temperature, 1.2 GSPS
04862-053
f
OUT
(MHz)
6000 100 200 300 400 500
NSD (dBm/Hz)
–150
–154
–156
–152
–158
–160
–162
–164
–166
–168
–170
1GSPS
1.2GSPS
Figure 55. AD9736 8-Tone NSD vs. fOUT over fDAC, 25°C
04862-054
f
OUT
(MHz)
6000 100 200 300 400 500
NSD (dBm/Hz)
–150
–154
–156
–152
–158
–160
–162
–164
–166
–168
–170
+85°C
+25°C
–40°C
Figure 56. AD9736 8-Tone NSD vs. fOUT over Temperature, 1.2 GSPS
04862-055
5500 50 100 150 200 250 300 350 400 450 500
–159
–158
–160
–157
–161
–162
–163
–164
–165
–166
f
OUT
(MHz)
NSD (dBm/Hz)
Figure 57. AD9736 1-Tone NSD vs. fOUT over 50 Parts, 1.2 GSPS, 25°C
04862-056
5500 50 100 150 200 250 300 350 400 450 500
–162
–163
–161
–164
–165
–166
–167
fOUT (MHz)
NSD (dBm/Hz)
Figure 58. AD9736 8-Tone NSD vs. fOUT over 50 Parts, 1.2 GSPS, 25°C
AD9734/AD9735/AD9736
Rev. A | Page 27 of 72
AD9735, AD9734 DYNAMIC PERFORMANCE, 20 mA FULL SCALE
04862-060
f
OUT
(MHz)
6000 50 100 150 200 250 300 350 400 450 500 550
SFDR (dBc)
80
75
70
65
60
55
50
800MSPS
1GSPS
1.2GSPS
Figure 59. AD9735 SFDR vs. fOUT over fDAC, 1.2 GSPS
04862-061
f
OUT
(MHz)
6000 50 100 150 200 250 300 350 400 450 500 550
SFDR (dBc)
80
75
70
65
60
55
50
800MSPS
1GSPS
1.2GSPS
Figure 60. AD9734 SFDR vs. fOUT over fDAC, 1.2 GSPS
04862-062
f
OUT
(MHz)
6000 50 100 150 200 250 300 350 400 450 500 550
IMD (dBc)
90
85
80
75
70
65
60
55
50
800MSPS
1GSPS
1.2GSPS
Figure 61. AD9735 IMD vs. fOUT over fDAC, 1.2 GSPS
04862-063
f
OUT
(MHz)
6000 50 100 150 200 250 300 350 400 450 500 550
IMD (dBc)
90
85
80
75
70
65
60
55
50
800MSPS
1GSPS
1.2GSPS
Figure 62. AD9734 IMD vs. fOUT over fDAC, 1.2 GSPS
04862-064
f
OUT
(MHz)
6000 50 100 150 200 250 300 350 400 450 500 550
NSD (dBc/Hz)
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
1 TONE
8 TONES
Figure 63. AD9735 NSD vs. fOUT, 1.2 GSPS
04862-065
f
OUT
(MHz)
6000 50 100 150 200 250 300 350 400 450 500 550
NSD (dBc/Hz)
–149
–147
–145
–151
–153
–155
–157
–159
–161
–163
–165
1 TONE
8 TONES
Figure 64. AD9734 NSD vs. fOUT, 1.2 GSPS
AD9734/AD9735/AD9736
Rev. A | Page 28 of 72
AD973x WCDMA ACLR, 20 mA FULL SCALE
04862-057
#ATTEN 6dB
PAVG
10
W1 S2
CENTER 134.83MHz
#RES BW 30kHz
VBW 300kHz SPAN 33.88MHz
SWEEP 109.9ms (601pts)
REF –22.75dBm
#AVG
LOG 10dB/
RMS RESULTS OFFSET FREQ REF BW dBc dBm dBc dBm
CARRIER POWER 5.00MHz 3.840MHz –81.65 –92.37 –81.39 –92.11
–10.72dBm/ 10.0MHz 3.840MHz –82.06 –92.78 –82.43 –93.16
3.84000MHz 15.0MHz 3.884MHz –82.11 –92.83 –82.39 –93.11
LOWER UPPER
Figure 65. AD9736 WCDMA Carrier at 134.83 MHz, fDAC = 491.52 MSPS
04862-058
RMS RESULTS OFFSET FREQ REF BW dBc dBm dBc dBm
CARRIER POWER 5.00MHz 3.840MHz –80.32 –91.10 –80.60 –91.38
–10.72dBm/ 10.0MHz 3.840MHz –81.13 –91.91 –80.75 –91.53
3.84000MHz 15.0MHz 3.884MHz –80.43 –91.21 –81.36 –92.13
LOWER UPPER
PAVG
10 S2
CENTER 134.83MHz
#RES BW 30kHz
VBW 300kHz
#ATTEN 6dB
SPAN 33.88MHz
SWEEP 109.9ms (601pts)
REF –22.75dBm
#AVG
LOG 10dB/
Figure 66. AD9735 WCDMA Carrier at 134.83 MHz, fDAC = 491.52 MSPS
04862-059
RMS RESULTS OFFSET FREQ REF BW dBc dBm dBc dBm
CARRIER POWER 5.00MHz 3.840MHz –71.07 –81.83 –71.23 –81.99
–10.76dBm/ 10.0MHz 3.840MHz –70.55 –81.31 –71.42 –82.19
3.84000MHz 15.0MHz 3.884MHz –70.79 –81.56 –71.25 –82.01
LOWER UPPER
PAVG
10 S2
CENTER 134.83MHz
#RES BW 30kHz
VBW 300kHz
#ATTEN 6dB
SPAN 33.88MHz
SWEEP 109.9ms (601pts)
REF –22.75dBm
#AVG
LOG 10dB/
Figure 67. AD9734 WCDMA Carrier at 134.83 MHz, fDAC = 491.52 MSPS
AD9734/AD9735/AD9736
Rev. A | Page 29 of 72
SPI REGISTER MAP
Write 0 to unspecified or reserved bit locations. Reading these bits returns unknown values.
Table 9. SPI Register Map
Reg. Addr. Default Pin Mode
Dec. Hex.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) (Hex)
0 00 MODE SDIO_DIR LSBFIRST RESET LONG_INS 2X MODE FIFO MODE DATAFRMT PD 00 00
1 01 IRQ LVDS SYNC CROSS RESERVED IE_LVDS IE_SYNC IE_CROSS RESERVED 00 00
2 02 FSC_1 SLEEP FSC<9> FSC<8> 02 02
3 03 FSC_2 FSC<7> FSC<6> FSC<5> FSC<4> FSC<3> FSC<2> FSC<1> FSC<0> 00 00
4 04 LVDS_CNT1 MSD<3> MSD<2> MSD<1> MSD<0> MHD<3> MHD<2> MHD<1> MHD<0> 00 00
5 05 LVDS_CNT2 SD<3> SD<2> SD<1> SD<0> LCHANGE ERR_HI ERR_LO CHECK 00 00
6 06 LVDS_CNT3 LSURV LAUTO LFLT<3> LFLT<2> LFLT<1> LFLT<0> LTRH<1> LTRH<0> 00 00
7 07 SYNC_CNT1 FIFOSTAT3 FIFOSTAT2 FIFOSTAT1 FIFOSTAT0 VALID SCHANGE PHOF<1> PHOF<0> 00 00
8 08 SYNC_CNT2 SSURV SAUTO SFLT<3> SFLT<2> SFLT<1> SFLT<0> RESERVED STRH<0> 00 00
9 09 RESERVED
10 0A CROS_CNT1 UPDEL<5> UPDEL<4> UPDEL<3> UPDEL<2> UPDEL<1> UPDEL<0> 00 00
11 0B CROS_CNT2 DNDEL<5> DNDEL<4> DNDEL<3> DNDEL<2> DNDEL<1> DNDEL<0> 00 00
12 0C RESERVED
13 0D RESERVED
14 0E ANA_CNT1 MSEL<1> MSEL<0> TRMBG<2> TRMBG<1> TRMBG<0> C0 C0
15 0F ANA_CNT2 HDRM<7> HDRM<6> HDRM<5> HDRM<4> HDRM<3> HDRM<2> HDRM<1> HDRM<0> CA CA
16 10 RESERVED
17 11 BIST_CNT SEL<1> SEL<0> SIG_READ LVDS_EN SYNC_EN CLEAR 00 00
18 12 BIST<7:0>
19 13 BIST<15:8>
20 14 BIST<23:16>
21 15 BIST<31:24>
22 16 CCLK_DIV RESERVED RESERVED RESERVED RESERVED CCD<3> CCD<2> CCD<1> CCD<0> 00 00
AD9734/AD9735/AD9736
Rev. A | Page 30 of 72
SPI REGISTER DETAILS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Reset value for write registers
in bold text.
MODE REGISTER (REG. 0)
ADDR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00 MODE SDIO_DIR LSB/MSB RESET LONG_INS 2× MODE FIFO MODE DATAFRMT PD
Table 10. Mode Register Bit Descriptions
Bit Name Read/Write Description
SDIO_DIR WRITE 0, input only per SPI standard.
1, bidirectional per SPI standard.
LSB/MSB WRITE 0, MSB first per SPI standard.
1, LSB first per SPI standard.
NOTE: Only change LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit
order errors.
RESET WRITE 0, execute software reset of SPI and controllers, reload default register values except Registers 0x00
and 0x04.
1, set software reset, write 0 on the next (or any following) cycle to release the reset.
LONG_INS WRITE 0, short (single-byte) instruction word.
1, long (two-byte) instruction word, not necessary since the maximum internal address is REG31
(0x1F).
2×_MODE WRITE 0, disable 2× interpolation filter.
1, enable 2× interpolation filter.
FIFO_MODE WRITE 0, disable FIFO synchronization.
1, enable FIFO synchronization.
DATAFRMT WRITE 0, signed input DATA with midscale = 0x0000.
1, unsigned input DATA with midscale = 0x2000.
PD WRITE 0, enable LVDS Receiver, DAC, and clock circuitry.
1, power down LVDS Receiver, DAC, and clock circuitry.
INTERRUPT REQUEST REGISTER (IRQ) (REG. 1)
ADDR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x01 IRQ LVDS SYNC CROSS RESERVED IE_LVDS IE_SYNC IE_CROSS RESERVED
Table 11. Interrupt Register Bit Descriptions
Bit Name Read/Write Description
LVDS WRITE Don’t care.
READ
0, no active LVDS receiver interrupt.
1, interrupt in LVDS receiver occurred.
SYNC WRITE Don’t care.
READ
0, no active SYNC logic interrupt.
1, interrupt in SYNC logic occurred.
CROSS WRITE Don’t care.
READ
0, no active CROSS logic interrupt.
1, interrupt in CROSS logic occurred.
IE_LVDS WRITE 0, reset LVDS receiver interrupt and disable future LVDS receiver interrupts.
1, enable LVDS receiver interrupt to activate IRQ pin.
IE_SYNC WRITE 0, reset SYNC logic interrupt and disable future SYNC logic interrupts.
1, enable SYNC logic interrupt to activate IRQ pin.
IE_CROSS WRITE 0, reset CROSS logic interrupt and disable future CROSS logic interrupts.
1, enable CROSS logic interrupt to activate IRQ pin.
AD9734/AD9735/AD9736
Rev. A | Page 31 of 72
FULL SCALE CURRENT (FSC) REGISTERS (REG. 2, REG. 3)
ADDR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x02 FSC_1 SLEEP – – – – – FSC<9> FSC<8>
0x03 FSC_2 FSC<7> FSC<6> FSC<5> FSC<4> FSC<3> FSC<2> FSC<1> FSC<0>
Table 12. Full Scale Current Output Register Bit Descriptions
Bit Name Read/Write Description
SLEEP WRITE 0, enable DAC output.
1, set DAC output current to 0 mA.
FSC<9:0> WRITE 0x000, 10 mA full-scale output current.
0x200, 20 mA full-scale output current.
0x3FF, 30 mA full-scale output current.
LVDS CONTROLLER (LVDS_CNT) REGISTERS (REG. 4, REG. 5, REG. 6)
ADDR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x04 LVDS_CNT1 MSD<3> MSD<2> MSD<1> MSD<0> MHD<3> MHD<2> MHD<1> MHD<0>
0x05 LVDS_CNT2 SD<3> SD<2> SD<1> SD<0> LCHANGE ERR_HI ERR_LO CHECK
0x06 LVDS_CNT3 LSURV LAUTO LFLT<3> LFLT<2> LFLT<1> LFLT<0> LTRH<1> LTRH<0>
Table 13. LVDS Controller Register Bit Descriptions
Bit Name Read/Write Description
MSD<3:0> WRITE 0x0, set setup delay for the measurement system.
READ
If ( LAUTO = 1), the latest measured value for the setup delay.
If ( LAUTO = 0), readback of the last SPI write to this bit.
MHD<3:0> WRITE 0x0, set hold delay for the measurement system.
READ
If ( LAUTO = 1), the latest measured value for the hold delay.
If ( LAUTO = 0), readback of the last SPI write to this bit.
SD<3:0> WRITE 0x0, set sample delay.
READ
If ( LAUTO = 1), the result of a measurement cycle is stored in this register.
If ( LAUTO = 0), readback of the last SPI write to this bit.
LCHANGE READ 0, no change from previous measurement.
1, change in value from the previous measurement.
NOTE: The average filter and the threshold detection are not applied to this bit.
ERR_HI READ One of the 15 LVDS inputs is above the input voltage limits of the IEEE reduced link specification.
ERR_LO READ One of the 15 LVDS inputs is below the input voltage limits of the IEEE reduced link specification.
CHECK READ 0, phase measurement—sampling in the previous or following DATA cycle.
1, phase measurement—sampling in the correct DATA cycle.
LSURV WRITE 0, the controller stops after completion of the current measurement cycle.
1, continuous measurements are taken and an interrupt is issued if the clock alignment drifts beyond the
threshold value.
LAUTO WRITE 0, sample delay is not automatically updated.
1, continuously starts measurement cycles and updates the sample delay according to the measurement.
NOTE: LSURV (Reg. 6, Bit 7) must be set to 1 and the LVDS IRQ (Reg. 1, Bit 3) must be set to 0 for AUTO mode.
LFLT<3:0> WRITE 0x0, average filter length, Delay = Delay + Delta Delay/2^ LFLT <3:0>, values greater than 12 (0x0C) are
clipped to 12.
LTRH<2:0> WRITE 000, set auto update threshold values.
AD9734/AD9735/AD9736
Rev. A | Page 32 of 72
SYNC CONTROLLER (SYNC_CNT) REGISTERS (REG. 7, REG. 8)
ADDR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x07 SYNC_CNT1 FIFOSTAT3 FIFOSTAT2 FIFOSTAT1 FIFOSTAT0 VALID SCHANGE PHOF<1> PHOF<0>
0x08 SYNC_CNT2 SSURV SAUTO SFLT<3> SFLT<2> SFLT<1> SFLT<0> RESERVED STRH<0>
Table 14. Sync Controller Register Bit Descriptions
Bit Name Read/Write Description
FIFOSTAT<2:0> READ Position of FIFO read counter ranges from 0 to 7.
FIFOSTAT<3> READ 0, SYNC logic OK.
1, error in SYNC logic.
VALID READ
0, FIFOSTAT<3:0> is not valid yet.
1, FIFOSTAT<3:0> is valid after a reset.
SCHANGE READ 0, no change in FIFOSTAT<3:0>.
1, FIFOSTAT<3:0> has changed since the previous measurement cycle when SSURV = 1 (surveillance mode
active).
PHOF<1:0> WRITE 00, change the readout counter.
READ
Current setting of the readout counter (PHOF<1:0>) in surveillance mode (SSURV = 1) after an interrupt.
Current calculated optimal readout counter value in AUTO mode (SAUTO = 1).
SSURV WRITE 0, the controller stops after completion of the current measurement cycle.
1, continuous measurements are taken and an interrupt is issued if the readout counter drifts beyond the
threshold value.
SAUTO WRITE
0, readout counter (PHOF<3:0>) is not automatically updated.
1, continuously starts measurement cycles and updates the readout counter according to the
measurement.
NOTE: SSURV (Reg. 8, Bit 7) must be set to 1 and the SYNC IRQ (Reg. 1, Bit 2) must be set to 0 for AUTO
mode.
SFLT<3:0> WRITE 0x0, average filter length, FIFOSTAT = FIFOSTAT + Delta FIFOSTAT/2 ^ SFLT<3:0>; values greater than 12
(0x0C) are clipped to 12.
STRH<0> WRITE 0, if FIFOSTAT<2:0> = 0 or 7, a sync interrupt is generated.
1, if FIFOSTAT<2:0> = 0, 1, 6 or 7, a sync interrupt is generated.
CROSS CONTROLLER (CROS_CNT) REGISTERS (REG. 10, REG. 11)
ADDR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0A CROS_CNT1 – – UPDEL<5> UPDEL<4> UPDEL<3> UPDEL<2> UPDEL<1> UPDEL<0>
0x0B CROS_CNT2 – – DNDEL<5> DNDEL<4> DNDEL<3> DNDEL<2> DNDEL<1> DNDEL<0>
Table 15. Cross Controller Register Description
Bit Name Read/Write Description
UPDEL<5:0> WRITE 0x00, move the differential output stage switching point up, set to 0 if DNDEL is non-zero.
DNDEL<5:0> WRITE 0x00, move the differential output stage switching point down, set to 0 if UPDEL is non-zero.
AD9734/AD9735/AD9736
Rev. A | Page 33 of 72
ANALOG CONTROL (ANA_CNT) REGISTERS (REG. 14, REG. 15)
ADDR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0E ANA_CNT1 MSEL<1> MSEL<0> – – – TRMBG<2> TRMBG<1> TRMBG<0>
0x0F ANA_CNT2 HDRM<7> HDRM<6> HDRM<5> HDRM<4> HDRM<3> HDRM<2> HDRM<1> HDRM<0>
Table 16. Analog Control Register Bit Descriptions
Bit Name Read/Write Description
MSEL<1:0> WRITE 00, mirror roll off frequency control = bypass.
01, mirror roll off frequency control = narrowest bandwidth.
10, mirror roll off frequency control = medium bandwidth.
11, mirror roll off frequency control = widest bandwidth.
NOTE: See the plot in the Analog Control Registers section.
TRMBG<2:0> WRITE 000, band gap temperature characteristic trim.
NOTE: See the plot in the Analog Control Registers section.
HDRM<7:0> WRITE 0xCA, output stack headroom control.
HDRM<7:4> set reference offset from AVDD33 (VCAS centering).
HDRM<3:0> set overdrive (current density) trim (temperature tracking).
Note: Set to 0xCA for optimum performance.
BUILT-IN SELF TEST CONTROL (BIST_CNT) REGISTERS (REG. 17, REG. 18, REG. 19, REG. 20, REG. 21)
ADDR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x11 BIST_CNT SEL<1> SEL<0> SIG_READ – – LVDS_EN SYNC_EN CLEAR
0x12 BIST<7:0> BIST<7> BIST<6> BIST<5> BIST<4> BIST<3> BIST<2> BIST<1> BIST<0>
0x13 BIST<15:8> BIST<15> BIST<14> BIST<13> BIST<12> BIST<11> BIST<10> BIST<9> BIST<8>
0x14 BIST<23:16> BIST<23> BIST<22> BIST<21> BIST<20> BIST<19> BIST<18> BIST<17> BIST<16>
0x15 BIST<31:24> BIST<31> BIST<30> BIST<29> BIST<28> BIST<27> BIST<26> BIST<25> BIST<24>
Table 17. BIST Control Register Bit Descriptions
Bit Name Read/Write Description
SEL<1:0> WRITE 00, write result of the LVDS Phase 1 BIST to BIST<31:0>.
01, write result of the LVDS Phase 2 BIST to BIST<31:0>.
10, write result of the SYNC Phase 1 BIST to BIST<31:0>.
11, write result of the SYNC Phase 2 BIST to BIST<31:0>.
SIG_READ WRITE 0, no action.
1, enable BIST signature readback.
LVDS_EN WRITE 0, no action.
1, enable LVDS BIST.
SYNC_EN WRITE 0, no action.
1, enable SYNC BIST.
CLEAR WRITE 0, no action.
1, clear all BIST registers.
BIST<31:0> READ Results of the built-in self test.
AD9734/AD9735/AD9736
Rev. A | Page 34 of 72
CONTROLLER CLOCK PREDIVIDER (CCLK_DIV) READING REGISTER (REG. 22)
ADR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x16 CCLK_DIV RESERVED RESERVED RESERVED RESERVED CCD<3> CCD<2> CCD<1> CCD<0>
Table 18. Controller Clock Predivider Register Bit Descriptions
Bit Name Read/Write Description
CCD<3:0> WRITE 0x0, controller clock = DACCLK/16.
0x1, controller clock = DACCLK/32.
0x2, controller clock = DACCLK/64 …
0xF, controller clock = DACCLK/524288.
NOTE: The 100 MHz to 1.2 GHz DACCLK must be divided to less than 10 MHz for correct operation. CCD<3:0>
must be programmed to divide the DACCLK so that this relationship is not violated. Controller clock =
DACCLK/(2 ^ ( CCD<3:0> + 4 )).
AD9734/AD9735/AD9736
Rev. A | Page 35 of 72
THEORY OF OPERATION
The AD9736, AD9735, and AD9734 are 14-bit, 12-bit, and
10-bit DACs that run at an update rate up to 1.2 GSPS. Input
data can be accepted up to the full 1.2 GSPS rate, or a 2×
interpolation filter can be enabled (2× mode) allowing full
speed operation with a 600 MSPS input data rate. The DATA
and DATACLK_IN inputs are parallel LVDS, meeting the IEEE
reduced swing LVDS specifications with the exception of input
hysteresis. The DATACLK_IN input runs at one-half the input
DATA rate in a double data rate (DDR) format. Each edge of
DATACLK_IN transfers DATA into the AD9736, as shown in
Figure 79.
The DACCLK−/DACCLK+ inputs (Pin E1 and Pin F1) directly
drive the DAC core to minimize clock jitter. The DACCLK
signal is also divided by 2 (1× and 2× mode), then output as the
DATACLK_OUT. The DATACLK_OUT signal clocks the data
source. The DAC expects DDR LVDS data (DB<13:0>) aligned
with the DDR input clock (DATACLK_IN) from a circuit simi-
lar to the one shown in Figure 96. Table 19 shows the clock
relationships.
Table 19. AD973x Clock Relationship
MODE DACCLK DATACLK_OUT DATACLK_IN DATA
1× 1.2 GHz 600 MHz 600 MHz 1.2 GSPS
2× 1.2 GHz 600 MHz 300 MHz 600 MSPS
Maintaining correct alignment of data and clock is a common
challenge with high speed DACs, complicated by changes in
temperature and other operating conditions. Using the
DATACLK_OUT signal to generate the data allows most of the
internal process, temperature, and voltage delay variation to be
cancelled. The AD973x further simplifies this high speed data
capture problem with two adaptive closed-loop timing
controllers.
One timing controller manages the LVDS data and data clock
alignment (LVDS controller), and the other manages the LVDS
data and DACCLK alignment (sync controller).
The LVDS controller locates the data transitions and delays the
DATACLK_IN so that its transition is in the center of the valid
data window. The sync controller manages the FIFO that moves
data from the LVDS DATACLK_IN domain to the DACCLK
domain.
Both controllers can operate in manual mode under external
processor control, in surveillance mode where error conditions
generate external interrupts, or in automatic mode where errors
are automatically corrected.
The LVDS and sync controllers include moving average filtering
for noise immunity and variable thresholds to control activity.
Normally, the controllers are set to run in automatic mode,
making any necessary adjustments without dropping or dupli-
cating samples sent to the DAC. Both controllers require initial
calibration prior to entering automatic update mode.
The AD973x analog output changes 35 DACCLK cycles after
the input data changes in 1× mode with the FIFO disabled. The
FIFO adds up to eight additional cycles of delay. This delay is
read from the SPI port. Internal clock delay variation is less
than a single DACCLK cycle at 1.2 GHz (833 ps).
Stopping the AD973x DATACLK_IN while the DACCLK is still
running can lead to unpredictable output signals. This occurs
because the internal digital signal path is interleaved. The last
two samples clocked into the DAC continue to be clocked out
by DACCLK even after DATACLK_IN has stopped. The result-
ing output signal is at a frequency of one-half fDAC, and the
amplitude depends on the difference between the last two
samples.
Control of the AD973x functions is via the serially programmed
registers listed in Table 9. Optionally, a limited number of func-
tions can be directly set by external pins in pin mode.
AD9734/AD9735/AD9736
Rev. A | Page 36 of 72
SERIAL PERIPHERAL INTERFACE
The AD973x serial port is a flexible, synchronous serial
communications port, allowing easy interface to many
industry-standard microcontrollers and microprocessors. The
serial I/O is compatible with most synchronous transfer
formats, including both the Motorola SPI® and Intel® SSR
protocols. The interface allows read/write access to all registers
that configure the AD973x. Single- or multiple-byte transfers
are supported, as well as most significant bit first (MSB-first) or
least significant bit first (LSB-first) transfer formats. The
AD973x serial interface port can be configured as a single pin
I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO).
SDO (PIN G14)
SDIO (PIN F14)
S
CLK (PIN G13)
CSB (PIN F13)
AD973x
SPI PORT
04862-066
Figure 68. AD973x SPI Port
The AD973x can optionally be configured via external pins
rather than the serial interface. When the PIN_MODE input
(Pin L1) is high, the serial interface is disabled and its pins are
reassigned for direct control of the DAC. Specific functionality
is described in the Pin Mode Operation section.
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the
AD973x. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD973x, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD973x serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write, the number of bytes in
the data transfer, and the starting register address for the first
byte of the data transfer. The first eight SCLK rising edges of
each communication cycle are used to write the instruction byte
into the AD973x.
The remaining SCLK edges are for Phase 2 of the communica-
tion cycle. Phase 2 is the actual data transfer between the
AD973x and the system controller. Phase 2 of the communica-
tion cycle is a transfer of 1, 2, 3, or 4 data bytes as determined
by the instruction byte. Using one multibyte transfer is the
preferred method. Single-byte data transfers are useful to
reduce CPU overhead when register access requires one byte
only. Registers change immediately upon writing to the last bit
of each transfer byte.
CSB (Chip Select) can be raised after each sequence of 8 bits
(except the last byte) to stall the bus. The serial transfer resumes
when CSB is lowered. Stalling on nonbyte boundaries resets
the SPI.
SHORT INSTRUCTION MODE (8-BIT INSTRUCTION)
The short instruction byte is shown in the following table:
MSB LSB
I7 I6 I5 I4 I3 I2 I1 I0
R/W N1 N0 A4 A3 A2 A1 A0
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic high indicates read operation. Logic 0 indicates a write
operation. N1, N0, Bit 6, and Bit 5 of the instruction byte
determine the number of bytes to be transferred during the data
transfer cycle. The bit decodes are shown in Table 20.
A4, A3, A2, A1, A0, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte, determine which register is accessed during
the data transfer portion of the communications cycle. For
multibyte transfers, this address is the starting byte address. The
remaining register addresses are generated by the AD973x,
based on the LSBFIRST bit (Reg. 0, Bit 6).
Table 20. Byte Transfer Count
N1 N2 Description
0 0 Transfer 1 byte
0 1 Transfer 2 bytes
1 0 Transfer 3 bytes
1 1 Transfer 4 bytes
LONG INSTRUCTION MODE (16-BIT INSTRUCTION)
The long instruction bytes are shown in the following table:
MSB LSB
I15 I14 I13 I12 I11 I10 I9 I8
R/W N1 N0 A12 A11 A10 A9 A8
I7 I6 I5 I4 I3 I2 I1 I0
A7 A6 A5 A4 A3 A2 A1 A0
If LONG_INS = 1 (Reg. 0, Bit 4), the instruction byte is
extended to 2 bytes where the second byte provides an
additional 8 bits of address information. Address 0x00 to
Address 0x1F are equivalent in short and long instruction
modes. The AD973x does not use any addresses greater than 31
(0x1F), so always set LONG_INS = 0.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD973x and to run the internal state machines. The maximum
frequency of SCLK is 20 MHz. All data input to the AD973x is
registered on the rising edge of SCLK. All data is driven out of
the AD973x on the rising edge of SCLK.
AD9734/AD9735/AD9736
Rev. A | Page 37 of 72
CSB—Chip Select
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should stay
low during the entire communication cycle.
SDIO—Serial Data I/O
Data is always written into the AD973x on this pin. However,
this pin can be used as a bidirectional data line. The configu-
ration of this pin is controlled by SDIO_DIR at Reg. 0, Bit 7.
The default is Logic 0, which configures the SDIO pin as
unidirectional.
SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the
AD973x operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
MSB/LSB TRANSFERS
The AD973x serial port can support both MSB-first or LSB-first
data formats. This functionality is controlled by LSBFIRST at
Reg. 0, Bit 6. The default is MSB first (LSBFIRST = 0).
When LSBFIRST = 0 (MSB first), the instruction and data bytes
must be written from the most significant bit to the least
significant bit. Multibyte data transfers in MSB-first format start
with an instruction byte that includes the register address of the
most significant data byte. Subsequent data bytes should follow
in order from high address to low address. In MSB-first mode,
the serial port internal byte address generator decrements for
each data byte of the multibyte communication cycle.
When LSBFIRST = 1 (LSB first), the instruction and data bytes
must be written from least significant bit to most significant bit.
Multibyte data transfers in LSB-first format start with an
instruction byte that includes the register address of the least
significant data byte followed by multiple data bytes. The serial
port internal byte address generator increments for each byte of
the multibyte communication cycle.
The AD973x serial port controller data address decrements
from the data address written toward 0x00 for multibyte I/O
operations if the MSB-first mode is active. The serial port
controller address increments from the data address written
toward 0x1F for multibyte I/O operations if the LSB-first mode
is active.
NOTES ON SERIAL PORT OPERATION
The AD973x serial port configuration is controlled by Reg. 0,
Bit 4, Bit 5, Bit 6, and Bit 7. Note that the configuration changes
immediately upon writing to the last bit of the register.
For multibyte transfers, writing to this register can occur during
the middle of the communication cycle. Care must be taken to
compensate for this new configuration for the remaining bytes
of the current communication cycle. The same considerations
apply to setting the software reset, RESET (Reg. 0, Bit 5). All
registers are set to their default values except Reg. 0 and Reg. 4,
which remain unchanged.
Use of only single-byte transfers when changing serial port
configurations or initiating a software reset is highly
recommended. In the event of unexpected programming
sequences, the AD973x SPI can become inaccessible. For
example, if user code inadvertently changes the LONG_INS bit
or the LSBFIRST bit, the following bits experience unexpected
results. The SPI can be returned to a known state by writing an
incomplete byte (1 to 7 bits) of all 0s followed by 3 bytes of
0x00. This returns to MSB-first short instructions
(Reg. 0 = 0x00), so the device can be reinitialized.
R/W N1 N0 A4 A3 A2 A1 A0 D7
N
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
04862-067
Figure 69. Serial Register Interface Timing, MSB-First Write
R/W N1 N0 A4 A3 A2 A1 A0
D7
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
04862-068
D7
Figure 70. Serial Register Interface Timing, MSB-First Read
A0 A1 A2 A3 A4 N0 N1 R/W D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
04862-069
Figure 71. Serial Register Interface Timing, LSB-First Write
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
A0 A1 A2 A3 A4 N0 N1 R/W D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
04862-070
D0
D0
Figure 72. Serial Register Interface Timing, LSB-First Read
AD9734/AD9735/AD9736
Rev. A | Page 38 of 72
INSTRUCTION BIT 6INSTRUCTION BIT 7
CSB
SCLK
SDIO
t
DS
t
DS
t
DH
t
PWH
t
PWL
t
SCLK
04862-071
Figure 73. Timing Diagram for SPI Register Write
I1 I0 D7 D6 D5
t
DV
t
DNV
CSB
S
CLK
S
DIO
04862-072
Figure 74. Timing Diagram for SPI Register Read
After the last instruction bit is written to the SDIO pin, the
driving signal must be set to a high impedance in time for the
bus to turn around. The serial output data from the AD973x is
enabled by the falling edge of SCLK. This causes the first output
data bit to be shorter than the remaining data bits, as shown in
Figure 74.
To assure proper reading of data, read the SDIO or SDO pin
prior to changing the SCLK from low to high. Due to the more
complex multibyte protocol, multiple AD973x devices cannot
be daisy-chained on the SPI bus. Multiple DACs should be
controlled by independent CSB signals.
PIN MODE OPERATION
When the PIN_MODE input (Pin L1) is set high, the SPI port is
disabled. The SPI port pins are remapped, as shown in Table 21.
The function of these pins is described in Table 22. The remain-
ing PIN_MODE register settings are shown in Table 9.
Table 21. SPI_MODE vs. PIN_MODE Inputs
Pin Number PIN_MODE = 0 PIN_MODE = 1
E13 IRQ UNSIGNED
F13 CSB 2×
G13 SCLK FSC0
E14 RESET PD
F14 SDIO FIFO
G14 SDO FSC1
Table 22. PIN_MODE Input Functions
Mnemonic Function
UNSIGNED 0, twos complement input data format
1, unsigned input data format
2× 0, interpolation disabled
1, interpolation = 2× enabled
FSC1, FSC0 00, sleep mode
01, 10 mA full-scale output current
10, 20 mA full-scale output current
11, 30 mA full-scale output current
PD 0, chip enabled
1, chip in power-down state
FIFO 0, input FIFO disabled
1, input FIFO enabled
Care must be taken when using PIN_MODE because only the
control bits shown in Table 22 can be changed. If the remaining
register default values are not suitable for the desired operation,
PIN_MODE cannot be used. If the FIFO is enabled, the
controller clock must be less than 10 MHz. This limits the DAC
clock to 160 MHz.
RESET OPERATION
The RESET pin forces all SPI register contents to their default
values (see Table 9), which places the DAC in a known state.
The software reset bit forces all SPI register contents, except
Reg. 0 and Reg. 4, to their default values.
The internal reset signal is derived from a logical OR operation
on the RESET pin state and from the software reset state. This
internal reset signal drives all SPI registers to their default
values, except Reg. 0 and Reg. 4, which are unaffected. The data
registers are not affected by either reset.
The software reset is asserted by writing 1 to Reg. 0, Bit 5. It
may be cleared on the next SPI write cycle or a later write cycle.
PROGRAMMING SEQUENCE
The AD973x registers should be programmed in this order:
1. Reset hardware.
2. Make changes to SPI port configuration, if necessary.
3. Input format, if unsigned.
4. Interpolation, if in 2× mode.
5. Calibrate and set the LVDS controller.
6. Enable the FIFO.
7. Calibrate and set the sync controller.
Step 1 through Step 4 are required, while Step 5 through Step 7
are optional. The LVDS controller can help assure proper data
reception in the DAC with changes in temperature and voltage.
The sync controller manages the FIFO to assure proper transfer
of the received data to the DAC core with changes in
temperature and voltage. The DAC is intended to operate with
both controllers active unless data and clock alignment is
managed externally.
AD9734/AD9735/AD9736
Rev. A | Page 39 of 72
INTERPOLATION FILTER
In 2× mode, the input data is interpolated by a factor of 2 so
that it aligns with the DAC update rate. The interpolation filter
is a hard-coded, 55-tap, symmetric FIR with a 0.001 dB pass-
band flatness and a stop-band attenuation of about 90 dB. The
transition band runs from 20% of fDAC to 30% of fDAC. The FIR
response is shown in Figure 75 where the frequency axis is
normalized to fDAC. Figure 76 shows the pass-band flatness and
Table 23 shows the 16-bit filter coefficients.
Table 23. FIR Interpolation Filter Coefficients
Coefficient Number Coefficient Number Tap Weight
1 55 −7
2 54 0
3 53 +24
4 52 0
5 51 −62
6 50 0
7 49 +135
8 48 0
9 47 −263
10 46 0
11 45 +471
12 44 0
13 43 −793
14 42 0
15 41 +1273
16 40 0
17 39 −1976
18 38 0
19 37 +3012
20 36 0
21 35 −4603
22 34 0
23 33 +7321
24 32 0
25 31 −13270
26 30 0
27 29 +41505
28 +65535
04862-073
FREQUENCY NORMALIZED TO
fDAC
0.500 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
MAGNITUDE (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Figure 75. Interpolation Filter Response
04862-074
FREQUENCY NORMALIZED TO
fDAC
0.250 0.100.05 0.15 0.20
MAGNITUDE (dB)
0.10
0.06
0.08
0.02
–0.02
–0.06
0.04
0
–0.04
–0.08
–0.10
Figure 76. Interpolation Filter Pass-Band Flatness
DATA INTERFACE CONTROLLERS
Two internal controllers are utilized in the operation of the
AD973x. The first controller helps maintain optimum LVDS
data sampling; the second controller helps maintain optimum
synchronization between the DACCLK and the incoming data.
The LVDS controller is responsible for optimizing the sampling
of the data from the LVDS bus (DB13:0), while the sync
controller resolves timing problems between the DAC_CLK
(CLK+, CLK−) and the DATACLK. A block diagram of these
controllers is shown in Figure 77.
DATACLK_OUT
DATACLK
DATACLK_IN
FIFO DAC
LVDS
SAMPLE
LOGIC
CLK
CONTROL
LVDS
CONTROLLER
DB<13:0>
DATA
SOURCE
i.e., FPGA
SYNC
LOGIC
SYNC
CONTROLLER
04862-075
Figure 77. Data Controllers
The controllers are clocked with a divided-down version of the
DAC_CLK. The divide ratio is set utilizing the controller clock
predivider bits (CCD<3:0>) located at Reg. 22, Bits 3:0 to
generate the controller clock as follows:
Controller Clock = DAC_CLK/(2(CCD<3:0> + 4))
Note that the controller clock cannot exceed 10 MHz for correct
operation. Until CCD<3:0> is properly programmed to meet
this requirement, the DAC output may not be stable. This
means the FIFO cannot be enabled in PIN_MODE unless the
DACCLK is less than 160 MHz.
AD9734/AD9735/AD9736
Rev. A | Page 40 of 72
The LVDS and sync controllers are independently operated in
three modes via SPI port Reg. 6 and Reg. 8:
• Manual mode
• Surveillance mode
• Auto mode
In manual mode, all of the timing measurements and updates
are externally controlled via the SPI.
In surveillance mode, each controller takes measurements and
calculates a new optimal value continuously. The result of the
measurement is passed through an averaging filter before
evaluating the results for increased noise immunity. The filtered
result is compared to a threshold value set via Reg. 6 and Reg. 8
of the SPI port. If the error is greater than the threshold, an
interrupt is triggered and the controller stops.
Reg. 1 of the SPI port controls the interrupts with Bit 3 and Bit 2
enabling the respective interrupts and Bit 7 and Bit 6 indicating
the respective controller interrupt. If an interrupt is enabled, it
also activates the AD973x IRQ pin. To clear an interrupt, the
interrupt enable bit of the respective controller must be set to 0
for at least 1 controller clock cycle (controller clock <10 MHz).
Auto mode is almost identical to surveillance mode. Instead
of triggering an interrupt and stopping the controller, the
controller automatically updates its settings to the newly
calculated optimal value and continues to run.
LVDS SAMPLE LOGIC
A simplified diagram of the AD973x LVDS data sampling
engine is shown in Figure 78 and the timing diagram is shown
in Figure 79.
The incoming LVDS data is latched by the data sampling signal
(DSS), which is derived from DATACLK_IN. The LVDS
controller delays DATACLK_IN to create the data sampling
signal (DSS), which is adjusted to sample the LVDS data in the
center of the valid data window. The skew between the
DATACLK_IN and the LVDS data bits (DB<13:0>) must be
minimal for proper operation. Therefore, it is recommended
that the DATACLK_IN be generated in the same manner as the
LVDS data bits (DB<13:0>) with the same driver and data lines
(that is, it should just be another LVDS data bit running a
constant 01010101… sequence, as shown in Figure 96).
If the DATACLK_IN signal is stopped, the DACCLK continues
to generate an output signal based on the last two values
clocked into the registers that drive D1 and D2, as shown in
Figure 78. If these two registers are not equal, a large output at a
frequency of one-half fDAC can be generated at the DAC output.
DB<13:0>
DATACLK_IN LVDS
RX
DELAYED
CLOCK
SIGNAL
CLOCK
SAMPLING
SIGNAL
CHECK
D1
D2
DATA SAMPLING
SIGNAL
LVDS
RX
MSD<3:0>
DELAY
MSD<3:0>
DELAY
FF
SD<3:0>
SAMPLE DELAY
FF
FF
DBL
DBU
04862-076
Figure 78. Internal LVDS Data Sampling Logic
SAMPLE
DELAY
PROP DELAY
TO LATCH
PROP DELAY
TO LATCH
CLK TO DB SKEW
DB13:0
D1
D2
DATACLK_IN
DATA SAMPLING
SIGNAL (DSS)
04862-077
Figure 79. Internal LVDS Data Sampling Logic Timing
LVDS SAMPLE LOGIC CALIBRATION
The internal DSS delay must be calibrated to optimize the data
sample timing. Once calibrated, the AD973x generates an IRQ
or automatically corrects its timing if temperature or voltage
variations change the timing too much. This calibration is done
using the delayed clock sampling signal (CSS) to sample the
delayed clock signal (DCS). The LVDS sampling logic finds the
edges of the DATACLK_IN signal and, from this measurement,
the center of the valid data window is located.
The internal delay line that derives the delayed DSS from
DATACLK_IN is controlled by SD3:0 (Reg. 5, Bits 7:4), while
the DCS is controlled by MSD3:0 (Reg. 4, Bits 7:4), and the CSS
is controlled by MHD3:0 (Reg. 4, Bits 3:0).
DATACLK_IN transitions must be time aligned with the LVDS
data (DB<13:0>) transitions. This allows the CSS, derived from
the DATACLK_IN, to find the valid data window of DB<13:0>
by locating the DATACLK_IN edges. The latching (rising) edge
of CSS is initially placed using Bits SD<3:0> and can then be
shifted to the left using MSD<3:0> and to the right using
MHD<3:0>. When CSS samples the DCS and the result is 1
(which can be read back via the check bit at Reg. 5, Bit 0), the
sampling occurs in the correct data cycle.
AD9734/AD9735/AD9736
Rev. A | Page 41 of 72
To find the leading edge of the data cycle, increment the
measured setup delay until the check bit goes low. To find the
trailing edge, increment the measured hold delay (MHD) until
check goes low. Always set MHD = 0 when incrementing MSD
and vice versa.
The incremental units of SD, MSD, and MHD are in units of real
time, not fractions of a clock cycle. The nominal step size is 80 ps.
OPERATING THE LVDS CONTROLLER IN
MANUAL MODE VIA THE SPI PORT
The manual operation of the LVDS controller allows the user to
step through both the setup and hold delays to calculate the
optimal sampling delay (that is, the center of the data eye).
With SD<3:0> and MHD<3:0> set to 0, increment the setup time
delay (MSD<3:0>, Reg. 4, Bits 7:4) until the check bit (Reg. 5,
Bit 0) goes low and record this value. This locates the leading
DATACLK_IN (and data) transition, as shown in Figure 80.
With SD<3:0> and MSD<3:0> set to 0, increment the hold time
delay (MHD<3:0>, Reg. 4, Bits 3:0) until the check bit (Reg. 5,
Bit 0) goes low and record this value. This locates the trailing
DATACLK_IN (and DB<13:0>) transition, as shown in Figure
81.
Once both DATACLK_IN edges are located, the sample delay
(SD<3:0>, Reg. 5, Bits 7:4) must be updated by
Sample Delay = (MHD − MSD)/2
After updating SD<3:0>, verify that the sampling signal is in the
middle of the valid data window by adjusting both MHD and
MSD with the new sample delay until the check bit goes low.
The new MHD and MSD values should be equal to or within
one unit delay if SD<3:0> was set correctly.
MHD and MSD may not be equal to or within one unit delay if
the external clock jitter and noise exceeds the internal delay
resolution. Differences of 2, 3, or more are possible and can
require more filtering to provide stable operation.
The sample delay calibration should be performed prior to
enabling surveillance mode or auto mode.
SETUP TIME (
t
S
)
SAMPLE DELAY
MSD<3:0> = 0 1 2 3 4 5
CSS SAMPLE DCS
CHECK = 1
SD<3:0>
DB<13:0>
DATACLK_IN
CSS WITH
MHD<3:0> = 0
DSC DELAYED
BY MSD<3:0>
04862-078
Figure 80. Setup Delay Measurement
SETUP TIME (
t
S) HOLD TIME (
t
H)
SAMPLE DELAY CSS SAMPLE DCS
CHECK = 1 1 1 1 1 0 CHECK = 1
SD<3:0>
0
4862-079
MSD<3:0> = 0 1 2 3 4 5
DB<13:0>
DATACLK_IN
CSS WITH
MHD<3:0> = 0
DSC DELAYED
BY MSD<3:0> = 0
Figure 81. Hold Delay Measurement
OPERATING THE LVDS CONTROLLER IN
SURVEILLANCE AND AUTO MODE
In surveillance mode, the controller searches for the edges of
the data eye in the same manner as in the manual mode of
operation and triggers an interrupt if the clock sampling signal
(CSS) has moved more than the threshold value set by
LTRH<1:0> (Reg. 6, Bits 1:0).
There is an internal filter that averages the setup and hold time
measurements to filter out noise and glitches on the clock lines.
Average Value = (MHD – MSD)/2
New Average = Average Value + ( Average/2 ^ LFLT<3:0>)
If an accumulating error in the average value causes it to exceed
the threshold value (LTHR<1:0>), an interrupt is issued.
The maximum allowable value for LFLT<3:0> is 12. If
LFLT<3:0> is too small, clock jitter and noise can cause erratic
behavior. In most cases, LFLT can be set to the maximum value.
In surveillance mode, the ideal sampling point should first be
found using manual mode and then applied to the sample delay
registers. Set the threshold and filter values depending on how
far the CSS signal is allowed to drift before an interrupt occurs.
Then, set the surveillance bit high (Reg. 6, Bit 7) and monitor
the interrupt signal either via the SPI port (Reg. 1, Bit 7) or the
IRQ pin.
In auto mode, follow the same steps to set up the sample delay,
threshold, and filter length. To run the controller in auto mode,
both the LAUTO (Reg. 6, Bit 6) and LSURV (Reg. 6, Bit 7) bits
need to be set to 1. In auto mode, the LVDS interrupt should be
set low (Reg. 1, Bit 3) to allow the sample delay to be automati-
cally updated if the threshold value is exceeded.
AD9734/AD9735/AD9736
Rev. A | Page 42 of 72
SYNC LOGIC AND CONTROLLER
A FIFO structure is utilized to synchronize the data transfer
between the DACCLK and the DATACLK_IN clock domains.
The sync controller writes data from DB<13:0> into an 8-word
memory register based on a cyclic write counter clocked by the
DSS, which is a delayed version of DACCLK_IN. The data is
read out of the memory based on a second cyclic read counter
clocked by DACCLK. The 8-word FIFO shown in Figure 82
provides sufficient margin to maintain proper timing under
most conditions. The sync logic is designed to prevent the read
and write pointers from crossing. If the timing drifts far enough
to require an update of the phase offset (PHOF<1:0>), two
samples are duplicated or dropped. Figure 83 shows the timing
diagram for the sync logic.
8 WORD
MEMORY
READ
COUNTER
PHOF<1:0>
DACCLK
FIFOSTAT<2:0>
DSS
M0
M7
ZD
DAC<13:0>
ADDER
WRITE
COUNTER
FF
DAC<13:0>
04862-080
Figure 82. Sync Logic Block Diagram
SYNC LOGIC AND CONTROLLER OPERATION
The relationship between the readout pointer and the write
pointer initially is unknown because the startup relationship
between DACCLK and DATACLK_IN is unknown. The sync
logic measures the relative phase between the two counters with
the zero detect block and the flip-flop in Figure 82. The relative
phase is returned in FIFOSTAT<2:0> (Reg. 7, Bits 6:4), and sync
logic errors are indicated by FIFOSTAT<3> (Reg. 7, Bit 7). If
FIFOSTAT<2:0> returns a value of 0 or 7, the memory is
sampling in a critical state (read and write pointers are close to
crossing).
If the FIFOSTAT<2:0> returns a value of 3 or 4, the memory is
sampling at the optimal state (read and write pointers are
farthest apart). If FIFOSTAT<2:0> returns a critical value, the
pointer can be adjusted with the phase offset PHOF<1:0> (Reg.
7, Bits 1:0). Due to the architecture of the FIFO, the phase offset
can only adjust the read pointer in steps of 2.
OPERATION IN MANUAL MODE
To start operating the DAC in manual mode, allow DACCLK
and DATACLK_IN to stabilize, then enable FIFO mode (Reg. 0,
Bit 2). Read FIFOSTAT<2:0> (Reg. 7, Bits 6:4) to determine if
adjustment is needed. For example, if FIFOSTAT<2:0> = 6, the
timing is not yet critical, but it is not optimal.
To return to an optimal state (FIFOSTAT<2:0> = 4), the
PHOF<1:0> (Reg. 7, Bits 1:0) needs to be set to 1. Setting
PHOF<1:0> = 1 effectively increments the read pointer by 2.
This causes the write pointer value to be captured two clocks
later, decreasing FIFOSTAT<2:0> from 6 to 4.
OPERATION IN SURVEILLANCE AND AUTO MODES
Once FIFOSTAT<2:0> is manually placed in an optimal state,
the AD973x sync logic can run in surveillance or auto mode. To
start, turn on surveillance mode by setting SSURV = 1 (Reg. 8,
Bit 7), then enable the sync interrupt (Reg. 1, Bit 2).
If STRH<0> = 0 (Reg. 8, Bit 0), an interrupt occurs if
FIFOSTAT<2:0> = 0 or 7. If STRH<0> = 1 (Reg. 8, Bit 0), an
interrupt occurs if FIFOSTAT<2:0> = 0, 1, 6, or 7. The interrupt
is read at Reg. 1, Bit 6 at the AD973x IRQ pin.
To enter auto mode, complete the preceding steps then set
SAUTO = 1 (Reg. 8, Bit 6). Next, set the sync interrupt = 0
(Reg. 1, Bit 2), to allow the phase offset (PHOF<1:0>) to be
automatically updated if FIFOSTAT<2:0> violates the threshold
value. The FIFOSTAT signal is filtered to improve noise
immunity and reduce unnecessary phase offset updates. The
filter operates with the following algorithm:
FIFOSTAT = FIFOSTAT + ΔFIFOSTAT/2 ^ SFLT<3:0>
where:
0 ≤ SFLT<3:0> ≤ 12
Values greater than 12 are set to 12. If SFLT<3:0> is too small,
clock jitter and noise can cause erratic behavior. Normally, SFLT
can be set to the maximum value.
FIFO BYPASS
When the FIFO_MODE bit (Reg. 1, Bit 2) is set to 0, the FIFO
is bypassed with a mux. When the FIFO is enabled, the pipeline
delay through the AD973x increases by the delta between the
FIFO read pointer and write pointer plus 4 more clock periods.
AD9734/AD9735/AD9736
Rev. A | Page 43 of 72
D
INTERNAL DELAY
DACCLK
DATACLK_OU
T
DATACLK_IN
DATA_IN A
A
B
B
01
2 3456701 2345670
45670 12 34 1 2345670
C
C
D
D
E
E
F
F
G
G
H
H
I
I
J
J
K
K
L
L
M
ABC D E F G H IJKLM
M
N
N
I
A
O
OQ
P
P
QR
DSS1
DSS2
D2
WRITE_PTR1
SAFE ZONE
DATA 'A' CAN BE
SAFELY READ FROM
THE FIFO IN THE
SAFE ZONE. IN THE
ERROR ZONE, THE
POINTERS MAY
BRIEFLY OVERLAP
DUE TO CLOCK JITTER
OR NOISE.
FIFOSTAT IS SET
EQUAL TO THE
WRITE POINTER
EACH TIME THE
READ POINTER
CHANGES FROM
7 TO 0.
ERROR ZONE
M0
M1 B
C
E
F
G
444
H
J
M2
M3
M4
M5
M6
M7
READ_PTR1
FIFOSTAT
DAC_DATA
D1
EXTERNAL DELAY
SAMPLE_HOLD
SAMPLE_SETUP
SAMPLE_DELAY
04862-081
Figure 83. Sync Logic Timing Diagram
AD9734/AD9735/AD9736
Rev. A | Page 44 of 72
DIGITAL BUILT-IN SELF TEST (BIST)
OVERVIEW
The AD973x includes an internal signature generator that
processes incoming data to create unique signatures. These
signatures are read back from the SPI port, allowing verification
of correct data transfer into the AD973x. BIST vectors provided
on the AD973x-EB evaluation board CD check the full width
data input or individual bits for PCB debug, utilizing the
procedure in the AD973X BIST Procedure section. Alterna-
tively, any vector can be used provided the expected signature is
calculated in advance.
The MATLAB® routine, in the Generating Expected Signatures
section, calculates the expected signature. BIST verifies correct
data transfer because not all errors are always evident on a
spectrum analyzer. There are four BIST signature generators
that can be read back using Reg. 18 to Reg. 21, based on the
setting of the BIST selection bits (Reg. 17, Bits 7:6), as shown in
Table 24. The BIST signature returned from the AD973x
depends on the digital input during the test. Because the filters
in the DAC have memory, it is important to put the correct idle
value on the DATA input to flush the memory prior to reading
the BIST signature.
Placing the idle value on the data input also allows the BIST to
be set up while the DAC clock is running. The idle value should
be all 0s in unsigned mode (0x0000) and all 0s except for the
MSB in twos complement mode (0x2000).
The BIST consists of two stages; the first stage is after the LVDS
receiver and the second stage is after the FIFO. The first BIST
stage verifies correct sampling of the data from the LVDS bus
while the second BIST stage verifies correct synchronization
between the DAC_CLK domain and the DATACLK_IN
domain. The BIST vector is generated using 32-bit LFSR
signature logic. Because the internal architecture is a 2-bus
parallel system, there are two 32-bit LFSR signature logic blocks
on both the LVDS and SYNC blocks. Figure 84 shows where the
LVDS and SYNC phases are located.
Table 24. BIST Selection Bits
Bit SEL<1> SEL<0>
LVDS Phase 1 0 0
LVDS Phase 2 0 1
SYNC Phase 1 1 0
SYNC Phase 2 1 1
LVDS
RX
DB<13:0>
DATACLK_IN
SYNC LOGIC
FIFO 2x
D1
D2
DAC
LVDS
BIST
PH1
(RISE)
LVDS
BIST
PH2
(FALL)
SYNC
BIST
PH1
(RISE)
SYNC
BIST
PH2
(FALL)
SPI PORT
04862-082
Figure 84. Block Diagram Showing LVDS and SYNC Phase 1 and SYNC Phase 2
AD9734/AD9735/AD9736
Rev. A | Page 45 of 72
AD973x BIST PROCEDURE
1. Set RESET pin = 1.
2. Set input DATA = 0x0000 for signed (0x2000 for
unsigned).
3. Enable DATACLK_IN if it is not already running.
4. Run for at least 16 DATACLK_IN cycles.
5. Set RESET pin = 0.
6. Run for at least 16 DATACLK_IN cycles.
7. Set RESET pin = 1.
8. Run for at least 16 DATACLK_IN cycles.
9. Set RESET pin = 0.
10. Set desired operating mode (1× mode and signed data are
default values and expected for the supplied BIST vectors).
11. Set CLEAR (Reg. 17, Bit 0), SYNC_EN (Reg. 17, Bit 1),
and LVDS_EN (Reg. 17, Bit 2) high.
12. Wait 50 DATACLK_IN cycles to allow 0s to propagate
through and clear sync signatures.
13. Set CLEAR low.
14. Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and
Reg. 18) for each of the four SEL (Reg. 17, Bits 7:6) values
and verify they are all 0x00.
LVDS Phase 1
a. Reg. 17 set to 0x26 (SEL1 = 0, SEL0 = 0,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
LVDS Phase 2
a. Reg. 17 set to 0x66 (SEL1= 0, SEL0 = 1,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
SYNC Phase 1
a. Reg. 17 set to 0xA6 (SEL1= 1, SEL0 = 0,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
SYNC Phase 2
a. Reg. 17 set to 0xE6 (SEL1= 1, SEL0 = 1,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
15. Clock the BIST vector into the AD973x.
16. After the BIST vector is clocked into the part, hold DATA
= 0x0000 for signed (0x2000 for unsigned); otherwise, the
additional nonzero data changes the signature.
17. Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and
Reg. 18, as described in Step 14 ) for each of the four SEL
(Reg. 17, Bits 7:6) values, and verify that they match the
expected signatures shown in Table 25.
18. Flush the BIST circuitry. This must be done once before
valid data can be read. Loop back to Step 11 and rerun the
test to obtain the correct result.
Each time BIST mode is entered, this flush needs to
be performed once. Multiple BIST runs can be performed
without reflushing, as long as the device remains in
BIST mode.
AD973x EXPECTED BIST SIGNATURES
The BIST vectors provided on the AD973x-EB CD are in signed
mode, so no programming is necessary for the part to pass the
BIST. The BIST vector is for 1×, no FIFO, and signed data.
For testing all 14 input bits, use the vector all_bits_unsnew.txt
and verify against the signatures in Table 25.
Table 25. Expected BIST Data Readback for All Bits
LVDS Phase 1 LVDS Phase 2 SYNC Phase 1 SYNC Phase 2
CF71487C 66DF5250 CF71487C 66DF5250
For individual bit tests, use the vectors named bitn.txt (where n
is the desired bit number being tested) and compare them
against the values in Table 26.
Table 26. Expected BIST Data Readback for Individual Bits
Vector
Bit
Number
LVDS Rise
Expected
LVDS Fall
Expected
bit0.txt 0 AABF0A00 2A400500
bit1.txt 1 2BBF0A00 6B400500
bit2.txt 2 29BE0A00 E9400500
bit3.txt 3 2DBC0A00 ED410500
bit4.txt 4 25B80A00 E5430500
bit5.txt 5 35B00A00 F5470500
bit6.txt 6 15A00A00 D54F0500
bit7.txt 7 55800A00 955F0500
bit8.txt 8 D5C00A00 157F0500
bit9.txt 9 D5410A00 153E0500
bit10.txt 10 D5430B00 15BC0500
bit11.txt 11 D5470900 15B80400
bit12.txt 12 D54F0D00 15B00600
bit13.txt 13 D55F0500 15A00200
Note the following for Table 26:
• The term rise refers to Phase 1 and fall refers to Phase 2.
• Byte order is Decimal Register Address 21, Address 20,
Address 19, and Address 18.
• SYNC phase should always equal LVDS phase in 1× mode.
AD9734/AD9735/AD9736
Rev. A | Page 46 of 72
GENERATING EXPECTED SIGNATURES
The following MATLAB code duplicates the internal logic of
the AD973x. To use it, save this code in a file called bist.m.
--- begin bist.m ---
function [ ret1 , ret2] = bist(vec)
ret1 = bist1(vec(1:2:length(vec)-1));
ret2 = bist1(vec(2:2:length(vec)));
function ret = bist1(v)
sum = zeros(1,32);
for i = 1 :length(v)
if v(i) ~= 0
su(1) = ~xor(sum(32) ,bitget(v(i),1));
su(2) = ~xor(sum(1) ,bitget(v(i),2));
su(3) = ~xor(sum(2) ,bitget(v(i),3));
su(4) = ~xor(sum(3) ,bitget(v(i),4));
su(5) = ~xor(sum(4) ,bitget(v(i),5));
su(6) = ~xor(sum(5) ,bitget(v(i),6));
su(7) = ~xor(sum(6) ,bitget(v(i),7));
su(8) = ~xor(sum(7) ,bitget(v(i),8));
su(9) = ~xor(sum(8) ,bitget(v(i),9));
su(10) = ~xor(sum(9) ,bitget(v(i),10));
su(11) = ~xor(sum(10) ,bitget(v(i),11));
su(12) = ~xor(sum(11) ,bitget(v(i),12));
su(13) = ~xor(sum(12) ,bitget(v(i),13));
su(14) = ~xor(sum(13) ,bitget(v(i),14));
su(15) = sum(14); su(16) = sum(15);
su(17) = sum(16); su(18) = sum(17);
su(19) = sum(18); su(20) = sum(19);
su(21) = sum(20); su(22) = sum(21);
su(23) = sum(22); su(24) = sum(23);
su(25) = sum(24); su(26) = sum(25);
su(27) = sum(26); su(28) = sum(27);
su(29) = sum(28); su(30) = sum(29);
su(31) = sum(30); su(32) = sum(31);
sum = su;
end
end % for ret = dec2hex( 2.^[0:31]× sum',8);
--- end bist.m ---
To generate the expected BIST signatures, follow this procedure:
1. Start MATLAB and type the following at the command
prompt:
t = round(randn(1,100) × 213/8+213) ;
[ b1 b2 ] = bist(t)
The first statement creates a random vector of 14-bit
words, with a length of 100.
2. Set t equal to any desired vector, or take this random vector
and input it to the AD973x.
3. Alter the command randn(1,100) to change the vector
length as desired.
4. Type b1 at the command line to see the calculated
signature for the LVDS BIST, Phase 1.
5. Type b2 to see the value for LVDS BIST, Phase 2.
The values returned for b1 and b2 each are 32-bit hex values.
They correspond to Reg. 18, Reg. 19, Reg. 20, and Reg. 21,
where b1 is the value read for SEL<1:0> = 0, 0 (see Table 17)
and b2 is the value read for SEL<1:0> = 0, 1.
When the DAC is in 1× mode, the signature at SYNC BIST,
Phase 1 should equal the signature at LVDS BIST, Phase 1. The
same is true for Phase 2.
AD9734/AD9735/AD9736
Rev. A | Page 47 of 72
CROSS CONTROLLER REGISTERS
The AD973x differential output stage is adjustable to equalize
the charge injection into the positive and negative outputs. This
adjustment impacts certain performance characteristics, such as
harmonic distortion or IMD. System performance can be en-
hanced by adjusting the cross controller.
If the system is calibrated after manufacture, adjust the cross
controller offsets to provide optimum performance. To start,
increment DNDEL<5:0> (Reg. 11, Bits 5:0) while observing
HD2 (second harmonic distortion) and/or IMD to find the
desired optimum. If DNDEL does not influence the perform-
ance, set it to 0 and increment UPDEL<5:0> (Reg. 10, Bits 5:0).
Based on system characterization, set one of these controls to
the maximum value to yield the best performance.
Figure 85 shows the effect of UPDEL and DNDEL.
04862-083
INCREMENT DNDEL TO MOVE
THE CROSSING TOWARD THE
IDEAL VALUE
IDEAL DIFFERENTIAL OUTPUT
CROSSING ALIGNMENT
INCREMENT UPDEL TO MOVE
THE CROSSING TOWARD THE
IDEAL VALUE
Figure 85. Effect of UPDEL and DNDEL
AD9734/AD9735/AD9736
Rev. A | Page 48 of 72
ANALOG CONTROL REGISTERS
The AD973x includes some registers for optimizing its analog
performance. These registers include temperature trim for the
band gap, noise reduction in the output current mirror, and
output current mirror headroom adjustments.
BAND GAP TEMPERATURE CHARACTERISTIC
TRIM BITS
Using TRMBG<2:0> (Reg. 14, Bits 2:0), the temperature
characteristic of the internal band gap can be trimmed to
minimize the drift over temperature, as shown in Figure 86.
–50 –40 –30 –20
–10
010203040506070 8090
TEMPERATURE (°C)
VREF (V)
1.23
1.22
1.21
1.2
1.19
1.18
04862-084
000
010
001
011
101
110
111
100
Figure 86. Band Gap Temperature Characteristic for Various TRMBG Values
The temperature changes are sensitive to process variations,
and Figure 86 may not be representative of all fabrication lots.
Optimum adjustment requires measurement of the device
operation at two temperatures and development of a trim
algorithm to program the correct TRMBG<2:0> values in
external nonvolatile memory.
MIRROR ROLL-OFF FREQUENCY CONTROL
With MSEL <1:0> (Reg. 14, Bits 7:6), the user can adjust the
noise contribution of the internal current mirror to optimize
the 1/f noise. Figure 87 shows MSEL vs. the 1/f noise with
20 mA full-scale current into a 50 resistor.
F (kHz)
NOISE (IdBm/Hz)
–
110
–115
–120
–125
–130
–140
–135
1 10 100
04862-0-085
MSEL0
MSEL2
MSEL1
MSEL3
Figure 87. 1/f Noise with Respect to MSEL Bits
HEADROOM BITS
HDRM<7:0> (Reg. 15, Bits 7:0) are for internal evaluation.
Changing the default reset values is not recommended.
VOLTAGE REFERENCE
The AD973x output current is set by a combination of digital
control bits and the I120 reference current, as shown in
Figure 88.
CURRENT
SCALING
FSC<9:0>
AD973x
DAC
IFULL-SCALE
10kΩ
1nF
V
REF
I120
AVSS
I120
V
BG
1.2V
+
–
04862-086
Figure 88. Voltage Reference Circuit
The reference current is obtained by forcing the band gap
voltage across an external 10 kΩ resistor from I120 (Pin B14) to
ground. The 1.2 V nominal band gap voltage (VREF) generates a
120 µA reference current in the 10 kΩ resistor. This current is
adjusted digitally by FSC<9:0> (Reg. 2, Reg. 3) to set the output
full-scale current IFS:
⎟
⎠
⎞
⎜
⎝
⎛⎟
⎠
⎞
⎜
⎝
⎛><×+×= 0.9
1024
192
72 FSC
R
V
IREF
FS
AD9734/AD9735/AD9736
Rev. A | Page 49 of 72
The full-scale output current range is approximately 10 mA to
30 mA for register values from 0x000 to 0x3FF. The default
value of 0x200 generates 20 mA full scale. The typical range is
shown in Figure 89.
35
30
25
20
IFS (mA)
15
10
5
0
0 200 400 600 800
DAC GAIN CODE
1000
04862-087
Figure 89. IFS vs. DAC Gain Code
Always connect a 10 kΩ resistor from the I120 pin to ground
and use the digital controls to vary the full-scale current. The
AD973x is not a multiplying DAC. Applying an analog signal to
I120 is not supported.
VREF (Pin C14) must be bypassed to ground with a 1 nF
capacitor. The band gap voltage is present on this pin and can
be buffered for use in external circuitry. The typical output
impedance is near 5 kΩ. If desired, an external reference can be
used to overdrive the internal reference by connecting it to the
VREF pin.
IPTAT (Pin D14) is used for factory testing. Leave this pin
floating.
AD9734/AD9735/AD9736
Rev. A | Page 50 of 72
APPLICATIONS INFORMATION
DRIVING THE DACCLK INPUT
The DACCLK input requires a low jitter differential drive
signal. It is a PMOS input differential pair powered from the
1.8 V supply, so it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 800 mV p-p about the 400 mV common-
mode voltage. While these input levels are not directly LVDS
compatible, DACCLK can be driven by an offset ac-coupled
LVDS signal, as shown in Figure 90.
04862-088
LVDS_P_IN CLK+
50Ω
50Ω
0.1μF
0.1μF
LVDS_N_IN CLK–
V
CM
= 400mV
Figure 90. LVDS DACCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to DACCLK, as shown in Figure 107. Use of a CMOS or TTL
clock can also be acceptable for lower sample rates. It is routed
through a CMOS to LVDS translator, then ac-coupled, as
described previously. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 91.
04862-089
50Ω
50Ω
TTL OR CMOS
CLK INPUT CLK+
CLK–
V
CM
= 400mV
BAV99ZXCT
HIGH SPEED
DUAL DIODE
0.1μF
Figure 91. TTL or CMOS DACCLK Drive Circuit
A simple bias network for generating VCM is shown in
Figure 92. It is important to use CVDD18 and CVSS for the
clock bias circuit. Any noise or other signal that is coupled onto
the clock is multiplied by the DAC digital input signal and may
degrade the DAC performance.
0
4862-090
0.1µF 1nF
1nF
V
CM
= 400m
V
CVDD
1.8V
CVSS
1kΩ
2
87
Ω
Figure 92. DACCLK VCM Generator Circuit
AD9734/AD9735/AD9736
Rev. A | Page 51 of 72
DAC OUTPUT DISTORTION SOURCES
The second harmonic is mostly due to an imbalance in the
output load. The dc transfer characteristic of the DAC is capable
of second harmonic distortion of at least −75 dBc. Output load
imbalance or digital data noise coupling onto DACCLK causes
additional second harmonic distortion.
The DAC architecture inherently generates third harmonics, the
levels of which depend on the output frequency and amplitude
generated. If any output signal is rectified and coupled back
onto the DAC clock, it can generate additional third-harmonic
energy.
The distortion components should be identical in amplitude
and phase at both AD973x outputs. Even though each single-
ended output includes a large amount of second-harmonic
energy, a careful differential-to-single-ended conversion can
remove most of it. Optimum performance at high intermediate
frequency (IF) output is obtained with the output circuit shown
in Figure 93.
This is the configuration implemented on the evaluation board
(Figure 107). The 20 Ω series resistors allow the DAC to drive a
less reactive load, which improves distortion. Further improvement
is realized by adding the Balun T3 to help provide an equal load
to both DAC outputs.
04862-091
IOUTA
IOUTB
J2, 50ΩOUTPUT
AVSS
R17
20Ω
156
5
1
3443
R19
20Ω
T3
T1AVSS
R8
50Ω
R6
50Ω
Figure 93. IF Signal Output Circuit
Because T1 has a differential input, but a single-ended output,
Pin 4 of T1 has a higher capacitance to ground due to parasitics
to Pin 3. T1 Pin 6 has lower parasitic capacitance to ground
because it drives 50 Ω at Pin 1. This presents an unbalanced
load to the DAC output, so T3 is added to improve the load
balancing. Refer to Figure 107 for the transformer part numbers.
AD9734/AD9735/AD9736
Rev. A | Page 52 of 72
DC-COUPLED DAC OUTPUT
In some cases, it may be desirable to dc-couple the AD973x
output. The best method for doing this is shown in Figure 94.
This circuit can be used with voltage or current feedback
amplifiers. Because the DAC output current is driving a virtual
ground, this circuit may offer enhanced settling times. The
settling time is limited by the op amp rather than by the DAC.
This circuit is intended for use where the amplifiers can be
powered by a bipolar supply.
04862-092
IOUTA
DAC
OUTPUT
20mA
FULL SCALE
IOUTB
100Ω
100Ω
100Ω
500Ω
500Ω
100Ω
500Ω
500Ω
AVSS
AVSS OUTPUT
2V p-p
+1V TO –1V
2V p-p
0V TO –2V
Figure 94. Op Amp I to V Conversion Output Circuit
An alternate circuit is shown in Figure 95. It suffers from dc
offset at the output unless the DAC load resistors are small,
relative to the amplifier gain and feedback resistors.
04862-093
IOUTA
OUTPUT
AVSS
IOUTB
25Ω
25Ω2kΩ
AVSS
2kΩ1kΩ
1kΩ
DAC OUTPUT
20mA
FULL SCALE
2V p-p
0V TO –2V
0.5V p-p
0V TO –0.5V
Figure 95. Differential Op Amp Output Circuit
AD9734/AD9735/AD9736
Rev. A | Page 53 of 72
DAC DATA SOURCES
The circuit shown in Figure 96 allows optimum data alignment
when running the AD973x at full speed. This circuit can be
easily implemented in the FPGA or ASIC used to drive the
digital input. It is important to use the DATACLK_OUT signal
because it helps to cancel some of the timing errors. In this
configuration, DATACLK_OUT generates the DDR LVDS
DATACLK_IN to drive the AD973x. The circuit aligns the
DATACLK_IN and the digital input data (DB<13:0>) as
required by the AD973x. The LVDS controller in the AD973x
uses DATACLK_IN to generate the internal DSS to capture the
incoming data in the center of the valid data window.
04862-094
MUX
MUX
D1
DATACLK_OUT
FROM AD9736 (DDR)
DATACLK_IN
TO AD9736 (DDR)
DB(13:0) TO AD9736
DATA SOURCE
LOGIC 0
LOGIC 1
DATA2
DATA1
D2
Figure 96. Recommended FPGA/ASIC Configuration for Driving AD9736
Digital Inputs, 1× Mode
04862-095
DATA1
DATA2
AC
AC
E
B
ABC
D
BD
D1
D2
DB
DATACLK_OUT+
DATACLK_IN+
Figure 97. FPGA/ASIC Timing for Driving AD973x Digital Inputs, 1× Mode
To operate in 2× mode, the circuit in Figure 96 must be
modified to include a divide-by-2 block in the path of
DATACLK_OUT. Without this additional divider, the data and
DATACLK_IN runs 2× too fast. DATACLK_OUT is always
DACCLK/2.
Contact FPGA vendors directly regarding the maximum output
data rates supported by their products.
04862-096
MUX
MUX
D1
DATACLK_OUT
FROM AD9736 (DDR)
DATACLK_IN
TO AD9736 (DDR)
DB(13:0) TO AD9736
DATA SOURCE
LOGIC 1
LOGIC 0
DATA2
DATA1
D2
÷
2
Figure 98. Recommended FPGA/ASIC Configuration for Driving AD9736
Digital Inputs, 2× Mode
04862-097
CLK_OUT+/2
DATA2
DATA1
AC
AC
E
B
ABC
D
BD
D1
D2
DB
DATACLK_OUT+
DATACLK_IN+
Figure 99. FPGA/ASIC Timing for Driving AD973x Digital Inputs, 2× Mode
AD9734/AD9735/AD9736
Rev. A | Page 54 of 72
INPUT DATA TIMING
The AD973x is intended to operate with the LVDS and sync
controllers running to compensate for timing drift due to
voltage and temperature variations. In this mode, the key to
correct data capture is to present valid data for a minimum
amount of time. The AD973x minimum valid data time is
measured by increasing the input data rate to the point of
failure. The nominal supply voltages are used and the
temperature is set to the worst case of 85°C. The input
data is verified via the BIST signature registers, because the
DAC output does not run as fast as the input data logic. The
following example explains how the minimum data valid
period is calculated for the typical performance case.
These factors must be considered in determining the minimum
valid data window at the receiver input:
• Data rise and fall times: 100 ps (rise + fall)
• Internal clock jitter: 10 ps
(DATACLK_OUT + DATACLK_IN)
• Bit-to-bit skew: 50 ps
• Bit-to-DATACLK_IN skew: 50 ps
• Internal data sampling signal resolution: 80 ps
For nominal silicon, the BIST typically indicates failure at
2.15 GSPS or a DACCLK period of 465 ps. The valid data
window is calculated by subtracting all the other variables
from the total data period:
Minimum Data Valid Time = DACCLK Period − Data Rise −
Data Fall − Jitter − Bit-to-Bit Skew − Bit-to-DATACLK_IN Skew
− Data Sampling Signal Resolution
For the 400 mV p-p LVDS signal case:
Minimum Data Valid = 465 ps − 100 ps − 10 ps − 50 ps −
80 ps = 465 ps − 240 ps = 225 ps
For correct data capture, the input data must be valid for 225 ps.
Slower edges, more jitter, or more skew require an increase in
the clock period to maintain the minimum data valid period.
Table 27 shows the typical minimum data valid period (tMDE) for
400 mV p-p differential and 250 mV p-p differential LVDS swings.
The ability of the AD973x to capture incoming data is
dependent on the speed of the silicon, which varies from lot to
lot. The typical (or average) silicon speed operates with data
that is valid for 225 ps at 85°C. Statistically, the worst extreme
for slow silicon may require up to a 344 ps valid data period, as
specified in Table 2 .
Table 27. Typical Minimum Data Valid Times
Differential Input
Voltage
BIST
Max fCLK
Min Clock
Period
Typ Min Data
Valid at Receiver
400 mV 2.15 GHz 465 ps 225 ps
250 mV 2.00 GHz 500 ps 260 ps
At 1.2 GHz, the typical 400 mV p-p minimum data valid period
of 225 ps leaves 608 ps for external factors. Under the same
conditions, the worst expected minimum data valid period of
344 ps leaves 489 ps for external data uncertainty.
The 100 mV LVDS VOD threshold test is a dc test to verify that
the input logic state changes. It does not indicate the operating
speed. The ability of the receiver to recover the data depends on
the input signal overdrive. With a 250 mV input, there is a
150 mV overdrive, and with a 400 mV signal, there is a 300 mV
overdrive. The relationship between overdrive level and timing
is very nonlinear. Higher levels of overdrive result in smaller
minimum valid data windows.
For typical silicon, decreasing the LVDS swing from 400 mV p-p
to 250 mV p-p requires the minimum data valid period to
increase by 15%. This is illustrated in Figure 100.
225ps
400mV
260ps
250mV
04862-098
Figure 100. Typical Minimum Valid Data Time (tMDE) vs. LVDS Swing
The minimum valid data window changes with temperature,
voltage, and process. The maximum value presented in the
specification table was determined from a 6σ distribution in the
worst-case conditions.
AD9734/AD9735/AD9736
Rev. A | Page 55 of 72
SYNCHRONIZATION TIMING
When more than one AD973x must be synchronized or when
a constant group delay must be maintained, the internal
controllers cannot be used. If the FIFO is enabled, the delay
between multiple AD973x devices is unknown. If the
DATACLK_OUT from multiple devices is used, there is an
uncertainty of two DACCLK periods because the initial phase
of DATACLK_OUT with respect to DACCLK cannot be
controlled. This means one DAC must be used to provide
DATACLK_OUT for all synchronized DACs and all timing
must be externally managed. The following timing information
allows system timing to be calculated so that multiple AD973xs
can be synchronized.
DATACLK_OUT changes relative to the rising edge of
DACCLK+ and is delayed, as shown in Figure 101. Because
DACCLK is divided by 2 to create DATACLK_OUT, the phase
of DATACLK_OUT can be 0° or 180°. There is no way to
predict or control this relationship. It can be different after each
power cycle and is not affected by hardware or software resets.
t
DDCO
DACCLK
DATACLK_OUT
04862-099
Figure 101. DACCLK to DATACLK_OUT Delay
The incoming data is de-interleaved internally as shown in
Figure 78. In Figure 78, DBU (upper) and DBL (lower) represent
the de-interleaved data paths. Each edge of DATACLK_IN
latches an incoming sample in two alternating registers. The
DATACLK_IN to data setup and hold definitions are illustrated
in Figure 102. All the data input must be valid during the setup-
and-hold period. External skew effectively increases the setup
and hold times that the data source must meet.
04862-100
DATACLK_IN
OR DATACLK_OUT
DATA_IN
t
DH
t
DSU
Figure 102. Standard Definitions for DATACLK_IN or DATACLK_OUT to
Data Setup and Hold, SD = 0
While correct DATA_IN vs. DATACLK_IN timing is critical,
the transition of the incoming data to the DACCLK domain is
equally critical. By referencing the incoming DATA and
DATACLK_IN timing to the DATACLK_OUT signal, some
timing uncertainty can be removed. The DATACLK_OUT
timing very closely tracks the timing of the DACCLK-
controlled registers. Any variation in the path delay affects both
paths in almost the same way. If DATACLK_OUT is not used,
the full DACCLK to DATACLK_OUT path variation reduces
the external timing margin. Figure 101 shows a simplified view
of the internal clocking scheme with the relevant delay paths.
The internal architecture is interleaved such that each phase has
twice as long to make the transition across the clock domains.
This results in an extremely narrow window where the
incoming data must be held stable.
Table 28 shows the timing parameters for Figure 101 and
Figure 102. These parameters were measured for a sample of
five devices from five silicon lots. Worst-case fast and slow skew
lots were included in addition to the nominal (or average) lot.
The typical −40°C to typical +85°C spread illustrates the
variability with temperature for a single lot. Adding in lot-to-lot
variation with the fast and slow lots indicates the worst-case
spread in timing.
The timing varies such that all of the parameters move in the
same direction. For example, if the DATACLK_IN to data setup
time is fast, the hold time is similarly fast. The DACCLK to
DATACLK_OUT delay and the DATACLK_OUT to data setup
and hold is also at the fast end of the range.
Note that the polarities of setup-and-hold values in Table 28
conform to the standard convention of setup time occurring
prior to the latching edge and hold time occurring after the
latching edge, as shown in Figure 102.
Table 28. AD973x Clock and Data Timing Parameters
Symbol and Definition Fast −40°C Typ −40°C All +25°C Typ +85°C Slow +85°C Unit
tDDCO − DACCLK to DATACLK_OUT Delay +1650 +1800 +1890 +2050 +2350 ps
tDCISU − DATACLK_IN to DATA Setup −100 −120 −150 −170 −220 ps
tDCIH − DATACLK_IN to DATA Hold +210 +220 +240 +280 +360 ps
tDISU − DATACLK_OUT to DATA Setup +1310 +1440 +1611 +1710 +1970 ps
tDIH − DATACLK_OUT to DATA Hold −1250 −1360 −1548 −1640 −1890 ps
AD9734/AD9735/AD9736
Rev. A | Page 56 of 72
POWER SUPPLY SEQUENCING
The 1.8 V supplies should be enabled prior to enabling the 3.3 V supplies. Do not enable the 3.3 V supplies when the
1.8 V supplies are off.
04862-101
LVDS
RX
DATACLK_IN
DATACLK_IN DOMAIN DACCLK DOMAIN
DB<13:0>
PATH A
PATH B
DATACLK_OUT
D1A
DAC_DATA DAC_OUTPUT
D1
D2 D2A
SD<3:0>
SAMPLE DELAY
DACCLK
FF
FF
÷
2CLK
RX
FF
FF
SD<3:0>
SAMPLE DELAY
DATA SAMPLING
SIGNAL DAC SAMPLING
SIGNAL
COMMON SYSTEM CLOCK
DELAYS THROUGH PATH A AND B WILL TRACK,
THUS REDUCING TIMING UNCERTAINTY IN THE SYSTEM
LVDS
RX
LVDS
TX
DAC
CORE
Figure 103. Simplified Internal Clock Routing
AD9734/AD9735/AD9736
Rev. A | Page 57 of 72
AD973X EVALUATION BOARD SCHEMATICS
L1, L3, L4, L5, L6, AND L7
FERRITE BEAD CORE:
PANASONIC EXC–CL3225U1
DIGIKEY PN: P9811CT–ND
VSS
TP5
BLK
33DIG
VSS
TB1 1
TB1 2
L6 FERRITE
TP4
RED
VDD33
LC1210
C14
10
μ
F
6.3V
ACASE
+
VSSA
TP3
BLK
33ANA
VSSA
TB2 1
TB2 2
L1 FERRITE
TP1
RED
VDDA33
LC1210
C1
10
μ
F
6.3V
ACASE
+
VSSA
TP11
BLK
18ANA
VSSA
TB2 3
TB2 4
L3 FERRITE
TP9
RED
VDDC
LC1210
C10
10
μ
F
6.3V
L4 FERRITE
LC1210
ACASE
+
VSS
TP13
BLK
TP6
RED
TP14
BLK
VDD18A
VDD18B
VSS
TP7
RED
C22
10
μ
F
6.3V
L7 FERRITE
LC1210
L5 FERRITE
LC1210
18DIG
TB1 3
VSS
TB1 4
ACASE
+
C18
10
μ
F
6.3V
ACASE
+
POWER INPUT FILTERS
VSSAVSS
UNDER DUT
JP1
04862–102
Figure 104. Power Supply Input for AD973x Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 58 of 72
04862-103
IN1
IN2
IN3
IN4
IP1 A8
B8
C8
D8
A9
C19
4.7μF
6.3V
VSSA
VDD18B
VSS
C23
4.7μF
6.3V
C24
0.1μF
C25
1nF H1 VDD1
VDD2
VDD3
VDD5
VDD4
VDD6
VDD7
VDD8
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS21
NCK1
VSS22
VDD16
VDD15
VDD14
VDD12
VDD13
VDD11
VDD10
VDD9
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
LVDS13N
LVDS13P
LVDS12N
LVDS12P
LVDS11N
LVDS11P
LVDS10N
LVDS10P
LVDS9N
LVDS9P
LVDS8N
LVDS8P
LVDS7N
LVDS7P
LVDS6N
LVDS6P
VDD338
VDD337
VDD336
VDD335
SPI_MODE
LVDS0N
LVDS0P
LVDS1N
LVDS1P
LVDS2N
LVDS2P
LVDS3N
LVDS3P
LVDS4N
LVDS4P
LVDS5N
LVDS5P
LVDSCLKOUTN
LVDSCLKOUTP
LVDSCLKINN
LVDSCLKINP
VDD331
VDD332
VDD333
VDD334 BOTTOM
H2
H3
H4
J1
J2
J3
J4
K3
K4
L3
L4
L5
L6
M3
M4
M5
M6
K2
K1
L2
L1
M2
M1
N1
P1
N2
N3
P2
P3
N4
P4
N5
P5
N6
P6
L7
M7
N7
P7
H14
H13
H12
H11
J14
J13
J12
J11
K11
K12
L9
L10
L11
L12
M9
M10
M11
M12
K13
K14
L13
L14
M13
M14
N14
P14
N13
N12
P13
P12
N11
P11
N10
P10
N9
P9
L8
M8
N8
P8
VSS
C34
DNP
C20
0.1μF
C21
1nF
VDD18A
C7
DNP
VSS
VDD33
JP15
JP8
A
2
3
B
C6
DNP
IRQ
IPTAT SPARE
C9
1nF
R16
10kΩ
TP2
WHT
TP12
WHT
WHT
TP8
WHT
TP10
TP16
WHT
JP4
IRQ
RESET_A
RESET
SPCSB
SPSDI
JP3
4
3
SW1
VDD33
VSS;5
VSS
SPCLK
SPSDO
VREF I120
VDD33
C15
4.7μF
6.3V
C16
0.1μF
C17
1nF
CC060
A10
A11
B9
B10
B11
C9
C10
C11
D9
D10
D11
A12
A13
B12
B13
C12
C13
D12
D13
A14
IP2
IP3
IP4
TOP
33DDV
A5
A4 VSSA331
VSSA332
VSSA333
VSSA334
VSSA335
VSSA336
VSSA337
VSSA338
VSSA339
VSSA3310
VSSA3311
VSSA3312
VDDC1
VDDC2
VDDC3
VDDC4
VDDC5
VDDC6
VDDC7
VDDC8
VDDC9
VDDC11
VDDC10
VSSC1
CLKN
CLKP
VSSC2
VSSC3
VSSC4
VSSC5
VSSC6
VSSC7
VSSC8
VSSC9
VSSC10
VSSC11
VDDA331
VDDA332
VDDA333
VDDA334
VDDA335
VDDA336
VDDA337
VDDA338
SPARE
I120
VREF
IPTAT
SIGNED_IRQ
PD_RESET
2X_CSB
FIFO_SDIO
FSC0_SCLK
FSC1_SDO
SHIELD1
SHIELD2
SHIELD3
SHIELD4
SHIELD5
SHIELD6
HYDROGEN
U1
U1
HYDROGEN
VSSA
R5
10kΩ
RC1206
VSSA3314
VSSA3313
VSSA3315
VSSA3316
VSSA3317
VSSA3318
VSSA3319
VSSA3320
VSSA3321
VSSA3322
VSSA3323
VSSA3324
B4
D6
D5
D4
C6
C5
C4
D1
E1
F1
E2
E3
E4
F2
F3
F4
G1
G2
G3
G4
D3
C2
C1
B2
B1
A3
A2
D2
D14
E13
E14
F13
F14
G13
G14
E11
E12
F11
F12
G11
G12
C14
B14
A6
B5
A1
C5
CC063
DNP
C3
B6
B3
SSV
1
2
DB0N
C8
DNP
DB0P
DB1N
DB1P
DB2N
DB2P
DB3N
DB3P
DB4N
DB4P
DB5N
DB5P
DB6N
DB6P
DB7N
DB7P
DCLKNIN
DCLKPIN
IN
IP
AD9736
AD9736
A7
B7
C7
D7
CLKN
CLKP
VDDC
C11
6.3V
VSSA
4.7μFC12
0.1μF
C13
1nF
ACASE CC0603 CC0603
CC0603
CC0603
CC0603
CC0603
CC0603 CC0603
CC0603
VSSA
VSSA DB13N
DB13P
DB12N
DB12P
DB11N
DB11P
DB10N
DB10P
DB9N
DB9P
DB8N
DB8P
DCLKNOUT
DCLKPOUT
R1
0.1%
10kΩ
CC0603
RC0603
CC0603 CC0603 CC0603
CC0603
A
2
1
13
B
ACASE
ACASE
ACASE
ACASE
NOTE: AD9736 MSB –LSB BIT ORDER IS REVERSED
FROM THE CONNECTOR BIT ORDER.
C4
1nF
C3
0.1μF
C2
4.7μF
6.3V
VDDA33
Figure 105. Circuitry Local to AD973x, Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 59 of 72
DB13N
DB12N
DB13P
DB12P
VSS
DB11P
DB10P
DB8P
DB7P
DB7N
DB6N
DB0N
DB1N
DB2N
DB3N
DB4N
DB5N
DB0P
DB1P
DB2P
DB3P
DB4P
DB5P
G2
S2
G3 G4
S3 S4
G5 G6
S5 S6
G7 G8
S7 S8
G9 G10
S9 S10
G11 G12
S11 S12
G13 G14
S13 S14
G15 G16
S15 S16
G17 G18
S17 S18
G19 G20
S19 S20
G21 G22
S21 S22
G23 G24
S23 S24
G25 G26
S25 S26
G27 G28
S27 S28
G29 G30
S29 S30
G31 G32
S31 S32
G33 G34
S33 S34
G35 G36
S35 S36
G37 G38
S37 S38
G39 G40
S39 S40
G41 G42
S41 S42
G43 G44
S43 S44
G45 G46
S45 S46
G47 G48
S47 S48
G49 G50
G1
S1
J3
DCLKNIN
DCLKNOUT
DB8N
DB9N
DB10N
DB11N
DB6P
DCLKPIN
DCLKPOUT
DB9P
TESTOUTN
EXTCLK
TESTOUTP
NOTE: AD9736 MSB-LSB BIT ORDER IS REVERSED
FROM THE CONNECTOR BIT ORDER.
CONNECTOR
DB13
DB0
AD9736
DB0
DB13
TP15
WHT
JACK
JACK
FCN–268 F024–G/0 D
04862–104
Figure 106. High Speed Digital I/O Connector, AD973x Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 60 of 72
SP
SP
VSSA
6
5
34
2
1
1
43
6
J2
R4
300Ω
3
15
4
415mV COMMON
MODE VOLTAGE
400mV p–p
NOTE:
T1, T3, AND T3B ARE INSTALLED,
R6 AND R8 = 50Ω,
R7 = DNP
R17 AND R19 = 20Ω,
R161 AND R162 = 0Ω,
JUMPER ADDED FROM T1 PIN 3 TO
T1 PIN 2 ON THE REV. C EVAL BOARD.
J1
VSSA;3,4,5
SMA200UP
VSSA
T3A
T3B
T3
ADTL1–12XX
ETC1–1–13
SP
NC=2
ETC1–1–13 ETC1–1–13
T2
ADT2–1T–1P
4
51
3
PS
NC=2
C35
C36
0.1μF
0.1μF
CC0603CC0603
CC0603 CC0603
CC0603
CC0603CC0603
R20
R21
R3
1kΩ
R6
50Ω
C26
DNP
C27
DNP C38
1nF
C29
1nF
C28
0.1μF
CLKP
CLKN
VDDC
VSSA
25Ω
25Ω
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
R7
DNP
R17
20Ω
R161
0Ω
R162
0Ω
R18
DNP
R19
20Ω
RC0603
R8
50Ω
RC0603
RC0603
AN LVDS SIGNAL MAY BE USED
TO DRIVE C35 AND C36 IF R20 AND R21
ARE INCREASED TO 50Ω EACH.
R17 AND R19 CAN BE REMOVED AND T1
REPLACED WITH A 1:1 TRANSFORMER FOR
HIGHER OUTPUT AMPLITUDE IF MORE H2
IS ACCEPTABLE (TYPICALLY AT LOWER FOUT).
R17 AND R19 PRESENT A
MORE REAL LOAD TO THE
DAC WHICH IMPROVES
H2 PERFORMANCE.
T2 AND T4B ARE NOT POPULATED
T1:MINI-CIRCUITS
–3dB: 8-600MHz
–1dB: 13-300MHz
THIS CONFIGURATION PROVIDES OPTIMUM AC
PERFORMANCE FOR IF SIGNAL GENERATION.
TYPICAL SIGNAL LEVELS SHOWN FOR 50Ω LOAD.
VSSA
VSSA VSSA
VSSA
IN
IP
T3:M/A-COM
–1dB: 4.5-1000MHz
SP
6
5
34
2
1
T4B
T1
ADT2–1T–1P
4
5
3
1
PS
NC=2
VSSA;3,4,5
SMA200UP
04862–105
T3A IS NOT POPULATED
Figure 107. Clock Input and Analog Output, AD973x Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 61 of 72
IRQ
RESET_A
2
RC0603
RC0603
2
B
31
2
L9
6
1
2
4
5
3
P1
VSS L8
RC0805
9kΩR11
RC0805
9kΩR10
RC0805
9kΩR12
33DDV
VSS
VSS
VSS
VSS
VSS
VSS
USE THESE JUMPERS TO SET PIN_MODE
CONTROL SIGNALS OR CONNECT SPI PORT
SIGNALS IN SPI_MODE.
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
SPCSB
SPCLK
SPSDI
SPSDO
JP13
JP6
JP7
JP2
JP5
JP14
JP9
JP10
JP12
JP11
A
B
31
2
A
B
31
2
A
B
31
2
A
B
31
2
A
B
31
2
A
R13
10kΩR14
10kΩ
LC1210
LC1210
FERRITE
FERRITE
FERRITE BEAD CORE:
PANASONIC EXC-CL3225U1
DIGIKEY PN: P9811CT-ND
74AC14
12
U5
VSS;7
VDD33;14
74AC14
34
U5
VSS;7
VDD33;14
74AC14
56
U5
VSS;7
VDD33;14
74AC14
43
U6
VSS;7
VDD33;14
74AC14
65
U6
VSS;7
VDD33;14
74AC14
1213
U6
VSS;7
VDD33;14
74AC14
21
U6
VSS;7
VDD33;14
74AC14
1312
U5
VSS;7
VDD33;14
74AC14
1110
U5
VSS;7
VDD33;14
74AC14
98
U5
VSS;7
VDD33;14
VSS
74AC14
1011
U6
VSS;7
VDD33;14
74AC14
89
U6
VSS;7
VDD33;14
ACASE CC0805
+C30
4.7μF
6.3V
C31
0.1μF
ACASE CC0805
+C32
4.7μF
6.3V
C33
0.1μF
SPI PORT
04862–106
Figure 108. SPI Port Interface, AD973x Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 62 of 72
AD973X EVALUATION BOARD PCB LAYOUT
04862-107
SILKSCREEN ERROR:
SPI AND PIN ARE REVERSED.
NOTE:
THE AD9736 IS
SOLDERED DIRECTLY
TO THE PCB. THE
SOCKET IS NOT INSTALLED.
Figure 109. CB Layout Top Placement, AD973x Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 63 of 72
04860-108
Figure 110. PCB Layout Layer 1, AD973x Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 64 of 72
04861-109
Figure 111. PCB Layout Layer 2, AD973x Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 65 of 72
04862-110
Figure 112. PCB Layout Layer 3, AD973x Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 66 of 72
014862-111
Figure 113. PCB Layout Layer 4, AD973x Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 67 of 72
04862-112
Figure 114. PCB Layout Bottom Placement, AD973x Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 68 of 72
04862-113
NOTES
1. MATERIAL: FOUR LAYER, FR4 GLASS–EPOXY LAMINATE
.062 +/- .007 THICK
1/4 OZ. COPPER CLAD – EXTERNAL LAYERS
PLATED TO 1 OUNCE
2 OZ. COPPER CLAD – INTERNAL LAYERS
2. PLATED THRU HOLES AND THE CONDUCTIVE PATTERN
ELECTROPLATED WITH .001 INCH MIN. THICK COPPER.
TERMINAL AREAS AND EXPOSED PLATED THRU HOLES TO B
E
COATED WITH SOLDER AND HOT AIR LEVELED.
3. PROCESSING TOLERANCES:
A. CONDUCTIVE PATTERN FRON TO BACK REGISTRATION
+/– .002 INCH TOTAL
B. MINIMUM ANNULAR RING SURROUNDING HOLES .002 INCH.
C. FINISHED CONDUCTIVE PATTERN +/– .0005 INCH
OF APERTURE SIZE.
4. WARP AND TWIST +/– .005 INCH PER INCH.
5. DIMENTIONS: ARE FOR THE FINISHED PART
6. SOLDER MASK: LIQUID PHOTO IMAGABLE SOLDER MASK
COLOR GREEN, BOTH
SIDES USING THE PATTERN(S) PROVIDED. NO MASK
IS PERMITTED ON THE EXPOSED AREAS. SOLDER
MASK TO ETCH REGISTRATION +/– .002 INCH TOTAL
7. SCREENING: SCREEN COMPONENT OUTLINES AND
NOMENCLATURE USING OPAQUE WHITE INK ON THE
PRIMARY AND SECONDARY SIDES (AS REQUIRED).
NOMENCLATURE SHALL BE LEGIBLE. SCREEN TO ETCH
REGISTRATION +/– .005 INCH TOTAL.
8. SURFACES: PUNCHED OR MACHINED SURFACES 125 MICRO
INCHES RMS MAX.
9. BREAK ALL SHARP EDGES .015 R MAX.
10. FABRICATION VENDOR TO ADD UL VENDOR ID NUMBER
IN THIS AREA ON THE SECONDARY SIDE
11. DO NOT DRILL. FOR GOLD PLATED SOCKETED VERSION ONLY.
Figure 115. PCB Fabrication Detail, AD973x Evaluation Board, Rev. F
AD9734/AD9735/AD9736
Rev. A | Page 69 of 72
OUTLINE DIMENSIONS
12.10
12.00 SQ
11.90
SEATING
PLANE
0.43 MAX
0.25 MIN
DETAIL A
0.55
0.50
0.45
0.12 MAX
COPLANARITY
1.00 MAX
0.85 MIN
BALL DIAMETER
0.80 BSC
0.80
REF
10.40
BSC SQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
14 13 12 1110 8 76321
95
4
A
1 CORNE
R
INDEX AREA
TOP VIEW
BALL A1
INDICATOR
DETAIL A
BOTTOM
VIEW
1.40 MAX
COMPLIANT TO JEDEC STANDARDS MO-205-AE.
Figure 116. 160-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-160-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9734BBC −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9734BBCRL −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9734BBCZ1 −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9734BBCZRL1 −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9735BBC −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9735BBCZ1 −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9735BBCRL −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9735BBCZRL1 −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9736BBC −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9736BBCRL −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9736BBCZ1 −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9736BBCZRL1 −40°C to +85°C 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-1
AD9734-EB Evaluation Board
AD9735-EB Evaluation Board
AD9736-EB Evaluation Board
1 Z = Pb-free part.
AD9734/AD9735/AD9736
Rev. A | Page 70 of 72
NOTES
AD9734/AD9735/AD9736
Rev. A | Page 71 of 72
NOTES
AD9734/AD9735/AD9736
Rev. A | Page 72 of 72
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04862-0-9/06(A)
