10-/12-/14-Bit, 1200 MSPS DACS AD9734/AD9735/AD9736 FEATURES FUNCTIONAL BLOCK DIAGRAM RESET A reduced-specification LVDS interface is utilized to achieve the high sample rate. The output current can be programmed over a range of 8.66 mA to 31.66 mA. The AD973x family is manufactured on a 0.18 m CMOS process and operates from 1.8 V and 3.3 V supplies for a total power consumption of 380 mW in bypass mode. It is supplied in a 160-lead chip scale ball grid array for reduced package parasitics. CLOCK DISTRIBUTION S3 2x BAND GAP C2 VREF IOUTA 14-, 12-, 10-BIT DAC CORE REFERENCE CURRENT C1S1 IOUTB S2 I120 Figure 1. PRODUCT HIGHLIGHTS 1. Low noise and intermodulation distortion (IMD) features enable high quality synthesis of wideband signals at intermediate frequencies up to 600 MHz. 2. Double data rate (DDR) LVDS data receivers support the maximum conversion rate of 1200 MSPS. 3. Direct pin programmability of basic functions or SPI port access offers complete control of all AD973x family functions. 4. Manufactured on a CMOS process, the AD973x family uses a proprietary switching technique that enhances dynamic performance. 5. The current output(s) of the AD9736 family are easily configured for single-ended or differential circuit topologies. GENERAL DESCRIPTION The AD9736, AD9735, and AD9734 are high performance, high frequency DACs that provide sample rates of up to 1200 MSPS, permitting multicarrier generation up to their Nyquist frequency. The AD9736 is the 14-bit member of the family, while the AD9735 and the AD9734 are the 12-bit and 10-bit members, respectively. They include a serial peripheral interface (SPI) port that provides for programming of many internal parameters and enables readback of status registers. C3 04862-001 DB[13:0]+ DB[13:0]- C2 C3 SYNCHRONIZER DATACLK_IN+ DATACLK_IN- C1 CONTROLLER SPI LVDS DRIVER DATACLK_OUT+ DATACLK_OUT- APPLICATIONS Broadband communications systems Cellular infrastructure (digital predistortion) Point-to-point wireless CMTS/VOD Instrumentation, automatic test equipment Radar, avionics DACCLK- DACCLK+ IRQ S1 S2 S3 SDIO SDO CSB SCLK LVDS RECEIVER Pin-compatible family Excellent dynamic performance AD9736: SFDR = 82 dBc at fOUT = 30 MHz AD9736: SFDR = 69 dBc at fOUT = 130 MHz AD9736: IMD = 87 dBc at fOUT = 30 MHz AD9736: IMD = 82 dBc at fOUT = 130 MHz LVDS data interface with on-chip 100 terminations Built-in self test LVDS sampling integrity LVDS-to-DAC data transfer integrity Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz) 1.8/3.3 V dual-supply operation Adjustable analog output 8.66 mA to 31.66 mA (RL = 25 to 50 ) On-chip 1.2 V reference 160-lead chip scale ball grid array (CSP_BGA) package Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. AD9734/AD9735/AD9736 TABLE OF CONTENTS Features .............................................................................................. 1 Full Scale Current (FSC) Registers (Reg. 2, Reg. 3)............... 31 Applications....................................................................................... 1 LVDS Controller (LVDS_CNT) Registers (Reg. 4, Reg. 5, Reg. 6) ............................................................... 31 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 Digital Specifications ................................................................... 6 AC Specifications.......................................................................... 8 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution.................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Location of Supply and Control Pins....................................... 16 Terminology .................................................................................... 17 Typical Performance Characteristics ........................................... 18 SYNC Controller (SYNC_CNT) Registers (Reg. 7, Reg. 8)............................................................................ 32 Cross Controller (CROS_CNT) Registers (Reg. 10, Reg. 11)........................................................................ 32 Analog Control (ANA_CNT) Registers (Reg. 14, Reg. 15)........................................................................ 33 Built-In Self Test Control (BIST_CNT) Registers (Reg. 17, Reg. 18, Reg. 19, Reg. 20, Reg. 21)........................... 33 Controller Clock Predivider (CCLK_DIV) Reading Register (Reg. 22) ....................................................................... 34 Theory of Operation ...................................................................... 35 Serial Peripheral Interface ............................................................. 36 General Operation of the Serial Interface............................... 36 Short Instruction Mode (8-Bit Instruction) ........................... 36 Long Instruction Mode (16-Bit Instruction).......................... 36 Serial Interface Port Pin Descriptions ..................................... 36 SCLK--Serial Clock............................................................... 36 AD9736 Static Linearity, 10 mA Full Scale ............................. 18 CSB--Chip Select................................................................... 37 AD9736 Static Linearity, 20 mA Full Scale ............................. 19 SDIO--Serial Data I/O.......................................................... 37 AD9736 Static Linearity, 30 mA Full Scale ............................. 20 AD9735 Static Linearity, 10 mA, 20 mA, 30 mA Full Scale...................................................................................... 21 AD9734 Static Linearity, 10 mA, 20 mA, 30 mA Full Scale...................................................................................... 22 AD9736 Power Consumption, 20 mA Full Scale....................... 23 AD9736 Dynamic Performance, 20 mA Full Scale................ 24 SDO--Serial Data Out .......................................................... 37 MSB/LSB Transfers .................................................................... 37 Notes on Serial Port Operation ................................................ 37 Pin Mode Operation .................................................................. 38 RESET Operation....................................................................... 38 Programming Sequence ............................................................ 38 AD9735, AD9734 Dynamic Performance, 20 mA Full Scale...................................................................................... 27 Interpolation Filter..................................................................... 39 AD973x WCDMA ACLR, 20 mA Full Scale .......................... 28 Data Interface Controllers......................................................... 39 SPI Register Map............................................................................. 29 LVDS Sample Logic.................................................................... 40 SPI Register Details ........................................................................ 30 LVDS Sample Logic Calibration............................................... 40 Mode Register (Reg. 0) .............................................................. 30 Operating the LVDS Controller in Manual Mode via the SPI Port ........................................................................................ 41 Interrupt Request Register (IRQ) (Reg. 1) .............................. 30 Rev. A | Page 2 of 72 AD9734/AD9735/AD9736 Operating the LVDS Controller in Surveillance and Auto Mode ...................................................................................41 SYNC Logic and Controller...........................................................42 SYNC Logic and Controller Operation....................................42 Operation in Manual Mode.......................................................42 Operation in Surveillance and Auto Modes ............................42 FIFO Bypass.................................................................................42 Digital Built-In Self Test (BIST) ....................................................44 Overview ......................................................................................44 AD973x BIST Procedure............................................................45 AD973x Expected BIST Signatures ..........................................45 Generating Expected Signatures ...............................................46 Cross Controller Registers .............................................................47 Analog Control Registers ...............................................................48 Band Gap Temperature Characteristic Trim Bits ...................48 Mirror Roll-Off Frequency Control .........................................48 Headroom Bits.............................................................................48 Voltage Reference........................................................................48 Applications Information...............................................................50 Driving the DACCLK Input ......................................................50 DAC Output Distortion Sources...................................................51 DC-Coupled DAC Output.............................................................52 DAC Data Sources ..........................................................................53 Input Data Timing ..........................................................................54 Synchronization Timing.................................................................55 Power Supply Sequencing ..............................................................56 AD973X Evaluation Board Schematics ........................................57 AD973X Evaluation Board PCB Layout.......................................62 Outline Dimensions........................................................................69 Ordering Guide ...........................................................................69 REVISION HISTORY 9/06--Rev. 0 to Rev. A Updated Format.................................................................. Universal Changes to Table 1 ............................................................................5 Changes to Table 2 ............................................................................6 Changes to Table 3 ............................................................................8 Inserted Table 5..................................................................................9 Replaced Pin Configuration and Function Descriptions Section ..............................................................................................10 Changes to Figure 27 to Figure 38 ................................................21 Changes to Figure 40 ......................................................................23 Changes to Table 9 ..........................................................................29 Changes to Figure 103 ....................................................................56 Changes to Figure 105 ....................................................................58 Changes to Figure 107 ....................................................................60 Changes to Figure 108 ....................................................................61 Changes to Figure 115 ....................................................................68 Updated Outline Dimensions........................................................69 Changes to Ordering Guide...........................................................69 4/05--Revision 0: Initial Version Rev. A | Page 3 of 72 AD9734/AD9735/AD9736 SPECIFICATIONS DC SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1x mode, 25 , 1% balanced load, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ANALOG OUTPUTS Offset Error Gain Error (With Internal Reference) Gain Error (Without Internal Reference) Full-Scale Output Current Output Compliance Range Output Resistance Output Capacitance TEMPERATURE DRIFT Offset Gain Reference Voltage 1 REFERENCE Internal Reference Voltage1 Output Resistance 2 ANALOG SUPPLY VOLTAGES AVDD33 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD33 DVDD18 SUPPLY CURRENTS 1x Mode, 1.2 GSPS IAVDD33 ICVDD18 IDVDD33 IDVDD18 FIR Bypass (1x) Mode 2x Mode, 1.2 GSPS IAVDD33 ICVDD18 IDVDD33 IDVDD18 FIR 2x Interpolation Filter Enabled Min AD9736 Typ 14 Max Min AD9735 Typ 12 Max Min AD9734 Typ 10 Max Unit Bits -5.6 -2.1 1.0 0.6 +5.6 +2.1 -1.5 -0.5 0.50 0.25 +1.5 +0.5 -0.5 -0.1 0.12 0.06 +0.5 +0.1 LSB LSB -0.01 0.005 1.0 +0.01 -0.01 0.005 1.0 +0.01 -0.01 0.005 1.0 +0.01 % FSR % FSR 1.0 8.66 -1.0 20.2 1.0 31.66 +1.0 8.66 -1.0 20.2 1.0 31.66 1.0 8.66 -1.0 20.2 % FSR 31.66 +1.0 10 1 10 1 10 1 mA V M pF 0 80 40 0 80 40 0 80 40 ppm/C ppm/C ppm/C 1.14 1.2 5 1.26 1.14 1.2 5 1.26 1.14 1.2 5 1.26 V k 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 V V 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 V V 25 47 10 122 380 25 47 10 122 380 25 47 10 122 380 mA mA mA mA mW 25 47 10 234 550 25 47 10 234 550 25 47 10 234 550 mA mA mA mA mW Rev. A | Page 4 of 72 AD9734/AD9735/AD9736 Parameter Static, No Clock IAVDD33 ICVDD18 IDVDD33 IDVDD18 FIR Bypass (1x) Mode Sleep Mode, No Clock IAVDD33 FIR Bypass (1x) Mode Power-Down Mode 3 IAVDD33 ICVDD18 IDVDD33 IDVDD18 FIR Bypass (1x) Mode Min AD9736 Typ Max 25 8 10 2 133 Min AD9735 Typ Max 25 8 10 2 133 Min AD9734 Typ Max 25 8 10 2 133 Unit mA mA mA mA mW 2.5 59 3.15 65 2.5 59 3.15 65 2.5 59 3.15 65 mA mW 0.01 0.02 0.01 0.01 0.12 0.13 0.12 0.12 0.11 1.24 0.01 0.02 0.01 0.01 0.12 0.13 0.12 0.12 0.11 1.24 0.01 0.02 0.01 0.01 0.12 0.13 0.12 0.12 0.11 1.24 mA mA mA mA mW 1 Default band gap adjustment (Reg. 0x0E <2:0> = 0x0). Use an external amplifier to drive any external load. 3 Typical wake-up time is 8 s with recommended 1 nF capacitor on VREF pin. 2 Rev. A | Page 5 of 72 AD9734/AD9735/AD9736 DIGITAL SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1x mode, 25 , 1% balanced load, unless otherwise noted. LVDS drivers and receivers are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter LVDS DATA INPUT (DB[13:0]+, DB[13:0]-) DB+ = VIA, DB- = VIB Input Voltage Range, VIA or VIB Input Differential Threshold, VIDTH Input Differential Hysteresis, VIDTHH - VIDTHL Receiver Differential Input Impedance, RIN LVDS Input Rate LVDS Minimum Data Valid Period (tMDE) LVDS CLOCK INPUT (DATACLK_IN+, DATACLK_IN-) DATACLK_IN+ = VIA, DATACLK_IN- = VIB Input Voltage Range, VIA or VIB Input Differential Threshold, 1 VIDTH Input Differential Hysteresis, VIDTHH - VIDTHL Receiver Differential Input Impedance, RIN Maximum Clock Rate LVDS CLOCK OUTPUT (DATACLK_OUT+, DATACLK_ OUT-) DATACLK_OUT+ = Voa, DATACLK_OUT- = Vob 100 Termination Output Voltage High, VOA or VOB Output Voltage Low, VOA or VOB Output Differential Voltage, |VOD| Output Offset Voltage, VOS Output Impedance, Single-Ended, RO RO Mismatch Between A and B, RO Change in |VOD| Between 0 and 1, |VOD| Change in VOS Between 0 and 1, VOS Output Current--Driver Shorted to Ground, ISA, ISB Output Current--Drivers Shorted Together, ISAB Power-Off Output Leakage, |IXA|, |IXB| Maximum Clock Rate DAC CLOCK INPUT (CLK+, CLK-) Input Voltage Range, CLK- or CLK+ Differential Peak-to-Peak Voltage Common-Mode Voltage Maximum Clock Rate SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (fSCLK, 1/tSCLK) Minimum Pulse Width High, tPWH Minimum Pulse Width Low, tPWL Minimum SDIO and CSB to SCLK Setup, tDS Minimum SCLK to SDIO Hold, tDH Maximum SCLK to Valid SDIO and SDO, tDV Minimum SCLK to Invalid SDIO and SDO, tDNV Rev. A | Page 6 of 72 Min Typ 825 -100 Max Unit 1575 +100 mV mV mV MSPS ps 20 80 1200 120 344 825 -100 1575 +100 20 80 600 120 1375 1025 150 1150 80 200 100 250 1250 120 10 25 25 20 4 10 600 0 400 300 1200 800 400 800 1600 500 20 20 20 10 5 20 5 mV mV mV MHz mV mV mV mV % mV mV mA mA mA MHz mV mV MHz MHz ns ns ns ns ns ns AD9734/AD9735/AD9736 Parameter INPUT (SDI, SDIO, SCLK, CSB) Voltage in High, VIH Voltage in Low, VIL Current in High, IIH Current in Low, IIL SDIO OUTPUT Voltage out High, VOH Voltage out Low, VOL Current out High, IOH Current out Low, IOL Min Max Unit -10 -10 0.8 +10 +10 V V A A 2.4 0 3.6 0.4 2.0 Typ 3.3 0 4 4 1 Refer to the Input Data Timing section for recommended LVDS differential drive levels. Rev. A | Page 7 of 72 V V mA mA AD9734/AD9735/AD9736 AC SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1x mode, 25 , 1% balanced load, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Maximum Update Rate SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 800 MSPS fOUT = 20 MHz fDAC = 1200 MSPS fOUT = 50 MHz fOUT = 100 MHz fOUT = 316 MHz fOUT = 550 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 1200 MSPS fOUT2 = fOUT + 1.25 MHz fOUT = 40 MHz fOUT = 50 MHz fOUT = 100 MHz fOUT = 316 MHz fOUT = 550 MHz NOISE SPECTRAL DENSITY (NSD) Single Tone fDAC = 1200 MSPS fOUT = 50 MHz fOUT = 100 MHz fOUT = 241MHz fOUT = 316 MHz fOUT = 550 MHz Eight-Tone fDAC = 1200 MSPS, 500 kHz Tone Spacing fOUT = 50 MHz fOUT = 100 MHz fOUT = 241MHz fOUT = 316 MHz fOUT = 550 MHz Min AD9736 Typ 1200 Max Min AD9735 Typ Max 1200 Min AD9734 Typ Max 1200 Unit MSPS 75 75 75 dBc 80 77 63 55 76 74 63 54 76 71 60 53 dBc dBc dBc dBc 88 85 84 70.5 65 84 84 81 67 60 83 83 79 66 60 dBc dBc dBc dBc dBc -158.5 -165 -164 -160.5 -158 -155 -162 -161 -159.5 -157 -155 -154 -154 -155 -152 -149 dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz -163.3 -166.5 -166 -165 -164 -162 -163 -163 -161.5 -162 -160 -154 -152 -150.5 -151 -150 dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz Rev. A | Page 8 of 72 AD9734/AD9735/AD9736 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD33 DVDD33 DVDD18 CVDD18 AVSS AVSS DVSS CLK+, CLK- PIN_MODE DATACLK_IN, DATACLK_OUT LVDS Data Inputs IOUTA, IOUTB I120, VREF, IPTAT IRQ, CSB, SCLK, SDO, SDIO, RESET Junction Temperature Storage Temperature With Respect to AVSS DVSS DVSS CVSS DVSS CVSS CVSS CVSS DVSS DVSS Min -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V Max +3.6 V +3.6 V +1.98 V +1.98 V +0.3 V +0.3 V +0.3 V CVDD18 + 0.18 V DVDD33 + 0.3 V DVDD33 + 0.3 V DVSS AVSS AVSS DVSS -0.3 V -1.0 V -0.3 V -0.3 V DVDD33 + 0.3 V AVDD33 + 0.3 V AVDD33 + 0.3 V DVDD33 + 0.3 V -65C 150C +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type 160-Lead Ball, CSP_BGA JA 1 31.2 Unit C/W 1 JA measurement in still air. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Note that this device in its current form does not meet Analog Devices' standard requirements for ESD as measured against the charged device model (CDM). As such, special care should be used when handling this product, especially in a manufacturing environment. Analog Devices will provide a more ESD-hardy product in the near future at which time this warning will be removed from this data sheet. Rev. A | Page 9 of 72 AD9734/AD9735/AD9736 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D DACCLK- E DACCLK+ F G H J K DB13 (MSB) L DB12 DB0 (LSB) M DB11 N 04862-005 DB9 DB10 DB8 DB7 DB6 DATACLK_IN DB5 DATACLK_OUT DB4 DB3 DB2 DB1 P Figure 2. AD9736 Digital LVDS Input, Clock I/O (Top View) Table 6. AD9736 Pin Function Descriptions Pin No. A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3 A4, A5, A6, A9, A10, A11, B4, B5, B6, B9, B10, B11, C4, C5, C6, C9, C10, C11, D4, D5, D6, D9, D10, D11 A7, B7, C7, D7 A8, B8, C8, D8 A12, A13, B12, B13, C12, C13, D12, D13 A14 B14 Mnemonic CVDD18 AVSS Description 1.8 V Clock Supply. Analog Supply Ground. IOUTB IOUTA AVDD33 DNC I120 C14 VREF D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4 D14 CVSS IPTAT E1, F1 E11, E12, F11, F12, G11, G12 E13 DACCLK-/DACCLK+ AVSS IRQ/UNSIGNED E14 RESET/PD F13 CSB/2x F14 G13 G14 H1, H2, H3, H4, H11, H12, H13, H14, J1, J2, J3, J4, J11, J12, J13, J14 SDIO/FIFO SCLK/FSC0 SDO/FSC1 DVDD18 DAC Negative Output. 10 mA to 30 mA full-scale output current. DAC Positive Output. 10 mA to 30 mA full-scale output current. 3.3 V Analog Supply. Do Not Connect. Nominal 1.2 V Reference. Tie to analog ground via 10 k resistor to generate a 120 A reference current. Band Gap Voltage Reference I/O. Tie to analog ground via 1 nF capacitor; output impedance is approximately 5 k. Clock Supply Ground. Factory Test Pin. Output current, proportional to absolute temperature, is approximately 10 A at 25C with a slope of approximately 20 nA/C. Negative/Positive DAC Clock Input (DACCLK). Analog Supply Ground Shield. Tie to AVSS at the DAC. If PIN_MODE = 0, IRQ: Active low open-drain interrupt request output, pull up to DVDD33 with 10 k resistor. If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = twos complement input data format, 1 = unsigned. If PIN_MODE = 0, RESET: 1 resets the AD9736. If PIN_MODE = 1, PD: 1 puts the AD9736 in the power-down state. See the Serial Peripheral Interface section and the Pin Mode Operation section for pin description. See the Pin Mode Operation section for pin description. See the Pin Mode Operation section for pin description. See the Pin Mode Operation section for pin description. 1.8 V Digital Supply. Rev. A | Page 10 of 72 AD9734/AD9735/AD9736 Pin No. K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6, L9, L10, L11, L12, M3, M4, M5, M6, M9, M10, M11, M12 K13, K14 Mnemonic DVSS Description Digital Supply Ground. DB<13>-/DB<13>+ L1 PIN_MODE L7, L8, M7, M8, N7, N8, P7, P8 L13, L14 DVDD33 DB<12>-/DB<12>+ M2, M1 DB<0>-/DB<0>+ M13, M14 DB<11>-/DB<11>+ N1, P1 DB<1>-/DB<1>+ N2, P2 DB<2>-/DB<2>+ N3, P3 DB<3>-/DB<3>+ N4, P4 DB<4>-/DB<4>+ N5, P5 DB<5>-/DB<5>+ N6, P6 N10, P10 DATACLK_OUT-/ DATACLK_OUT+ DATACLK_IN-/ DATACLK_IN+ DB<6>-/DB<6>+ Negative/Positive Data Input Bit 13 (MSB). Conforms to IEEE-1596 reduced range link. 0 = SPI Mode. SPI is enabled. 1 = PIN Mode. SPI is disabled; direct pin control. 3.3 V Digital Supply. Negative/Positive Data Input Bit 12. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 11. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Output Clock. Conforms to IEEE-1596 reduced range link. N11, P11 DB<7>-/DB<7>+ N12, P12 DB<8>-/DB<8>+ N13, P13 DB<9>-/DB<9>+ N14, P14 DB<10>-/DB<10>+ N9, P9 Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 9. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 10. Conforms to IEEE-1596 reduced range link. Rev. A | Page 11 of 72 AD9734/AD9735/AD9736 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D DACCLK- E DACCLK+ F G H J K DB11 (MSB) L DB10 DB9 NC M N 04862-115 DB8 DB7 DB6 DB5 DB4 DATACLK_IN DB3 DATACLK_OUT DB2 DB1 NC DB0 (LSB) P Figure 3. AD9735 Digital LVDS Input, Clock I/O (Top View) Table 7. AD9735 Pin Function Descriptions Pin No. A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3 A4, A5, A6, A9, A10, A11, B4, B5, B6, B9, B10, B11, C4, C5, C6, C9, C10, C11, D4, D5, D6, D9, D10, D11 A7, B7, C7, D7 A8, B8, C8, D8 A12, A13, B12, B13, C12, C13, D12, D13 A14 B14 Mnemonic CVDD18 AVSS Description 1.8 V Clock Supply. Analog Supply Ground. IOUTB IOUTA AVDD33 DNC I120 C14 VREF D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4 D14 CVSS IPTAT E1, F1 E11, E12, F11, F12, G11, G12 E13 DACCLK-/DACCLK+ AVSS IRQ/UNSIGNED E14 RESET/PD F13 CSB/2x F14 G13 G14 H1, H2, H3, H4, H11, H12, H13, H14, J1, J2, J3, J4, J11, J12, J13, J14 K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6, L9, L10, L11, L12, M3, M4, M5, M6, M9, M10, M11, M12 SDIO/FIFO SCLK/FSC0 SDO/FSC1 DVDD18 DAC Negative Output. 10 mA to 30 mA full-scale output current. DAC Positive Output. 10 mA to 30 mA full-scale output current. 3.3 V Analog Supply. Do Not Connect. Nominal 1.2 V Reference. Tie to analog ground via 10 k resistor to generate a 120 A reference current. Band Gap Voltage Reference I/O. Tie to analog ground via 1 nF capacitor; output impedance approximately 5 k. Clock Supply Ground. Factory Test Pin; Output current, proportional to absolute temperature, is approximately 10 A at 25C with a slope of approximately 20 nA/C. Negative/Positive DAC Clock Input (DACCLK). Analog Supply Ground Shield. Tie to AVSS at the DAC. If PIN_MODE = 0, IRQ: Active low open-drain interrupt request output, pull up to DVDD33 with 10 k resistor. If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = twos complement input data format, 1 = unsigned. If PIN_MODE = 0, RESET: 1 resets the AD9735. If PIN_MODE = 1, PD: 1 puts the AD9735 in the power-down state. See the Serial Peripheral Interface section and the Pin Mode Operation section for pin description. See the Pin Mode Operation section for pin description. See the Pin Mode Operation section for pin description. See the Pin Mode Operation section for pin description. 1.8 V Digital Supply. DVSS Digital Supply Ground. Rev. A | Page 12 of 72 AD9734/AD9735/AD9736 Pin No. K13, K14 Mnemonic DB<11>-/DB<11>+ L1 PIN_MODE L7, L8, M7, M8, N7, N8, P7, P8 L13, L14 DVDD33 DB<10>-/DB<10>+ M1, M2 M13, M14 NC DB<9>-/DB<9>+ N1, P1 N2, P2 NC DB<0>-/DB<0>+ N3, P3 DB<1>-/DB<1>+ N4, P4 DB<2>-/DB<2>+ N5, P5 DB<3>-/DB<3>+ N6, P6 N10, P10 DATACLK_OUT-/ DATACLK_OUT+ DATACLK_IN-/ DATACLK_IN+ DB<4>-/DB<4>+ N11, P11 DB<5>-/DB<5>+ N12, P12 DB<6>-/DB<6>+ N13, P13 DB<7>-/DB<7>+ N14, P14 DB<8>-/DB<8>+ N9, P9 Description Negative/Positive Data Input Bit 11 (MSB). Conforms to IEEE-1596 reduced range link. 0 = SPI Mode. SPI is enabled. 1 = PIN Mode. SPI disabled; direct pin control. 3.3 V Digital Supply. Negative/Positive Data Input Bit 10. Conforms to IEEE-1596 reduced range link. No Connect. Negative/Positive Data Input Bit 9. Conforms to IEEE-1596 reduced range link. No Connect. Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Output Clock. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced range link. Rev. A | Page 13 of 72 AD9734/AD9735/AD9736 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D DACCLK- E DACCLK+ F G H J K DB9 (MSB) L DB8 NC M DB7 N 04862-114 DB6 DB5 DB4 DB3 DB2 DATACLK_IN DB1 DATACLK_OUT NC DB0 (LSB) NC NC P Figure 4. AD9734 Digital LVDS Input, Clock I/O (Top View) Table 8. AD9734 Pin Function Descriptions Pin No. A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3 A4, A5, A6, A9, A10, A11, B4, B5, B6, B9, B10, B11, C4, C5, C6, C9, C10, C11, D4, D5, D6, D9, D10, D11 A7, B7, C7, D7 A8, B8, C8, D8 A12, A13, B12, B13, C12, C13, D12, D13 A14 B14 Mnemonic CVDD18 AVSS Description 1.8 V Clock Supply. Analog Supply Ground. IOUTB IOUTA AVDD33 DNC I120 C14 VREF D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4 D14 CVSS IPTAT E1, F1 E11, E12, F11, F12, G11, G12 E13 DACCLK-/DACCLK+ AVSS IRQ/UNSIGNED E14 RESET/PD F13 CSB/2x F14 G13 G14 H1, H2, H3, H4, H11, H12, H13, H14, J1, J2, J3, J4, J11, J12, J13, J14 K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6, L9, L10, L11, L12, M3, M4, M5, M6, M9, M10, M11, M12 SDIO/FIFO SCLK/FSC0 SDO/FSC1 DVDD18 DAC Negative Output. 10 mA to 30 mA full-scale output current. DAC Positive Output. 10 mA to 30 mA full-scale output current. 3.3 V Analog Supply. Do Not Connect. Nominal 1.2 V Reference. Tie to analog ground via 10 k resistor to generate a 120 A reference current. Band Gap Voltage Reference I/O. Tie to analog ground via 1 nF capacitor; output impedance approximately 5 k. Clock Supply Ground. Factory Test Pin. Output current, proportional to absolute temperature, is approximately 10 A at 25C with a slope of approximately 20 nA/C. Negative/Positive DAC Clock Input (DACCLK). Analog Supply Ground Shield. Tie to AVSS at the DAC. If PIN_MODE = 0, IRQ: Active low open-drain interrupt request output, pull up to DVDD33 with 10 k resistor. If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = twos complement input data format, 1 = unsigned. If PIN_MODE = 0, RESET: 1 resets the AD9734. If PIN_MODE = 1, PD: 1 puts the AD9734 in the power-down state. See the Serial Peripheral Interface section and the Pin Mode Operation section for pin description. See the Pin Mode Operation section for pin description. See the Pin Mode Operation section for pin description. See the Pin Mode Operation section for pin description. 1.8 V Digital Supply. DVSS Digital Supply Ground. Rev. A | Page 14 of 72 AD9734/AD9735/AD9736 Pin No. K13, K14 Mnemonic DB<9>-/DB<9>+ L1 PIN_MODE L7, L8, M7, M8, N7, N8, P7, P8 L13, L14 DVDD33 DB<8>-/DB<8>+ M1, M2 M13, M14 NC DB<7>-/DB<7>+ N1, P1 N2, P2 N3, P3 N4, P4 NC NC NC DB<0>-/DB<0>+ N5, P5 DB<1>-/DB<1>+ N6, P6 N10, P10 DATACLK_OUT-/ DATACLK_OUT+ DATACLK_IN-/ DATACLK_IN+ DB<2>-/DB<2>+ N11, P11 DB<3>-/DB<3>+ N12, P12 DB<4>-/DB<4>+ N13, P13 DB<5>-/DB<5>+ N14, P14 DB<6>-/DB<6>+ N9, P9 Description Negative/Positive Data Input Bit 9 (MSB). Conforms to IEEE-1596 reduced range link. 0 = SPI Mode. SPI is enabled. 1 = PIN Mode. SPI is disabled; direct pin control. 3.3 V Digital Supply. Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced range link. No Connect. Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced range link. No Connect. No Connect. No Connect. Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Output Clock. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced range link. Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced range link. Rev. A | Page 15 of 72 AD9734/AD9735/AD9736 LOCATION OF SUPPLY AND CONTROL PINS 5 6 7 8 9 10 11 12 13 14 1 A A B B C C D D E E F F G G H H J J K K L L M M N N P P AVDD33, 3.3V, ANALOG SUPPLY AVSS, ANALOG SUPPLY GROUND SHIELD 2 3 4 5 6 7 8 4 5 6 7 8 9 10 11 12 13 14 DVDD33, 3.3V DIGITAL SUPPLY DVSS DIGITAL SUPPLY GROUND Figure 7. Digital Supply Pins (Top View) Figure 5. Analog Supply Pins (Top View) 1 3 DVDD18, 1.8V DIGITAL SUPPLY 04862-002 AVSS, ANALOG SUPPLY GROUND 2 9 10 11 12 13 14 A B 1 C 2 3 4 5 6 7 8 9 10 11 12 13 14 D A E B I120 F C VREF G D IPTAT H E J IRQ F K CSB SDIO G L SCLK SDO H J N K P PIN_MODE L CVDD18, 1.8V CLOCK SUPPLY CVSS, CLOCK SUPPLY GROUND 04862-003 M M 2x FIFO N FSC0 FSC1 Figure 8. Analog I/O and SPI Control Pins (Top View) Rev. A | Page 16 of 72 RESET PIN_MODE = 1, SPI DISABLED PD UNSIGNED P Figure 6. Clock Supply Pins (Top View) PIN_MODE = 0, SPI ENABLED 04862-006 4 04862-004 3 IOUTA 2 IOUTB 1 AD9734/AD9735/AD9736 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Differential Nonlinearity (DNL) The measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per C. For reference drift, the drift is reported in ppm per C. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Multitone Power Ratio The spurious-free dynamic range containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. Rev. A | Page 17 of 72 AD9734/AD9735/AD9736 TYPICAL PERFORMANCE CHARACTERISTICS AD9736 STATIC LINEARITY, 10 mA FULL SCALE 1.00 1.0 0.75 0.8 0.50 0.6 0.25 0.4 ERROR (LSB) ERROR (LSB) 0 -0.25 -0.50 -0.75 -1.00 0.2 0 -0.2 -0.4 -1.25 -0.6 -1.50 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE -1.0 04862-008 -2.00 0 Figure 9. AD9736 INL, -40C, 10 mA FS 2048 4096 6144 8192 10240 12288 14336 16384 CODE 04862-010 -0.8 -1.75 Figure 12. AD9736 DNL, -40C, 10 mA FS 1.00 1.0 0.75 0.8 0.50 0.6 0.25 0.4 ERROR (LSB) ERROR (LSB) 0 -0.25 -0.50 -0.75 -1.00 0.2 0 -0.2 -0.4 -1.25 -0.6 -1.50 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE -1.0 04862-008 -2.00 0 Figure 10. AD9736 INL, 25C, 10 mA FS 2048 4096 6144 8192 10240 12288 14336 16384 CODE 04862-011 -0.8 -1.75 Figure 13. AD9736 DNL, 25C, 10 mA FS 1.00 1.0 0.75 0.8 0.50 0.6 0.25 0.4 ERROR (LSB) -0.25 -0.50 -0.75 -1.00 0.2 0 -0.2 -0.4 -1.25 -0.6 -1.50 -2.00 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE Figure 11. AD9736 INL, 85C, 10 mA FS -1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE Figure 14. AD9736 DNL, 85C, 10 mA FS Rev. A | Page 18 of 72 04862-012 -0.8 -1.75 04862-009 ERROR (LSB) 0 AD9734/AD9735/AD9736 0.6 0.8 0.5 0.6 0.4 0.4 0.3 0.2 0.2 0 -0.2 -0.4 -0.6 0.1 0 -0.1 -0.2 -0.8 -0.3 -1.0 -0.4 -1.2 -0.5 2048 4096 6144 8192 10240 12288 14336 16384 CODE -0.6 0 0.6 0.8 0.5 0.6 0.4 0.4 0.3 0.2 0.2 ERROR (LSB) 1.0 0 -0.2 -0.4 -0.6 0 -0.2 -0.3 -0.4 -1.2 -0.5 2048 4096 6144 8192 10240 12288 14336 16384 CODE -0.6 0 0.6 0.8 0.5 0.6 0.4 0.4 0.3 0.2 0.2 ERROR (LSB) 1.0 0 -0.2 -0.4 -0.6 -0.2 -0.4 -1.2 -0.5 6144 8192 10240 12288 14336 16384 CODE 8192 10240 12288 14336 16384 CODE 0 -0.3 4096 6144 -0.1 -1.0 2048 4096 0.1 -0.8 0 2048 Figure 19. AD9736 DNL, 25C, 20 mA FS 04862-015 ERROR (LSB) Figure 16. AD9736 INL, 25C, 20 mA FS -1.4 8192 10240 12288 14336 16384 CODE -0.1 -1.0 0 6144 0.1 -0.8 -1.4 4096 Figure 18. AD9736 DNL, -40C, 20 mA FS 04862-014 ERROR (LSB) Figure 15. AD9736 INL, -40C, 20 mA FS 2048 04862-017 0 Figure 17. AD9736 INL, 85C, 20 mA FS -0.6 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE Figure 20. AD9736 DNL, 85C, 20 mA FS Rev. A | Page 19 of 72 04862-018 -1.4 04862-016 ERROR (LSB) 1.0 04862-013 ERROR (LSB) AD9736 STATIC LINEARITY, 20 mA FULL SCALE AD9734/AD9735/AD9736 AD9736 STATIC LINEARITY, 30 mA FULL SCALE 2.0 0.6 0.5 1.5 0.4 0.3 0.2 0.5 ERROR (LSB) 0 -0.5 -1.0 0 -0.1 -0.2 -0.3 -0.4 -1.5 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE -0.6 0 Figure 21. AD9736 INL, -40C, 30 mA FS 6144 8192 10240 12288 14336 16384 CODE 0.6 0.5 1.5 0.4 1.0 0.3 0.2 0.5 ERROR (LSB) ERROR (LSB) 4096 Figure 24. AD9736 DNL, -40C, 30 mA FS 2.0 0 -0.5 -1.0 0.1 0 -0.1 -0.2 -0.3 -0.4 -1.5 -0.5 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE -0.6 04862-020 -2.0 2048 04862-022 -0.5 04862-019 -2.0 0.1 0 Figure 22. AD9736 INL, 25C, 30 mA FS 2048 4096 6144 8192 10240 12288 14336 16384 CODE 04862-023 ERROR (LSB) 1.0 Figure 25. AD9736 DNL, 25C, 30 mA FS 2.0 1.0 1.5 0.5 1.0 0.5 0 0 ERROR (LSB) 0 0 -0.5 -0.5 -1.0 -0.5 -1.0 -1.5 -2.0 -1.0 -1.5 -2.5 -2.0 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE Figure 23. AD9736 INL, 85C, 30 mA FS -3.0 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE Figure 26. AD9736 DNL, 85C, 30 mA FS Rev. A | Page 20 of 72 04862-024 -1.5 04862-021 ERROR (LSB) 0 AD9734/AD9735/AD9736 AD9735 STATIC LINEARITY, 10 mA, 20 mA, 30 mA FULL SCALE 0.4 0.100 0.050 0.3 0 ERROR (LSB) ERROR (LSB) 0.2 0.1 -0.050 -0.100 0 -0.150 -0.1 512 1024 1536 2048 2560 3072 3584 4096 CODE -0.250 0 512 1024 1536 2048 2560 3072 3584 4096 3584 4096 3584 4096 CODE Figure 27. AD9735 INL, 25C, 10 mA FS 04862-028 0 04862-025 -0.2 -0.200 Figure 30. AD9735 DNL, 25C, 10 mA FS 0.15 0.100 0.075 0.10 0.050 0.05 ERROR (LSB) ERROR (LSB) 0.025 0 -0.05 0 -0.025 -0.050 -0.10 -0.075 -0.15 512 1024 1536 2048 2560 3072 3584 4096 CODE -0.125 0 1536 2048 2560 3072 Figure 31. AD9735 DNL, 25C, 20 mA FS 0.2 0.050 0.1 0 -0.050 0 -1.000 ERROR (LSB) -0.1 -0.2 -0.3 -1.150 -0.200 -0.250 -0.4 -0.300 -0.5 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 Figure 29. AD9735 INL, 25C, 30 mA FS -0.400 0 512 1024 1536 2048 CODE 2560 3072 Figure 32. AD9735 DNL, 25C, 30 mA FS Rev. A | Page 21 of 72 04862-030 -0.350 04862-027 ERROR (LSB) 1024 CODE Figure 28. AD9735 INL, 25C, 20 mA FS -0.6 512 04862-029 0 04862-026 -0.20 -0.100 AD9734/AD9735/AD9736 AD9734 STATIC LINEARITY, 10 mA, 20 mA, 30 mA FULL SCALE 0.04 0.03 0.02 0.02 ERROR (LSB) 0.04 0 0.01 0 -0.04 -0.01 -0.06 0 128 256 384 512 640 768 896 1024 CODE 04862-031 -0.02 -0.02 0 128 256 384 512 640 768 896 1024 CODE 04862-034 ERROR (LSB) 0.06 Figure 36. AD9734 DNL, 25C, 10 mA FS Figure 33. AD9734 INL, 25C, 10 mA FS 0.03 0.03 0.02 0.02 0.01 0.01 ERROR (LSB) -0.01 -0.02 0 -0.01 -0.03 -0.04 -0.02 0 128 256 384 512 CODE 640 768 896 1024 -0.03 04862-032 -0.06 0 128 256 384 512 640 768 896 1024 896 1024 CODE 04862-035 -0.05 Figure 37. AD9734 DNL, 25C, 20 mA FS Figure 34. AD9734 INL, 25C, 20 mA FS 0.01 0.06 0.04 0 0.02 -0.01 ERROR (LSB) 0 -0.02 -0.04 -0.06 -0.02 -0.03 -0.04 -0.08 -0.12 0 128 256 384 512 640 768 CODE 896 1024 -0.06 0 128 256 384 512 640 768 CODE Figure 38. AD9734 DNL, 25C, 30 mA FS Figure 35. AD9734 INL, 25C, 30 mA FS Rev. A | Page 22 of 72 04862-036 -0.05 -0.10 04862-033 ERROR (LSB) ERROR (LSB) 0 AD9734/AD9735/AD9736 AD9736 POWER CONSUMPTION, 20 mA FULL SCALE 0.50 0.7 0.45 0.6 TOTAL 0.40 TOTAL 0.5 0.25 0.20 DVDD18 0.15 DVDD18 0.3 CVDD18 0.2 AVDD33 0.10 DVDD33 0 250 500 750 fDAC (MHz) 1000 1250 1500 0 DVDD33 AVDD33 0.1 CVDD18 0.05 0 0.4 0 250 500 750 1000 1250 1500 fDAC (MHz) Figure 40. AD9736, 2x Interpolation Mode Power vs. fDAC at 25C Figure 39. AD9736 1x Mode Power vs. fDAC at 25C Rev. A | Page 23 of 72 04862-038 POWER (W) 0.30 04862-037 POWER (W) 0.35 AD9734/AD9735/AD9736 80 75 800MSPS IMD (dBc) SFDR (dBc) 70 65 60 1.2GSPS 1GSPS 50 0 50 100 150 200 250 300 350 400 450 500 550 600 fOUT (MHz) 04862-039 55 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 0 50 100 150 200 Figure 41. AD9736 SFDR vs. fOUT over fDAC at 25C 300 350 400 450 500 550 Figure 44. AD9736 IMD vs. fOUT over 50 Parts, 25C,1.2 GSPS 80 90 85 75 1GSPS 80 70 75 IMD (dBc) SFDR (dBc) 250 fOUT (MHz) 04862-042 AD9736 DYNAMIC PERFORMANCE, 20 mA FULL SCALE 65 +85C 60 70 800MSPS 65 1.2GSPS -40C 60 +25C 55 50 100 150 200 250 300 350 400 450 500 550 600 fOUT (MHz) 50 0 100 200 300 400 500 600 fOUT (MHz) Figure 42. AD9736 SFDR vs. fOUT over Temperature 04862-043 0 04862-040 50 55 Figure 45. AD9736 IMD vs. fOUT over fDAC at 25C 90 78 76 85 74 80 72 75 IMD (dBc) 68 66 64 62 -40C 70 +25C +85C 65 60 60 58 56 52 0 50 100 150 200 250 300 350 fOUT (MHz) 400 450 500 550 50 0 100 200 300 400 500 600 fOUT (MHz) Figure 43. AD9736 SFDR vs. fOUT over 50 Parts, 25C, 1.2 GSPS Figure 46. AD9736 IMD vs. fOUT over Temperature, 1.2 GSPS Rev. A | Page 24 of 72 04862-044 55 54 04862-041 SFDR (dBc) 70 AD9734/AD9735/AD9736 95 90 90 85 IMD 0dBFS 80 75 IMD (dBc) SFDR 75 70 -6dBFS 65 65 60 60 55 0 10 fOUT (MHz) 100 50 0 300 400 500 600 Figure 50. AD9736 IMD vs. fOUT over AOUT, 25C, 1.2 GSPS 90 90 THIRD-ORDER IMD 85 85 SFDR 80 SFDR, IMD (dBc) 75 70 65 75 70 SFDR_1x 65 60 60 55 55 0 50 100 150 200 fOUT (MHz) SFDR_2x 80 250 300 350 50 04862-046 SFDR, IMID (dBc) 200 fOUT (MHz) Figure 47. AD9736 Low Frequency IMD and SFDR vs. fOUT, 25C, 1.2 GSPS 50 100 Figure 48. AD9736 IMD and SFDR vs. fOUT, 25C, 1.2 GSPS, 2x Interpolation 0 50 100 150 200 250 300 350 fOUT (MHz) 04862-049 55 -12dBFS 70 04862-048 80 04862-045 IMD AND SFDR (dBc) 85 Figure 51. AD9736 SFDR vs. fOUT, 25C, 1.2 GSPS, 1x and 2x Interpolation 80 90 75 85 THIRD-ORDER IMD_1x 70 80 -12dBFS 55 -6dBFS 70 65 50 60 45 55 40 0 100 200 300 fOUT (MHz) 400 500 600 Figure 49. AD9736 SFDR vs. fOUT over AOUT, 25C, 1.2 GSPS 50 04862-047 SFDR (dBc) 0dBFS 60 75 0 50 100 150 200 fOUT (MHz) 250 300 350 04862-050 SFDR, IMD (dBc) THIRD-ORDER IMD_2x 65 Figure 52. AD9736 IMD vs. fOUT, 25C, 1.2 GSPS, 1x and 2x Interpolation Rev. A | Page 25 of 72 AD9734/AD9735/AD9736 -150 -150 -152 -152 -154 -154 -156 1.2GSPS -160 -162 -160 -164 -166 -166 -168 -168 0 100 200 300 fOUT (MHz) 400 500 600 -170 -40C +25C 0 100 200 300 400 500 600 fOUT (MHz) Figure 56. AD9736 8-Tone NSD vs. fOUT over Temperature, 1.2 GSPS Figure 53. AD9736 1-Tone NSD vs. fOUT over fDAC, 25C -150 -157 -152 -158 -154 -159 -156 NSD (dBm/Hz) +85C -158 -40C -160 +25C -162 -164 -160 -161 -162 -163 -164 -166 -165 -168 100 200 300 fOUT (MHz) 400 500 600 0 50 100 150 200 250 300 350 400 450 500 550 fOUT (MHz) Figure 54. AD9736 1-Tone NSD vs. fOUT over Temperature, 1.2 GSPS 04862-055 -166 0 04862-052 -170 +85C -162 -164 -170 NSD (dBm/Hz) -158 04862-054 -158 NSD (dBm/Hz) 1GSPS 04862-051 NSD (dBm/Hz) -156 Figure 57. AD9736 1-Tone NSD vs. fOUT over 50 Parts, 1.2 GSPS, 25C -150 -161 -152 -154 -162 NSD (dBm/Hz) -158 -160 -162 1GSPS -163 -164 -165 -164 1.2GSPS -166 -166 -170 0 100 200 300 fOUT (MHz) 400 500 600 Figure 55. AD9736 8-Tone NSD vs. fOUT over fDAC, 25C -167 0 50 100 150 200 250 300 fOUT (MHz) 350 400 450 500 550 04862-056 -168 04862-053 NSD (dBm/Hz) -156 Figure 58. AD9736 8-Tone NSD vs. fOUT over 50 Parts, 1.2 GSPS, 25C Rev. A | Page 26 of 72 AD9734/AD9735/AD9736 AD9735, AD9734 DYNAMIC PERFORMANCE, 20 mA FULL SCALE 80 90 85 75 1GSPS 80 800MSPS 75 IMD (dBc) SFDR (dBc) 70 65 60 800MSPS 70 1.2GSPS 65 1GSPS 60 0 50 100 150 200 250 300 350 400 450 500 550 600 fOUT (MHz) 50 04862-060 50 55 1.2GSPS 0 Figure 59. AD9735 SFDR vs. fOUT over fDAC, 1.2 GSPS 50 100 150 200 250 300 350 400 450 500 550 600 fOUT (MHz) 04862-063 55 Figure 62. AD9734 IMD vs. fOUT over fDAC, 1.2 GSPS 80 -150 -152 75 -154 -156 NSD (dBc/Hz) 800MSPS 65 1GSPS 60 -160 -162 8 TONES -166 1.2GSPS 0 50 100 150 200 250 300 350 400 450 500 550 600 fOUT (MHz) -168 -170 0 50 Figure 60. AD9734 SFDR vs. fOUT over fDAC, 1.2 GSPS Figure 63. AD9735 NSD vs. fOUT, 1.2 GSPS 90 -145 1GSPS -147 85 -149 80 800MSPS 8 TONES -151 NSD (dBc/Hz) 75 70 65 1.2GSPS -153 1 TONE -155 -157 -159 60 -161 55 0 50 100 150 200 250 300 350 400 450 500 550 600 fOUT (MHz) -165 0 50 100 150 200 250 300 350 400 450 500 550 600 fOUT (MHz) Figure 64. AD9734 NSD vs. fOUT, 1.2 GSPS Figure 61. AD9735 IMD vs. fOUT over fDAC, 1.2 GSPS Rev. A | Page 27 of 72 04862-065 50 -163 04862-062 IMD (dBc) 100 150 200 250 300 350 400 450 500 550 600 fOUT (MHz) 04862-064 55 50 1 TONE -158 -164 04862-061 SFDR (dBc) 70 AD9734/AD9735/AD9736 AD973x WCDMA ACLR, 20 mA FULL SCALE REF -22.75dBm #AVG LOG 10dB/ 04862-057 #ATTEN 6dB PAVG 10 W1 S2 CENTER 134.83MHz #RES BW 30kHz RMS RESULTS CARRIER POWER -10.72dBm/ 3.84000MHz VBW 300kHz OFFSET FREQ 5.00MHz 10.0MHz 15.0MHz REF BW 3.840MHz 3.840MHz 3.884MHz LOWER dBc dBm -81.65 -92.37 -82.06 -92.78 -82.11 -92.83 SPAN 33.88MHz SWEEP 109.9ms (601pts) UPPER dBc -81.39 -82.43 -82.39 dBm -92.11 -93.16 -93.11 Figure 65. AD9736 WCDMA Carrier at 134.83 MHz, fDAC = 491.52 MSPS REF -22.75dBm #AVG LOG 10dB/ 04862-058 #ATTEN 6dB PAVG 10 S2 CENTER 134.83MHz #RES BW 30kHz RMS RESULTS CARRIER POWER -10.72dBm/ 3.84000MHz VBW 300kHz OFFSET FREQ 5.00MHz 10.0MHz 15.0MHz REF BW 3.840MHz 3.840MHz 3.884MHz LOWER dBc dBm -80.32 -91.10 -81.13 -91.91 -80.43 -91.21 SPAN 33.88MHz SWEEP 109.9ms (601pts) UPPER dBc -80.60 -80.75 -81.36 dBm -91.38 -91.53 -92.13 Figure 66. AD9735 WCDMA Carrier at 134.83 MHz, fDAC = 491.52 MSPS REF -22.75dBm #AVG LOG 10dB/ 04862-059 #ATTEN 6dB PAVG 10 S2 CENTER 134.83MHz #RES BW 30kHz RMS RESULTS CARRIER POWER -10.76dBm/ 3.84000MHz VBW 300kHz OFFSET FREQ 5.00MHz 10.0MHz 15.0MHz SPAN 33.88MHz SWEEP 109.9ms (601pts) REF BW 3.840MHz 3.840MHz 3.884MHz LOWER dBc dBm -71.07 -81.83 -70.55 -81.31 -70.79 -81.56 UPPER dBc -71.23 -71.42 -71.25 dBm -81.99 -82.19 -82.01 Figure 67. AD9734 WCDMA Carrier at 134.83 MHz, fDAC = 491.52 MSPS Rev. A | Page 28 of 72 AD9734/AD9735/AD9736 SPI REGISTER MAP Write 0 to unspecified or reserved bit locations. Reading these bits returns unknown values. Table 9. SPI Register Map Reg. Addr. Dec. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Hex. 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default (Hex) Pin Mode (Hex) MODE IRQ FSC_1 FSC_2 LVDS_CNT1 LVDS_CNT2 LVDS_CNT3 SYNC_CNT1 SYNC_CNT2 RESERVED CROS_CNT1 CROS_CNT2 RESERVED RESERVED ANA_CNT1 ANA_CNT2 RESERVED BIST_CNT BIST<7:0> BIST<15:8> BIST<23:16> BIST<31:24> CCLK_DIV SDIO_DIR LVDS SLEEP FSC<7> MSD<3> SD<3> LSURV FIFOSTAT3 SSURV LSBFIRST SYNC RESET CROSS LONG_INS RESERVED 2X MODE IE_LVDS FIFO MODE IE_SYNC FSC<6> MSD<2> SD<2> LAUTO FIFOSTAT2 SAUTO FSC<5> MSD<1> SD<1> LFLT<3> FIFOSTAT1 SFLT<3> FSC<4> MSD<0> SD<0> LFLT<2> FIFOSTAT0 SFLT<2> FSC<3> MHD<3> LCHANGE LFLT<1> VALID SFLT<1> FSC<2> MHD<2> ERR_HI LFLT<0> SCHANGE SFLT<0> DATAFRMT IE_CROSS FSC<9> FSC<1> MHD<1> ERR_LO LTRH<1> PHOF<1> RESERVED PD RESERVED FSC<8> FSC<0> MHD<0> CHECK LTRH<0> PHOF<0> STRH<0> 00 00 02 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 UPDEL<5> DNDEL<5> UPDEL<4> DNDEL<4> UPDEL<3> DNDEL<3> UPDEL<2> DNDEL<2> UPDEL<1> DNDEL<1> UPDEL<0> DNDEL<0> 00 00 00 00 HDRM<4> HDRM<3> TRMBG<2> HDRM<2> TRMBG<1> HDRM<1> TRMBG<0> HDRM<0> C0 CA C0 CA LVDS_EN SYNC_EN CLEAR 00 00 CCD<2> CCD<1> CCD<0> 00 00 MSEL<1> HDRM<7> MSEL<0> HDRM<6> HDRM<5> SEL<1> SEL<0> SIG_READ RESERVED RESERVED RESERVED RESERVED CCD<3> Rev. A | Page 29 of 72 AD9734/AD9735/AD9736 SPI REGISTER DETAILS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Reset value for write registers in bold text. MODE REGISTER (REG. 0) ADDR 0x00 Name MODE Bit 7 SDIO_DIR Bit 6 LSB/MSB Bit 5 RESET Bit 4 LONG_INS Bit 3 2x MODE Bit 2 FIFO MODE Bit 1 DATAFRMT Bit 0 PD Table 10. Mode Register Bit Descriptions Bit Name SDIO_DIR Read/Write WRITE LSB/MSB WRITE RESET WRITE LONG_INS WRITE 2x_MODE WRITE FIFO_MODE WRITE DATAFRMT WRITE PD WRITE Description 0, input only per SPI standard. 1, bidirectional per SPI standard. 0, MSB first per SPI standard. 1, LSB first per SPI standard. NOTE: Only change LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit order errors. 0, execute software reset of SPI and controllers, reload default register values except Registers 0x00 and 0x04. 1, set software reset, write 0 on the next (or any following) cycle to release the reset. 0, short (single-byte) instruction word. 1, long (two-byte) instruction word, not necessary since the maximum internal address is REG31 (0x1F). 0, disable 2x interpolation filter. 1, enable 2x interpolation filter. 0, disable FIFO synchronization. 1, enable FIFO synchronization. 0, signed input DATA with midscale = 0x0000. 1, unsigned input DATA with midscale = 0x2000. 0, enable LVDS Receiver, DAC, and clock circuitry. 1, power down LVDS Receiver, DAC, and clock circuitry. INTERRUPT REQUEST REGISTER (IRQ) (REG. 1) ADDR 0x01 Name IRQ Bit 7 LVDS Bit 6 SYNC Bit 5 CROSS Bit 4 RESERVED Bit 3 IE_LVDS Bit 2 IE_SYNC Table 11. Interrupt Register Bit Descriptions Bit Name LVDS Read/Write WRITE READ SYNC WRITE READ CROSS WRITE READ IE_LVDS WRITE IE_SYNC WRITE IE_CROSS WRITE Description Don't care. 0, no active LVDS receiver interrupt. 1, interrupt in LVDS receiver occurred. Don't care. 0, no active SYNC logic interrupt. 1, interrupt in SYNC logic occurred. Don't care. 0, no active CROSS logic interrupt. 1, interrupt in CROSS logic occurred. 0, reset LVDS receiver interrupt and disable future LVDS receiver interrupts. 1, enable LVDS receiver interrupt to activate IRQ pin. 0, reset SYNC logic interrupt and disable future SYNC logic interrupts. 1, enable SYNC logic interrupt to activate IRQ pin. 0, reset CROSS logic interrupt and disable future CROSS logic interrupts. 1, enable CROSS logic interrupt to activate IRQ pin. Rev. A | Page 30 of 72 Bit 1 IE_CROSS Bit 0 RESERVED AD9734/AD9735/AD9736 FULL SCALE CURRENT (FSC) REGISTERS (REG. 2, REG. 3) ADDR 0x02 0x03 Name FSC_1 FSC_2 Bit 7 SLEEP FSC<7> Bit 6 - FSC<6> Bit 5 Bit 4 Bit 3 Bit 2 - FSC<5> - FSC<4> - FSC<3> - FSC<2> Bit 1 FSC<9> FSC<1> Bit 0 FSC<8> FSC<0> Bit 1 MHD<1> ERR_LO LTRH<1> Bit 0 MHD<0> CHECK LTRH<0> Table 12. Full Scale Current Output Register Bit Descriptions Bit Name SLEEP Read/Write WRITE FSC<9:0> WRITE Description 0, enable DAC output. 1, set DAC output current to 0 mA. 0x000, 10 mA full-scale output current. 0x200, 20 mA full-scale output current. 0x3FF, 30 mA full-scale output current. LVDS CONTROLLER (LVDS_CNT) REGISTERS (REG. 4, REG. 5, REG. 6) ADDR 0x04 0x05 0x06 Name LVDS_CNT1 LVDS_CNT2 LVDS_CNT3 Bit 7 MSD<3> SD<3> LSURV Bit 6 MSD<2> SD<2> LAUTO Bit 5 MSD<1> SD<1> LFLT<3> Bit 4 MSD<0> SD<0> LFLT<2> Bit 3 MHD<3> LCHANGE LFLT<1> Bit 2 MHD<2> ERR_HI LFLT<0> Table 13. LVDS Controller Register Bit Descriptions Bit Name MSD<3:0> Read/Write WRITE READ MHD<3:0> WRITE READ SD<3:0> WRITE READ LCHANGE READ ERR_HI ERR_LO CHECK READ READ READ LSURV WRITE LAUTO WRITE LFLT<3:0> WRITE LTRH<2:0> WRITE Description 0x0, set setup delay for the measurement system. If ( LAUTO = 1), the latest measured value for the setup delay. If ( LAUTO = 0), readback of the last SPI write to this bit. 0x0, set hold delay for the measurement system. If ( LAUTO = 1), the latest measured value for the hold delay. If ( LAUTO = 0), readback of the last SPI write to this bit. 0x0, set sample delay. If ( LAUTO = 1), the result of a measurement cycle is stored in this register. If ( LAUTO = 0), readback of the last SPI write to this bit. 0, no change from previous measurement. 1, change in value from the previous measurement. NOTE: The average filter and the threshold detection are not applied to this bit. One of the 15 LVDS inputs is above the input voltage limits of the IEEE reduced link specification. One of the 15 LVDS inputs is below the input voltage limits of the IEEE reduced link specification. 0, phase measurement--sampling in the previous or following DATA cycle. 1, phase measurement--sampling in the correct DATA cycle. 0, the controller stops after completion of the current measurement cycle. 1, continuous measurements are taken and an interrupt is issued if the clock alignment drifts beyond the threshold value. 0, sample delay is not automatically updated. 1, continuously starts measurement cycles and updates the sample delay according to the measurement. NOTE: LSURV (Reg. 6, Bit 7) must be set to 1 and the LVDS IRQ (Reg. 1, Bit 3) must be set to 0 for AUTO mode. 0x0, average filter length, Delay = Delay + Delta Delay/2^ LFLT <3:0>, values greater than 12 (0x0C) are clipped to 12. 000, set auto update threshold values. Rev. A | Page 31 of 72 AD9734/AD9735/AD9736 SYNC CONTROLLER (SYNC_CNT) REGISTERS (REG. 7, REG. 8) ADDR 0x07 0x08 Name SYNC_CNT1 SYNC_CNT2 Bit 7 FIFOSTAT3 SSURV Bit 6 FIFOSTAT2 SAUTO Bit 5 FIFOSTAT1 SFLT<3> Bit 4 FIFOSTAT0 SFLT<2> Bit 3 VALID SFLT<1> Bit 2 SCHANGE SFLT<0> Bit 1 PHOF<1> RESERVED Bit 0 PHOF<0> STRH<0> Table 14. Sync Controller Register Bit Descriptions Bit Name FIFOSTAT<2:0> FIFOSTAT<3> Read/Write READ READ VALID READ SCHANGE READ PHOF<1:0> WRITE READ SSURV WRITE SAUTO WRITE SFLT<3:0> WRITE STRH<0> WRITE Description Position of FIFO read counter ranges from 0 to 7. 0, SYNC logic OK. 1, error in SYNC logic. 0, FIFOSTAT<3:0> is not valid yet. 1, FIFOSTAT<3:0> is valid after a reset. 0, no change in FIFOSTAT<3:0>. 1, FIFOSTAT<3:0> has changed since the previous measurement cycle when SSURV = 1 (surveillance mode active). 00, change the readout counter. Current setting of the readout counter (PHOF<1:0>) in surveillance mode (SSURV = 1) after an interrupt. Current calculated optimal readout counter value in AUTO mode (SAUTO = 1). 0, the controller stops after completion of the current measurement cycle. 1, continuous measurements are taken and an interrupt is issued if the readout counter drifts beyond the threshold value. 0, readout counter (PHOF<3:0>) is not automatically updated. 1, continuously starts measurement cycles and updates the readout counter according to the measurement. NOTE: SSURV (Reg. 8, Bit 7) must be set to 1 and the SYNC IRQ (Reg. 1, Bit 2) must be set to 0 for AUTO mode. 0x0, average filter length, FIFOSTAT = FIFOSTAT + Delta FIFOSTAT/2 ^ SFLT<3:0>; values greater than 12 (0x0C) are clipped to 12. 0, if FIFOSTAT<2:0> = 0 or 7, a sync interrupt is generated. 1, if FIFOSTAT<2:0> = 0, 1, 6 or 7, a sync interrupt is generated. CROSS CONTROLLER (CROS_CNT) REGISTERS (REG. 10, REG. 11) ADDR 0x0A 0x0B Name CROS_CNT1 CROS_CNT2 Bit 7 - - Bit 6 - - Bit 5 UPDEL<5> DNDEL<5> Bit 4 UPDEL<4> DNDEL<4> Bit 3 UPDEL<3> DNDEL<3> Bit 2 UPDEL<2> DNDEL<2> Bit 1 UPDEL<1> DNDEL<1> Table 15. Cross Controller Register Description Bit Name UPDEL<5:0> DNDEL<5:0> Read/Write WRITE WRITE Description 0x00, move the differential output stage switching point up, set to 0 if DNDEL is non-zero. 0x00, move the differential output stage switching point down, set to 0 if UPDEL is non-zero. Rev. A | Page 32 of 72 Bit 0 UPDEL<0> DNDEL<0> AD9734/AD9735/AD9736 ANALOG CONTROL (ANA_CNT) REGISTERS (REG. 14, REG. 15) ADDR 0x0E 0x0F Name ANA_CNT1 ANA_CNT2 Bit 7 MSEL<1> HDRM<7> Bit 6 MSEL<0> HDRM<6> Bit 5 - HDRM<5> Bit 4 - HDRM<4> Bit 3 - HDRM<3> Bit 2 TRMBG<2> HDRM<2> Bit 1 TRMBG<1> HDRM<1> Bit 0 TRMBG<0> HDRM<0> Table 16. Analog Control Register Bit Descriptions Bit Name MSEL<1:0> Read/Write WRITE Description TRMBG<2:0> WRITE 000, band gap temperature characteristic trim. NOTE: See the plot in the Analog Control Registers section. HDRM<7:0> WRITE 0xCA, output stack headroom control. HDRM<7:4> set reference offset from AVDD33 (VCAS centering). HDRM<3:0> set overdrive (current density) trim (temperature tracking). Note: Set to 0xCA for optimum performance. 00, mirror roll off frequency control = bypass. 01, mirror roll off frequency control = narrowest bandwidth. 10, mirror roll off frequency control = medium bandwidth. 11, mirror roll off frequency control = widest bandwidth. NOTE: See the plot in the Analog Control Registers section. BUILT-IN SELF TEST CONTROL (BIST_CNT) REGISTERS (REG. 17, REG. 18, REG. 19, REG. 20, REG. 21) ADDR 0x11 0x12 0x13 0x14 0x15 Name BIST_CNT BIST<7:0> BIST<15:8> BIST<23:16> BIST<31:24> Bit 7 SEL<1> BIST<7> BIST<15> BIST<23> BIST<31> Bit 6 SEL<0> BIST<6> BIST<14> BIST<22> BIST<30> Bit 5 SIG_READ BIST<5> BIST<13> BIST<21> BIST<29> Bit 4 - BIST<4> BIST<12> BIST<20> BIST<28> Bit 3 - BIST<3> BIST<11> BIST<19> BIST<27> Bit 2 LVDS_EN BIST<2> BIST<10> BIST<18> BIST<26> Table 17. BIST Control Register Bit Descriptions Bit Name SEL<1:0> Read/Write WRITE SIG_READ WRITE LVDS_EN WRITE SYNC_EN WRITE CLEAR WRITE BIST<31:0> READ Description 00, write result of the LVDS Phase 1 BIST to BIST<31:0>. 01, write result of the LVDS Phase 2 BIST to BIST<31:0>. 10, write result of the SYNC Phase 1 BIST to BIST<31:0>. 11, write result of the SYNC Phase 2 BIST to BIST<31:0>. 0, no action. 1, enable BIST signature readback. 0, no action. 1, enable LVDS BIST. 0, no action. 1, enable SYNC BIST. 0, no action. 1, clear all BIST registers. Results of the built-in self test. Rev. A | Page 33 of 72 Bit 1 SYNC_EN BIST<1> BIST<9> BIST<17> BIST<25> Bit 0 CLEAR BIST<0> BIST<8> BIST<16> BIST<24> AD9734/AD9735/AD9736 CONTROLLER CLOCK PREDIVIDER (CCLK_DIV) READING REGISTER (REG. 22) ADR 0x16 Name CCLK_DIV Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 CCD<3> Bit 2 CCD<2> Bit 1 CCD<1> Bit 0 CCD<0> Table 18. Controller Clock Predivider Register Bit Descriptions Bit Name CCD<3:0> Read/Write WRITE Description 0x0, controller clock = DACCLK/16. 0x1, controller clock = DACCLK/32. 0x2, controller clock = DACCLK/64 ... 0xF, controller clock = DACCLK/524288. NOTE: The 100 MHz to 1.2 GHz DACCLK must be divided to less than 10 MHz for correct operation. CCD<3:0> must be programmed to divide the DACCLK so that this relationship is not violated. Controller clock = DACCLK/(2 ^ ( CCD<3:0> + 4 )). Rev. A | Page 34 of 72 AD9734/AD9735/AD9736 THEORY OF OPERATION The AD9736, AD9735, and AD9734 are 14-bit, 12-bit, and 10-bit DACs that run at an update rate up to 1.2 GSPS. Input data can be accepted up to the full 1.2 GSPS rate, or a 2x interpolation filter can be enabled (2x mode) allowing full speed operation with a 600 MSPS input data rate. The DATA and DATACLK_IN inputs are parallel LVDS, meeting the IEEE reduced swing LVDS specifications with the exception of input hysteresis. The DATACLK_IN input runs at one-half the input DATA rate in a double data rate (DDR) format. Each edge of DATACLK_IN transfers DATA into the AD9736, as shown in Figure 79. The DACCLK-/DACCLK+ inputs (Pin E1 and Pin F1) directly drive the DAC core to minimize clock jitter. The DACCLK signal is also divided by 2 (1x and 2x mode), then output as the DATACLK_OUT. The DATACLK_OUT signal clocks the data source. The DAC expects DDR LVDS data (DB<13:0>) aligned with the DDR input clock (DATACLK_IN) from a circuit similar to the one shown in Figure 96. Table 19 shows the clock relationships. Table 19. AD973x Clock Relationship MODE 1x 2x DACCLK 1.2 GHz 1.2 GHz DATACLK_OUT 600 MHz 600 MHz DATACLK_IN 600 MHz 300 MHz DATA 1.2 GSPS 600 MSPS Maintaining correct alignment of data and clock is a common challenge with high speed DACs, complicated by changes in temperature and other operating conditions. Using the DATACLK_OUT signal to generate the data allows most of the internal process, temperature, and voltage delay variation to be cancelled. The AD973x further simplifies this high speed data capture problem with two adaptive closed-loop timing controllers. One timing controller manages the LVDS data and data clock alignment (LVDS controller), and the other manages the LVDS data and DACCLK alignment (sync controller). The LVDS controller locates the data transitions and delays the DATACLK_IN so that its transition is in the center of the valid data window. The sync controller manages the FIFO that moves data from the LVDS DATACLK_IN domain to the DACCLK domain. Both controllers can operate in manual mode under external processor control, in surveillance mode where error conditions generate external interrupts, or in automatic mode where errors are automatically corrected. The LVDS and sync controllers include moving average filtering for noise immunity and variable thresholds to control activity. Normally, the controllers are set to run in automatic mode, making any necessary adjustments without dropping or duplicating samples sent to the DAC. Both controllers require initial calibration prior to entering automatic update mode. The AD973x analog output changes 35 DACCLK cycles after the input data changes in 1x mode with the FIFO disabled. The FIFO adds up to eight additional cycles of delay. This delay is read from the SPI port. Internal clock delay variation is less than a single DACCLK cycle at 1.2 GHz (833 ps). Stopping the AD973x DATACLK_IN while the DACCLK is still running can lead to unpredictable output signals. This occurs because the internal digital signal path is interleaved. The last two samples clocked into the DAC continue to be clocked out by DACCLK even after DATACLK_IN has stopped. The resulting output signal is at a frequency of one-half fDAC, and the amplitude depends on the difference between the last two samples. Control of the AD973x functions is via the serially programmed registers listed in Table 9. Optionally, a limited number of functions can be directly set by external pins in pin mode. Rev. A | Page 35 of 72 AD9734/AD9735/AD9736 SERIAL PERIPHERAL INTERFACE The AD973x serial port is a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI(R) and Intel(R) SSR protocols. The interface allows read/write access to all registers that configure the AD973x. Single- or multiple-byte transfers are supported, as well as most significant bit first (MSB-first) or least significant bit first (LSB-first) transfer formats. The AD973x serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO). SDO (PIN G14) SCLK (PIN G13) SPI PORT CSB (PIN F13) The short instruction byte is shown in the following table: MSB I7 R/W I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0 R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic high indicates read operation. Logic 0 indicates a write operation. N1, N0, Bit 6, and Bit 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 20. A4, A3, A2, A1, A0, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction byte, determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD973x, based on the LSBFIRST bit (Reg. 0, Bit 6). AD973x 04862-066 SDIO (PIN F14) SHORT INSTRUCTION MODE (8-BIT INSTRUCTION) Figure 68. AD973x SPI Port The AD973x can optionally be configured via external pins rather than the serial interface. When the PIN_MODE input (Pin L1) is high, the serial interface is disabled and its pins are reassigned for direct control of the DAC. Specific functionality is described in the Pin Mode Operation section. GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communication cycle with the AD973x. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD973x, coincident with the first eight SCLK rising edges. The instruction byte provides the AD973x serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD973x. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD973x and the system controller. Phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. Using one multibyte transfer is the preferred method. Single-byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. CSB (Chip Select) can be raised after each sequence of 8 bits (except the last byte) to stall the bus. The serial transfer resumes when CSB is lowered. Stalling on nonbyte boundaries resets the SPI. Table 20. Byte Transfer Count N1 0 0 1 1 N2 0 1 0 1 Description Transfer 1 byte Transfer 2 bytes Transfer 3 bytes Transfer 4 bytes LONG INSTRUCTION MODE (16-BIT INSTRUCTION) The long instruction bytes are shown in the following table: MSB I15 R/W I7 A7 I14 N1 I6 A6 I13 N0 I5 A5 I12 A12 I4 A4 I11 A11 I3 A3 I10 A10 I2 A2 I9 A9 I1 A1 LSB I8 A8 I0 A0 If LONG_INS = 1 (Reg. 0, Bit 4), the instruction byte is extended to 2 bytes where the second byte provides an additional 8 bits of address information. Address 0x00 to Address 0x1F are equivalent in short and long instruction modes. The AD973x does not use any addresses greater than 31 (0x1F), so always set LONG_INS = 0. SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK--Serial Clock The serial clock pin is used to synchronize data to and from the AD973x and to run the internal state machines. The maximum frequency of SCLK is 20 MHz. All data input to the AD973x is registered on the rising edge of SCLK. All data is driven out of the AD973x on the rising edge of SCLK. Rev. A | Page 36 of 72 AD9734/AD9735/AD9736 CSB--Chip Select Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. SDIO--Serial Data I/O Data is always written into the AD973x on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by SDIO_DIR at Reg. 0, Bit 7. The default is Logic 0, which configures the SDIO pin as unidirectional. SDO--Serial Data Out Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD973x operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. MSB/LSB TRANSFERS For multibyte transfers, writing to this register can occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. The same considerations apply to setting the software reset, RESET (Reg. 0, Bit 5). All registers are set to their default values except Reg. 0 and Reg. 4, which remain unchanged. Use of only single-byte transfers when changing serial port configurations or initiating a software reset is highly recommended. In the event of unexpected programming sequences, the AD973x SPI can become inaccessible. For example, if user code inadvertently changes the LONG_INS bit or the LSBFIRST bit, the following bits experience unexpected results. The SPI can be returned to a known state by writing an incomplete byte (1 to 7 bits) of all 0s followed by 3 bytes of 0x00. This returns to MSB-first short instructions (Reg. 0 = 0x00), so the device can be reinitialized. INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB R/W N1 N0 A4 A3 A2 A1 A0 D7N D6N D5N Figure 69. Serial Register Interface Timing, MSB-First Write INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK SDIO R/W N1 N0 A4 A3 A2 A1 A0 The AD973x serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB-first mode is active. The serial port controller address increments from the data address written toward 0x1F for multibyte I/O operations if the LSB-first mode is active. D6N D5N D30 D20 D10 D00 D6N D5N D30 D20 D10 D00 D7 SDO When LSBFIRST = 1 (LSB first), the instruction and data bytes must be written from least significant bit to most significant bit. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle. D30 D20 D10 D00 04862-067 SDIO 04862-068 When LSBFIRST = 0 (MSB first), the instruction and data bytes must be written from the most significant bit to the least significant bit. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow in order from high address to low address. In MSB-first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. SCLK D7 Figure 70. Serial Register Interface Timing, MSB-First Read INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK SDIO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4N D5N D6N D7N 04862-069 The AD973x serial port can support both MSB-first or LSB-first data formats. This functionality is controlled by LSBFIRST at Reg. 0, Bit 6. The default is MSB first (LSBFIRST = 0). Figure 71. Serial Register Interface Timing, LSB-First Write INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK The AD973x serial port configuration is controlled by Reg. 0, Bit 4, Bit 5, Bit 6, and Bit 7. Note that the configuration changes immediately upon writing to the last bit of the register. SDIO A0 A1 A2 A3 A4 N0 N1 R/W D10 D20 D4N D5N D6N D7N D10 D20 D4N D5N D6N D7N D0 SDO D0 Figure 72. Serial Register Interface Timing, LSB-First Read Rev. A | Page 37 of 72 04862-070 NOTES ON SERIAL PORT OPERATION AD9734/AD9735/AD9736 tDS Table 22. PIN_MODE Input Functions tSCLK Mnemonic UNSIGNED CSB tPWH tPWL SCLK 2x tDH INSTRUCTION BIT 7 SDIO 04862-071 tDS INSTRUCTION BIT 6 FSC1, FSC0 Figure 73. Timing Diagram for SPI Register Write CSB PD SCLK SDIO I1 I0 D7 FIFO tDV D6 D5 04862-072 tDNV Figure 74. Timing Diagram for SPI Register Read After the last instruction bit is written to the SDIO pin, the driving signal must be set to a high impedance in time for the bus to turn around. The serial output data from the AD973x is enabled by the falling edge of SCLK. This causes the first output data bit to be shorter than the remaining data bits, as shown in Figure 74. To assure proper reading of data, read the SDIO or SDO pin prior to changing the SCLK from low to high. Due to the more complex multibyte protocol, multiple AD973x devices cannot be daisy-chained on the SPI bus. Multiple DACs should be controlled by independent CSB signals. PIN MODE OPERATION When the PIN_MODE input (Pin L1) is set high, the SPI port is disabled. The SPI port pins are remapped, as shown in Table 21. The function of these pins is described in Table 22. The remaining PIN_MODE register settings are shown in Table 9. Table 21. SPI_MODE vs. PIN_MODE Inputs Pin Number E13 F13 G13 E14 F14 G14 PIN_MODE = 0 IRQ CSB SCLK RESET SDIO SDO PIN_MODE = 1 UNSIGNED 2x FSC0 PD FIFO FSC1 Function 0, twos complement input data format 1, unsigned input data format 0, interpolation disabled 1, interpolation = 2x enabled 00, sleep mode 01, 10 mA full-scale output current 10, 20 mA full-scale output current 11, 30 mA full-scale output current 0, chip enabled 1, chip in power-down state 0, input FIFO disabled 1, input FIFO enabled Care must be taken when using PIN_MODE because only the control bits shown in Table 22 can be changed. If the remaining register default values are not suitable for the desired operation, PIN_MODE cannot be used. If the FIFO is enabled, the controller clock must be less than 10 MHz. This limits the DAC clock to 160 MHz. RESET OPERATION The RESET pin forces all SPI register contents to their default values (see Table 9), which places the DAC in a known state. The software reset bit forces all SPI register contents, except Reg. 0 and Reg. 4, to their default values. The internal reset signal is derived from a logical OR operation on the RESET pin state and from the software reset state. This internal reset signal drives all SPI registers to their default values, except Reg. 0 and Reg. 4, which are unaffected. The data registers are not affected by either reset. The software reset is asserted by writing 1 to Reg. 0, Bit 5. It may be cleared on the next SPI write cycle or a later write cycle. PROGRAMMING SEQUENCE The AD973x registers should be programmed in this order: 1. Reset hardware. 2. Make changes to SPI port configuration, if necessary. 3. Input format, if unsigned. 4. Interpolation, if in 2x mode. 5. Calibrate and set the LVDS controller. 6. Enable the FIFO. 7. Calibrate and set the sync controller. Step 1 through Step 4 are required, while Step 5 through Step 7 are optional. The LVDS controller can help assure proper data reception in the DAC with changes in temperature and voltage. The sync controller manages the FIFO to assure proper transfer of the received data to the DAC core with changes in temperature and voltage. The DAC is intended to operate with both controllers active unless data and clock alignment is managed externally. Rev. A | Page 38 of 72 AD9734/AD9735/AD9736 0.10 INTERPOLATION FILTER 0.08 0.06 0.04 MAGNITUDE (dB) In 2x mode, the input data is interpolated by a factor of 2 so that it aligns with the DAC update rate. The interpolation filter is a hard-coded, 55-tap, symmetric FIR with a 0.001 dB passband flatness and a stop-band attenuation of about 90 dB. The transition band runs from 20% of fDAC to 30% of fDAC. The FIR response is shown in Figure 75 where the frequency axis is normalized to fDAC. Figure 76 shows the pass-band flatness and Table 23 shows the 16-bit filter coefficients. Tap Weight -7 0 +24 0 -62 0 +135 0 -263 0 +471 0 -793 0 +1273 0 -1976 0 +3012 0 -4603 0 +7321 0 -13270 0 +41505 +65535 0 -0.10 0 0.05 0.10 0.15 0.20 FREQUENCY NORMALIZED TO fDAC 0.25 04862-074 -0.08 -10 Figure 76. Interpolation Filter Pass-Band Flatness DATA INTERFACE CONTROLLERS Two internal controllers are utilized in the operation of the AD973x. The first controller helps maintain optimum LVDS data sampling; the second controller helps maintain optimum synchronization between the DACCLK and the incoming data. The LVDS controller is responsible for optimizing the sampling of the data from the LVDS bus (DB13:0), while the sync controller resolves timing problems between the DAC_CLK (CLK+, CLK-) and the DATACLK. A block diagram of these controllers is shown in Figure 77. DATACLK DATACLK_OUT CLK CONTROL DATACLK_IN DATA SOURCE i.e., FPGA LVDS CONTROLLER SYNC CONTROLLER SYNC LOGIC LVDS SAMPLE LOGIC DB<13:0> FIFO DAC Figure 77. Data Controllers The controllers are clocked with a divided-down version of the DAC_CLK. The divide ratio is set utilizing the controller clock predivider bits (CCD<3:0>) located at Reg. 22, Bits 3:0 to generate the controller clock as follows: -20 Controller Clock = DAC_CLK/(2(CCD<3:0> + 4)) -30 Note that the controller clock cannot exceed 10 MHz for correct operation. Until CCD<3:0> is properly programmed to meet this requirement, the DAC output may not be stable. This means the FIFO cannot be enabled in PIN_MODE unless the DACCLK is less than 160 MHz. -40 -50 -60 -70 -80 -90 -100 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 FREQUENCY NORMALIZED TO fDAC 0.45 0.50 04862-073 MAGNITUDE (dB) -0.04 04862-075 Coefficient Number 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 0 -0.02 -0.06 Table 23. FIR Interpolation Filter Coefficients Coefficient Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 0.02 Figure 75. Interpolation Filter Response Rev. A | Page 39 of 72 AD9734/AD9735/AD9736 DBU The LVDS and sync controllers are independently operated in three modes via SPI port Reg. 6 and Reg. 8: Manual mode * Surveillance mode * Auto mode FF D1 FF D2 DBL DATA SAMPLING SIGNAL SD<3:0> SAMPLE DELAY In manual mode, all of the timing measurements and updates are externally controlled via the SPI. DATACLK_IN LVDS RX MSD<3:0> DELAY In surveillance mode, each controller takes measurements and calculates a new optimal value continuously. The result of the measurement is passed through an averaging filter before evaluating the results for increased noise immunity. The filtered result is compared to a threshold value set via Reg. 6 and Reg. 8 of the SPI port. If the error is greater than the threshold, an interrupt is triggered and the controller stops. DELAYED CLOCK SIGNAL CHECK FF MSD<3:0> DELAY CLOCK SAMPLING SIGNAL 04862-076 * LVDS RX DB<13:0> Figure 78. Internal LVDS Data Sampling Logic CLK TO DB SKEW DB13:0 Reg. 1 of the SPI port controls the interrupts with Bit 3 and Bit 2 enabling the respective interrupts and Bit 7 and Bit 6 indicating the respective controller interrupt. If an interrupt is enabled, it also activates the AD973x IRQ pin. To clear an interrupt, the interrupt enable bit of the respective controller must be set to 0 for at least 1 controller clock cycle (controller clock <10 MHz). DATACLK_IN PROP DELAY TO LATCH DATA SAMPLING SIGNAL (DSS) PROP DELAY TO LATCH D1 D2 04862-077 Auto mode is almost identical to surveillance mode. Instead of triggering an interrupt and stopping the controller, the controller automatically updates its settings to the newly calculated optimal value and continues to run. SAMPLE DELAY Figure 79. Internal LVDS Data Sampling Logic Timing LVDS SAMPLE LOGIC CALIBRATION LVDS SAMPLE LOGIC A simplified diagram of the AD973x LVDS data sampling engine is shown in Figure 78 and the timing diagram is shown in Figure 79. The incoming LVDS data is latched by the data sampling signal (DSS), which is derived from DATACLK_IN. The LVDS controller delays DATACLK_IN to create the data sampling signal (DSS), which is adjusted to sample the LVDS data in the center of the valid data window. The skew between the DATACLK_IN and the LVDS data bits (DB<13:0>) must be minimal for proper operation. Therefore, it is recommended that the DATACLK_IN be generated in the same manner as the LVDS data bits (DB<13:0>) with the same driver and data lines (that is, it should just be another LVDS data bit running a constant 01010101... sequence, as shown in Figure 96). If the DATACLK_IN signal is stopped, the DACCLK continues to generate an output signal based on the last two values clocked into the registers that drive D1 and D2, as shown in Figure 78. If these two registers are not equal, a large output at a frequency of one-half fDAC can be generated at the DAC output. The internal DSS delay must be calibrated to optimize the data sample timing. Once calibrated, the AD973x generates an IRQ or automatically corrects its timing if temperature or voltage variations change the timing too much. This calibration is done using the delayed clock sampling signal (CSS) to sample the delayed clock signal (DCS). The LVDS sampling logic finds the edges of the DATACLK_IN signal and, from this measurement, the center of the valid data window is located. The internal delay line that derives the delayed DSS from DATACLK_IN is controlled by SD3:0 (Reg. 5, Bits 7:4), while the DCS is controlled by MSD3:0 (Reg. 4, Bits 7:4), and the CSS is controlled by MHD3:0 (Reg. 4, Bits 3:0). DATACLK_IN transitions must be time aligned with the LVDS data (DB<13:0>) transitions. This allows the CSS, derived from the DATACLK_IN, to find the valid data window of DB<13:0> by locating the DATACLK_IN edges. The latching (rising) edge of CSS is initially placed using Bits SD<3:0> and can then be shifted to the left using MSD<3:0> and to the right using MHD<3:0>. When CSS samples the DCS and the result is 1 (which can be read back via the check bit at Reg. 5, Bit 0), the sampling occurs in the correct data cycle. Rev. A | Page 40 of 72 AD9734/AD9735/AD9736 To find the leading edge of the data cycle, increment the measured setup delay until the check bit goes low. To find the trailing edge, increment the measured hold delay (MHD) until check goes low. Always set MHD = 0 when incrementing MSD and vice versa. SETUP TIME (tS) DB<13:0> DATACLK_IN SAMPLE DELAY SD<3:0> MSD<3:0> = 0 1 2 3 4 5 The incremental units of SD, MSD, and MHD are in units of real time, not fractions of a clock cycle. The nominal step size is 80 ps. CHECK = 1 1 1 1 1 0 With SD<3:0> and MHD<3:0> set to 0, increment the setup time delay (MSD<3:0>, Reg. 4, Bits 7:4) until the check bit (Reg. 5, Bit 0) goes low and record this value. This locates the leading DATACLK_IN (and data) transition, as shown in Figure 80. With SD<3:0> and MSD<3:0> set to 0, increment the hold time delay (MHD<3:0>, Reg. 4, Bits 3:0) until the check bit (Reg. 5, Bit 0) goes low and record this value. This locates the trailing DATACLK_IN (and DB<13:0>) transition, as shown in Figure 81. Figure 81. Hold Delay Measurement OPERATING THE LVDS CONTROLLER IN SURVEILLANCE AND AUTO MODE In surveillance mode, the controller searches for the edges of the data eye in the same manner as in the manual mode of operation and triggers an interrupt if the clock sampling signal (CSS) has moved more than the threshold value set by LTRH<1:0> (Reg. 6, Bits 1:0). There is an internal filter that averages the setup and hold time measurements to filter out noise and glitches on the clock lines. Average Value = (MHD - MSD)/2 New Average = Average Value + ( Average/2 ^ LFLT<3:0>) Once both DATACLK_IN edges are located, the sample delay (SD<3:0>, Reg. 5, Bits 7:4) must be updated by Sample Delay = (MHD - MSD)/2 If an accumulating error in the average value causes it to exceed the threshold value (LTHR<1:0>), an interrupt is issued. After updating SD<3:0>, verify that the sampling signal is in the middle of the valid data window by adjusting both MHD and MSD with the new sample delay until the check bit goes low. The new MHD and MSD values should be equal to or within one unit delay if SD<3:0> was set correctly. MHD and MSD may not be equal to or within one unit delay if the external clock jitter and noise exceeds the internal delay resolution. Differences of 2, 3, or more are possible and can require more filtering to provide stable operation. The sample delay calibration should be performed prior to enabling surveillance mode or auto mode. SETUP TIME (tS) DB<13:0> DATACLK_IN The maximum allowable value for LFLT<3:0> is 12. If LFLT<3:0> is too small, clock jitter and noise can cause erratic behavior. In most cases, LFLT can be set to the maximum value. In surveillance mode, the ideal sampling point should first be found using manual mode and then applied to the sample delay registers. Set the threshold and filter values depending on how far the CSS signal is allowed to drift before an interrupt occurs. Then, set the surveillance bit high (Reg. 6, Bit 7) and monitor the interrupt signal either via the SPI port (Reg. 1, Bit 7) or the IRQ pin. In auto mode, follow the same steps to set up the sample delay, threshold, and filter length. To run the controller in auto mode, both the LAUTO (Reg. 6, Bit 6) and LSURV (Reg. 6, Bit 7) bits need to be set to 1. In auto mode, the LVDS interrupt should be set low (Reg. 1, Bit 3) to allow the sample delay to be automatically updated if the threshold value is exceeded. CSS SAMPLE DCS CSS WITH MHD<3:0> = 0 04862-078 DSC DELAYED BY MSD<3:0> CHECK = 1 CHECK = 1 04862-079 DSC DELAYED BY MSD<3:0> = 0 The manual operation of the LVDS controller allows the user to step through both the setup and hold delays to calculate the optimal sampling delay (that is, the center of the data eye). MSD<3:0> = 0 1 2 3 4 5 CSS SAMPLE DCS CSS WITH MHD<3:0> = 0 OPERATING THE LVDS CONTROLLER IN MANUAL MODE VIA THE SPI PORT SAMPLE DELAY SD<3:0> HOLD TIME (tH) Figure 80. Setup Delay Measurement Rev. A | Page 41 of 72 AD9734/AD9735/AD9736 SYNC LOGIC AND CONTROLLER A FIFO structure is utilized to synchronize the data transfer between the DACCLK and the DATACLK_IN clock domains. The sync controller writes data from DB<13:0> into an 8-word memory register based on a cyclic write counter clocked by the DSS, which is a delayed version of DACCLK_IN. The data is read out of the memory based on a second cyclic read counter clocked by DACCLK. The 8-word FIFO shown in Figure 82 provides sufficient margin to maintain proper timing under most conditions. The sync logic is designed to prevent the read and write pointers from crossing. If the timing drifts far enough to require an update of the phase offset (PHOF<1:0>), two samples are duplicated or dropped. Figure 83 shows the timing diagram for the sync logic. 8 WORD MEMORY M0 DAC<13:0> ADDER DSS FF FIFOSTAT<2:0> PHOF<1:0> WRITE COUNTER READ COUNTER DACCLK 04862-080 ZD To start operating the DAC in manual mode, allow DACCLK and DATACLK_IN to stabilize, then enable FIFO mode (Reg. 0, Bit 2). Read FIFOSTAT<2:0> (Reg. 7, Bits 6:4) to determine if adjustment is needed. For example, if FIFOSTAT<2:0> = 6, the timing is not yet critical, but it is not optimal. To return to an optimal state (FIFOSTAT<2:0> = 4), the PHOF<1:0> (Reg. 7, Bits 1:0) needs to be set to 1. Setting PHOF<1:0> = 1 effectively increments the read pointer by 2. This causes the write pointer value to be captured two clocks later, decreasing FIFOSTAT<2:0> from 6 to 4. OPERATION IN SURVEILLANCE AND AUTO MODES Once FIFOSTAT<2:0> is manually placed in an optimal state, the AD973x sync logic can run in surveillance or auto mode. To start, turn on surveillance mode by setting SSURV = 1 (Reg. 8, Bit 7), then enable the sync interrupt (Reg. 1, Bit 2). If STRH<0> = 0 (Reg. 8, Bit 0), an interrupt occurs if FIFOSTAT<2:0> = 0 or 7. If STRH<0> = 1 (Reg. 8, Bit 0), an interrupt occurs if FIFOSTAT<2:0> = 0, 1, 6, or 7. The interrupt is read at Reg. 1, Bit 6 at the AD973x IRQ pin. DAC<13:0> M7 OPERATION IN MANUAL MODE Figure 82. Sync Logic Block Diagram SYNC LOGIC AND CONTROLLER OPERATION The relationship between the readout pointer and the write pointer initially is unknown because the startup relationship between DACCLK and DATACLK_IN is unknown. The sync logic measures the relative phase between the two counters with the zero detect block and the flip-flop in Figure 82. The relative phase is returned in FIFOSTAT<2:0> (Reg. 7, Bits 6:4), and sync logic errors are indicated by FIFOSTAT<3> (Reg. 7, Bit 7). If FIFOSTAT<2:0> returns a value of 0 or 7, the memory is sampling in a critical state (read and write pointers are close to crossing). If the FIFOSTAT<2:0> returns a value of 3 or 4, the memory is sampling at the optimal state (read and write pointers are farthest apart). If FIFOSTAT<2:0> returns a critical value, the pointer can be adjusted with the phase offset PHOF<1:0> (Reg. 7, Bits 1:0). Due to the architecture of the FIFO, the phase offset can only adjust the read pointer in steps of 2. To enter auto mode, complete the preceding steps then set SAUTO = 1 (Reg. 8, Bit 6). Next, set the sync interrupt = 0 (Reg. 1, Bit 2), to allow the phase offset (PHOF<1:0>) to be automatically updated if FIFOSTAT<2:0> violates the threshold value. The FIFOSTAT signal is filtered to improve noise immunity and reduce unnecessary phase offset updates. The filter operates with the following algorithm: FIFOSTAT = FIFOSTAT + FIFOSTAT/2 ^ SFLT<3:0> where: 0 SFLT<3:0> 12 Values greater than 12 are set to 12. If SFLT<3:0> is too small, clock jitter and noise can cause erratic behavior. Normally, SFLT can be set to the maximum value. FIFO BYPASS When the FIFO_MODE bit (Reg. 1, Bit 2) is set to 0, the FIFO is bypassed with a mux. When the FIFO is enabled, the pipeline delay through the AD973x increases by the delta between the FIFO read pointer and write pointer plus 4 more clock periods. Rev. A | Page 42 of 72 AD9734/AD9735/AD9736 DACCLK INTERNAL DELAY DATACLK_OUT EXTERNAL DELAY DATACLK_IN DATA_IN A C B D E F G I H J K L M N P O Q R SAMPLE_HOLD SAMPLE_SETUP SAMPLE_DELAY DSS1 C A D1 G E I Q O M K DSS2 0 2 1 3 H F 4 5 6 7 2 3 B DATA 'A' CAN BE SAFELY READ FROM THE FIFO IN THE SAFE ZONE. IN THE ERROR ZONE, THE POINTERS MAY BRIEFLY OVERLAP DUE TO CLOCK JITTER OR NOISE. 0 FIFOSTAT IS SET EQUAL TO THE WRITE POINTER EACH TIME THE READ POINTER CHANGES FROM 7 TO 0. D E F G H M7 DAC_DATA 7 C M6 FIFOSTAT 6 J M2 READ_PTR1 5 4 P I M1 M5 1 N A M0 M4 0 L ERROR ZONE SAFE ZONE M3 J 4 5 6 7 0 1 2 3 4 4 5 6 7 0 1 2 4 A B C D 3 4 4 E F Figure 83. Sync Logic Timing Diagram Rev. A | Page 43 of 72 G H I J K L M 04862-081 WRITE_PTR1 D B D2 AD9734/AD9735/AD9736 DIGITAL BUILT-IN SELF TEST (BIST) OVERVIEW Placing the idle value on the data input also allows the BIST to be set up while the DAC clock is running. The idle value should be all 0s in unsigned mode (0x0000) and all 0s except for the MSB in twos complement mode (0x2000). The AD973x includes an internal signature generator that processes incoming data to create unique signatures. These signatures are read back from the SPI port, allowing verification of correct data transfer into the AD973x. BIST vectors provided on the AD973x-EB evaluation board CD check the full width data input or individual bits for PCB debug, utilizing the procedure in the AD973X BIST Procedure section. Alternatively, any vector can be used provided the expected signature is calculated in advance. The BIST consists of two stages; the first stage is after the LVDS receiver and the second stage is after the FIFO. The first BIST stage verifies correct sampling of the data from the LVDS bus while the second BIST stage verifies correct synchronization between the DAC_CLK domain and the DATACLK_IN domain. The BIST vector is generated using 32-bit LFSR signature logic. Because the internal architecture is a 2-bus parallel system, there are two 32-bit LFSR signature logic blocks on both the LVDS and SYNC blocks. Figure 84 shows where the LVDS and SYNC phases are located. The MATLAB(R) routine, in the Generating Expected Signatures section, calculates the expected signature. BIST verifies correct data transfer because not all errors are always evident on a spectrum analyzer. There are four BIST signature generators that can be read back using Reg. 18 to Reg. 21, based on the setting of the BIST selection bits (Reg. 17, Bits 7:6), as shown in Table 24. The BIST signature returned from the AD973x depends on the digital input during the test. Because the filters in the DAC have memory, it is important to put the correct idle value on the DATA input to flush the memory prior to reading the BIST signature. Table 24. BIST Selection Bits Bit LVDS Phase 1 LVDS Phase 2 SYNC Phase 1 SYNC Phase 2 SEL<1> 0 0 1 1 SEL<0> 0 1 0 1 D1 DB<13:0> LVDS BIST PH1 (RISE) LVDS RX DATACLK_IN FIFO 2x SYNC BIST PH1 (RISE) DAC D2 SYNC LOGIC SYNC BIST PH2 (FALL) SPI PORT Figure 84. Block Diagram Showing LVDS and SYNC Phase 1 and SYNC Phase 2 Rev. A | Page 44 of 72 04862-082 LVDS BIST PH2 (FALL) AD9734/AD9735/AD9736 AD973x BIST PROCEDURE 17. Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and Reg. 18, as described in Step 14 ) for each of the four SEL (Reg. 17, Bits 7:6) values, and verify that they match the expected signatures shown in Table 25. 18. Flush the BIST circuitry. This must be done once before valid data can be read. Loop back to Step 11 and rerun the test to obtain the correct result. 1. Set RESET pin = 1. 2. Set input DATA = 0x0000 for signed (0x2000 for unsigned). 3. Enable DATACLK_IN if it is not already running. 4. Run for at least 16 DATACLK_IN cycles. 5. Set RESET pin = 0. 6. Run for at least 16 DATACLK_IN cycles. 7. Set RESET pin = 1. 8. Run for at least 16 DATACLK_IN cycles. AD973x EXPECTED BIST SIGNATURES 9. Set RESET pin = 0. 10. Set desired operating mode (1x mode and signed data are default values and expected for the supplied BIST vectors). The BIST vectors provided on the AD973x-EB CD are in signed mode, so no programming is necessary for the part to pass the BIST. The BIST vector is for 1x, no FIFO, and signed data. 11. Set CLEAR (Reg. 17, Bit 0), SYNC_EN (Reg. 17, Bit 1), and LVDS_EN (Reg. 17, Bit 2) high. For testing all 14 input bits, use the vector all_bits_unsnew.txt and verify against the signatures in Table 25. 12. Wait 50 DATACLK_IN cycles to allow 0s to propagate through and clear sync signatures. Table 25. Expected BIST Data Readback for All Bits 13. Set CLEAR low. 14. Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and Reg. 18) for each of the four SEL (Reg. 17, Bits 7:6) values and verify they are all 0x00. LVDS Phase 1 a. Reg. 17 set to 0x26 (SEL1 = 0, SEL0 = 0, SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1). b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17. LVDS Phase 2 a. Reg. 17 set to 0x66 (SEL1= 0, SEL0 = 1, SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1). b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17. SYNC Phase 1 a. Reg. 17 set to 0xA6 (SEL1= 1, SEL0 = 0, SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1). b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17. SYNC Phase 2 a. Reg. 17 set to 0xE6 (SEL1= 1, SEL0 = 1, SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1). b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17. Each time BIST mode is entered, this flush needs to be performed once. Multiple BIST runs can be performed without reflushing, as long as the device remains in BIST mode. LVDS Phase 1 CF71487C 15. Clock the BIST vector into the AD973x. 16. After the BIST vector is clocked into the part, hold DATA = 0x0000 for signed (0x2000 for unsigned); otherwise, the additional nonzero data changes the signature. LVDS Phase 2 66DF5250 SYNC Phase 1 CF71487C SYNC Phase 2 66DF5250 For individual bit tests, use the vectors named bitn.txt (where n is the desired bit number being tested) and compare them against the values in Table 26. Table 26. Expected BIST Data Readback for Individual Bits Vector bit0.txt bit1.txt bit2.txt bit3.txt bit4.txt bit5.txt bit6.txt bit7.txt bit8.txt bit9.txt bit10.txt bit11.txt bit12.txt bit13.txt Bit Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 LVDS Rise Expected AABF0A00 2BBF0A00 29BE0A00 2DBC0A00 25B80A00 35B00A00 15A00A00 55800A00 D5C00A00 D5410A00 D5430B00 D5470900 D54F0D00 D55F0500 LVDS Fall Expected 2A400500 6B400500 E9400500 ED410500 E5430500 F5470500 D54F0500 955F0500 157F0500 153E0500 15BC0500 15B80400 15B00600 15A00200 Note the following for Table 26: * The term rise refers to Phase 1 and fall refers to Phase 2. * Byte order is Decimal Register Address 21, Address 20, Address 19, and Address 18. * SYNC phase should always equal LVDS phase in 1x mode. Rev. A | Page 45 of 72 AD9734/AD9735/AD9736 GENERATING EXPECTED SIGNATURES To generate the expected BIST signatures, follow this procedure: The following MATLAB code duplicates the internal logic of the AD973x. To use it, save this code in a file called bist.m. 1. --- begin bist.m --function [ ret1 , ret2] = bist(vec) ret1 = bist1(vec(1:2:length(vec)-1)); ret2 = bist1(vec(2:2:length(vec))); function ret = bist1(v) sum = zeros(1,32); for i = 1 :length(v) if v(i) ~= 0 su(1) = ~xor(sum(32) ,bitget(v(i),1)); su(2) = ~xor(sum(1) ,bitget(v(i),2)); su(3) = ~xor(sum(2) ,bitget(v(i),3)); su(4) = ~xor(sum(3) ,bitget(v(i),4)); su(5) = ~xor(sum(4) ,bitget(v(i),5)); su(6) = ~xor(sum(5) ,bitget(v(i),6)); su(7) = ~xor(sum(6) ,bitget(v(i),7)); su(8) = ~xor(sum(7) ,bitget(v(i),8)); su(9) = ~xor(sum(8) ,bitget(v(i),9)); su(10) = ~xor(sum(9) ,bitget(v(i),10)); su(11) = ~xor(sum(10) ,bitget(v(i),11)); su(12) = ~xor(sum(11) ,bitget(v(i),12)); su(13) = ~xor(sum(12) ,bitget(v(i),13)); su(14) = ~xor(sum(13) ,bitget(v(i),14)); su(15) = sum(14); su(16) = sum(15); su(17) = sum(16); su(18) = sum(17); su(19) = sum(18); su(20) = sum(19); su(21) = sum(20); su(22) = sum(21); su(23) = sum(22); su(24) = sum(23); su(25) = sum(24); su(26) = sum(25); su(27) = sum(26); su(28) = sum(27); su(29) = sum(28); su(30) = sum(29); su(31) = sum(30); su(32) = sum(31); sum = su; end end % for ret = dec2hex( 2.^[0:31]x sum',8); --- end bist.m --- Start MATLAB and type the following at the command prompt: t = round(randn(1,100) x 213/8+213) ; [ b1 b2 ] = bist(t) The first statement creates a random vector of 14-bit words, with a length of 100. 2. Set t equal to any desired vector, or take this random vector and input it to the AD973x. 3. Alter the command randn(1,100) to change the vector length as desired. 4. Type b1 at the command line to see the calculated signature for the LVDS BIST, Phase 1. 5. Type b2 to see the value for LVDS BIST, Phase 2. The values returned for b1 and b2 each are 32-bit hex values. They correspond to Reg. 18, Reg. 19, Reg. 20, and Reg. 21, where b1 is the value read for SEL<1:0> = 0, 0 (see Table 17) and b2 is the value read for SEL<1:0> = 0, 1. When the DAC is in 1x mode, the signature at SYNC BIST, Phase 1 should equal the signature at LVDS BIST, Phase 1. The same is true for Phase 2. Rev. A | Page 46 of 72 AD9734/AD9735/AD9736 CROSS CONTROLLER REGISTERS Figure 85 shows the effect of UPDEL and DNDEL. If the system is calibrated after manufacture, adjust the cross controller offsets to provide optimum performance. To start, increment DNDEL<5:0> (Reg. 11, Bits 5:0) while observing HD2 (second harmonic distortion) and/or IMD to find the desired optimum. If DNDEL does not influence the performance, set it to 0 and increment UPDEL<5:0> (Reg. 10, Bits 5:0). Based on system characterization, set one of these controls to the maximum value to yield the best performance. Rev. A | Page 47 of 72 INCREMENT DNDEL TO MOVE THE CROSSING TOWARD THE IDEAL VALUE IDEAL DIFFERENTIAL OUTPUT CROSSING ALIGNMENT INCREMENT UPDEL TO MOVE THE CROSSING TOWARD THE IDEAL VALUE 04862-083 The AD973x differential output stage is adjustable to equalize the charge injection into the positive and negative outputs. This adjustment impacts certain performance characteristics, such as harmonic distortion or IMD. System performance can be enhanced by adjusting the cross controller. Figure 85. Effect of UPDEL and DNDEL AD9734/AD9735/AD9736 ANALOG CONTROL REGISTERS -110 The AD973x includes some registers for optimizing its analog performance. These registers include temperature trim for the band gap, noise reduction in the output current mirror, and output current mirror headroom adjustments. NOISE (IdBm/Hz) -115 BAND GAP TEMPERATURE CHARACTERISTIC TRIM BITS Using TRMBG<2:0> (Reg. 14, Bits 2:0), the temperature characteristic of the internal band gap can be trimmed to minimize the drift over temperature, as shown in Figure 86. -120 MSEL3 -125 MSEL1 -130 MSEL0 MSEL2 04862-0-085 -135 1.23 -140 1 10 F (kHz) Figure 87. 1/f Noise with Respect to MSEL Bits VREF (V) 001 1.21 010 HEADROOM BITS 011 HDRM<7:0> (Reg. 15, Bits 7:0) are for internal evaluation. Changing the default reset values is not recommended. 100 1.2 101 VOLTAGE REFERENCE 110 1.19 0 10 20 30 40 50 60 70 04862-084 111 1.18 -50 -40 -30 -20 -10 100 80 90 The AD973x output current is set by a combination of digital control bits and the I120 reference current, as shown in Figure 88. TEMPERATURE (C) AD973x Figure 86. Band Gap Temperature Characteristic for Various TRMBG Values FSC<9:0> VBG 1.2V The temperature changes are sensitive to process variations, and Figure 86 may not be representative of all fabrication lots. Optimum adjustment requires measurement of the device operation at two temperatures and development of a trim algorithm to program the correct TRMBG<2:0> values in external nonvolatile memory. VREF - I120 1nF + 10k AVSS DAC CURRENT SCALING IFULL-SCALE I120 04862-086 1.22 000 Figure 88. Voltage Reference Circuit MIRROR ROLL-OFF FREQUENCY CONTROL With MSEL <1:0> (Reg. 14, Bits 7:6), the user can adjust the noise contribution of the internal current mirror to optimize the 1/f noise. Figure 87 shows MSEL vs. the 1/f noise with 20 mA full-scale current into a 50 resistor. The reference current is obtained by forcing the band gap voltage across an external 10 k resistor from I120 (Pin B14) to ground. The 1.2 V nominal band gap voltage (VREF) generates a 120 A reference current in the 10 k resistor. This current is adjusted digitally by FSC<9:0> (Reg. 2, Reg. 3) to set the output full-scale current IFS: I FS = Rev. A | Page 48 of 72 VREF 192 x 72 + x FSC < 9.0 > R 1024 AD9734/AD9735/AD9736 The full-scale output current range is approximately 10 mA to 30 mA for register values from 0x000 to 0x3FF. The default value of 0x200 generates 20 mA full scale. The typical range is shown in Figure 89. VREF (Pin C14) must be bypassed to ground with a 1 nF capacitor. The band gap voltage is present on this pin and can be buffered for use in external circuitry. The typical output impedance is near 5 k. If desired, an external reference can be used to overdrive the internal reference by connecting it to the VREF pin. 35 30 25 20 IPTAT (Pin D14) is used for factory testing. Leave this pin floating. 15 10 5 0 04862-087 IFS (mA) Always connect a 10 k resistor from the I120 pin to ground and use the digital controls to vary the full-scale current. The AD973x is not a multiplying DAC. Applying an analog signal to I120 is not supported. 0 200 400 600 800 1000 DAC GAIN CODE Figure 89. IFS vs. DAC Gain Code Rev. A | Page 49 of 72 AD9734/AD9735/AD9736 APPLICATIONS INFORMATION DRIVING THE DACCLK INPUT 0.1F VCM = 400mV CLK- 04862-088 50 0.1F 50 CLK+ CLK- 50 BAV99ZXCT HIGH SPEED DUAL DIODE VCM = 400mV Figure 91. TTL or CMOS DACCLK Drive Circuit A simple bias network for generating VCM is shown in Figure 92. It is important to use CVDD18 and CVSS for the clock bias circuit. Any noise or other signal that is coupled onto the clock is multiplied by the DAC digital input signal and may degrade the DAC performance. CLK+ 50 LVDS_N_IN 0.1F VCM = 400mV Figure 90. LVDS DACCLK Drive Circuit If a clean sine clock is available, it can be transformer-coupled to DACCLK, as shown in Figure 107. Use of a CMOS or TTL clock can also be acceptable for lower sample rates. It is routed through a CMOS to LVDS translator, then ac-coupled, as described previously. Alternatively, it can be transformercoupled and clamped, as shown in Figure 91. Rev. A | Page 50 of 72 CVDD 1.8V 1k 1nF 287 0.1F 1nF CVSS Figure 92. DACCLK VCM Generator Circuit 04862-090 LVDS_P_IN TTL OR CMOS CLK INPUT 04862-089 The DACCLK input requires a low jitter differential drive signal. It is a PMOS input differential pair powered from the 1.8 V supply, so it is important to maintain the specified 400 mV input common-mode voltage. Each input pin can safely swing from 200 mV p-p to 800 mV p-p about the 400 mV commonmode voltage. While these input levels are not directly LVDS compatible, DACCLK can be driven by an offset ac-coupled LVDS signal, as shown in Figure 90. AD9734/AD9735/AD9736 DAC OUTPUT DISTORTION SOURCES This is the configuration implemented on the evaluation board (Figure 107). The 20 series resistors allow the DAC to drive a less reactive load, which improves distortion. Further improvement is realized by adding the Balun T3 to help provide an equal load to both DAC outputs. The DAC architecture inherently generates third harmonics, the levels of which depend on the output frequency and amplitude generated. If any output signal is rectified and coupled back onto the DAC clock, it can generate additional third-harmonic energy. The distortion components should be identical in amplitude and phase at both AD973x outputs. Even though each singleended output includes a large amount of second-harmonic energy, a careful differential-to-single-ended conversion can remove most of it. Optimum performance at high intermediate frequency (IF) output is obtained with the output circuit shown in Figure 93. IOUTA R19 20 R8 50 R6 50 IOUTB 1 T3 J2, 50 OUTPUT 5 6 5 1 4 4 3 AVSS 3 R17 20 T1 AVSS 04862-091 The second harmonic is mostly due to an imbalance in the output load. The dc transfer characteristic of the DAC is capable of second harmonic distortion of at least -75 dBc. Output load imbalance or digital data noise coupling onto DACCLK causes additional second harmonic distortion. Figure 93. IF Signal Output Circuit Because T1 has a differential input, but a single-ended output, Pin 4 of T1 has a higher capacitance to ground due to parasitics to Pin 3. T1 Pin 6 has lower parasitic capacitance to ground because it drives 50 at Pin 1. This presents an unbalanced load to the DAC output, so T3 is added to improve the load balancing. Refer to Figure 107 for the transformer part numbers. Rev. A | Page 51 of 72 AD9734/AD9735/AD9736 DC-COUPLED DAC OUTPUT An alternate circuit is shown in Figure 95. It suffers from dc offset at the output unless the DAC load resistors are small, relative to the amplifier gain and feedback resistors. 0.5V p-p 0V TO -0.5V IOUTA DAC OUTPUT 20mA FULL SCALE IOUTB 100 25 1k 2k AVSS 25 1k 2V p-p 0V TO -2V OUTPUT 2k AVSS 2V p-p 0V TO -2V IOUTA Figure 95. Differential Op Amp Output Circuit 100 500 OUTPUT AVSS 100 500 IOUTB 2V p-p +1V TO -1V 500 AVSS 100 04862-092 DAC OUTPUT 20mA FULL SCALE 500 Figure 94. Op Amp I to V Conversion Output Circuit Rev. A | Page 52 of 72 04862-093 In some cases, it may be desirable to dc-couple the AD973x output. The best method for doing this is shown in Figure 94. This circuit can be used with voltage or current feedback amplifiers. Because the DAC output current is driving a virtual ground, this circuit may offer enhanced settling times. The settling time is limited by the op amp rather than by the DAC. This circuit is intended for use where the amplifiers can be powered by a bipolar supply. AD9734/AD9735/AD9736 DAC DATA SOURCES The circuit shown in Figure 96 allows optimum data alignment when running the AD973x at full speed. This circuit can be easily implemented in the FPGA or ASIC used to drive the digital input. It is important to use the DATACLK_OUT signal because it helps to cancel some of the timing errors. In this configuration, DATACLK_OUT generates the DDR LVDS DATACLK_IN to drive the AD973x. The circuit aligns the DATACLK_IN and the digital input data (DB<13:0>) as required by the AD973x. The LVDS controller in the AD973x uses DATACLK_IN to generate the internal DSS to capture the incoming data in the center of the valid data window. To operate in 2x mode, the circuit in Figure 96 must be modified to include a divide-by-2 block in the path of DATACLK_OUT. Without this additional divider, the data and DATACLK_IN runs 2x too fast. DATACLK_OUT is always DACCLK/2. Contact FPGA vendors directly regarding the maximum output data rates supported by their products. DATA SOURCE DATA SOURCE D1 DATA1 DB(13:0) TO AD9736 MUX DATA2 DATA2 LOGIC 1 LOGIC 0 04862-094 DATACLK_IN TO AD9736 (DDR) MUX DB(13:0) TO AD9736 MUX DATACLK_IN TO AD9736 (DDR) D2 D2 LOGIC 0 LOGIC 1 MUX 04862-096 D1 DATA1 DATACLK_OUT FROM AD9736 (DDR) /2 DATACLK_OUT FROM AD9736 (DDR) Figure 96. Recommended FPGA/ASIC Configuration for Driving AD9736 Digital Inputs, 1x Mode Figure 98. Recommended FPGA/ASIC Configuration for Driving AD9736 Digital Inputs, 2x Mode DATACLK_OUT+ DATACLK_OUT+ DATA2 D1 A C D B A DATA1 C D2 DB CLK_OUT+/2 E D B A DATA2 B D1 C A C D B A C 04862-095 Figure 97. FPGA/ASIC Timing for Driving AD973x Digital Inputs, 1x Mode DB DATACLK_IN+ D B D2 DATACLK_IN+ E A B C 04862-097 DATA1 Figure 99. FPGA/ASIC Timing for Driving AD973x Digital Inputs, 2x Mode Rev. A | Page 53 of 72 AD9734/AD9735/AD9736 INPUT DATA TIMING The AD973x is intended to operate with the LVDS and sync controllers running to compensate for timing drift due to voltage and temperature variations. In this mode, the key to correct data capture is to present valid data for a minimum amount of time. The AD973x minimum valid data time is measured by increasing the input data rate to the point of failure. The nominal supply voltages are used and the temperature is set to the worst case of 85C. The input data is verified via the BIST signature registers, because the DAC output does not run as fast as the input data logic. The following example explains how the minimum data valid period is calculated for the typical performance case. The ability of the AD973x to capture incoming data is dependent on the speed of the silicon, which varies from lot to lot. The typical (or average) silicon speed operates with data that is valid for 225 ps at 85C. Statistically, the worst extreme for slow silicon may require up to a 344 ps valid data period, as specified in Table 2. Table 27. Typical Minimum Data Valid Times Differential Input Voltage 400 mV 250 mV These factors must be considered in determining the minimum valid data window at the receiver input: * Data rise and fall times: 100 ps (rise + fall) * Internal clock jitter: 10 ps (DATACLK_OUT + DATACLK_IN) * Bit-to-bit skew: 50 ps * Bit-to-DATACLK_IN skew: 50 ps * Internal data sampling signal resolution: 80 ps For nominal silicon, the BIST typically indicates failure at 2.15 GSPS or a DACCLK period of 465 ps. The valid data window is calculated by subtracting all the other variables from the total data period: Minimum Data Valid Time = DACCLK Period - Data Rise - Data Fall - Jitter - Bit-to-Bit Skew - Bit-to-DATACLK_IN Skew - Data Sampling Signal Resolution BIST Max fCLK 2.15 GHz 2.00 GHz Min Clock Period 465 ps 500 ps Typ Min Data Valid at Receiver 225 ps 260 ps At 1.2 GHz, the typical 400 mV p-p minimum data valid period of 225 ps leaves 608 ps for external factors. Under the same conditions, the worst expected minimum data valid period of 344 ps leaves 489 ps for external data uncertainty. The 100 mV LVDS VOD threshold test is a dc test to verify that the input logic state changes. It does not indicate the operating speed. The ability of the receiver to recover the data depends on the input signal overdrive. With a 250 mV input, there is a 150 mV overdrive, and with a 400 mV signal, there is a 300 mV overdrive. The relationship between overdrive level and timing is very nonlinear. Higher levels of overdrive result in smaller minimum valid data windows. For typical silicon, decreasing the LVDS swing from 400 mV p-p to 250 mV p-p requires the minimum data valid period to increase by 15%. This is illustrated in Figure 100. 225ps For the 400 mV p-p LVDS signal case: 400mV Minimum Data Valid = 465 ps - 100 ps - 10 ps - 50 ps - 80 ps = 465 ps - 240 ps = 225 ps 260ps 04862-098 250mV For correct data capture, the input data must be valid for 225 ps. Slower edges, more jitter, or more skew require an increase in the clock period to maintain the minimum data valid period. Table 27 shows the typical minimum data valid period (tMDE) for 400 mV p-p differential and 250 mV p-p differential LVDS swings. Figure 100. Typical Minimum Valid Data Time (tMDE) vs. LVDS Swing The minimum valid data window changes with temperature, voltage, and process. The maximum value presented in the specification table was determined from a 6 distribution in the worst-case conditions. Rev. A | Page 54 of 72 AD9734/AD9735/AD9736 SYNCHRONIZATION TIMING When more than one AD973x must be synchronized or when a constant group delay must be maintained, the internal controllers cannot be used. If the FIFO is enabled, the delay between multiple AD973x devices is unknown. If the DATACLK_OUT from multiple devices is used, there is an uncertainty of two DACCLK periods because the initial phase of DATACLK_OUT with respect to DACCLK cannot be controlled. This means one DAC must be used to provide DATACLK_OUT for all synchronized DACs and all timing must be externally managed. The following timing information allows system timing to be calculated so that multiple AD973xs can be synchronized. DATACLK_OUT changes relative to the rising edge of DACCLK+ and is delayed, as shown in Figure 101. Because DACCLK is divided by 2 to create DATACLK_OUT, the phase of DATACLK_OUT can be 0 or 180. There is no way to predict or control this relationship. It can be different after each power cycle and is not affected by hardware or software resets. DACCLK tDDCO 04862-099 DATACLK_OUT Figure 101. DACCLK to DATACLK_OUT Delay The incoming data is de-interleaved internally as shown in Figure 78. In Figure 78, DBU (upper) and DBL (lower) represent the de-interleaved data paths. Each edge of DATACLK_IN latches an incoming sample in two alternating registers. The DATACLK_IN to data setup and hold definitions are illustrated in Figure 102. All the data input must be valid during the setupand-hold period. External skew effectively increases the setup and hold times that the data source must meet. DATACLK_IN OR DATACLK_OUT While correct DATA_IN vs. DATACLK_IN timing is critical, the transition of the incoming data to the DACCLK domain is equally critical. By referencing the incoming DATA and DATACLK_IN timing to the DATACLK_OUT signal, some timing uncertainty can be removed. The DATACLK_OUT timing very closely tracks the timing of the DACCLKcontrolled registers. Any variation in the path delay affects both paths in almost the same way. If DATACLK_OUT is not used, the full DACCLK to DATACLK_OUT path variation reduces the external timing margin. Figure 101 shows a simplified view of the internal clocking scheme with the relevant delay paths. The internal architecture is interleaved such that each phase has twice as long to make the transition across the clock domains. This results in an extremely narrow window where the incoming data must be held stable. Table 28 shows the timing parameters for Figure 101 and Figure 102. These parameters were measured for a sample of five devices from five silicon lots. Worst-case fast and slow skew lots were included in addition to the nominal (or average) lot. The typical -40C to typical +85C spread illustrates the variability with temperature for a single lot. Adding in lot-to-lot variation with the fast and slow lots indicates the worst-case spread in timing. The timing varies such that all of the parameters move in the same direction. For example, if the DATACLK_IN to data setup time is fast, the hold time is similarly fast. The DACCLK to DATACLK_OUT delay and the DATACLK_OUT to data setup and hold is also at the fast end of the range. Note that the polarities of setup-and-hold values in Table 28 conform to the standard convention of setup time occurring prior to the latching edge and hold time occurring after the latching edge, as shown in Figure 102. tDSU tDH 04862-100 DATA_IN Figure 102. Standard Definitions for DATACLK_IN or DATACLK_OUT to Data Setup and Hold, SD = 0 Table 28. AD973x Clock and Data Timing Parameters Symbol and Definition tDDCO - DACCLK to DATACLK_OUT Delay tDCISU - DATACLK_IN to DATA Setup tDCIH - DATACLK_IN to DATA Hold tDISU - DATACLK_OUT to DATA Setup tDIH - DATACLK_OUT to DATA Hold Fast -40C +1650 -100 +210 +1310 -1250 Typ -40C +1800 -120 +220 +1440 -1360 Rev. A | Page 55 of 72 All +25C +1890 -150 +240 +1611 -1548 Typ +85C +2050 -170 +280 +1710 -1640 Slow +85C +2350 -220 +360 +1970 -1890 Unit ps ps ps ps ps AD9734/AD9735/AD9736 POWER SUPPLY SEQUENCING The 1.8 V supplies should be enabled prior to enabling the 3.3 V supplies. Do not enable the 3.3 V supplies when the 1.8 V supplies are off. DATACLK_IN DOMAIN DACCLK DOMAIN D1 FF DAC_DATA LVDS RX FF DATA SAMPLING SIGNAL SD<3:0> SD<3:0> SAMPLE DELAY DELAY SAMPLE DATACLK_IN DATACLK_OUT LVDS RX LVDS TX DAC CORE DAC_OUTPUT D2A D2 FF DAC SAMPLING SIGNAL PATH A /2 CLK RX DACCLK PATH B COMMON SYSTEM CLOCK DELAYS THROUGH PATH A AND B WILL TRACK, THUS REDUCING TIMING UNCERTAINTY IN THE SYSTEM Figure 103. Simplified Internal Clock Routing Rev. A | Page 56 of 72 04862-101 DB<13:0> D1A FF AD9734/AD9735/AD9736 AD973X EVALUATION BOARD SCHEMATICS TP4 RED FERRITE VDD33 LC1210 + ACASE C14 10F 6.3V VSS TB1 2 L7 TP7 RED FERRITE LC1210 18DIG TB1 3 VSS TP5 BLK L5 VDD18B + C22 ACASE 10F 6.3V FERRITE LC1210 TP13 BLK TP6 RED + ACASE VSS TB1 4 VSS VDD18A L1, L3, L4, L5, L6, AND L7 FERRITE BEAD CORE: PANASONIC EXC-CL3225U1 DIGIKEY PN: P9811CT-ND C18 10F 6.3V TP14 BLK VSS JP1 VSS L1 33ANA TB2 1 FERRITE LC1210 VSSA TB2 4 C1 10F 6.3V TP3 BLK L3 FERRITE LC1210 L4 VSSA POWER INPUT FILTERS TP9 RED VDDC + ACASE FERRITE LC1210 VSSA UNDER DUT VDDA33 + ACASE VSSA TB2 2 18ANA TB2 3 TP1 RED C10 10F 6.3V TP11 BLK VSSA Figure 104. Power Supply Input for AD973x Evaluation Board, Rev. F Rev. A | Page 57 of 72 04862-102 L6 33DIG TB1 1 Rev. A | Page 58 of 72 Figure 105. Circuitry Local to AD973x, Evaluation Board, Rev. F ACASE 04862-103 VSSA 6.3V 4.7F C11 VDDC C13 C12 1nF CC0603 0.1F CC0603 CLKN CLKP DNP CC063 C5 A7 B7 C7 D7 A4 A5 A6 B4 B5 B6 C4 C5 C6 D4 D5 D6 A1 A2 A3 B1 B2 B3 C1 C2 C3 D2 D3 D1 E1 F1 E2 E3 E4 F2 F3 F4 G1 G2 G3 G4 HYDROGEN TOP IP1 IN1 IP2 IN2 AD9736 IP3 IN3 IP4 IN4 VSSA331 VSSA3313 VSSA332 VSSA3314 VSSA333 VSSA3315 VSSA334 VSSA3316 VSSA335 VSSA3317 VSSA336 VSSA3318 VSSA337 VSSA3319 VSSA338 VSSA3320 VSSA339 VSSA3321 VSSA3310 VSSA3322 VSSA3311 VSSA3323 VSSA3312 VSSA3324 VDDA331 VDDC1 VDDA332 VDDC2 VDDA333 VDDC3 VDDA334 VDDC4 VDDA335 VDDC5 VDDA336 VDDC6 VDDA337 VDDC7 VDDA338 VDDC8 SPARE VDDC9 I120 VDDC10 VDDC11 VREF VSSC1 IPTAT CLKN SIGNED_IRQ CLKP PD_RESET VSSC2 2X_CSB VSSC3 FIFO_SDIO VSSC4 FSC0_SCLK VSSC5 FSC1_SDO VSSC6 SHIELD1 VSSC7 SHIELD2 VSSC8 SHIELD3 VSSC9 SHIELD4 VSSC10 SHIELD5 VSSC11 U1 SHIELD6 CC060 C4 1nF C3 0.1F R5 10k SPCSB SPSDI SPCLK SPSDO 4 3 TP16 WHT SPARE VSS VSS;5 SW1 RESET JP3 VSS ACASE 1 2 C9 1nF VSSA R1 0.1% 10k VSSA VDD33 CC0603 C24 0.1F VDD33 VSS ACASE VDD33 C21 1nF DB13N DB13P DB12N DB12P DB11N DB11P DB10N DB10P DB9N DB9P DB8N DB8P DCLKNOUT DCLKPOUT JP15 CC0603 DNP CC0603 C7 C25 1nF 3 A B 2 1 JP8 3 A B 2 1 C20 0.1F CC0603 H1 H2 H3 H4 J1 J2 J3 J4 K3 K4 L3 L4 L5 L6 M3 M4 M5 M6 K2 K1 L2 L1 M2 M1 N1 P1 N2 P2 N3 P3 N4 P4 N5 P5 N6 P6 L7 M7 N7 P7 HYDROGEN VDD16 VDD1 U1 VDD15 VDD2 AD9736 VDD14 VDD3 VDD13 VDD4 VDD12 VDD5 VDD11 VDD6 VDD10 VDD7 VDD9 VDD8 VSS20 VSS1 VSS19 VSS2 VSS18 VSS3 VSS17 VSS4 VSS16 VSS5 VSS15 VSS6 VSS14 VSS7 VSS13 VSS8 VSS12 VSS9 VSS11 VSS10 VSS21 LVDS13N NCK1 LVDS13P VSS22 LVDS12N SPI_MODE LVDS12P LVDS0N LVDS11N LVDS0P LVDS11P LVDS1N LVDS10N LVDS1P LVDS10P LVDS2N LVDS9N LVDS2P LVDS9P LVDS3N LVDS8N LVDS3P LVDS8P LVDS4N LVDS7N LVDS4P LVDS7P LVDS5N LVDS6N LVDS5P LVDS6P LVDSCLKOUTN LVDSCLKINN LVDSCLKOUTP LVDSCLKINP VDD331 VDD338 VDD332 VDD337 VDD333 VDD336 VDD334 VDD335 BOTTOM H14 H13 H12 H11 J14 J13 J12 J11 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 K13 K14 L13 L14 M13 M14 N14 P14 N13 P13 N12 P12 N11 P11 N10 P10 N9 P9 L8 M8 N8 P8 NOTE: AD9736 MSB -LSB BIT ORDER IS REVERSED FROM THE CONNECTOR BIT ORDER. C15 CC0603 C16 CC0603 C17 0.1F 1nF 4.7F 6.3V WHT WHT TP8 TP10 VREF I120 CC0603 CC0603 C19 4.7F 6.3V VDD18A C23 4.7F 6.3V VDD33 RC0603 RESET_A TP12 WHT IPTAT IRQ JP4 C2 4.7F 6.3V VSS ACASE VDDA33 ACASE VSSA VDD18B IRQ TP2 C6 WHT CC0603 R16 10k DNP CC0603 VSSA A8 B8 C8 D8 A9 A10 A11 B9 B10 B11 C9 C10 C11 D9 D10 D11 A12 A13 B12 B13 C12 C13 D12 D13 A14 B14 C14 D14 E13 E14 F13 F14 G13 G14 E11 E12 F11 F12 G11 G12 IN IP VSS DNP CC0603 C34 DB0N DB0P DB1N DB1P DB2N DB2P DB3N DB3P DB4N DB4P DB5N DB5P DB6N DB6P DB7N DB7P DCLKNIN DCLKPIN CC0603 C8 DNP AD9734/AD9735/AD9736 RC1206 Rev. A | Page 59 of 72 Figure 106. High Speed Digital I/O Connector, AD973x Evaluation Board, Rev. F DB0 DB13 DB13 DB0 04862-104 AD9736 CONNECTOR NOTE: AD9736 MSB-LSB BIT ORDER IS REVERSED FROM THE CONNECTOR BIT ORDER. EXTCLK TESTOUTP TP15 WHT JACK TESTOUTN G1 S1 G3 S3 G5 S5 G7 S7 G9 S9 G11 S11 G13 S13 G15 S15 G17 S17 G19 S19 G21 S21 G23 S23 G25 S25 G27 S27 G29 S29 G31 S31 G33 S33 G35 S35 G37 S37 G39 S39 G41 S41 G43 S43 G45 S45 G47 S47 G49 G2 S2 G4 S4 G6 S6 G8 S8 G10 S10 G12 S12 G14 S14 G16 S16 G18 S18 G20 S20 G22 S22 G24 S24 G26 S26 G28 S28 G30 S30 G32 S32 G34 S34 G36 S36 G38 S38 G40 S40 G42 S42 G44 S44 G46 S46 G48 S48 G50 JACK FCN-268 F024-G/0 D J3 VSS DB0P DB1P DB2P DB3P DB4P DB5P DB6P DB7P DCLKPIN DCLKPOUT DB8P DB9P DB10P DB11P DB12P DB13P DB13N DB12N DB11N DB10N DB9N DB8N DCLKNOUT DCLKNIN DB7N DB6N DB5N DB4N DB3N DB2N DB1N DB0N AD9734/AD9735/AD9736 Rev. A | Page 60 of 72 Figure 107. Clock Input and Analog Output, AD973x Evaluation Board, Rev. F 04862-105 VSSA IP IN R7 DNP RC0603 RC0603 VSSA RC0603 RC0603 RC0603 R19 20 R17 20 RC0603 R18 DNP RC0603 R17 AND R19 PRESENT A MORE REAL LOAD TO THE DAC WHICH IMPROVES H2 PERFORMANCE. R8 50 R6 50 RC0603 VSSA J1 VSSA;3,4,5 SMA200UP R162 0 R161 0 S T3 NC=2 S P P 5 4 3 2 1 P T3B T3:M/A-COM -1dB: 4.5-1000MHz S P NC=2 S S P P T4B NC=2 S T1 5 4 3 2 1 ETC1-1-13 4 5 6 1 1 0.1F 0.1F VSSA 415mV COMMON MODE VOLTAGE 400mV p-p C36 C35 C28 C29 DNP 1nF C38 1nF CC0603 VSSA VDDC CLKN CLKP AN LVDS SIGNAL MAY BE USED TO DRIVE C35 AND C36 IF R20 AND R21 ARE INCREASED TO 50 EACH. 0.1F C27 CC0603 CC0603 DNP VSSA VSSA;3,4,5 SMA200UP J2 C26 CC0603 CC0603 300 R4 1k R3 RC0603 R17 AND R19 CAN BE REMOVED AND T1 REPLACED WITH A 1:1 TRANSFORMER FOR HIGHER OUTPUT AMPLITUDE IF MORE H2 IS ACCEPTABLE (TYPICALLY AT LOWER FOUT). T1:MINI-CIRCUITS -3dB: 8-600MHz -1dB: 13-300MHz 5 ADT2-1T-1P 3 6 4 ETC1-1-13 4 3 1 3 VSSA T2 AND T4B ARE NOT POPULATED ETC1-1-13 1 3 4 5 6 T2 ADT2-1T-1P T3A ADTL1-12XX CC0603 CC0603 RC0603 R21 25 RC0603 T3A IS NOT POPULATED THIS CONFIGURATION PROVIDES OPTIMUM AC PERFORMANCE FOR IF SIGNAL GENERATION. TYPICAL SIGNAL LEVELS SHOWN FOR 50 LOAD. JUMPER ADDED FROM T1 PIN 3 TO T1 PIN 2 ON THE REV. C EVAL BOARD. NOTE: T1, T3, AND T3B ARE INSTALLED, R6 AND R8 = 50, R7 = DNP R17 AND R19 = 20, R161 AND R162 = 0, RC0603 R20 25 AD9734/AD9735/AD9736 Rev. A | Page 61 of 72 Figure 108. SPI Port Interface, AD973x Evaluation Board, Rev. F 04862-106 VDD33 VDD33 1 1 1 A B 2 JP10 A B 2 JP9 A B 2 JP14 A B 2 JP13 VSS IRQ 1 JP12 3 A B 2 VSS VSS RC0603 VSS R13 10k JP5 VSS JP6 VSS VSS JP7 JP2 3 3 3 3 RESET_A 1 JP11 3 A B 2 SPSDO VDD33 SPSDI VDD33 SPCLK VDD33 SPCSB 1 RC0603 VDD33 R14 10k 2 VSS;7 VDD33;14 5 VSS;7 VDD33;14 3 VSS;7 VDD33;14 1 74AC14 6 74AC14 4 74AC14 1 2 4 6 13 74AC14 8 R10 11 R11 12 10 8 FERRITE 74AC14 U6 74AC14 FERRITE RC0805 9k RC0805 9k RC0805 9k 2 6.3V + C30 ACASE 4.7F VDD33 R12 VSS;7 VDD33;14 9 VSS;7 VDD33;14 U6 LC1210 L9 13 VSS;7 VDD33;14 74AC14 LC1210 L8 VSS;7 VDD33;14 9 VSS;7 VDD33;14 11 U5 U5 U6 10 74AC14 U5 FERRITE BEAD CORE: PANASONIC EXC-CL3225U1 DIGIKEY PN: P9811CT-ND VSS 74AC14 U6 74AC14 U6 12 74AC14 VSS;7 VDD33;14 VSS;7 VDD33;14 5 VSS;7 VDD33;14 3 VSS;7 VDD33;14 74AC14 U6 U5 U5 U5 SPI PORT USE THESE JUMPERS TO SET PIN_MODE CONTROL SIGNALS OR CONNECT SPI PORT SIGNALS IN SPI_MODE. CC0805 C31 0.1F + C32 P1 6.3V ACASE 4.7F 2 1 2 3 4 5 6 CC0805 C33 0.1F AD9734/AD9735/AD9736 AD9734/AD9735/AD9736 04862-107 NOTE: THE AD9736 IS SOLDERED DIRECTLY TO THE PCB. THE SOCKET IS NOT INSTALLED. SILKSCREEN ERROR: SPI AND PIN ARE REVERSED. AD973X EVALUATION BOARD PCB LAYOUT Figure 109. CB Layout Top Placement, AD973x Evaluation Board, Rev. F Rev. A | Page 62 of 72 04860-108 AD9734/AD9735/AD9736 Figure 110. PCB Layout Layer 1, AD973x Evaluation Board, Rev. F Rev. A | Page 63 of 72 04861-109 AD9734/AD9735/AD9736 Figure 111. PCB Layout Layer 2, AD973x Evaluation Board, Rev. F Rev. A | Page 64 of 72 04862-110 AD9734/AD9735/AD9736 Figure 112. PCB Layout Layer 3, AD973x Evaluation Board, Rev. F Rev. A | Page 65 of 72 014862-111 AD9734/AD9735/AD9736 Figure 113. PCB Layout Layer 4, AD973x Evaluation Board, Rev. F Rev. A | Page 66 of 72 04862-112 AD9734/AD9735/AD9736 Figure 114. PCB Layout Bottom Placement, AD973x Evaluation Board, Rev. F Rev. A | Page 67 of 72 04862-113 4. WARP AND TWIST +/- .005 INCH PER INCH. 5. DIMENTIONS: ARE FOR THE FINISHED PART 6. SOLDER MASK: LIQUID PHOTO IMAGABLE SOLDER MASK COLOR GREEN, BOTH SIDES USING THE PATTERN(S) PROVIDED. NO MASK IS PERMITTED ON THE EXPOSED AREAS. SOLDER MASK TO ETCH REGISTRATION +/- .002 INCH TOTAL 7. SCREENING: SCREEN COMPONENT OUTLINES AND NOMENCLATURE USING OPAQUE WHITE INK ON THE PRIMARY AND SECONDARY SIDES (AS REQUIRED). NOMENCLATURE SHALL BE LEGIBLE. SCREEN TO ETCH REGISTRATION +/- .005 INCH TOTAL. 8. SURFACES: PUNCHED OR MACHINED SURFACES 125 MICRO INCHES RMS MAX. 9. BREAK ALL SHARP EDGES .015 R MAX. 10. FABRICATION VENDOR TO ADD UL VENDOR ID NUMBER IN THIS AREA ON THE SECONDARY SIDE 11. DO NOT DRILL. FOR GOLD PLATED SOCKETED VERSION ONLY. 3. PROCESSING TOLERANCES: A. CONDUCTIVE PATTERN FRON TO BACK REGISTRATION +/- .002 INCH TOTAL B. MINIMUM ANNULAR RING SURROUNDING HOLES .002 INCH. C. FINISHED CONDUCTIVE PATTERN +/- .0005 INCH OF APERTURE SIZE. NOTES 1. MATERIAL: FOUR LAYER, FR4 GLASS-EPOXY LAMINATE .062 +/- .007 THICK 1/4 OZ. COPPER CLAD - EXTERNAL LAYERS PLATED TO 1 OUNCE 2 OZ. COPPER CLAD - INTERNAL LAYERS 2. PLATED THRU HOLES AND THE CONDUCTIVE PATTERN ELECTROPLATED WITH .001 INCH MIN. THICK COPPER. TERMINAL AREAS AND EXPOSED PLATED THRU HOLES TO BE COATED WITH SOLDER AND HOT AIR LEVELED. AD9734/AD9735/AD9736 Figure 115. PCB Fabrication Detail, AD973x Evaluation Board, Rev. F Rev. A | Page 68 of 72 AD9734/AD9735/AD9736 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 12.10 12.00 SQ 11.90 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BALL A1 INDICATOR 10.40 BSC SQ TOP VIEW BOTTOM VIEW 0.80 REF DETAIL A A B C D E F G H J K L M N P 0.80 BSC 1.40 MAX DETAIL A 1.00 MAX 0.85 MIN 0.43 MAX 0.25 MIN 0.55 0.50 0.45 BALL DIAMETER SEATING PLANE 0.12 MAX COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-205-AE. Figure 116. 160-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-160-1) Dimensions shown in millimeters ORDERING GUIDE Model AD9734BBC AD9734BBCRL AD9734BBCZ1 AD9734BBCZRL1 AD9735BBC AD9735BBCZ1 AD9735BBCRL AD9735BBCZRL1 AD9736BBC AD9736BBCRL AD9736BBCZ1 AD9736BBCZRL1 AD9734-EB AD9735-EB AD9736-EB 1 Z = Pb-free part. Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) 160-Lead Chip Scale Package Ball Grid Array (CSP_BGA) Evaluation Board Evaluation Board Evaluation Board Rev. A | Page 69 of 72 Package Option BC-160-1 BC-160-1 BC-160-1 BC-160-1 BC-160-1 BC-160-1 BC-160-1 BC-160-1 BC-160-1 BC-160-1 BC-160-1 BC-160-1 AD9734/AD9735/AD9736 NOTES Rev. A | Page 70 of 72 AD9734/AD9735/AD9736 NOTES Rev. A | Page 71 of 72 AD9734/AD9735/AD9736 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04862-0-9/06(A) Rev. A | Page 72 of 72