M41T81M6TR - STMicroelectronics, Inc.

1/27June 2005

M41T81

Serial Access Real-Time Clock with Alarms

Rev 7

FEATURES SUMM ARY

■2.0 TO 5 .5 V C L O C K O PER AT IN G VOLTAGE

■COUNT ERS FOR TENTHS/HUNDREDTHS

OF SECONDS, SECONDS, MINUTES,

HOURS, DAY, DATE, MONT H, YEAR, AND

CENTURY

■AUTOMATIC SWITCH-OVER AND

DESELECT CIRCUITRY

■SERIA L INT ERFACE SU PPORTS I 2C BUS

(400kHz PROTOCOL)

■PROGRAMMABLE ALARM AN D

INTERRUPT FUNCTION (VAL ID EVEN

DURING BATTERY BACK-UP MO DE )

■WA TCHDOG TIMER

■POWER -DOWN TIME-STAMP (HT B it)

■LOW OPERATING CURRENT OF 400µ A

■BATTERY BA CK-UP NOT RECOM MENDED

FOR 3.0V APPLICATIONS (CAPACITOR

BACK-UP ONL Y)

■BATTERY OR SUPER- C AP BACK-UP

■OP ERAT ING TEMPER ATURE OF –40 TO

85°C

■ULTRA-L OW BA TTERY SUPP LY CURRENT

OF 1µA

Figure 1. Packages

SO8 (M)

8-pin SOIC

M41T81

2/27

TABLE OF CONTENTS

FEATUR ES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUM MARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signa l Na mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. 8-pin SOIC (M) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2-Wire Bus Chara cteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Stop data transfe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Acknowl edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. Acknowledg eme nt Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 7. Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. READ Mode S equen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 9. Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

WRITE M ode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Re tention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 10.WRITE Mode Seq uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CLOCK O PERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

TIMEKEEPER® Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Table 2. TIMEKEEPER® Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 13.Alarm Interrupt Reset Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 14.Back-up Mode Alarm Wavefo rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Alarm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Sq uare Wave Outp ut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

Table 4. S quare Wave Out put Frequen cy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Centur y Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Prefe rred Initial Power -on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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M41T81

Table 5. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Absolute Maximum Rati ngs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DC AND AC PARAM ETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. Operating a nd AC Measurement Cond itions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 15.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10. Crystal Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 16.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 17.Bus Timing Requiremen ts Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PACKAGE MECHANICAL INFORMATIO N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 18.SO8 – 8-lead Plastic Small Package Out line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14. SO8 – 8-lead P lastic Small Outline (150 mils body width), Package Mecha nical Data. . 24

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15. Orderi ng Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

REVISION HISTO RY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. Document Revisi on History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

M41T81

4/27

S UM MARY DESCRIPTION

The M41T81 Serial Access TIMEKEEPER®

SRAM is a low power Serial RTC with a built-in

32.768kHz oscillator (external crystal controlled).

Eight bytes of the SRAM (see Table 2., page 12)

are used for the clock/calendar function and are

configured in bina ry cod ed dec imal (BCD) form at.

An additional 12 bytes of SRAM provide status/

control of Alarm, Watchdog and Square Wave

functions. Addresse s and data are transferred se-

rially via a two line, bi-directional I2C in ter fac e. The

built-in address register is incremented automati-

cally after e ach WRITE or READ data byte.

The M41T81 has a built-in power sense circuit

which detects power failures and automatically

switches to the battery sup ply when a power fail-

ure occurs. The energy needed to sustain the

SRAM and clock ope ra tions can be supplied by a

small lithium button supply when a power failure

occurs.

Functions avai lable to the use r i nclude a non-v ol-

atile, time-of-day clock/calendar, Alarm interrupt s,

Watchdog Timer and programmable Square

Wave output. The eight clock address locations

contain the century, year, month, d ate, day, hour,

minute, second and tenths/hundredths of a sec-

ond in 24 hour BCD format. Corrections for 28, 29

(leap year - valid until year 2100), 30 and 31 day

months are made automat ically.

The M41T8 1 is supplied in an 8-pin SOIC.

Figure 2. Logic Diagram Tabl e 1. Signal Names

SCL

VCC

M41T81

VSS

SDA

IRQ/FT/OUT/SQW

VBAT

AI04613

XI Oscillator Input

XO Oscillator Output

IRQ/OUT/

FT/SQW Interrupt / Output Driv er / F requency

Test / Square Wave (Open Drain)

SDA Serial Data Input/Output

SCL Serial Clock Input

VBAT Battery Supply Voltage

VCC Supply Voltage

VSS Ground

NC No Connect

NF No Function

5/27

M41T81

Figure 3. 8-pin SOIC (M) Connections

Figu re 4. Blo ck Diagram

Note: 1. Ope n drain output

2. Square Wave fun ct i on has th e hi ghest pr i ori t y on IRQ / FT/ OU T/SQ W output.

3. VSO = VBAT – 0. 5V (typ)

1IRQ/FT/OUT/SQW

SDA

VBAT SCL

VSS

XI VCC

M41T81

AI04769

AI04616

REAL TIME CLOCK

CALENDAR

RTC W/ALARM

& CALIBRATION

WATCHDOG

SQUARE WAVE

FREQUENCY TEST

OUTPUT DRIVER

IRQ/FT/OUT/SQW(1,2)

INTERNAL

POWER

SQWE

AFE

SDA

SCL

VCC

COMPARE

I2C

INTERFACE

32KHz

OSCILLATOR

VBAT

CRYSTAL

VSO(3)

WRITE

PROTECT

OUT

M41T81

6/27

OPERATION

The M41T 81 clock operates as a s lave device on

the serial bus . Access is obtained by implementing

a start condition f ollowed by the correc t slave ad-

dress (D0h). The 20 bytes contained i n the device

can then be accessed s equential ly i n t he fol lowing

order:

1. Tenths/ Hundredths of a Second Register

2. Seconds Register

3. Min utes Register

4. Century/Hours Register

5. Day Register

6. D ate Register

7. Month Regist er

8. Yea r Register

9. Control Register

10. Watchdog Register

11 - 16. Ala rm Registers

17 - 19. Reserved

20. Square Wave Register

The M41T81 clock c ont inually monitors VCC for an

out-of-tolerance condition. Should VCC fall below

VSO, the de vice te rminates an ac ces s in progress

and resets the device address counter. Inputs to

the device will not be recognized at this time to

prevent erroneous data from being written to the

devi ce from a an ou t-of-tole ran ce system. The d e-

vice also automatically swit ches over to the battery

and powers down into an ultra l ow current mode of

operation to conserve battery life. As system pow-

er returns and VCC rises above VSO, the battery is

disconnected, and the power suppl y is switched to

external VCC.

For more information on Battery Storage Li fe refer

to Application Note AN1012.

2-Wire Bus Characteristics

The bus is intended for communication between

different ICs. It consists of two lines: a bi -direction-

al data signal (SDA) and a clock signal (SCL).

Both the SDA and SCL lines mus t be connected to

a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

– Data transfer may be initiated only when the

bus i s not busy.

– During data transfer, the data line must remain

stable whenever the clock line is High.

– Changes in the data line, while the clock line is

H igh, will be inte rpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer . A change in the state of the

data line, from high to Low, while the clock is High,

defines the START condi tion.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition .

Data Va lid. The state of the data line represents

valid data when after a start condition, the dat a line

is stable for the duration of the high period of the

clock signal. The data on the line may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a start condi tion

and terminated with a stop condition. The number

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each rec eiver ack nowl-

edges with a ninth bit .

By definition a dev ice t hat gives o ut a m essag e is

called “transmitter,” the receiving dev ice that gets

the message is called “receiver.” The device that

controls the message is called “master.” The de-

vices that are controlled by th e ma ster are called

“slaves.”

Acknowledge. E ac h byte of eig ht bits is foll owed

by one Acknowledge B it. Thi s Acknowledge Bit is

a low level put on t he bus by the receiver whereas

the master generates an extra ac knowled ge relat-

ed clock pulse. A slave receiver which is ad-

dressed is obliged to generate an acknowledge

after the reception of each byte that has been

clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times mus t

be taken int o account. A master recei ver must sig-

nal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that

has been clocked out of the slave. In this case the

transmitter must l eave the data l ine High to enable

the mast er to generate the S TOP condition.

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M41T81

Figure 5. Serial Bus Data Transfer Sequen ce

Figure 6. Acknowledgement Sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

M41T81

8/27

READ Mode

In this mode the master reads the M41T81 slave

after setting the slave address (see Figure

8., page 9). Following the WRITE Mode Control

Bit (R/W=0) and the Acknowledge Bit, the word

address 'An' is written to the on-chip address

pointer. Next the START condition and slave ad-

dress are repeated followed by the READ Mode

Control Bit (R/W=1). At this point the master trans-

mitter becomes the master receiver. The data byte

which was addressed will be transmitted and the

master receiver will send an Acknowledge Bit to

the slave transmitter. The address pointer is only

incremented on reception of an Acknowledge

Clock. The M41T81 slave transmitter will now

place the data byte at address An+1 on the bus,

the master receiver reads and acknowledges the

new byte and the ad dress p ointer is incremented

to “An+2.”

This cycle of reading consecutive addresses will

continue until the master receiver sends a STOP

condition to the slave transmitter.

The system-to-user transfer of clock data will be

halted whenever the address bei ng read is a clock

address (00h to 07h). The update will re su me due

to a Stop Condition or when the pointer increments

to any non-clock address (08h-13h).

Note: This is true bot h in READ Mode and WRITE

Mode.

An alternate READ Mode may al so be implement-

ed whereby the master reads the M41T81 slave

without first w ri tin g to the (volatile) addres s point-

er. The first address that is read is the last one

stored in the p ointer (see Figure 9. , page 9).

Figure 7. Slave Address Locat ion

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

9/27

M41T81

Figure 8. READ Mode Sequence

Figure 9. Alternative READ Mode Se quence

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

M41T81

10/27

WRITE Mod e

In this mode the master transmitter transmits to

the M41T81 slav e receiver. Bus protocol is shown

in Fig ure 10., page 10. Following the STA RT con-

dition and slave address, a logic '0' (R/W=0) is

placed on the bus and indicates to the addressed

dev ic e t h at word addre s s “ An ” w ill follow a nd is t o

be written to the on-chip addres s pointer. The data

word to be written to the memory is strobed in nex t

and the internal address pointer is increme nted to

the next address location on the reception of an

acknowledge clock. The M41T81 slave receiver

will send an acknowledge clock to the master

transmitter after i t has received the slave address

see Figure 7., page 8 and again after it has re-

ceived the word address and each data byte.

Data Reten tion Mode

With valid VCC applied, the M41T81 can be ac-

cessed as des cribed ab ov e with REA D or WRI TE

Cycles. Should the supply voltage decay, the pow-

er input will be switched from the VCC pin to the

battery when V CC falls below the Batt ery B ack-up

Switchover Voltage (VSO). At this time the clock

registers will be maintained by the attached bat-

tery supply. On power-up, when VCC returns to a

nominal value, write protection continues for trec

(see Figure 16., page 22 , Table 11., page 22).

For a further, more detailed review of lifetime cal-

culations, please see Appl ication Note AN1012.

Figure 10. WRI TE Mode Sequenc e

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

11/27

M41T81

C LOCK OP ERATION

The 20-byte Regi ster Map (see Table 2., page 12)

is used to bot h set the clock and to re ad the date

and time from the clock, in a bi nary coded decimal

format. Tenths /H undredths of S econds, Second s,

Minutes, and Hours are contained within the first

four registers.

Note: The Tent hs /Hun dredths of S eco nds c annot

be written to any value other than “00.”

Bits D6 and D7 of Clock Register 03h (Century/

Hours Register) contain the CENTURY ENABLE

Bit (CEB) and the CENTURY Bit (CB). Setting

CEB to a '1' will cause CB to toggle, either from '0'

to '1' or fr om '1' to '0' at the turn of the century (de-

pending upon its initial state). If CEB is set to a '0,'

CB will not toggle. B its D0 through D2 of Register

04h contain the Day (day of week). Registers 05h,

06h, and 07h contain the Date (day of month),

Month and Years. The ninth clock register is the

Control Register (this is described in the Clock

Calibration section). Bit D7 of Register 01h con-

ta ins the STOP Bi t ( ST). Setting thi s b i t to a ' 1 ' wil l

cause the oscillator to stop. If the device i s expect-

ed to spend a significant amount of time on the

shelf, the oscillator may be stopped to reduc e cur-

rent drain. When reset t o a '0' the oscillator restarts

within one second.

The eight Clock Registers may be read one byte at

a time, or in a sequent ial block. Provision has been

made to assure that a clock update does not occur

while any of the eight clock addresses are being

read. If a clock address is being read, an update of

the clock registers will be halted. T his will prevent

a transition of data duri ng the RE AD.

Power-down Ti me-Stamp

When a power fa ilure occurs, the HT B it will auto-

matica lly be set t o a '1 .' Th i s will p reve n t the clo ck

from updating the TIMEKEEPER® registers, and

will allow the user to read the exact time of the

power-down event . Resetting the HT Bit t o a '0' will

allow the clock to update the TIMEKEEPER re g is-

ters with the current time. For more information,

see Applicat ion Note AN1572.

TIMEKEEPER® Registers

The M41T81 offers 20 internal registers which

contain Clock, Alarm, Watchdog, Flag, Square

Wave and Control data. These register s are mem-

ory l ocations which contai n external (user accessi-

ble) and internal copies of the data (usually

referred to as BiPORT™ TIMEKEEPER cel ls) . The

external copies are independent of internal func-

tions except that they are updated p eriodically by

the simultaneous tr ansfer of the incremented inter-

nal copy. The internal divider (or clock) ch ain will

be reset upon the completion of a WRITE to any

clock addr ess.

The system-to-user transfer of clock data will be

halted whenever the address bei ng read is a clock

address (00h to 07h). The update will resume ei-

ther due to a Stop Condition or when the pointer

increments to any non-clock address (08h-13h).

TIMEKEEPER and Alarm Registers store data in

BCD. Control, Watchdog and Square Wave Reg-

isters store data in Binary Format.

M41T81

12/27

Table 2. T IME KE EPER® Re gister Map

Keys: S = Sig n Bit

FT = Frequency Test Bit

ST = Stop Bit

0 = Must be set to '0'

BMB0-BMB4 = Watchdog Multiplier Bits

CE B = C entury Enable Bit

CB = Centur y Bi t

OUT = Output level

ABE = Alarm in Bat te ry Back-u p Mode Enable Bit

AFE = Alarm Flag Enable Fla g

RB 0-RB1 = Wa tc hdog Res ol ution Bit s

RP T 1-RPT5 = A l arm Repeat M ode B i ts

WDF = Watchdog F l ag (Read only)

AF = A l arm F l ag (Read o nl y)

SQWE = Square Wave Enable

RS 0-RS3 = SQW F requency

HT = Halt Updat e B i t

Addr Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

00h 0.1 Seconds 0.01 Seconds Seconds 00-99

01h ST 10 Seconds Seconds Seconds 00-59

02h 0 10 Minutes Minutes Minutes 00-59

03h CEB CB 10 Hours Hours (24 Hour Format) Century/

Hours 0-1/00-23

04h 0 0 0 0 0 Day of Week Day 01-7

05h 0 0 10 Date Date: Day of Month Date 01-31

06h 0 0 0 10M Month Month 01-12

07h 10 Years Year Year 00-99

08h OUT FT S Calibration Control

09h 0 BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

0Ah AFE SQWE ABE Al 10M Alarm Month Al Month 01-12

0Bh RPT4 RPT5 AI 10 Date Alarm Date Al Date 01-31

0Ch RPT3 HT AI 10 Hour Alarm Hour Al Hour 00-23

0Dh RPT2 Alarm 10 Minutes Alarm Minutes Al Min 00-59

0Eh RPT1 Alarm 10 Seconds Alarm Seconds Al Sec 00-59

0FhWDFAF000000 Flags

10h00000000Reserved

11h00000000Reserved

12h00000000Reserved

13hRS3RS2RS1RS00000SQW

13/27

M41T81

Ca libr a ting t h e C lock

The M41T81 i s driven by a quartz controlled oscil-

lator with a nominal frequency of 32,768Hz. The

devices are t ested not exceed ±35 ppm (parts per

million) oscillator frequency error at 25oC, which

equates t o about + 1.9 to –1.1 m inutes per month

(see Figure 11., page 14). When the Calibration

circuit i s properly employed, accuracy improves to

better than ±2 ppm at 25°C.

The oscillation rate of crystals changes with tem-

perature. The M41T81 design employs periodic

counter correction. The calibration circuit adds or

subtracts counts from the o scillator di vider circuit

at the divide by 256 stage, as shown in Figure

12., page 14. The number of times pulses which

are blanked (subtracted, negative calibration) or

split (added, positive calibration) depends upon

the value loaded into the five Calibration B its f ound

in the Control Register. Adding counts speeds the

clock up, subtracting count s slows the clock down.

The Calibration Bits occupy the five lower order

bits (D4-D0) in the Control Register 08h. These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The firs t 62 minutes i n t he cycle may , once

per minute, h ave one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, o nly th e first 2

minutes in the 64 minute cycle will b e modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step in the calibration register (see Figure

12., page 14). Assuming t hat the oscillator is run-

ning at exactly 32,768Hz, each of the 31 incre-

ments in the Calibration byte would represent

+10.7 or –5.35 seconds per month which corre-

sponds to a total range of +5.5 or –2.75 minutes

per month.

Two methods are available for ascertaining how

much cal ibration a giv en M41T81 may requi re.

The first involves setting the clock, lett i ng it run for

a month and comparing it to a known accurate ref -

erence and r ecordi ng dev iation over a fi xed period

of time. Calibration values, including the number of

seconds lost or gained in a given period, can be

found in Application Note AN934, “TIMEKEEP-

ER® CALIBRATION.” This allows the designer to

give the end user the ability to calibrate the clock

as the environment r equires, even if the final prod-

uct is packaged in a non-user serviceable enclo-

sure. The designer could provide a simple utility

that accesses the Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT/OUT/SQW pin. The pin will toggle at

512Hz, when the Stop Bit (ST, D7 of 01h) is '0,' the

Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm

Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the

Square Wave Enable Bit (SQWE, D6 of 0Ah) i s '0'

and the Watchdog Register (09h = 0) is reset.

Any deviation from 512Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of

512.010124Hz would indicate a +20 ppm oscillator

frequency error, requiring a –10 (XX001010) to be

loaded into the Calibration Byte for correction.

Note that setting or changing the Calibration Byte

does not affect the Frequency Test output fre-

quency.

The IRQ/FT/OUT/ SQW pin is an open drain output

which requires a pull-up resistor to VCC fo r proper

operation. A 500-10k resistor is recommended in

order to c ontrol the rise time. The FT Bit is cleared

on power-down.

M41T81

14/27

Figure 11. Crys tal Accuracy Acro ss Tem p eratur e

Figu re 12 . Cl ock C al ib r at i on

AI07888

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

= –0.036 ppm/°C2 ± 0.006 ppm/°C2

∆F= K x (T – TO)2

TO = 25°C ± 5°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

15/27

M41T81

Setting Alarm Clock Registers

Address locations 0Ah-0E h cont ain the alarm se t-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second or repeat every year, month,

day, hour, minute, or second. It can also be pro-

grammed to go off whi le the M41T81 is in the bat-

tery back-up mode to serve as a system wake-up

call.

Bits RPT5-RPT1 put the alarm in the repeat mode

of operation. Table 3., page 16 shows the possible

configurations. Codes not listed in the table default

to the once per second mode to quickly alert the

user of an incorrect al arm setting.

When the clock information matches the alarm

clock settings based on the match criteria d efi ned

by RPT5-RPT1, the AF (Alarm Flag) is se t . If AFE

(Alarm Flag Enable) is also set (and SQWE is '0.'),

the alarm condition activates the IRQ/FT/OUT/

SQW pin.

Note: If the address pointer is allowed to incre-

ment to the Flag Registe r ad dress, an alarm con-

dition will not cause the Interrupt/Flag to occur until

the address pointer is moved to a different ad-

dress. It should also be noted that if the last ad-

dress written is the “Alarm Seconds,” the address

pointer will increment to t he Flag address, causing

this situation to oc cur.

The IRQ/FT/OUT/SQW output is cleared by a

READ to the Flags Register as shown in Figure

13. A subsequent READ of the Flags Register is

necessary to see that the value of the Alarm Flag

has been reset to '0.'

The IRQ/FT/OUT/SQW pin can also be activated

in the battery back-up mode. The IRQ/FT/OUT/

SQW will go low if an alarm occ urs and both A BE

(Alarm in Battery Back-up M ode Enable) and AFE

are set. Figure 14 illustrates the back-up mode

alarm timing.

Figure 13. Alarm Interrupt Reset Waveform

Figure 14. Back-up Mode Alarm Wave form

IRQ/FT/OUT/SQW

ACTIVE FLAG

0Fh0Eh 10h

HIGH-Z

AI04617

VCC

IRQ/FT/OUT/SQW

ABE and AFE Bits

AF Bit in Flags

HIGH-Z

VSO

trec

AI05663

M41T81

16/27

Table 3. Alarm Repeat Modes

Watchdog Timer

The watchdog timer can be used to det ect an out-

of-control microprocessor. The us er program s the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address 09h.

Bits BMB4-BMB0 store a binary mul tiplier and the

two lower order bits RB1-RB0 select the resolu-

tion, where 00 = 1/16 second, 01 = 1/4 second,

10 = 1 second, and 11 = 4 seconds. The amount

of time-out is then determined to be the multiplica-

tion of the five-b it m ultiplie r value with the resolu-

tion. (For example: writing 00001110 in the

Watchdog Register = 3*1, or 3 seconds). If the

processor does not reset t he timer within the spec-

ified period, the M41T81 sets the WDF (Watc hdog

Flag) and generates a watchdog interrupt .

The watc hdog timer can be reset by having the mi-

croprocessor perform a WRITE of the Watchdog

Should the watchdog timer time-out, a value of

00h needs to be written to the Watchdog Regi ster

in order to clear the IRQ/FT/OUT/SQW pin. This

will also disable the watchdog function until it is

again programm ed corr ectly. A READ of the Flags

The watchdog function is automatically disabled

upon power-up and the Watchdog Register is

cleared. If the watchdog function is set, the fre-

quency test function is activated, and the SQWE

Bit is '0,' the watchdog function prevails and the

frequency test function is denied.

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting

1 1 1 1 1 Once per Second

1 1 1 1 0 Once per Minute

1 1 1 0 0 Once per Hour

11000 Once per Day

1 0 0 0 0 Once per Month

00000 Once per Year

17/27

M41T81

Square Wave Out put

The M41T81 offers the user a programmable

square wave function which is output on the SQW

pin. RS3-RS0 bits located in 13h establish the

square wave output f requency. These frequencies

are listed in Table 4. Once the selection of the

SQW f requency has been completed, the IRQ /FT/

OUT/SQW pin can be turned on and of f under soft-

ware control with the Square Wave Enable Bit

(SQWE) located in Register 0Ah.

Table 4. Square Wave Outpu t Frequency

Square Wave Bits Square Wave

RS3 RS2 RS1 RS0 Frequency Units

0000None-

000132.768kHz

00108.192kHz

00114.096kHz

01002.048kHz

01011.024kHz

0110512Hz

0111256Hz

1000128Hz

100164Hz

101032Hz

101116Hz

11008Hz

11014Hz

11102Hz

11111Hz

M41T81

18/27

Century Bit

Bits D7 and D6 of Clock Register 03h contain the

CENTURY ENABLE Bi t (CEB) and the CENTURY

Bit ( CB). Setting CEB to a '1' will cause CB to tog-

gle, either from a '0' to '1' or from '1' to '0' at the turn

of the century (depending upon its initial state). If

CEB is set to a '0,' CB will not toggle.

Output Driver Pin

When the F T Bit, AFE Bit , SQ WE Bi t, and Wa tch-

dog Register are not set, the IRQ/FT/OUT/SQW

pin becomes an output driver that reflects the con-

tents of D7 of the Control Register. In other words ,

when D7 (OUT Bit) and D6 (FT Bit) of address lo-

cation 08h are a '0,' then the IRQ/FT/OUT/SQW

pin will be driven low .

Note: The I RQ/ FT/OUT/ SQW pin is an open drai n

which requires an external pull-up resistor.

Preferred I nit ia l Power-on Defau lt

Upon initial application of power to the device, the

following register bits are set to a '0' state: Watch-

dog Register; AFE; ABE; SQWE; and FT. The fol -

lowin g b i ts a r e set t o a '1' sta te : ST; OUT; and HT

(see Table 5., page 18).

Table 5. Preferred Default Values

Not e: 1. BMB0- BMB4 , RB0, RB1.

2. State of othe r control b it s u ndefined.

3. UC = Unchanged

Condition ST HT Out FT AFE SQWE ABE WATCHDOG

Initial Po wer-up(2) 1110000 0

Subsequent P ow er-up (with battery

back-up)(3) UC 1 UC 0 UC UC UC 0

19/27

M41T81

MAXI MUM RAT IN G

Stressing the device above the rating listed in the

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Oper ating sections of this specification i s

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics S URE P rogram and other rel-

evant quality documents.

Table 6. Absolute Maximum Ratings

Note: 1. For S O8 package, Lead-free (Pb- free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C

for greater than 30 seconds).

2. For SO8 package, standard (SnPb) lead finish: Reflow at peak temper ature of 240°C (tot al thermal budget not to exceed 180°C for

betw een 90 t o 150 sec o nds) .

CAUTION: Ne gative undersh oot s below –0.3 volt s are not allowed on any pin whil e i n the Battery Bac k-up Mod e

Sym Parameter Value Unit

TSTG Storage Temperature (VCC Off, Oscillator Off) SOIC –55 to 125 °C

VCC Supply Voltage –0.3 to 7 V

TSLD Lead Solder Temperature for 10 Seconds Lead-free lead finish(1) 260 °C

Standard (SnPb)

lead finish(2) 240 °C

VIO Input or Output Voltages –0.3 to Vcc+0.3 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

M41T81

20/27

DC AND AC PARAM ETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests pe rf ormed unde r t he Measure-

ment Condition s listed in the relevant ta bles. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 7. Operating and AC Measurem en t Conditions

Note: Output Hi -Z is defi ned as the poi nt where data is no l onger dri ven.

Figu re 15. AC Measure m e nt I/ O Wav eform

Table 8. Capacitance

Note: 1. Effective c apacitance measured wi t h power suppl y at 5V ; sample d only, not 100% tested.

2. At 25° C, f = 1MHz.

3. Outputs deselected .

Parameter M41T81

Supply Voltage (VCC)2.0 to 5.5V

Ambient Operating Temperature (TA)–40 to 85°C

Load Capacitance (CL)100pF

Input Rise and Fall Times ≤ 50ns

Input Pulse Voltages 0.2VCC to 0.8 VCC

Input and Output Timing Ref. Voltages 0.3VCC to 0.7 VCC

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 7 pF

COUT(3) Output Capacitance 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 50 ns

21/27

M41T81

Table 9. DC Characteristics

Note: 1. Vali d for Ambient Operating Temperature : TA = –40 t o 85°C; VCC = 2.0 to 5. 5V (e x cept wh ere not e d).

2. STMic roelectronics recommends t he RAYO VAC B R1225 or B R1632 (or equivalent) as the batt ery sup pl y.

3. After switc hover (VSO), VBAT (min) can be 2.0V for crystal with RS = 40KΩ.

4. For re chargeable back-up, VBAT (max) m ay be cons i dered VCC.

5. For IRQ/FT/OUT/S QW pi n (Open Drain )

Table 10. Crystal Electrical Characteristics

Note: 1. Externally supplied. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-

26S: 1TJS12 5F H2A21 2, (SMD ) quartz crys tal for indust rial t em peratu re operations. KDS c an be contac te d at ko uhou@kd sj . co.jp

or http :/ /ww w.kdsj.c o. j p for further infor m at ion on this cr ystal type .

2. Load capacitors are i ntegrat ed withi n t he M41T81. Circ ui t board layout considerations for the 3 2. 768kHz crysta l o f mi ni m um trace

leng ths and iso l ation from RF generating signals should be ta ken into ac count.

Sym Parameter Test Condition(1) Min Typ Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current Switch Freq = 400kHz 400 µA

ICC2 Supply Current (standby) SCL,SDA = VCC – 0.3V 100 µA

VIL Input Low Voltage –0.3 0.3VCC V

VIH Input High Voltage 0.7VCC VCC + 0.3 V

VOL Output Low Vo ltage IOL = 3.0mA 0.4 V

Output Low Voltage (Open Drain)(5) IOL = 10mA 0.4 V

Pull-up Supply Voltage (Open Drain) IRQ/OUT/FT/SQW 5.5 V

VBAT(2) Battery Supply Voltage 2.5(3) 33.5(4) V

IBAT Battery Supply Current TA = 25°C, VCC = 0V

Oscillator ON, VBAT = 3V 0.6 1 µA

Sym Parameter(1,2) Min Typ Max Units

fOResonant Frequency 32.768 kHz

RSSeries Resistance 60 kΩ

CLLoad Capacitance 12.5 pF

M41T81

22/27

Figure 16. Power Down /U p Mode AC Waveform s

Table 11. Power Down/U p AC Characteri stics

Note: 1. VCC fall time should not exceed 5mV/µ s.

2. Vali d for Ambient Operating Tem perat ure: TA = –40 to 85 °C; VCC = 2.0 t o 5.5V (e xcept wh ere not ed).

Table 12. Power Down/U p Trip Points DC Characteristic s

Note: 1. All voltages referenced to VSS.

2. Vali d for Ambient Operating Tem perat ure: TA = –40 to 85 °C; VCC = 2.0 t o 5.5V (e xcept wh ere not ed).

Symbol Parameter(1,2) Min Typ Max Unit

tPD SCL and SD A at VIH before Power Down 0nS

trec SCL and SDA at VIH after Power Up 10 µS

Sym Parameter(1,2) Min Typ Max Unit

VSO Battery Back-up Switchover Voltage VBAT – 0.80 VBAT – 0.50 VBAT – 0.30 V

AI00596

VCC

trec

tPD

VSO

SDA

SCL DON'T CARE

23/27

M41T81

Figure 17. Bus Timing Requirements Sequence

Table 13. AC Characteristics

Note: 1. Vali d for Ambient Operating Temperature : TA = –40 t o 85°C; VCC = 2.0 to 5. 5V (e x cept wh ere not e d).

2. Tran smi tter must i nternally provide a hol d time to bri dge the undefined region (300ns m ax) of the fall i ng edge of SCL.

Sym Parameter(1) Min Typ Max Units

fSCL SCL Clock Frequency 0 400 kHz

tLOW Clock Low Period 1.3 µs

tHIGH Clock High Period 600 ns

tRSDA and SCL Rise Time 300 ns

tFSDA and SCL Fall Time 300 ns

tHD:STA START Condition Hold Time

(after this period the first clock pulse is generated) 600 ns

tSU:STA START Condition Setup Time

(only relevant for a repeated start condition) 600 ns

tSU:DAT(2) Data Setup Time 100 ns

tHD:DAT Data Hold Time 0 µs

tSU:STO STOP Condition Setup Time 600 ns

tBUF Time the bus must be free before a new

transmission can start 1.3 µs

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

M41T81

24/27

P ACKAGE MECHANICAL INFO RMATION

Figure 18. SO8 – 8-lead Plastic Small Packag e Outl i ne

No te : D rawing is not to scal e.

Table 14. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package M echan ical Data

Symb mm inches

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e1.27– –0.050– –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

ddd 0.10 0.004

SO-A

ddd

LA1 α

h x 45˚

25/27

M41T81

PART NUMBERING

Table 15. Ordering Information Scheme

For other options, or for more information on any aspec t of thi s device, pl ease cont act the ST Sales Office

nearest you.

Example: M41T 81 M 6 E

Device Type

M41T

Supply Voltage and Write Protect Voltage

81 = VCC = 2.0 to 5.5V

Package

M = SO8

Temperature Range

6 = –40°C to 85°C

Shipping Method

For SO8:

blank = Tubes (Not for New Design - Use E)

E = Lead-free P a ckage , Tubes

F = Lead-free P a ckage , Tape & Reel

TR = Tape & Reel (Not for New Design - Use F)

M41T81

26/27

REVISION HISTORY

Table 16. Document Revi sion History

M41T81, 41T81, T8 1Serial, Seria l, Serial, Serial , Serial , Serial, Serial, Serial, Seria l, Seria l, Serial, Serial , Serial, Serial, Serial, Serial, Seria l, Serial, Serial , Serial, Serial, Serial, Serial, Serial, Serial, Serial , Serial,

Serial, Serial, Serial, Se rial, Seria l, Serial, Serial, Serial, Seria l, Seri al, Serial , Serial, Se rial, S erial, Serial, Serial, Serial, Seria l, Access, Access, Access, Access, Access, Access, Access, Access, A ccess, Access,

Access, Access, Acces s, Access , Access, A ccess, Access , Access, A ccess, Access , Access, A ccess, Access , Access , Access, A ccess, Acce ss, Access, Access, Ac cess, Access, A ccess, Ac cess, Access, Ac-

cess, Access, Access, Access, Access, Access, Access, Access, Acce ss, Access, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Access,

Access, Acces s, Acce ss, Access, Acce ss, Access, Acce ss, Access, Acce ss, Access, Acce ss, Access, Acce ss, Access, Acce ss, Access, Interface, Inte rface, Interface, Interfa ce, In terfac e, Inte rfa ce, Interface,

Inte rface, Int erface, In terf ace, I nterface, Int erface, In ter face, Interfa ce, In terface, I nterface, Int erface, In terf ace, I nterface, Int erface, In ter face, Interfa ce, In terface, In te rface, Interfa ce, In terf ace, I nterface, Interfa ce,

Interfa ce, Interface, Interface, Interfa ce, Interface, Interface, Interface, Inte rface, Interface, Interface, Interfac e, Interface, In terface, Interface, Interface, Interface, Interface, Interface, Interface , Interface, Clock,

Clock , Clock, Clock, Clock, Clock, Clock , Clock, Clock, Clock, Clock, Clo ck, Clock, Cloc k, Clock, Clock, Clock, Clock , Clock, Clock, Clo ck, Clock, Clock, Clock, Cloc k, Clock, Clock, Clock, Clock , Clock, Clock,

Clock , Clock, Clock, Clock, Clo ck, Clock, Clock, Cloc k, Clock, Cloc k, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, RTC, RTC, RT C, RTC, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RTC, RTC,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RTC, RT C, RTC, RTC, RTC,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Programmable, Programmable, Prog r ammable, P rogram m able, Pr o gr ammabl e, Progr ammabl e, Program ma-

bl e, Progra mmable, Prog r am m able, Prog r am m able, P r ogramma ble, P r og r am ma ble, Programma ble, Progra mm a bl e, Progra mmable , Pr ogra mmable, Programmab le, Programmable, Programmable, Programma -

ble, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable,

Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable,

Pr ogra mma ble, Prog ram mabl e, Pr ogr ammabl e, Pr ogr amm able, Pro gramm abl e, Pr ogr ammab le , Pro gra mmabl e, Pr ogr am mable , Pr ogr ammabl e, P rog ramma ble, Prog ram mabl e Ala rm, P rogr amm able A lar m, Pro -

grammab le Alarm, Programm able Alarm , Programm able Alarm, P rogrammable Alarm, P rogrammable Alarm, Programma ble Alarm, Programm able Alarm, Programmable Al arm, Alarm, Alarm, Ala rm, Alarm,

Ala rm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Ala rm, Alarm , Alarm, Alarm, Alarm , Alarm, Alarm, Alarm, Alarm, Alarm , Ala rm, Al arm , Alarm, Al arm, Alarm, A larm, Alarm , A larm, Alarm, Ala rm, A larm,

Alarm, A larm , Alarm, Alarm, Alarm, Alarm , Alarm, Alarm, A la rm, Interrupt, Interrupt, Interrupt, Interrupt, Interru pt, Interrupt, Interrupt, In terrupt, Inte rru pt, Inte rrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,

Interrupt, Interrupt, Interru p t, Interru p t, Interrupt, Interrupt, Interrupt, In terrupt, Inte rru pt, Interrupt, Interrupt, Interru pt, Interrupt, Interrupt, Interru p t, Interrupt, Interrupt, Interrupt, In terrupt, Inte rrupt, Interrupt, In ter-

rupt, Interrupt, Interrupt, Interrupt, In terrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interru pt, Interrupt, Interrupt, Interrupt, Interrupt, Interru p t, Interrupt, In terrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interru pt,

rupt, Interrupt, Interrupt, Inte rrupt, Interrupt, Interrupt, Interrupt, In terrupt, Inte rrupt, Interrupt, In terrupt, Interrup t, Interrupt, Interrupt, Interrupt, Watchdog, Watc hdog, Watchdog, Wa tchdog, Watchdog, W atchdog,

Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,

Watchdog, Watchdog, Watch d og, Watchdog, Watchdog, Watchdog, Wa tchdog, Watchdog, Battery, Battery, Battery, Ba ttery, Battery , Battery, Ba ttery, Battery, Ba ttery, Battery, Ba ttery, B a ttery, Battery , Battery,

Battery, B attery, Battery, Battery, Battery, Battery, Battery, Battery , Ba ttery, Battery, Battery, Ba ttery, Battery, Battery, B attery, Battery, Battery, Battery , Battery, Batt ery, Batt ery, Battery, Batt ery, Batt ery, Battery,

Battery, Battery, Batt ery, Battery, Battery, Ba ttery, Batte ry, Batte ry, Battery, Battery, Batt ery, Battery, Battery, Ba tte ry, Battery, Battery, Battery , Battery, Bat tery, Battery, Ba tter y, Switchover, Switchover, Switcho-

ver, Switchover , Switchover, Switchover, Switchover, Swit chover, Switchover, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backu p, Backup, Backup, Backup, Backup, Backup, Backup, Backup,

Backup, Backup, Bac kup, Backup, Backup, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write

Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, W rite Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Industrial,

Industria l, In dustrial , In dustrial , In dustrial, Industri al, Industrial, Industrial, Industria l, I ndustrial , Indu strial , vIndustria l, Industrial, Indust rial, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC,

SOIC, SOIC, SOIC, S OIC

Date Revision Revision Details

December 2001 1.0 First Issue

21-Jan-02 1.1 Fix table footnotes (Table 9, 10)

01-May-02 1.2 Modify reflow time and temperature footnote (Table 6)

05-Jun-02 1.3 Modify Data Retention text, Trip Points (Table 12)

10-Jun-02 1.4 Corrected Supply Voltage values (Table 6, 7)

03-Jul-02 1.5 Modify DC Characteristics, Crystal Electrical table footnotes, Preferred Default Values

(Table 9, 10, 5)

11-Oct-02 1.6 Add marketing status (Figure 3; Table 15); adjust footnotes (Figure 3; Table 9)

21-Jan-03 1.7 Add embedded crystal package option (Figure 2, 4, 23; Table 16); modified pre-

existing mechanical drawing (Figure 18; Table 14).

05-Mar-03 1.8 Correct dimensions (Figure 23; Table 16); remove SNAPHAT® package option

12-Sep-03 2.0 Updated disclaimer, v2.2 template; add SOX18 package (Figure 3, 5, 22; Table 15)

27-Apr-04 3.0 Reformatted; update characteristics (Figure 5, 4, 4, 11, 14, ; Table 1, 6, 9, 12, 15)

17-Jun-04 4.0 Ref ormatted; add Lead-free information; add dual footprint connections (Figure 6;Table

6, 15)

7-Sep-04 5.0 Update f ootprint and Maximum Ratings (Figure 6; Table 6)

13-Sep-04 6.0 Update max ratings (Table 6)

03-Jun-05 7 Remove SOX18 and SOX28 references (Figure 1, 2; Table 1, 6, 10, 15)

27/27

M41T81

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