PCI ExpressTM Clock Generator 841S01 DATA SHEET General Description Features The 841S01 is a PLL-based clock generator specifically designed for PCI_ExpressTM Clock Generation applications. This device generates a 100MHz HCSL clock. The device offers a HCSL (Host Clock Signal Level) clock output from a clock input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating. * * * * * * * * * * The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -0.5%. Block Diagram One 0.7V current mode differential HCSL output pair Crystal oscillator interface: 25MHz Output frequency: 100MHz RMS period jitter: 3ps (maximum) Cycle-to-cycle jitter: 35ps (maximum) I2C support with readback capabilities up to 400kHz Spread Spectrum for electromagnetic interference (EMI) reduction 3.3V operating supply mode 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment 25MHz XTAL_IN OSC PLL Divider Network VSS VDD SRCT0 SRCC0 VDD VSS IREF VSS SRCT0 SRCC0 XTAL_OUT SDATA Pullup SCLK Pullup I2C Logic 16 15 14 13 12 11 10 9 VDD SDATA SCLK XTAL_OUT XTAL_IN VDD VSS VDDA 841S01 16-Lead TSSOP 5mm x 4.4mm x 0.925mm package body G Package Top View IREF 841S01 Rev B 11/16/15 1 2 3 4 5 6 7 8 1 (c)2015 Integrated Device Technology, Inc. 841S01 DATA SHEET Table 1. Pin Descriptions Number Name 1, 6, 8, 10 VSS Power Type Ground for core and SRC outputs. Description 2, 5, 11, 16 VDD Power Power supply for core and SRC outputs. 3, 4 SRCT0, SRCC0 Output Differential output pair. HCSL interface levels. 7 IREF Input An external fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode SRCCx, SRCTx clock outputs. 9 VDDA Power Analog supply pin. 12, 13 XTAL_IN, XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 14 SCLK Input Pullup I2C SMBus compatible SCLK. This pin has an internal pullup resistor, but is in high-impedance in power-down mode. LVCMOS/LVTTL interface levels. 15 SDATA I/O Pullup I2C SMBus compatible SDATA. This pin has an internal pullup resistor, but is in high-impedance in power-down mode. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k Rev B 11/16/15 Test Conditions 2 Minimum Typical Maximum Units PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3A.Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation. 6:5 Chip select address, set to "00" to access device. 4:0 Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be "00000". Table 3B. Block Read and Block Write Protocol Bit 1 2:8 Description = Block Write Start Slave address - 7 bits Bit Description = Block Read 1 Start 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count - 8 bits 20 Repeat start 20:27 28 29:36 37 38:45 46 Acknowledge from slave 21:27 Slave address - 7 bits Data byte 1 - 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop 30:37 Byte Count from slave - 8 bits 38 Acknowledge 39:46 Data Byte 1 from slave - 8 bits 47 Acknowledge 48:55 Data Byte 2 from slave - 8 bits 56 Acknowledge Data Bytes from Slave/Acknowledge Data Byte N from slave - 8 bits Not Acknowledge Rev B 11/16/15 3 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Table 3C. Byte Read and Byte Write Protocol Bit Description = Byte Write 1 Start 2:8 Bit Description = Byte Read 1 Slave address - 7 bits Start 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits 11:18 Command Code - 8 bits Acknowledge from slave 19 Acknowledge from slave Data Byte- 8 bits 20 Repeat start 19 20:27 28 Acknowledge from slave 29 Stop 21:27 Slave address - 7 bits 28 Read 29 Acknowledge from slave 30:37 Data from slave - 8 bits 38 Not Acknowledge 39 Stop Control Registers Table 4A. Byte 0: Control Register 0 Bit @Pup Name 7 0 Reserved Reserved 6 1 Reserved Reserved 5 1 Reserved 4 1 3 1 2 1 Table 4C. Byte 2: Control Register 2 Bit @Pup Name 7 1 SRCT/C Spread Spectrum Selection 0 = -0.35%, 1 = - 0.5% Reserved 6 1 Reserved Reserved Reserved Reserved 5 1 Reserved Reserved Reserved Reserved 4 0 Reserved Reserved SRC[T/C]0 Output Enable 0 = Disable (Hi-Z) 1 = Enable 3 1 Reserved Reserved 2 0 SRC 1 1 Reserved Reserved 0 0 Reserved Reserved SRC[T/C]0 Description 1 0 Reserved Reserved 0 0 Reserved Reserved Description SRC Spread Spectrum Enable 0 = Spread Off, 1 = Spread On NOTE: Pup denotes Power-up. Table 4B. Byte 1: Control Register 1 Table 4D. Byte 3:Control Register 3 Bit @Pup Name Description 7 0 Reserved Reserved Bit @Pup Name Description 1 Reserved Reserved 6 0 Reserved Reserved 7 5 0 Reserved Reserved 6 0 Reserved Reserved 4 0 Reserved Reserved 5 1 Reserved Reserved 3 0 Reserved Reserved 4 0 Reserved Reserved 1 Reserved Reserved 2 0 Reserved Reserved 3 1 0 Reserved Reserved 2 1 Reserved Reserved 0 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved NOTE: Pup denotes Power-up. Rev B 11/16/15 4 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Table 4E. Byte 4: Control Register 4 Table 4G. Byte 6: Control Register 6 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 1 Reserved Reserved Table 4F. Byte 5: Control Register 5 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 Rev B 11/16/15 0 Reserved Bit @Pup Name Description 7 0 TEST_SEL REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N TEST Clock Mode Entry Control 0 = Normal Operation, 1 = REF/N or Hi-Z Mode 6 0 TEST_MODE 5 0 Reserved Reserved 4 1 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Table 4H. Byte 7: Control Register 7 Reserved 5 Bit @Pup Name Description 7 0 Revision Code Bit 3 6 0 Revision Code Bit 2 5 0 Revision Code Bit 1 4 0 Revision Code Bit 0 3 0 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 1 Vendor ID Bit 0 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 86.9C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 5A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C Symbol Parameter VDD Core Supply Voltage VDDA Analog Supply Voltage IDD IDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VDD - 0.22 3.3 VDD V Power Supply Current 80 mA Analog Supply Current 22 mA Table 5B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current SDATA, SCLK VDD = VIN = 3.465V IIL Input Low Current SDATA, SCLK VDD = 3.465V, VIN = 0V Rev B 11/16/15 Test Conditions Minimum Typical Maximum 2.2 6 -150 Units V 1.0 V 10 A A PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET AC Electrical Characteristics Table 6. AC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C Symbol Parameter fref Frequency SCLK SCLK Frequency Frequency Tolerance; NOTE 1 Test Conditions Minimum XTAL 50 ppm External Reference 0 ppm 47 53 % 9.9970 10.0533 ns 35 ps Average Period; NOTE 4 tjit(cc) SRCT/C Cycle-to-Cycle Jitter; NOTE 2, 3 tjit(per) Period Jitter, RMS; NOTE 2, 3, 5 tR / tF SRCT/SRCC Rise/Fall Time; NOTE 6 tRFM Rise/Fall Time Matching; NOTE 7 tDC XTAL_IN Duty Cycle; NOTE 8 2.42 3 ps 700 ps 20 % 47.5 52.5 % 145 ps 875 mV 150 tR / tF Rise/Fall Time Variation VHIGH Voltage High 520 VLOW Voltage Low -150 VOX Output Crossover Voltage Minimum Undershoot Voltage VRB Ring Back Voltage MHz kHz tPERIOD Maximum Overshoot Voltage Units 400 SRCT/SRCC Output Duty Cycle; NOTE 2, 3 VOVS Maximum 25 odc VUDS Typical @ 0.7V Swing 250 mV 550 VHIGH + 0.3 -0.3 mV V V 0.2 V NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: With recommended crystal. NOTE 2: Measured at crossing point VOX. NOTE 3: Measured using a 50 to GND termination. NOTE 4: Measured at crossing point VOX at 100MHz. NOTE 5: If using the RMS period jitter to calculate peak-to-peak jitter, then use the typical RMS period jitter specification times the RMS multiplier. For example, for a bit error rate of 10E-12, the peak-to-peak jitter would be 2.42ps x 14 = 33.88ps. NOTE 6: Measured from VOL = 0.175V to VOH = 0.525V. NOTE 7: Determined as a fraction of 2*(tR - tF) / (tR + tF). NOTE 8: The device will operate reliably with input duty cycles up to 30/70% but the REF clock duty cycle will not be within specification. Rev B 11/16/15 7 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Parameter Measurement Information 3.3V5% 3.3V5% HIGH VDD VREF VDDA LOW 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements Reference Point (Trigger Edge) Histogram Mean Period (First edge after trigger) 3.3V HCSL Output Load AC Test Circuit RMS Period Jitter SRCC0 SRCC0 SRCT0 SRCT0 tcycle n tcycle n+1 tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period SRCC0 SRCT0 HCSL Output Rise/Fall Time Rev B 11/16/15 8 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Applications Information Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Table 7. Recommended Crystal Specifications Symbol Parameter Value Crystal Cut Fundamental at Cut Resonance Parallel Resonance CL Load Capacitance 18pF CO Shunt Capacitance 5pF - 7pF ESR Equivalent Series Resistance 20 - 50 Output Driver Current The 841S01 outputs are HCSL current drive with the current being set with a resistor from IREF to ground. For a 50 pc board trace, the drive current would typically be set with a RREF of 475 which products an IREF of 2.32mA. The IREF is multiplied by a current mirror to an output drive of 6*2.32mA or 13.92mA. See Figure 1 for current mirror and output drive details. IREF RREF RL RL Figure 1. HCSL Current Mirror and Output Drive PCI EXPRESSTM CLOCK GENERATOR 9 Rev B 11/16/15 841S01 DATA SHEET Recommended Termination Figure 2A is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI ExpressTMand HCSL output types. 0.5" Max Rs All traces should be 50 impedance single-ended or 100 differential. 1-14" 0-0.2" 22 to 33 +/-5% L1 L2 L4 L1 L2 L4 0.5 - 3.5" L5 L5 PCI Expres s PCI Expres s Connector Driver 0-0.2" L3 L3 PCI Expres s Add-in Card 49.9 +/- 5% Rt Figure 2A. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 2B is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will 0.5" Max Rs 0 to 33 L1 be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0 to 33. All traces should be 50 impedance single-ended or 100 differential. 0-18" 0-0.2" L2 L3 L2 L3 0 to 33 L1 PCI Expres s Driver 49.9 +/- 5% Rt Figure 2B. Recommended Termination (where a point-to-point connection can be used) Rev B 11/16/15 10 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Schematic Layout Figure 3 shows an example of 841S01 application schematic. In this example, the device is operated at VDD = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 18pF and C2 = 18pF is recommended for frequency accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment for optimize the frequency accuracy. For this device, the crystal load capacitors are required for proper operation. supply isolation is required. The 841S01 provides separate power supplies to isolate noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power R1 33 SRCT0 Zo = 50 R2 + 33 SRCC0 Zo = 50 - VDD VDD 8 7 6 5 4 3 2 1 IREF R4 50 Recommended for PCI Express Add-In Card U1 HCSL Termination VSS IREF VSS VDD SRCC0 SRCT0 VDD VSS R5 R3 50 475 VDDA VSS VDD XTAL_IN XTAL_OUT SCLK SDATA VDD Optional R9 Zo = 50 R10 + 0-33 SRCC0 9 10 11 12 13 14 15 16 VDD 0-33 SRCT0 Zo = 50 - VDDA R7 50 VDD R6 10 C3 10uF VDD C4 0.1u 25MHz C1 18pF X1 F p 8 1 VDD 3.3V R9 SP R10 SP Recommended for PCI Express Point-to-Point Connection BLM18BB221SN1 1 C2 18pF R8 50 HCSL Optional Termination Ferrite Bead C7 C3 0.1uF SCLK SDATA VDD (U1-2) 2 10uF (U1-5) C5 0.1uF (U1-11) C6 0.1uF VDD C6 0.1uF (U1-16) C7 0.1uF Figure 3. 841S01 Application Schematic Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, PCI EXPRESSTM CLOCK GENERATOR good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. 11 Rev B 11/16/15 841S01 DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the 841S01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 841S01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. The maximum current at 70C is as follows: IDD_MAX = 75mA IDDA_MAX = 20mA * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(75mA + 20mA) = 329.175mW * Power (outputs)MAX = 44.5mW/Loaded Output pair Total Power_MAX = 329.175mW + 44.5mW = 373.675mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.9C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.374W * 86.9C/W = 102.5C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 8. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Rev B 11/16/15 0 1 2.5 86.9C/W 82.5C/W 80.4C/W 12 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 4. VDD IOUT = 17mA VOUT RREF = 475 1% RL 50 IC Figure 4. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX - VOUT) * IOUT, since VOUT - IOUT * RL = (VDD_MAX - IOUT * RL) * IOUT = (3.465V - 17mA * 50) * 17mA Total Power Dissipation per output pair = 44.5mW PCI EXPRESSTM CLOCK GENERATOR 13 Rev B 11/16/15 841S01 DATA SHEET Reliability Information Table 9. JA vs. Air Flow Table for a 16 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 86.9C/W 82.5C/W 80.4C/W Transistor Count The transistor count for 841S01 is: 1874 Package Outline and Package Dimensions Package Outline - G Suffix for 16 Lead TSSOP Table 10. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 Rev B 11/16/15 14 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Ordering Information Table 11. Ordering Information Part/Order Number 841S01CGLF 841S01CGLFT Marking 841S01CL 841S01CL Package "Lead-Free" 16 Lead TSSOP "Lead-Free" 16 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature 0C to 70C 0C to 70C NOTE: Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. PCI EXPRESSTM CLOCK GENERATOR 15 Rev B 11/16/15 841S01 DATA SHEET Revision History Sheet Rev Table Page B T4A 4 Corrected Control Register Table. 8/31/12 T11 15 Ordering Information - removed leaded devices. Updated data sheet format. 11/16/15 B Rev B 11/16/15 Description of Change Date 16 PCI EXPRESSTM CLOCK GENERATOR Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. 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