8- 10-, 12-Bit Video Speed cy ANALOG DEVICES Current and Voltage Out, D/A Converters FEATURES Current Settling Times to 15ns +1.5V Compliance Voltage Settling Times to 100ns (MDH) Monotonicity Guaranteed Over Temperature High Output Currents 15mA -30C to +85C Operating Range Industry Standard Pin Outs 20V, p-p Out (MDH) TTL or ECL Logic APPLICATIONS CRT Vector Displays Digitial Waveform Generation Automatic Test Equipment TV Picture Reconstruction GENERAL DESCRIPTION This broad family of digital-to-analog cor-verters represents the state of the art in modular, high speed, voltage and current output devices. The family consists of a total of 11 devices in 4 series (MDS, MDSE, MDSL and MDH) that allow the user to make engineering trade-offs between resolution, speed, output and logic type. The first 3 are high compliance current output units which make possible linear output swings greater than +1.5V. The voltage output MDH series contain a fast settling hybrid operational amplifier which provides +10V output at +50mA. To simplify selection these major specifications are summarized in Table 1. FULL SCALE FULL SCALE INPUT MODEL BITS OUTPUT SETTLING TIME LOGIC (Fastest Sectliag High Current Out) MDS-08 15 8 15mA 15ns to 0.4% FS TTL MDS-1020 10 15mA 20ns to 0.1% FS TTL MDS-1240 12 15mA 40ms to 0.025% FS TTL (MDS with ECL Logic) MDS-O815E 8 15mA 1ns to 0.4% FS ECL MDS-1020E 10 1l5mA 20ns to 0.1% FS ECL (Low Current MDS) MDSL-0825 8 5mA 2Sins to 0.1% TTL MDSL-1035 10 5mA 25ns to 0.1% TTL MDSL-1250 = 12 SmA 50ns to 0.025% TTL (Voltage Out MDSL) MDH-0870 8 10V/50mA 150ns to 0.4% TTL MDH-1001 10 10V/SOmA 200ns to 0.1% TTL MDH-1202 12 10V/50mA 500ns to 0.025% TTL Table 7. SPEED WITH PRECISION Analog Devices model MDS-1240 is the first D/A converter available with highly reliable, internal hybrid construction to achieve ultra-high speed operation. In fact, it is the fastest 12- bit D/A available, settling to 0.025% in 40ns. Hybrid construc- tion eliminates the thermal lag problem inherent in 12-bit D/As constructed with discrete components. This in turn means that the accuracy is maintained over the total frequency range of operation, yielding superior results for frequency do- main applications. The MDS-1240 is particularly well suited for CRT display ap- plications because of its unsurpassed speed and drive capa- bilities. The high output current (15mA) allows the use of low impedance loads so that settling times remain short even with higher output voltage levels. The ability to drive load ca- pacitance is at least 3 times that of other 12-bit D/As thus providing capability to drive a terminated transmission line directly. The MDS-815 and MDS-1020 provide similar per- formance at 8 and 10 bits, while the MDS-E units provide it with ECL logic. MDSL-0825, MDSL-1035 and MDSL-1250 also utilize this reliable hybrid construction. The use of laser trimmed resistor networks within the D/As not only elimi- nates thermal time lag errors but provide the linearity temp- co of 2ppm/C; guaranteeing monotonic operation over the extended temperature range of -30C to +85C. The power dissipation of the MDSL series is one-half that of competi- tive D/As, but a full 5mA output current is maintained. This allows driving transmission lines or other low impedance loads directly. (continued on page 195S) D/A CONVERTERS 1918SSPECIFICATIONS (typical @ +25C unless otherwise specified) CURRENT OUTPUT CURRENT OUTPUT MDS MDS-E (ECL) MODEL UNITS 0815 1020 1240 0815 1020 RESOLUTION Bits 8 10 12 8 10 LSB (Weight) UA 58.6 14.6 3.66 58.6 14.6 ACCURACY Initial (Adjust to 0) t%FS 0.2 0.05 0.012 0.2 0.05 Linearity (Integral) LSB max | 1/2 * * * * Monotonicity Guaranteed Over Operating Temp Range * * Zero Offset (Adjust to 0) 15nA max * * * * TEMPERATURE COEFFICIENTS Linearity ppm/c | 5 * 2 * 2 Gain ppm/'c 430 * 20 * * Offset (Bipolar) ppm/c | 15 * * * * STABILITY WITH TIME %/yr max| 0.5 * * * * DATA INPUTS Logic Compatability TTL * * ECL ECL Logic Voltage Levels Bit On Logic 1 Vv +210+5.0 * * -0.9 -0.9 Bit Off Logic OQ Vv 0 to +0.4 * * -1.7 -1.7 Logic Current (Each Bit) Bit On Logic 1 LA <50 * * * * Bit Off Logic 0 mA -8 * ~5 max * * MSB mA N/A * -10 max * * Coding All Units Binary (BIN) for Unipolar, * * Offset Binary (OBN) for Bipolar * * OUTPUT Current Range Unipolar mA Oto +15 * * Oto -15 Oto -15 Bipolar mA 7.5 * * * * Impedance (See Figure 3) G. 165 * 200 1% * * Comphance (MDH Voy) Vv +1.5, -2 * * ~1,5, +2 ~1,5, +2 Load Resistance for Vout (See Figure 5) Oto +1V Ge 112 * 100 * * tIV Si. 4.32k * 750 * * INFERNAL REFERENCE VOLTAGE OUT Vv N/A * -6.2 +5% * * SETTLING TIME? Current ns to %, 15 to 0.4 20 to 0.10 20 to 0.1 * 20 to 0.10 40 to 0.025 Unipolar Voltage (Ry, = 3002 || 10pF) ns to % Bipolar Voltage (Ry, = 2325Q ll 10pF) ne to % POWER REQUIREMENTS Range Vv tlitot1l6 * +14,5 to +16.5| * * Current at Nominal +V mA max | 105 120 55 * 120 Current at Nominal -V mA max [15 * 20 * * POWER SUPPLY REJECTION RATIO %/V 0.04 * * * +15V %IV -0,0001 ~15V (Bipolar) %IV ~-0.002 ~1SV (Unipolar) %IV ~0.2 TEMPERATURE RANGE Operating C -20 to +75 * -30 to +85 * * Storage C -55 to +85 * -55 to +125 * * CASE Diallyl Phthalate per MIL-M-14 Type SDG-F | * * Specifications same as MDS-0815. NOTES: *Ippm/C for current output. Op amp is SOUV/C. (See tables in Figures 15, 16 and 17, for overall TC in various configurations.) ? For Full Scale Step. 7192S D/A CONVERTERS 30 to +5V Out 40 to +10V Out 545V Out See Figures 15 and 16 for test circuits. Specifications subject to change without notice.CURRENT OUTPUT VOLTAGE OUT MDSL MDH 0825 1035 1250 0870 1001 1202 8 10 12 8 10 12 19.6 4,88 1.22 Depends on Vout 0.2 0,05 0.012 0,2 0.05 0.012 * * * # * ak * * * ae * ak * * * 10mV 10mV 1O0mV 2 2 2 2 2 2 20 20 20 20 20 20 * * * See Note 1 * * * tk * * * * * ie * * * * * * * * * * * i * a8 * * * * * * -1.6 -1.6 -1.6 -1.6 ~1.6 -1.6 * * * * * * * * * * * * * * * ef * * Oto +5 Oto +5 Oto +5 +50 max +50 max 50 max $2.5 2.5 +2.5 50 max +50 max +50 max 600 +1% 600 41% 600 41% 0.1 max 0.1 max 0.1 max * * * 10 +10 +10 300 300 300 N/A N/A N/A 2.325k 2.325k 2.325k N/A N/A N/A -6.2 5% -6.2 5% ~6.2 +5% -6.2 5% ~6.2 45% -6.2 +5% 25 to 0.1 25 to 0.1 5010 0.25 | 1500.2 25 to 0.10 50 to 0.25 45 to 0.4 70 to 0.1 70 to 0.1 70 to 0,47 100 to 0,1 200 to 0.0253 70 to 0,1 8010 0.05 9010 0.025 | 150 t0 0.4 200 tu 0,14 400 to 0.0254 75 to 0.4 100 to 0.1 100 to 0.1 100 to 0.45 130 to 0.15 250 to 0.0255 100 to 0,1 110 to 0,05 125 to 0,025 +12 to 15 +412 to +15 12 to 15 414.5 to +16.5 +145 to t16.5 +14.5 to 416.5 26 26 26 50 50 50 16 16 16 35 35 35 0.0001 0,0001 0.0001 0.003 0.003 0.003 0.001 0.001 0,001 0.01 0.01 0.01 0.2 0.15 0.15 0.15 0,15 0.15 -30 to +85 -30 to +85 ~30 to +85 -30 to +85 -30 to +85 -30 to +85 ~S5S5to+125 -55to+125 -55to +125 | -55 to +125 -55 to +125 -55 to +125 * aK * * * * D/A CONVERTERS 193SMDS-0815, 0815E, 1020, 1020E OUTLINE DIMENSIONS Dimensions shown in inches and (mm). +-_ 2.3 (58.01 es + 0.43 {10.92) 2.3 (68.0) MDS-0815_- MDS:1020 MDS-0815E MDS-1020E T 0.04 (1.02) DIA | j Loos (6.4) ry . an 7 a 10} T 9 4 BE 4 bt fo 6 t. 5 va 4 4 3 LT 14 2 1 Ce BOTTOM VIEW | * Q.1 (2.54) GRID DOT ON TOP INDICATES POSITION OF PIN 4. MATING SOCKET MSB-1 1713 PIN DESIGNATIONS MDS-0815E, 1020E MDS-1240, MDSL-0825, 1035, 1250 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). i 2.0 (60.8) | 4 I; Tos (6.4) 0.25 64) 1LRe MDS.1240 MOSL-0825 MDSL-1250 MDSL-1035 0.02 (0.508) 2.0 {50.8) 16 t BOTTOM VIEW 0.1 (2.54) GRID DOT ON TOP INDICATES POSITION OF PIN 1 MATING SOCKET MSA-1 MDH-0870, 1001, 1202 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). j- L _ 0.25 4) 0.25 (6.45 4g i BOTTOM VIEW 2.0 (50.8) | feos (2.54) GRID DOT ON TOP INDICATES POSITION OF PIN 1. MATING SOCKET MSA-1 PIN DESIGNATIONS MDS-0815, MDS-1020 PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN. FUNCTION PIN FUNCTION 3 BIT 1 (INPUT (MSB) | 15 BIT 11 eur 1 BIT 1iMSB)| 9 BIT 9 : BIT 1{MSB) 9 BITS 4 BIT 2 INPUT 16 BIT 12 INPU 2 BIT 2 10 BIT 10 , BIT 2 10 BIT 10 5 BIT 3 INPUT 17 - REFERENCE INPUT . 6 BIT 4 INPUT 18 REFERENCE OUTPUT 3 BIT 3 11 +15V u BIT3 11 -15V 4 BIT 4 12 OFFSET BIT4 12 OFFSET 7 BIT 5 INPUT . ones OUTPUT 5 BIT 5 13 COMMON & BITS 13 COMMON 10 BIT 6 INPUT 6 BIT 6 14 OUTPUT i BIT6 14 OUTPUT 11 BIT 7 INPUT 30 GROUND 7 BIT7 15 COMMON 7 BIT7 5 COMMON 12 BIT 8 INPUT 31 -15V POWER INPUT 8 BIT 8 16 -15V gE BIT 8 16 +15V 13. BIT9 INPUT 32 +15V POWER INPUT 14 BIT 10 (INPUT +15V -15V MDSE Pp Ev Tisv MDS IN DESIGNATIONS MDH-0870, 1001, 1202 11 16 (MSB} 1 PIN FUNCTION PIN FUNCTION BIT 1 O i 3 BIT TINPUT (MSB) | 17 REFERENCE INPUT BIT2 oO - OUTPUT 4 BIT 2 INPUT 18 REFERENCE OUTPUT BIT3 & bm 5 BIT 3 INPUT 22 ANALOG OUTPUT mee To] Pessoee |. 2 7 -BITSINPUT 25 INPUT BIT5 O -| bLADDER ~O OFFSET - ONPUTS 4 pire oS} a) SwivcHes. Lt REFERENCE 19 BIT 6 INPUT 26 ~- FIXED GAIN ait? o | | SOURCE 11 BIT 7 INPUT 28 CURRENT OUTPUT - 8 13 12 BIT 8 INPUT 29 OFFSET BITS OT mT common 13 BIT9 INPUT 30 GROUND BITS OT bo] 1S 14 BIT 10 INPUT 31 -15V POWER INPUT BIT 10 P| -O COMMON 15 BIT 14 INPUT 32 +15V POWER INPUT (LSB) 16 BIT 12 INPUT MDS and MDSE Block Diagram {MSB) 3 Zo = 6002 = ly = SMAF.S. 28 _ CURRENT BIT? oF OUTPUT err $ aA 424 9 sn 6 30 BIT 4 ANALOG we 3 ---O GROUND ar aver + ___f2z_, ANALOG a N BIT +10V (MAX) ; BIT6 oe CURRENT HYBRID +50MA (MAX) 158 28. CURRENT DIGITAL ay out OP-AMP _ ' of OUTPUT INPUTS ) BIT? o> CONVERTER 28 oo -IN ! Z HYBRID are b ! 10 CURRENT __|29 BIT9 a oe DIGITAL 1 oy OUTPUT O OFFSET BIT 10 & 2k 26 4 FIXED INPUTS | o D/A -6.2V BIT 110 | io 12 CONVERTER iC | B VOLTAGE 22 BIT 120 1BpF i oO 14 EURO ) + 15V (Ls8) 7 a2 e2v 29 ~b. REF b. : L[ o- REF IN &~4 AW - OFFSET ' 18 at {0 to -6.2V = Zin = 4.64 SOURCE 237k i 6 b- -15V 0 TO5MA e120 sasy BIT 12 > OUTPUT) x LSB | 70 -15V 30 7~| 18 REF OUT o Io GND REF dace V7 | IN OUT MDS-1240 and MDSL Series Block Diagram 194S D/A CONVERTERS PIN DESIGNATIONS MDS-1240, MDSL-0825, 1035, 1250 MDH Series Block Diagram(continued from page 191S) Each D/A is housed in industry standard size cases, and each has an internal precision reference. Bipolar operation is achieved by external pin interconnection. In normal circumstances, no external components are required for operation into low im- pedance loads. Designed primarily for PCB mounting, these D/As may also be plugged into standard DIL sockets mounted " : un on 1.8 centers (MDS series 2. centers). For ultra-high reliability, this D/A series is optionally avail- able with burn-in extended beyond the Analog Devices standard of 96 hours at +25C. NOTES ON FAST-SETTLING D/A CONVERTERS Invariably, fast-settling D/A converters use current rather than voltage switching. There are inherent advantages to current-switching converters, since it eliminates an output amplifier. If there is no output amplifier, there is no slew rate limitation which slows settling. The absence of an output amplifier also rneans there are no overshoot and ringing problems often associated with feed- back amplifiers. The settling time of a current-switching D/A converter, then, is based on: 1. The RC time constant of the converter output. 2. The settling time of the output current change. If the settling time of the D/A converter under consideration is determined by the RC time constant, the output capacitance and output impedance become very important. As a typical example in the Analog Devices D/A converters, output capacitance is 5pF, and nominal output impedance is 16581. For test purposes, the output of these D/A converters are loaded with approximately 1502 . (There is no trick or gimmick in loading the output of the converter; it is done to provide an output voltage of approximately 1.0V to 1.2V.) This loading means RC = 80 X 5 X 107'* = 0.4ns. Since set- tling time is approximately 7 RC, the overall settling time, if determined by the RC time constant, would be 2.8ns. Based on this, it becomes obvious the RC time constant of such converters outputs is not the limiting factor in establishing set- tling time. Instead, the settling time of the converters is based primarily on the settling time of the overall (output) current change, since the effect of the RC time constant is swamped. Expressed in another way, this means settling time for the MDS series converters is relatively independent of load resis- tance, unless substantial load capacitance is present. The set- tling time of the output current, in turn, is based on: ? 1. The settling time of each switch witain the converter. 2. The time skew among the digital inputs which cause the switching action. Some manufacturers of fast-settling D/A converters spec set- thing time under the conditions of all digital inputs changing from 0 to 1, or vice versa. At first glance, it would appear this is the worst case condition for measuring settling time, since maximum current is being switched. Unfortunately, this method of specifying neglects an important characteristic of saturated logic ...the propagation delay for negative-going inputs is different from the delay for positive- going inputs on all forms of saturated logic. The TTL or DTL driving logic, and the D/A input circuits for current-switching D/As are subject to this same characteristic. Thus, the time skew of the individual current switches within the converter is worse when one or more input bits are out of phase with the others. This is true even for ideal inputs in which the digital inputs arrive simultaneously; if there is time skew among the bit inputs, of course, the problem becomes more pronounced. Note, settling times even better than those specified for the MDS series become possible if digital input bit arrivals are deskewed. These differences among the switches cause a discontinuity or glitch in the output. The true worst case glitch always occurs at the switching point of the Most Significant Bit or the center point of the output range, because nearly equal and opposite currents are being switched within the converter. In addition, all 0 to all 1 switching overlooks the prac- tical aspects involved. There are relatively few times when all of the input bits will be changing from one state to the other on successive input changes; however, the MSB will switch out of phase with all other bits each time the analog output of the converter crosses the midpoint. In considering the choice of a fast-settling D/A converter, then, the user should look for the following points in the data sheet: 1. If the settling time spec has all bits changing state identi- cally, it neglects the phenomenon associated with saturated logic discussed earlier. 2. Is the settling time specified with an impractically-low- impedance load? If the RC time constant of the converter output is the major factor in establishing settling time (because of high output Capacitance and/or resistance), a low impedance load helps make settling time look better. A low impedance load means the voltage being developed at the output is oftentimes too small to be useful. A higher-impedance load which can develop a useable output of 1.0V or more sometimes negates the fast settling time of the spec sheet. A test setup for this worst-case measurement is shown in Fig- ure 1. Two pulse generators are used to generate the required out-of-phase pulses, and the delays are adjusted for minimum skew. Figure 2 is an unretouched photo of the oscilloscope trance of an MDS-815 under test. 71 oO EXT. TRIG A TRACE MDS.0815 OSCILLOSCOPE TRIGGER B TRACE A RL APPROX PULSE GENS 15082 TEKTRONIX 454 A OR EQUIV PROBES. TEK P6054 HIGH SPEED TTL LOGIC GATES OR INVERTERS SUCH AS 74HO4 OR 74804 TYPE Figure 7. D/A CONVERTERS 195SANALOG OUTPUT BIPOLAR, NONINVERTING OFFSET BINARY +FS, -1LSB 11l....... 1 +1/2 FS 110........ 0 0 100........ 0 ~1/2 FS O10O........ 0 -FS O00........ 0 Table 2. og" TRACE 20MV/DIV oar TRACE 2v/DIV 50s DIV Figure 2. INTERNAL CURRENT DAC CHARACTERISTICS O GROUND CURRENT CONTROLLED BY INPUT DIGITAL CODE Figure 3. Current Equivalent Circuit eT Rorrset l 4) OFFSET Zo 0 OUTPUT | __}- GROUND | \ | | + | | L VOLTAGE CONTROLLED BY DIGITAL INPUT CODE Figure 4. Voltage Equivalent Circuit 2 T T T rs rote 1 1 1650QZ RL t ! b-~-- i VB Fa boon te - - +- CURVE 1 0 TO PEAK VOLTS UNIPOLAR OUTPUT CURVE 2 > ' PEAK TOPEAK VOLTS | | | BIPOLAR OUTPUT : 3 REF MOY > 78080 | | ' t ! ; + ' 16582 RL | os : be 1 | { | ULL lo BIPOLAR OUTPUT ANALOG OUTPUT UNIPOLAR, NONINVERTING STRAIGHT BINARY +FS, -1LSB 111l........ 1 +3/4 FS 110........ 0 +1/2 FS 100........ 0 +1/4 FS 010........ 0 0 000........ 0 . Input Coding 1p--+- 09 |}---}-- 0.8 --- 07} os }-}-- oS % ACCURACY G4 03 0.2 P BASIC CONNECTIONS TIME ns Figure 6. Accuracy vs. Time MDS and MDSE AND CALIBRATIONS MDS/MDSE-0815, 1020 (MSBY 4 12 BIT 1 2 o oFeset 2 BIT2 O 44 OUTPUT piGiTAL ' bia OV TO +1.5 MAX (MDS} OV TO -1.5V MAX (MDSE) CONVERTER INPUTS ! Ry = 25082 19 13 BIT9 O4 10 15 BIT 10 04 LSB COMMON Figure 7. Unipolar Output Current WITH INPUT CODE OF (mse) 12 OFFSET / 1000000000 ADJUST BIT1 oO ~ POTENTIOMETER FOR 2 ZERO VOLTS OUTPUT BIT2 oT OUTPUT A | D/A aad i CONVERTER 11AW MAX tg RL BIT O+ Bit 1304 (LSB) COMMON Figure 8. Bipolar Output Current MDS-1240, MDSL-0825, 1035, 1250 : 3 29 BIT1 O- ?-o cRouno s 28 OUTPUT Vo g P ov To +iv ES ' oy 300{2 MDSL., 10082 MDS-1240 ote. DIA 30 OUNPUTS ! 17 { CONVERTER 4 GROUND \ 12 | 3 1g REF OUT I = }. { i 10082 EXT O75 ops ex ait 12 o- 8 7 nef ADS LSB REE IN e -18V | +15V Pt} pi ft | 0 50 100 150 200 250 300 350 400k | ak Ry - 8 m Figure 5. VouT vs. Load Resistance MDS-0815, -1020 196S D/A CONVERTERS The 10082 POTENTIOMETER MAY BE OMITTED tf ABSOLUTE ACCURACY OF FULL SCALE IS NOT REQUIRED. IN THIS CASE PINS 17 AND 18 SHOULD BE SHORTFD AND THE FULL SCALE CURRENT WILE BE 5.1mA 5%. (MDS-1240, 1O.2mMA 5%} Figure 9. Unipolar Current Output(MDS-1240, MDSL-0825, 1035, 1250 continued) MSE 3 29 BIT1 O~ 1 o 4 ey A i 96 5 Sa! 50022 | oY Ao 5 ZERO OUTPUT oY } > +1V ES DIGITIAL 1 ott CONVERTER 3 2.32kQ (7502 MDS.1240) INPUTS oY 0 . ! 12 3 }--__- crouno 1 9 13 1g REF OUT 1 OD 14 R2 EXT 1 O557 1002 To FS errs 7 1k2 ADJ sit 12 0-8 LSB REF IN 31 32 -15V00 +15V CALIBRATION PROCEDURE WITH INPUT CODE 00000000000C ADJUST THE 5002 (R1) POTENTIOMETER FOR ~1.0000 VOLTS OUTPUT, WITH INPUT CODE 111111111111 ADJUST THE 10092 (R2)} POTENTIOMETER FOR +0.99976 VOLTS OUTPUT. Figure 10. Bipolar Current Output VOLTAGE OUTPUT MDS/MDSE-815, 1040 (MSB} 1 BIT 1 O4 BIT2 4 DIGITAL | ( INPUTS | BITS otf] BIT wo LSB) DIA CONVERTER 25 OFFSET 1 n. Ry [VOLTAGE OUTPUT Vo = Rip X 18mA output bo HOS-050 B OP AMP _0 15 Figure 11. Voltage Output MDS-1240, MDSE (all ) SEE NOTE -15V +15V le fo fe DIGTIAL INPUTS I 18 oH { Bit 12 LSB D/A CONVERTER NOTE: Ri 28 | VOLTAGE - _ OUTPUT - (Vout = Hosos0 = RT lo) 1002 OP AMP 30 -- GROUND 1g REF CUT R3 EXT 1002 FS 7 roma { ads REF IN FOR UNIPOLAR VOLTAGE OUTPUT CONNECT JUMPER BETWEEN PINS 29 AND 30. FOR BIPOLAR VOLTAGE OUTPUT CONNECT A 5002 POTENTIO- METER BETWEEN PINS 28 AND 29 AND ADJUST FOR ZERO OUTPUT WITH 100000000000 INPUT. Figure 12. Inverting Unipolar or Bipolar Voltage Output MDSL DIGITIAL SNPUTS NOTES: 1. CIRCUIT SHOWN FOR UNIPOLAR POSITIVE OUTPUT, OUTPUT SETTLING TIME iS APPROXI- MATELY 150ns. 2. FOR 0 TO +10V OUTPUT R2 = 3002, R1 = 9k2. 3. R3 1S ADJUSTED FOR DESIRED OUTPUT, RANGE |S APPROXIMATELY +5%. SEE NOTE -15V +15V ian od Boon g = @z an 6 R2$ 4 HOS-050 OP AMP VOLTAGE + OUTPU a Vout 2 RI R1 (IN kD) PY +37 VOLTS FS UNIPOLAR D/A 41} CONVERTER 30 i 10V (MAX) R4 AT 100mA t i | ! 1 oO 3002 > ! ! t \ i 1g REF OUT ! ! 7 REF IN ] Foor GROUND EXT FS ADJ 4, FOR BIPOLAR OUTPUT CONNECT 5002 POTENTIOMETER BETWEEN PINS 29 AND 28 AND UNGROUND PIN 29. R2 IS SET TO 2.32k.2, AND Vour (p-p) = 2 {R17 (IN kK) +1). 5,C11S APPROXIMATELY 10pF AND MAY BSE ADJUSTED FOR BEST TRANSIENT RESPONSE. Figure 13. Noninverting Unipolar or Bipolar Voltage Output APPLICATIONS -15V +15V OUTPUT VOLTAGE 31 [a2 SETTLING TIME = 20ns MSB 3 ze 13 21 Two MSB O 3 a } onan o- RI UP TO 2V ' oJ 5 [30 oS (ppl ; oJ : 20 o oy ! 1 74874 10 29 DIGITAL 1 O-7 ineut a] tee Toa0 INPUTS | O-4 REGISTER 3 Aig s15v 1 : 13 18 6 | oO a Lo -15v 1} o-4 R2 1 1 5 20062 +8V LSB 16 W 9 10 _ LSB of , [0 -5.2V A [ 1,5, 12, 16 STROBE O stacpe NOTES ON DEGLITCHED D/A: | 40ns MAX UPDATE RATE = 11MHz 1, CONSULT DGM DATA SHEET FOR MIN FOR 0.01% ACCURACY DEGLITCH CIRCUIT DETAILS. 2. R11S VARIED TO OBTAIN DESIRED OUTPUT LEVEL: FOR 0 TO +1V OUT- PUT, R1= 1002. Figure 14. Ultra High-Speed Deglitched D/A D/A CONVERTERS 1978MDH SERIES APPLICATIONS By using external feedback resistor and capacitor as shown in Figures 15 and 16, other full scale output ranges from 2V to 10V mav be obtained. * USE INVERTER OR -15V wor 5 10k MAY BE Wee SEE OMITTED NOTE 2 CURRENT 15V MSB 3 .28 OUTPUT Birt OF 2 3220, U oY] | 5 22 ANALOG OUTPUT ' 6 -_O Vo = UP TO 10V +50mA \ ; T OUTPUT CURRENT (SEE BELOW) \ 0 MOH aRc oy D/A 25 _-INPUT R eater ! 11] converter [285 Wr 1 OTR 17 REF IN 1 373] po 1 OT 5002 + FS ADJ | 15 18 errs REF OUTPUT ait 12 018] 30 LSE. Lo Gno 31 32 -18V.+15V NOTES: 1. VALUE OF C 1S APPROXIMATE. A FIXED CAPACITOR WITH TOLERANCE OF *1pF MAY BE USED IF 50% DEGRADATION OF SETTLING TIME iS PERMITTED. IF SETTLING TIME IS TO BE OPTIMIZED, AN ADJUSTABLE CAPACI TOR SHOULD BE USED FOR C AND ADJUSTED FOR MINIMUM SETTLING TIME. 2. OFFSET NULLING MAY BE ACCOMPLISHED BY CONNECTING A 10k POTENTIOMETER BETWEEN +15V AND -15V, AND CONNECTING ITS ADJUST- ABLE TAP TO A 10k RESISTOR. THE OTHER END OF THE RESISTOR IS CONNECTED TO PIN 28. TYPICAL UNCOMP=NSATED OFFSET 15 1% OF FULL SCALE. FF Q FOR 2S COMPL. 2002 B OIGITAL INPUTS OFFSET ADS : 7 29 OFFSET oe | oe 4 24 +INPUT PR o-__4 124 ot INPUT 1 o 8 28 _ CURRENT OUTPUT ey 6 [28_ CURRENT OUTPUT J Of I 7 22 _ ANALOG OUTPUT | 2 81 MDH [-o_9 0 Vo DIGITAL oe DIA 25 -INPUT RE OR INPUTS Pog tt converter 7 bh REF I | 12} [7 oo. a 3 o__3] | 14 8009 > FS ADJ t 15 18 Qo |. ait12 o- 16 30 REF OUTPUT ~ LSB =e 7 [> | -15V-+15V NOTES: 1. The 2005: POTENTIOMETER IS ADJUSTED FOR AN CUTPUT OF -FS WITH ALL ZEROES IN THE CHGITAL INPUT, 2. THE $002 POTENTIOMETER IS ADJUSTED FOR AN OUTPUT OF +FS-1LSB WITH ALL 3, FOR TWO'S COMPLEMENT (2SC) OPERATION, AN EXTERNAL INVERTER MUST BE USED TO COMPLEMENT BIT 1 (MSB). 4. AN ADJUSTABLE CAPACITOR MAY SE USED FOR C AND ADJUSTED TO OPTIMIZE SET- VOLTAGE SETTLING OFFSET R c OUTPUT TIME TEMPCO Oto +2V 70ns 100uv/C 2k 1 0p Oto +5V 100ns 250UV/C 8k 2pF 0 to +10V 200ns 500uV/C 18k 0.5pF ONE'S IN THE DIGITAL INPUT. TLING TIME. VOLTAGE SETTLING OFFSET OUTPUT TIME TEMPCO Ry Cc R +1V 70ns 100nV C 383 10pF 2k +2V 100ns 200nV/C 383 2pF 6k t5V 100ns 250nV/C 91k = pF Bk +10V 200ns S00uV/PC 91k = O.5pF 18k Figure 15. Binary Coding Unipolar Output Configuration 198S D/A CONVERTERS Figure 16. Offset Binary Coding or 2s Comp Coding Bipolar Output Configuration