PIC18F2423/2523/4423/4523 Flash Microcontroller Programming Specification 1.0 DEVICE OVERVIEW 2.1 This document includes the programming specifications for the following devices: * PIC18F2423 * PIC18F4423 * PIC18F2523 * PIC18F4523 2.0 Hardware Requirements In High-Voltage ICSP mode, PIC18F2423/2523/4423/ 4523 devices require two programmable power supplies: one for VDD and one for MCLR/VPP/RE3. Both supplies should have a minimum resolution of 0.25V. Refer to Section 6.0 "AC/DC Characteristics Timing Requirements for Program/Verify Test Mode" for additional hardware parameters. PROGRAMMING OVERVIEW PIC18F2423/2523/4423/4523 devices can be programmed using either the high-voltage In-Circuit Serial ProgrammingTM (ICSPTM) method or the low-voltage ICSP method. Both methods can be done with the device in the users' system. The low-voltage ICSP method is slightly different than the high-voltage method and these differences are noted where applicable. 2.1.1 LOW-VOLTAGE ICSP PROGRAMMING In Low-Voltage ICSP mode, PIC18F2423/2523/4423/ 4523 devices can be programmed using a VDD source in the operating range. The MCLR/VPP/RE3 pin does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. Refer to Section 6.0 "AC/DC Characteristics Timing Requirements for Program/Verify Test Mode" for additional hardware parameters. This programming specification applies to PIC18F2423/2523/4423/4523 devices in all package types. 2.2 Pin Diagrams The pin diagrams for the PIC18F2423/2523/4423/4523 family are shown in Figure 2-1 and Figure 2-2. TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2423/2523/4423/4523 During Programming Pin Name Pin Name Pin Type MCLR/VPP/RE3 VPP P Programming Enable VDD(2) VDD P Power Supply VSS(2) VSS P Ground RB5 PGM I Low-Voltage ICSPTM Input when LVP Configuration bit equals `1'(1) RB6 PGC I Serial Clock PGD I/O Serial Data RB7 Legend: Note 1: 2: Pin Description I = Input, O = Output, P = Power See Figure 5-1 for more information. All power supply (VDD) and ground (VSS) pins must be connected. (c) 2005 Microchip Technology Inc. DS39759A-page 1 PIC18F2423/2523/4423/4523 FIGURE 2-1: PIC18F2423/2523/4423/4523 FAMILY PIN DIAGRAMS 28-Pin SDIP, SOIC (300 MIL) PIC18F2423 PIC18F2523 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RA1 RA0 28-Pin QFN 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5/PGM RB4 RB3 RB2 RB1 RB0 VDD VSS RC7 RC6 RC5 RC4 MCLR/VPP/RE3 RB7/PGD RB6/PGC RB5/PGM RB4 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 VSS OSC1 OSC2 RC0 RC1 RC2 RC3 28 27 26 25 24 23 22 RA2 RA3 RA4 RA5 VSS OSC1 OSC2 1 2 3 4 5 6 7 PIC18F2423 PIC18F2523 21 20 19 18 17 16 15 RB3 RB2 RB1 RB0 VDD VSS RC7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 8 9 10 11 12 13 14 40-Pin PDIP (600 MIL) DS39759A-page 2 1 40 2 39 3 4 38 37 5 36 6 7 35 34 8 9 10 11 12 13 14 15 PIC18F4423 PIC18F4523 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 RE0 RE1 RE2 VDD VSS OSC1 OSC2 RC0 RC1 RC2 RC3 RD0 RD1 33 32 31 30 29 28 27 26 16 17 25 18 23 19 20 22 21 24 RB7/PGD RB6/PGC RB5/PGM RB4 RB3 RB2 RB1 RB0 VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 PIC18F2423/2523/4423/4523 FAMILY PIN DIAGRAMS RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 ICPORTS FIGURE 2-2: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIC18F4423 PIC18F4523 33 32 31 30 29 28 27 26 25 24 23 ICVPP RC0 OSC2 OSC1 VSS VDD RE2 RE1 RE0 RA5 RA4 RC6 D+/VP D-/VM RD3 RD2 RD1 RD0 VUSB RC2 RC1 RC0 ICPGC ICPGD RB4 RB5/PGM RB6/PGC RB7/PGD MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 44-Pin TQFP 44 43 42 41 40 39 38 37 36 35 34 44-Pin QFN PIC18F4423 PIC18F4523 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 OSC2 OSC1 VSS AVSS VDD AVDD RE2 RE1 RE0 RA5 RA4 RB3 NC RB4 RB5/PGM RB6/PGC RB7/PGD MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RC7 RD4 RD5 RD6 RD7 VSS AVDD VDD RB0 RB1 RB2 (c) 2005 Microchip Technology Inc. DS39759A-page 3 PIC18F2423/2523/4423/4523 2.3 TABLE 2-2: Memory Maps For PIC18F2523/4523 devices, the code memory space extends from 000000h to 007FFFh (32 Kbytes) in four 8-Kbyte blocks. Addresses 000000h through 0007FFh, however, define a "Boot Block" region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space. FIGURE 2-3: IMPLEMENTATION OF CODE MEMORY Device PIC18F2523 PIC18F4523 Code Memory Size (Bytes) 000000h-007FFFh (32K) MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18F2523/4523 DEVICES 000000h Code Memory 1FFFFFh MEMORY SIZE/DEVICE 32 Kbytes (PIC18F2523/4523) Unimplemented Read as `0' Address Range Boot Block 000000h 0007FFh Block 0 000800h 001FFFh 002000h Block 1 003FFFh 004000h Block 2 005FFFh 200000h 006000h Block 3 007FFFh 008000h Configuration and ID Space Unimplemented Reads all `0's 1FFFFFh 3FFFFFh Note: DS39759A-page 4 Sizes of memory areas are not to scale. (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 For PIC18F2423/4423 devices, the code memory space extends from 000000h to 003FFFh (16 Kbytes) in two 8-Kbyte blocks. Addresses 000000h through 0003FFh, however, define a "Boot Block" region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space. FIGURE 2-4: TABLE 2-3: IMPLEMENTATION OF CODE MEMORY Device Code Memory Size (Bytes) PIC18F2423 PIC18F4423 000000h-003FFFh (16K) MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18F2423/4423 DEVICES 000000h Code Memory 1FFFFFh MEMORY SIZE/DEVICE 16 Kbytes (PIC18F2423/4423) Unimplemented Read as `0' Address Range Boot Block 000000h 0007FFh Block 0 000800h 001FFFh 002000h Block 1 003FFFh 004000h 005FFFh 200000h 006000h 007FFFh 008000h Configuration and ID Space Unimplemented Reads all `0's 1FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. (c) 2005 Microchip Technology Inc. DS39759A-page 5 PIC18F2423/2523/4423/4523 In addition to the code memory space, there are three blocks that are accessible to the user through table reads and table writes. Their locations in the memory map are shown in Figure 2-5. Users may store identification information (ID) in eight ID registers. These ID registers are mapped in addresses 200000h through 200007h. The ID locations read out normally, even after code protection is applied. Locations 300000h through 30000Dh are reserved for the Configuration bits. These bits select various device options and are described in Section 5.0 "Configuration Word". These Configuration bits read out normally, even after code protection. Locations 3FFFFEh and 3FFFFFh are reserved for the device ID bits. These bits may be used by the programmer to identify what device type is being programmed and are described in Section 5.0 "Configuration Word". These device ID bits read out normally, even after code protection. FIGURE 2-5: 2.3.1 MEMORY ADDRESS POINTER Memory in the address space, 0000000h to 3FFFFFh, is addressed via the Table Pointer register, which is comprised of three Pointer registers: * TBLPTRU, at RAM address 0FF8h * TBLPTRH, at RAM address 0FF7h * TBLPTRL, at RAM address 0FF6h TBLPTRU TBLPTRH TBLPTRL Addr[21:16] Addr[15:8] Addr[7:0] The 4-bit command, `0000' (core instruction), is used to load the Table Pointer prior to using many read or write operations. CONFIGURATION AND ID LOCATIONS FOR PIC18F2423/2523/4423/4523 DEVICES 000000h Code Memory 01FFFFh Unimplemented Read as `0' 1FFFFFh Configuration and ID Space 2FFFFFh ID Location 1 200000h ID Location 2 200001h ID Location 3 200002h ID Location 4 200003h ID Location 5 200004h ID Location 6 200005h ID Location 7 200006h ID Location 8 200007h CONFIG1L 300000h CONFIG1H 300001h CONFIG2L 300002h CONFIG2H 300003h CONFIG3L 300004h CONFIG3H 300005h CONFIG4L 300006h CONFIG4H 300007h CONFIG5L 300008h CONFIG5H 300009h CONFIG6L 30000Ah CONFIG6H 30000Bh CONFIG7L 30000Ch CONFIG7H 30000Dh Device ID1 3FFFFEh Device ID2 3FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. DS39759A-page 6 (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 2.4 High-Level Overview of the Programming Process 2.5 Entering and Exiting High-Voltage ICSP Program/Verify Mode Figure 2-6 shows the high-level overview of the programming process. First, a Bulk Erase is performed. Next, the code memory, ID locations and data EEPROM are programmed (selected devices only, see Section 3.3 "Data EEPROM Programming"). These memories are then verified to ensure that programming was successful. If no errors are detected, the Configuration bits are then programmed and verified. As shown in Figure 2-7, the High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and then raising MCLR/VPP/RE3 to VIHH (high voltage). Once in this mode, the code memory, data EEPROM (selected devices only, see Section 3.3 "Data EEPROM Programming"), ID locations and Configuration bits can be accessed and programmed in serial fashion. Figure 2-8 shows the exit sequence. FIGURE 2-6: The sequence that enters the device into the Program/ Verify mode places all unused I/Os in the high-impedance state. HIGH-LEVEL PROGRAMMING FLOW Start FIGURE 2-7: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE Perform Bulk Erase P13 P12 P1 D110 Program Memory MCLR/VPP/RE3 Program IDs VDD PGD Program Data EE(1) PGC PGD = Input Verify Program FIGURE 2-8: EXITING HIGH-VOLTAGE PROGRAM/VERIFY MODE Verify IDs P16 Verify Data MCLR/VPP/RE3 Program Configuration Bits P17 P1 D110 VDD Verify Configuration Bits Done Note 1: Selected devices only, see Section 3.3 "Data EEPROM Programming". (c) 2005 Microchip Technology Inc. PGD PGC PGD = Input DS39759A-page 7 PIC18F2423/2523/4423/4523 2.6 Entering and Exiting Low-Voltage ICSP Program/Verify Mode When the LVP Configuration bit is `1' (see Section 5.3 "Single-Supply ICSP Programming"), the Low-Voltage ICSP mode is enabled. As shown in Figure 2-9, Low-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low, placing a logic high on PGM and then raising MCLR/VPP/RE3 to VIH. In this mode, the RB5/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. Figure 2-10 shows the exit sequence. The sequence that enters the device into the Program/ Verify mode places all unused I/Os in the high-impedance state. FIGURE 2-9: ENTERING LOW-VOLTAGE PROGRAM/VERIFY MODE Serial Program/Verify Operation The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/output during serial operation. Commands and data are transmitted on the rising edge of PGC, latched on the falling edge of PGC and are Least Significant bit (LSb) first. 2.7.1 4-BIT COMMANDS All instructions are 20 bits, consisting of a leading 4-bit command followed by a 16-bit operand, which depends on the type of command being executed. To input a command, PGC is cycled four times. The commands needed for programming and verification are shown in Table 2-4. Depending on the 4-bit command, the 16-bit operand represents 16 bits of input data or 8 bits of input data and 8 bits of output data. Throughout this specification, commands and data are presented as illustrated in Table 2-5. The 4-bit command is shown Most Significant bit (MSb) first. The command operand, or "Data Payload", is shown <MSB><LSB>. Figure 2-11 demonstrates how to serially present a 20-bit command/operand to the device. P12 P15 2.7 VIH MCLR/VPP/RE3 VDD VIH 2.7.2 PGM CORE INSTRUCTION The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to set up registers as appropriate for use with other commands. PGD PGC TABLE 2-4: PGD = Input COMMANDS FOR PROGRAMMING 4-Bit Command Description FIGURE 2-10: EXITING LOW-VOLTAGE PROGRAM/VERIFY MODE P16 MCLR/VPP/RE3 VDD PGM PGD VIH PGC PGD = Input DS39759A-page 8 P18 VIH Core Instruction (Shift in16-bit instruction) 0000 Shift out TABLAT register 0010 Table Read 1000 Table Read, post-increment 1001 Table Read, post-decrement 1010 Table Read, pre-increment 1011 Table Write 1100 Table Write, post-increment by 2 1101 Table Write, start programming, post-increment by 2 1110 Table Write, start programming 1111 TABLE 2-5: SAMPLE COMMAND SEQUENCE 4-Bit Command Data Payload 1101 3C 40 Core Instruction Table Write, post-increment by 2 (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 FIGURE 2-11: TABLE WRITE, POST-INCREMENT TIMING (1101) P2 1 2 3 4 P2A P2B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1 3 4 PGC P5A P5 P4 P3 PGD 1 0 1 1 0 0 0 0 4-Bit Command 0 0 0 1 0 0 0 4 C 16-Bit Data Payload 1 1 1 1 0 0 n n n n 3 Fetch Next 4-Bit Command PGD = Input (c) 2005 Microchip Technology Inc. DS39759A-page 9 PIC18F2423/2523/4423/4523 3.0 DEVICE PROGRAMMING Programming includes the ability to erase or write the various memory regions within the device. The code sequence to erase the entire device is shown in Table 3-2 and the flowchart is shown in Figure 3-1. Note: In all cases except high-voltage ICSP Bulk Erase, the EECON1 register must be configured in order to operate on a particular memory region. When using the EECON1 register to act on code memory, the EEPGD bit must be set (EECON1<7> = 1) and the CFGS bit must be cleared (EECON1<6> = 0). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort (e.g., erases) and this must be done prior to initiating a write sequence. The FREE bit must be set (EECON1<4> = 1) in order to erase the program space being pointed to by the Table Pointer. The erase or write sequence is initiated by setting the WR bit (EECON1<1> = 1). It is strongly recommended that the WREN bit only be set immediately prior to a program erase. 3.1 ICSP Erase 3.1.1 HIGH-VOLTAGE ICSP BULK ERASE Erasing code or data EEPROM is accomplished by configuring two Bulk Erase Control registers located at 3C0004h and 3C0005h. Code memory may be erased portions at a time, or the user may erase the entire device in one action. Bulk Erase operations will also clear any code-protect settings associated with the memory block erased. Erase options are detailed in Table 3-1. If data EEPROM is code-protected (CPD = 0), the user must request an erase of data EEPROM (e.g., 0084h as shown in Table 3-1). TABLE 3-1: BULK ERASE OPTIONS Description Data (3C0005h:3C0004h) Chip Erase 0F87h Erase Data EEPROM(1) 0084h Erase Boot Block 0081h Erase Config Bits 0082h Erase Code EEPROM Block 0 0180h Erase Code EEPROM Block 1 0280h Erase Code EEPROM Block 2 0480h Erase Code EEPROM Block 3 0880h Note 1: Selected devices only, see Section 3.3 "Data EEPROM Programming". A Bulk Erase is the only way to reprogram code-protect bits from an ON state to an OFF state. TABLE 3-2: BULK ERASE COMMAND SEQUENCE 4-Bit Data Command Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 0000 0000 0000 0000 1100 0E 6E 0E 6E 0E 6E 0F 0E 6E 0E 6E 0E 6E 87 0000 0000 00 00 00 00 FIGURE 3-1: 3C F8 00 F7 05 F6 0F 3C F8 00 F7 04 F6 87 Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 05h MOVWF TBLPTRL Write 0Fh to 3C0005h MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 8787h TO 3C0004h to erase entire device. NOP Hold PGD low until erase completes. BULK ERASE FLOW Start Write 0F0Fh to 3C0005h Write 8787h to 3C0004h to Erase Entire Device Delay P11 + P10 Time Done The actual Bulk Erase function is a self-timed operation. Once the erase has started (falling edge of the 4th PGC after the NOP command), serial execution will cease until the erase completes (parameter P11). During this time, PGC may continue to toggle but PGD must be held low. DS39759A-page 10 (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 FIGURE 3-2: BULK ERASE TIMING P10 1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 1 2 3 4 1 2 n n PGC P5A P5 PGD 0 0 1 1 4-Bit Command 1 1 0 16-Bit Data Payload 0 P5A P5 0 0 0 0 4-Bit Command 0 0 0 0 16-Bit Data Payload P11 0 0 0 0 4-Bit Command Erase Time 16-Bit Data Payload PGD = Input 3.1.2 LOW-VOLTAGE ICSP BULK ERASE When using low-voltage ICSP, the part must be supplied by the voltage specified in parameter D111 if a Bulk Erase is to be executed. All other Bulk Erase details as described above apply. If it is determined that a program memory erase must be performed at a supply voltage below the Bulk Erase limit, refer to the erase methodology described in Section 3.1.3 "ICSP Row Erase" and Section 3.2.1 "Modifying Code Memory". If it is determined that a data EEPROM erase (selected devices only, see Section 3.3 "Data EEPROM Programming") must be performed at a supply voltage below the Bulk Erase limit, follow the methodology described in Section 3.3 "Data EEPROM Programming" and write `1's to the array. 3.1.3 ICSP ROW ERASE Regardless of whether high or low-voltage ICSP is used, it is possible to erase one row (64 bytes of data), provided the block is not code or write-protected. Rows are located at static boundaries, beginning at program memory address 000000h, extending to the internal program memory limit (see Section 2.3 "Memory Maps"). The Row Erase duration is externally timed and is controlled by PGC. After the WR bit in EECON1 is set, a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9. After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. The code sequence to Row Erase a PIC18F2423/2523/ 4423/4523 device is shown in Table 3-3. The flowchart shown in Figure 3-3 depicts the logic necessary to completely erase a PIC18F2423/2523/4423/4523 device. The timing diagram that details the Start Programming command and parameters P9 and P10 is shown in Figure 3-5. Note: (c) 2005 Microchip Technology Inc. The TBLPTR register can point at any byte within the row intended for erase. DS39759A-page 11 PIC18F2423/2523/4423/4523 TABLE 3-3: ERASE CODE MEMORY CODE SEQUENCE 4-Bit Command Data Payload Core Instruction Step 1: Direct access to code memory and enable writes. 0000 0000 0000 8E A6 9C A6 84 A6 BSF BCF BSF EECON1, EEPGD EECON1, CFGS EECON1, WREN CLRF CLRF CLRF TBLPTRU TBLPTRH TBLPTRL Step 2: Point to first row in code memory. 0000 0000 0000 6A F8 6A F7 6A F6 Step 3: Enable erase and erase single row. 0000 0000 0000 88 A6 82 A6 00 00 BSF EECON1, FREE BSF EECON1, WR NOP - hold PGC high for time P9 and low for time P10. Step 4: Repeat step 3, with Address Pointer incremented by 64 until all rows are erased. FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW Start Addr = 0 Configure Device for Row Erases Start Erase Sequence and Hold PGC High for Time P9 Addr = Addr + 64 Hold PGC Low for Time P10 No All rows done? Yes Done DS39759A-page 12 (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 3.2 Code Memory Programming Programming code memory is accomplished by first loading data into the write buffer and then initiating a programming sequence. The write and erase buffer sizes, shown in Table 3-4, can be mapped to any location of the same size beginning at 000000h. The actual memory write sequence takes the contents of this buffer and programs the proper amount of code memory that contains the Table Pointer. The programming duration is externally timed and is controlled by PGC. After a Start Programming command is issued (4-bit command, `1111'), a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9. After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. TABLE 3-5: The code sequence to program a PIC18F2423/2523/ 4423/4523 device is shown in Table 3-5. The flowchart, shown in Figure 3-4, depicts the logic necessary to completely write a PIC18F2423/2523/4423/4523 device. The timing diagram that details the Start Programming command and parameters P9 and P10 is shown in Figure 3-5. Note: The TBLPTR register must point to the same region when initiating the programming sequence as it did when the write buffers were loaded. TABLE 3-4: WRITE AND ERASE BUFFER SIZES Devices Write Buffer Size (bytes) Erase Buffer Size (bytes) PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523 32 64 WRITE CODE MEMORY CODE SEQUENCE 4-Bit Command Data Payload Core Instruction Step 1: Direct access to code memory and enable writes. 0000 0000 8E A6 9C A6 BSF BCF EECON1, EEPGD EECON1, CFGS MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF <Addr[21:16]> TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 2: Load write buffer. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[15:8]> F7 <Addr[7:0]> F6 Step 3: Repeat for all but the last two bytes. 1101 <MSB><LSB> Write 2 bytes and post-increment address by 2. Step 4: Load write buffer for last two bytes. 1111 0000 <MSB><LSB> 00 00 Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented by 2 at each iteration of the loop. (c) 2005 Microchip Technology Inc. DS39759A-page 13 PIC18F2423/2523/4423/4523 FIGURE 3-4: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> N=N+1 All bytes written? No Yes N=1 LoopCount = LoopCount + 1 Start Write Sequence and Hold PGC High until Done and Wait P9 Hold PGC Low for Time P10 All locations done? No Yes Done FIGURE 3-5: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111) P10 1 2 3 4 1 3 2 4 5 6 15 16 1 2 3 4 PGC 2 3 P9 P5A P5 PGD 1 1 1 1 1 4-Bit Command n n n n n n n n 16-Bit Data Payload 0 0 0 0 4-Bit Command 0 Programming Time 0 0 16-Bit Data Payload PGD = Input DS39759A-page 14 (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 3.2.1 MODIFYING CODE MEMORY The previous programming example assumed that the device had been Bulk Erased prior to programming (see Section 3.1.1 "High-Voltage ICSP Bulk Erase"). It may be the case, however, that the user wishes to modify only a section of an already programmed device. The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in Section 4.2 "Verify Code Memory and ID Locations") and buffered. Modifications can be made on this buffer. Then, the block of code memory that was read out must be erased and rewritten with the modified data. The WREN bit must be set if the WR bit in EECON1 is used to initiate a write sequence. TABLE 3-6: MODIFYING CODE MEMORY 4-Bit Command Data Payload Core Instruction Step 1: Direct access to code memory. Step 2: Read and modify code memory (see Section 4.1 "Read Code Memory, ID Locations and Configuration Bits"). 0000 0000 8E A6 9C A6 BSF BCF EECON1, EEPGD EECON1, CFGS Step 3: Set the Table Pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[8:15]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF <Addr[21:16]> TBLPTRU <Addr[8:15]> TBLPTRH <Addr[7:0]> TBLPTRL Step 4: Enable memory writes and setup an erase. 0000 0000 84 A6 88 A6 BSF BSF EECON1, WREN EECON1, FREE Step 5: Initiate erase. 0000 0000 82 A6 00 00 BSF EECON1, WR NOP - hold PGC high for time P9 and low for time P10. Step 6: Load write buffer. The correct bytes will be selected based on the Table Pointer. 0000 0000 0000 0000 0000 0000 1101 . . . 1111 0000 0E <Addr[21:16]> 6E F8 0E <Addr[8:15]> 6E F7 0E <Addr[7:0]> 6E F6 <MSB><LSB> . . . <MSB><LSB> 00 00 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write 2 <Addr[21:16]> TBLPTRU <Addr[8:15]> TBLPTRH <Addr[7:0]> TBLPTRL bytes and post-increment address by 2. Repeat as many times as necessary to fill the write buffer Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. To continue modifying data, repeat Steps 2 through 6, where the Address Pointer is incremented by the appropriate number of bytes (see Table 3-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of the erase buffer. Step 7: Disable writes. 0000 94 A6 (c) 2005 Microchip Technology Inc. BCF EECON1, WREN DS39759A-page 15 PIC18F2423/2523/4423/4523 3.3 FIGURE 3-6: Data EEPROM Programming PROGRAM DATA FLOW Data EEPROM is accessed one byte at a time via an Address Pointer (register pair EEADRH:EEADR) and a data latch (EEDATA). Data EEPROM is written by loading EEADRH:EEADR with the desired memory location, EEDATA with the data to be written and initiating a memory write by appropriately configuring the EECON1 register. A byte write automatically erases the location and writes the new data (erase-before-write). Start Set Address Set Data When using the EECON1 register to perform a data EEPROM write, both the EEPGD and CFGS bits must be cleared (EECON1<7:6> = 00). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort and this must be done prior to initiating a write sequence. The write sequence is initiated by setting the WR bit (EECON1<1> = 1). Enable Write Start Write Sequence No WR bit clear? The write begins on the falling edge of the 4th PGC after the WR bit is set. It ends when the WR bit is cleared by hardware. Yes No After the programming sequence terminates, PGC must still be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. Done? Yes Done FIGURE 3-7: DATA EEPROM WRITE TIMING P10 1 2 3 4 1 2 1 15 16 2 PGC P5A P5 PGD 0 0 0 P11A n 0 4-Bit Command 16-Bit Data Payload Poll WR bit, Repeat until Clear (see below) BSF EECON1, WR n PGD = Input 1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 PGC P5 P5 P5A P5A Poll WR bit PGD 0 0 0 0 0 4-Bit Command MOVF EECON1, W, 0 PGD = Input DS39759A-page 16 0 0 0 4-Bit Command MOVWF TABLAT Shift Out Data (see Figure 4-4) PGD = Output (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 TABLE 3-7: PROGRAMMING DATA MEMORY 4-Bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 0000 9E A6 9C A6 BCF BCF EECON1, EEPGD EECON1, CFGS Step 2: Set the data EEPROM Address Pointer. 0000 0000 0000 0000 0E 6E OE 6E <Addr> A9 <AddrH> AA MOVLW MOVWF MOVLW MOVWF <Addr> EEADR <AddrH> EEADRH MOVLW MOVWF <Data> EEDATA BSF EECON1, WREN BSF EECON1, WR Step 3: Load the data to be written. 0000 0000 0E <Data> 6E A8 Step 4: Enable memory writes. 0000 84 A6 Step 5: Initiate write. 0000 82 A6 Step 6: Poll WR bit, repeat until the bit is clear. 0000 0000 0000 0010 50 A6 6E F5 00 00 <MSB><LSB> MOVF EECON1, W, 0 MOVWF TABLAT NOP Shift out data(1) Step 7: Hold PGC low for time P10. Step 8: Disable writes. 0000 94 A6 BCF EECON1, WREN Repeat steps 2 through 8 to write more data. Note 1: See Figure 4-4 for details on shift out data timing. (c) 2005 Microchip Technology Inc. DS39759A-page 17 PIC18F2423/2523/4423/4523 3.4 ID Location Programming The ID locations are programmed much like the code memory. The ID registers are mapped in addresses 200000h through 200007h. These locations read out normally even after code protection. Note: Table 3-8 demonstrates the code sequence required to write the ID locations. In order to modify the ID locations, refer to the methodology described in Section 3.2.1 "Modifying Code Memory". As with code memory, the ID locations must be erased before being modified. The user only needs to fill the first 8 bytes of the write buffer in order to write the ID locations. TABLE 3-8: WRITE ID SEQUENCE 4-Bit Command Data Payload Core Instruction Step 1: Direct access to code memory and enable writes. 0000 0000 8E A6 9C A6 BSF BCF EECON1, EEPGD EECON1, CFGS Step 2: Load write buffer with 8 bytes and write. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0E 20 6E F8 0E 00 6E F7 0E 00 6E F6 <MSB><LSB> <MSB><LSB> <MSB><LSB> <MSB><LSB> 00 00 DS39759A-page 18 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write NOP - 20h TBLPTRU 00h TBLPTRH 00h TBLPTRL 2 bytes and post-increment address by 2 bytes and post-increment address by 2 bytes and post-increment address by 2 bytes and start programming. hold PGC high for time P9 and low for 2. 2. 2. time P10. (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 3.5 Boot Block Programming 3.6 The code sequence detailed in Table 3-5 should be used, except that the address used in "Step 2" will be in the range of 000000h to 0007FFh. Configuration Bits Programming Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit command (`1111') is used, but only 8 bits of the following 16-bit payload will be written. The LSB of the payload will be written to even addresses and the MSB will be written to odd addresses. The code sequence to program two consecutive configuration locations is shown in Table 3-9. Note: TABLE 3-9: 4-Bit Command The address must be explicitly written for each byte programmed. The addresses can not be incremented in this mode. SET ADDRESS POINTER TO CONFIGURATION LOCATION Data Payload Core Instruction Step 1: Enable writes and direct access to config memory. 0000 0000 8E A6 8C A6 BSF BSF EECON1, EEPGD EECON1, CFGS Step 2(1): Set Table Pointer for config byte to be written. Write even/odd addresses. 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 1111 0000 Note 1: 0E 30 6E F8 0E 00 6E F7 0E 00 6E F6 <MSB ignored><LSB> 00 00 0E 01 6E F6 <MSB><LSB ignored> 00 00 MOVLW 30h MOVWF TBLPTRU MOVLW 00h MOVWF TBLPRTH MOVLW 00h MOVWF TBLPTRL Load 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. MOVLW 01h MOVWF TBLPTRL Load 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of Configuration bits. Always write all the Configuration bits before enabling the write protection for Configuration bits. FIGURE 3-8: CONFIGURATION PROGRAMMING FLOW Start Start Load Even Configuration Address Load Odd Configuration Address Program LSB Program MSB Delay P9 and P10 Time for Write Delay P9 and P10 Time for Write Done Done (c) 2005 Microchip Technology Inc. DS39759A-page 19 PIC18F2423/2523/4423/4523 4.0 READING THE DEVICE 4.1 Read Code Memory, ID Locations and Configuration Bits The 4-bit command is shifted in LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-1). This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read. Code memory is accessed one byte at a time via the 4-bit command, `1001' (table read, post-increment). The contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are serially output on PGD. TABLE 4-1: This technique will work to read any memory in the 000000h to 3FFFFFh address space, so it also applies to the reading of the ID and Configuration registers. READ CODE MEMORY SEQUENCE 4-Bit Command Data Payload Core Instruction Step 1: Set Table Pointer. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[15:8]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Addr[21:16] TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 2: Read memory and then shift out on PGD, LSb to MSb. 1001 00 00 FIGURE 4-1: TBLRD *+ TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001) 1 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 1 16 2 3 4 PGC P5 P5A P6 P14 PGD 1 0 0 LSb 1 1 2 3 4 5 Shift Data Out PGD = Input DS39759A-page 20 PGD = Output 6 MSb n n n n Fetch Next 4-Bit Command PGD = Input (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 4.2 Verify Code Memory and ID Locations The verify step involves reading back the code memory space and comparing it against the copy held in the programmer's buffer. Memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer's buffer. Refer to Section 4.1 "Read Code Memory, ID Locations and Configuration Bits" for implementation details of reading code memory. FIGURE 4-2: The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code memory has been verified. The post-increment feature of the table read 4-bit command may not be used to increment the Table Pointer beyond the code memory space. In a 64-Kbyte device, for example, a post-increment read of address FFFFh will wrap the Table Pointer back to 000000h, rather than point to unimplemented address 010000h. VERIFY CODE MEMORY FLOW Start Set TBLPTR = 0 Set TBLPTR = 200000h Read Low Byte with Post-Increment Read Low Byte with Post-Increment Read High Byte with Post-Increment Does Word = Expect data? Increment Pointer No Read High Byte with Post-Increment Does Word = Expect data? Failure, Report Error Yes No All code memory verified? Yes No Failure, Report Error Yes No All ID locations verified? Yes Done (c) 2005 Microchip Technology Inc. DS39759A-page 21 PIC18F2423/2523/4423/4523 4.3 FIGURE 4-3: Verify Configuration Bits READ DATA EEPROM FLOW A configuration address may be read and output on PGD via the 4-bit command, `1001'. Configuration data is read and written in a byte-wise fashion, so it is not necessary to merge two bytes into a word prior to a compare. The result may then be immediately compared to the appropriate configuration data in the programmer's memory for verification. Refer to Section 4.1 "Read Code Memory, ID Locations and Configuration Bits" for implementation details of reading configuration data. 4.4 Start Set Address Read Byte Read Data EEPROM Memory Move to TABLAT Data EEPROM is accessed one byte at a time via an Address Pointer (register pair EEADRH:EEADR) and a data latch (EEDATA). Data EEPROM is read by loading EEADRH:EEADR with the desired memory location and initiating a memory read by appropriately configuring the EECON1 register. The data will be loaded into EEDATA, where it may be serially output on PGD via the 4-bit command, `0010' (Shift Out Data Holding register). A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-4). Shift Out Data No Done? Yes Done The command sequence to read a single byte of data is shown in Table 4-2. TABLE 4-2: READ DATA EEPROM MEMORY 4-Bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 0000 9E A6 9C A6 BCF BCF EECON1, EEPGD EECON1, CFGS Step 2: Set the data EEPROM Address Pointer. 0000 0000 0000 0000 0E 6E OE 6E <Addr> A9 <AddrH> AA MOVLW MOVWF MOVLW MOVWF <Addr> EEADR <AddrH> EEADRH BSF EECON1, RD Step 3: Initiate a memory read. 0000 80 A6 Step 4: Load data into the Serial Data Holding register. 0000 0000 0000 0010 Note 1: 50 A8 6E F5 00 00 <MSB><LSB> MOVF EEDATA, W, 0 MOVWF TABLAT NOP Shift Out Data(1) The <LSB> is undefined. The <MSB> is the data. DS39759A-page 22 (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 FIGURE 4-4: 1 SHIFT OUT DATA HOLDING REGISTER TIMING (0010) 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 1 2 3 4 PGC P5 P5A P6 P14 PGD 0 1 0 LSb 1 0 2 3 4 5 6 4.5 Verify Data EEPROM A data EEPROM address may be read via a sequence of core instructions (4-bit command, `0000') and then output on PGD via the 4-bit command, `0010' (TABLAT register). The result may then be immediately compared to the appropriate data in the programmer's memory for verification. Refer to Section 4.4 "Read Data EEPROM Memory" for implementation details of reading data EEPROM. 4.6 Blank Check The term "Blank Check" means to verify that the device has no programmed memory cells. All memories must be verified: code memory, data EEPROM, ID locations and Configuration bits. The Device ID registers (3FFFFEh:3FFFFFh) should be ignored. PGD = Output FIGURE 4-5: n n n Fetch Next 4-Bit Command Shift Data Out PGD = Input n MSb PGD = Input BLANK CHECK FLOW Start Blank Check Device Is device blank? Yes Continue No Abort A "blank" or "erased" memory cell will read as a `1'. Therefore, Blank Checking a device merely means to verify that all bytes read as FFh except the Configuration bits. Unused (reserved) Configuration bits will read `0' (programmed). Refer to Table 5-1 for blank configuration expect data for the various PIC18F2423/2523/4423/ 4523 devices. Given that Blank Checking is merely code and data EEPROM verification with FFh expect data, refer to Section 4.4 "Read Data EEPROM Memory" and Section 4.2 "Verify Code Memory and ID Locations" for implementation details. (c) 2005 Microchip Technology Inc. DS39759A-page 23 PIC18F2423/2523/4423/4523 5.0 CONFIGURATION WORD 5.2 The device ID word for the PIC18F2423/2523/4423/ 4523 devices is located at 3FFFFEh:3FFFFFh. These bits may be used by the programmer to identify what device type is being programmed and read out normally, even after code or read protection. See Table 5-2 for a complete list of device ID values. The PIC18F2423/2523/4423/4523 devices have several Configuration Words. These bits can be set or cleared to select various device configurations. All other memory areas should be programmed and verified prior to setting Configuration Words. These bits may be read out normally, even after read or code protection. See Table 5-1 for a list of Configuration bits and device IDs and Table 5-3 for the Configuration bit descriptions. 5.1 Device ID Word FIGURE 5-1: READ DEVICE ID WORD FLOW Start ID Locations Set TBLPTR = 3FFFFE A user may store identification information (ID) in eight ID locations mapped in 200000h:200007h. It is recommended that the most significant nibble of each ID be Fh. In doing so, if the user code inadvertently tries to execute from the ID space, the ID data will execute as a NOP. Read Low Byte with Post-Increment Read High Byte with Post-Increment Done TABLE 5-1: CONFIGURATION BITS AND DEVICE IDs Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value CONFIG1H IESO FCMEN -- -- FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111 File Name 300001h 300002h CONFIG2L -- -- -- BORV1 BORV0 300003h CONFIG2H -- -- -- WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111 300005h CONFIG3H MCLRE -- -- -- -- LPT1OSC PBADEN CCP2MX 1--- -011 10-- -1-1 BOREN1 BOREN0 PWRTEN ---1 1111 300006h CONFIG4L DEBUG XINST -- -- -- LVP -- STVREN 300008h CONFIG5L -- -- -- -- CP3(1) CP2(1) CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB -- -- -- -- -- -- 11-- ---- 30000Ah CONFIG6L -- -- -- -- WRT3(1) WRT2(1) WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC -- -- -- -- -- 111- ---- 30000Ch CONFIG7L -- -- -- -- EBTR3(1) EBTR2(1) EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H -- EBTRB -- -- -- -- -- -- -1-- ---- 3FFFFEh DEVID1(2) DEV3 DEV2 DEV1 DEV0 REV3 REV2 REV1 REV0 xxxx xxxx(2) 3FFFFFh DEVID2(2) DEV11 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 0000 1100(2) Legend: Note 1: 2: x = unknown, - = unimplemented. Shaded cells are unimplemented, read as `0'. Unimplemented in PIC18F2423/4423 devices; maintain this bit set. DEVID registers are read-only and cannot be programmed by the user. TABLE 5-2: DEVICE ID VALUE Device ID Value Device DEVID2 DEVID1 11h 0101 xxxx PIC18F2523 11h 0001 xxxx PIC18F4423 10h 1101 xxxx PIC18F4523 10h 1001 xxxx PIC18F2423 Note: The `x's in DEVID1 contain the device revision code. DS39759A-page 24 (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 TABLE 5-3: PIC18F2423/2523/4423/4523 BIT DESCRIPTIONS Bit Name Configuration Words Description IESO CONFIG1H Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled FCMEN CONFIG1H Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled FOSC3:FOSC0 CONFIG1H Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal RC oscillator, CLKO function on RA6, port function on RA7 1000 = Internal RC oscillator, port function on RA6, port function on RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator BORV1:BORV0 CONFIG2L Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V BOREN1:BOREN0 CONFIG2L Brown-out Reset Enable bits 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software PWRTEN CONFIG2L Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDPS3:WDPS0 CONFIG2H Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WDTEN CONFIG2H Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) (c) 2005 Microchip Technology Inc. DS39759A-page 25 PIC18F2423/2523/4423/4523 TABLE 5-3: Bit Name PIC18F2423/2523/4423/4523 BIT DESCRIPTIONS (CONTINUED) Configuration Words Description MCLRE CONFIG3H MCLR Pin Enable bit 1 = MCLR pin enabled, RE3 input pin disabled 0 = RE3 input pin enabled, MCLR pin disabled LPT1OSC CONFIG3H Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation PBADEN CONFIG3H PORTB A/D Enable bit 1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset 0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset CCP2MX CONFIG3H CCP2 MUX bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 DEBUG CONFIG4L Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug XINST CONFIG4L Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) LVP CONFIG4L Low-Voltage Programming Enable bit 1 = Low-Voltage Programming enabled, RB5 is the PGM pin 0 = Low-Voltage Programming disabled, RB5 is an I/O pin STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled CP3 CONFIG5L Code Protection bits (Block 3 code memory area) 1 = Block 3 is not code-protected 0 = Block 3 is code-protected CP2 CONFIG5L Code Protection bits (Block 2 code memory area) 1 = Block 2 is not code-protected 0 = Block 2 is code-protected CP1 CONFIG5L Code Protection bits (Block 1 code memory area) 1 = Block 1 is not code-protected 0 = Block 1 is code-protected CP0 CONFIG5L Code Protection bits (Block 0 code memory area) 1 = Block 0 is not code-protected 0 = Block 0 is code-protected CPD CONFIG5H Code Protection bits (Data EEPROM) 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected CPB CONFIG5H Code Protection bits (Boot Block memory area) 1 = Boot Block is not code-protected 0 = Boot Block is code-protected WRT3 CONFIG6L Write Protection bits (Block 3 code memory area) 1 = Block 3 is not write-protected 0 = Block 3 is write-protected DS39759A-page 26 (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 TABLE 5-3: Bit Name PIC18F2423/2523/4423/4523 BIT DESCRIPTIONS (CONTINUED) Configuration Words Description WRT2 CONFIG6L Write Protection bits (Block 2 code memory area) 1 = Block 2 is not write-protected 0 = Block 2 is write-protected WRT1 CONFIG6L Write Protection bits (Block 1 code memory area) 1 = Block 1 is not write-protected 0 = Block 1 is write-protected WRT0 CONFIG6L Write Protection bits (Block 0 code memory area) 1 = Block 0 is not write-protected 0 = Block 0 is write-protected WRTD CONFIG6H Write Protection bit (Data EEPROM) 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected WRTB CONFIG6H Write Protection bit (Boot Block memory area) 1 = Boot Block is not write-protected 0 = Boot Block is write-protected WRTC CONFIG6H Write Protection bit (Configuration registers) 1 = Configuration registers are not write-protected 0 = Configuration registers are write-protected EBTR3 CONFIG7L Table Read Protection bit (Block 3 code memory area) 1 = Block 3 is not protected from table reads executed in other blocks 0 = Block 3 is protected from table reads executed in other blocks EBTR2 CONFIG7L Table Read Protection bit (Block 2 code memory area) 1 = Block 2 is not protected from table reads executed in other blocks 0 = Block 2 is protected from table reads executed in other blocks EBTR1 CONFIG7L Table Read Protection bit (Block 1 code memory area) 1 = Block 1 is not protected from table reads executed in other blocks 0 = Block 1 is protected from table reads executed in other blocks EBTR0 CONFIG7L Table Read Protection bit (Block 0 code memory area) 1 = Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks EBTRB CONFIG7H Table Read Protection bit (Boot Block memory area) 1 = Boot Block is not protected from table reads executed in other blocks 0 = Boot Block is protected from table reads executed in other blocks DEV11:DEV4 DEVID2 Device ID bits These bits are used with the DEV3:DEV0 bits in the DEVID1 register to identify part number. DEV3:DEV0 DEVID1 Device ID bits These bits are used with the DEV11:DEV4 bits in the DEVID2 register to identify part number. REV3:REV0 DEVID1 (c) 2005 Microchip Technology Inc. Revision ID bits These bits are used to indicate the revision of the device. DS39759A-page 27 PIC18F2423/2523/4423/4523 5.3 Single-Supply ICSP Programming The LVP bit in Configuration register, CONFIG4L, enables Single-Supply (Low-Voltage) ICSP Programming. The LVP bit defaults to a `1' (enabled) from the factory. If Single-Supply Programming mode is not used, the LVP bit can be programmed to a `0' and RB5/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed by entering the High-Voltage ICSP mode, where MCLR/VPP/RE3 is raised to VIHH. Once the LVP bit is programmed to a `0', only the High-Voltage ICSP mode is available and only the High-Voltage ICSP mode can be used to program the device. Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR/ VPP/RE3 pin. 2: While in Low-Voltage ICSP mode, the RB5 pin can no longer be used as a general purpose I/O. 5.4 Embedding Configuration Word Information in the HEX File To allow portability of code, a PIC18F2423/2523/4423/ 4523 programmer is required to read the Configuration Word locations from the hex file. If Configuration Word information is not present in the hex file, then a simple warning message should be issued. Similarly, while saving a hex file, all Configuration Word information must be included. An option to not include the Configuration Word information may be provided. When embedding Configuration Word information in the hex file, it should start at address 300000h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 5.5 Embedding Data EEPROM Information In the HEX File To allow portability of code, a PIC18F2423/2523/4423/ 4523 programmer is required to read the data EEPROM information from the hex file. If data EEPROM information is not present, a simple warning message should be issued. Similarly, when saving a hex file, all data EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the hex file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. DS39759A-page 28 5.6 Checksum Computation The checksum is calculated by summing the following: * The contents of all code memory locations * The Configuration Words, appropriately masked * ID locations (if any block is code-protected) The Least Significant 16 bits of this sum is the checksum. The contents of the data EEPROM are not used. 5.6.1 PROGRAM MEMORY When program memory contents are summed, each 16-bit word is added to the checksum. The contents of program memory from 000000h to the end of the last program memory block are used for this calculation. Overflows from bit 15 may be ignored. 5.6.2 CONFIGURATION WORDS For checksum calculations, unimplemented bits in Configuration Words should be ignored as such bits always read back as `1's. Each 8-bit Configuration Word is ANDed with a corresponding mask to prevent unused bits from affecting checksum calculations. The mask contains a `0' in unimplemented bit positions, or a `1' where a choice can be made. When ANDed with the value read out of a Configuration Word, only implemented bits remain. A list of suitable masks is provided in Table 5-5. 5.6.3 ID LOCATIONS Normally, the contents of these locations are defined by the user, but MPLAB(R) IDE provides the option of writing the device's unprotected 16-bit checksum in the 16 Most Significant bits of the ID locations (see MPLAB IDE "Configure/ID Memory" menu). The lower 16 bits are not used and remain clear. This is the sum of all program memory contents and Configuration Words (appropriately masked) before any code protection is enabled. If the user elects to define the contents of the ID locations, nothing about protected blocks can be known. If the user uses the preprotected checksum provided by MPLAB IDE, an indirect characteristic of the programmed code is provided. 5.6.4 CODE PROTECTION Blocks that are code-protected read back as all `0's and have no effect on checksum calculations. If any block is code-protected, then the contents of the ID locations are included in the checksum calculation. All Configuration Words and the ID locations can always be read out normally, even when the device is fully code-protected. Checking the code protection settings in Configuration Words can direct which, if any, of the program memory blocks can be read and if the ID locations should be used for checksum calculations. (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 TABLE 5-4: DEVICE BLOCK LOCATIONS AND SIZES Ending Address Memory Size Pins (bytes) Device Size (bytes) Boot Block Block 0 Block 1 Block 2 Block 3 Boot Block Block 0 Remaining Blocks Device Total PIC18F2423 16K 28 0007FF 001FFF 003FFF -- -- 2048 6144 8192 16384 PIC18F2523 32K 28 0007FF 001FFF 003FFF 005FFF 007FFF 2048 14336 16384 32768 PIC18F4423 16K 40 0007FF 001FFF 003FFF -- -- 2048 6144 8192 16384 PIC18F4523 32K 40 0007FF 001FFF 003FFF 005FFF 007FFF 2048 14336 16384 32768 Legend: -- = unimplemented. TABLE 5-5: CONFIGURATION WORD MASKS FOR COMPUTING CHECKSUMS Configuration Word (CONFIGxx) 1L Device 1H 2L 2H 3L 3H 4L 4H 5L 5H 6L 6H 7L 7H 8h 9h Ah Bh Ch Dh 40 Address (30000xh) 0h 1h 2h 3h 4h 5h 6h 7h PIC18F2423 00 CF 1F 1F 00 87 C5 00 03 C0 03 E0 03 PIC18F2523 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40 PIC18F4423 00 CF 1F 1F 00 87 C5 00 03 C0 03 E0 03 40 PIC18F4523 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40 Legend: Shaded cells are unimplemented. (c) 2005 Microchip Technology Inc. DS39759A-page 29 PIC18F2423/2523/4423/4523 6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: 25C is recommended Param No. D110 Sym Characteristic Min Max Units Conditions VIHH High-Voltage Programming Voltage on MCLR/VPP/RE3 VDD + 4.0 12.5 V (Note 2) D110A VIHL Low-Voltage Programming Voltage on MCLR/VPP/RE3 2.00 5.50 V (Note 2) D111 Supply Voltage During Programming 2.00 5.50 V Externally timed, row erases and all writes 3.0 5.50 V Self-timed, bulk erases only (Note 3) -- 300 A (Note 2) VDD D112 IPP Programming Current on MCLR/VPP/RE3 D113 IDDP Supply Current During Programming -- 10 mA D031 VIL Input Low Voltage VSS 0.2 VDD V D041 VIH Input High Voltage 0.8 VDD VDD V D080 VOL Output Low Voltage -- 0.6 V IOL = 8.5 mA @ 4.5V D090 VOH Output High Voltage VDD - 0.7 -- V IOH = -3.0 mA @ 4.5V D012 CIO Capacitive Loading on I/O pin (PGD) -- 50 pF To meet AC specifications P1 TR MCLR/VPP/RE3 Rise Time to Enter Program/Verify mode -- 1.0 s (Note 1, 2) P2 TPGC Serial Clock (PGC) Period 100 -- ns VDD = 5.0V 1 -- s VDD = 2.0V P2A TPGCL Serial Clock (PGC) Low Time 40 -- ns VDD = 5.0V 400 -- ns VDD = 2.0V 40 -- ns VDD = 5.0V VDD = 2.0V P2B TPGCH Serial Clock (PGC) High Time 400 -- ns P3 TSET1 Input Data Setup Time to Serial Clock 15 -- ns P4 THLD1 Input Data Hold Time from PGC 15 -- ns P5 TDLY1 Delay between 4-bit Command and Command Operand 40 -- ns P5A TDLY1A Delay between 4-bit Command Operand and Next 4-bit Command 40 -- ns P6 TDLY2 Delay between Last PGC of Command Byte to First PGC of Read of Data Word 20 -- ns P9 TDLY5 PGC High Time (minimum programming time) P10 TDLY6 PGC Low Time after Programming (high-voltage discharge time) P11 TDLY7 Delay to allow Self-Timed Data Write or Bulk Erase to occur Note 1: 1 -- ms 100 -- s 5 -- ms Externally timed 2: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions to occur. The maximum transition time is: 1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. When ICPORT = 1, this specification also applies to ICVPP. 3: At 0C-50C. DS39759A-page 30 (c) 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE (CONTINUED) Standard Operating Conditions Operating Temperature: 25C is recommended Param No. Sym Characteristic Min Max Units 4 -- ms P11A TDRWT Data Write Polling Time P12 THLD2 Input Data Hold Time from MCLR/VPP/RE3 2 -- s P13 TSET2 VDD Setup Time to MCLR/VPP/RE3 100 -- ns P14 TVALID Data Out Valid from PGC 10 -- ns P15 TSET3 PGM Setup Time to MCLR/VPP/RE3 2 -- s P16 TDLY8 Delay between Last PGC and MCLR/VPP/RE3 0 -- s P17 THLD3 MCLR/VPP/RE3 to VDD -- 100 ns P18 THLD4 MCLR/VPP/RE3 to PGM 0 -- s Note 1: Conditions (Note 2) (Note 2) 2: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions to occur. The maximum transition time is: 1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. When ICPORT = 1, this specification also applies to ICVPP. 3: At 0C-50C. (c) 2005 Microchip Technology Inc. DS39759A-page 31 PIC18F2423/2523/4423/4523 NOTES: DS39759A-page 32 (c) 2005 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2005 Microchip Technology Inc. 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