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GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-053317 March 2013
290 x 290 3.5Gb/s Crosspoint Switch with Trace Equalization and Output
De-emphasis
GX3290
www.semtech.com
Key Features
• 290 x 290 crosspoint switch architecture supporting
broadcast and multi-cast modes
• Supports all data rates up to 3.5Gb/s
• Low power consumption: 34.25W typical (all channels
active)
• Sophisticated, dynamic on-chip power management
control
• Independent, programmable input trace equalization
to reduce deterministic jitter (ISI)
• Independent, programmable output de-emphasis for
driving long board traces
• High-speed, video-optimized control for multi-format
applications
• Built-in system test features with on-chip PRBS
generators and analyzers
• 2.5V analog core voltage, 1.8V digital core voltage
• Input and output voltages support either 1.2V, 1.8V or
2.5V CML
• JTAG-controlled boundary scan
• Selectable parallel/serial host interface
• 50mm x 50mm BGA (2377 ball)
• Operating temperature range: 0°C to +85°C
• RoHS compliant
Applications
Large m x n cascaded routers/switch fabrics for:
• Professional broadcast applications
• Enterprise and carrier applications
• High-speed automated test equipment
• 10GbE and InfiniBand networks
Description
The GX3290 is a low-power, high-speed 290 x 290
crosspoint switch, with robust signal conditioning circuits
for driving and receiving high-speed signals through
backplanes.
The device typically consumes 34.25W of power with all
channels operational, and features sophisticated,
dynamically scalable power management. Unused
portions of the core are automatically turned off without
affecting the operation of the remaining channels.
The signal conditioning features of the GX3290 include
per-input programmable equalization and per-output
programmable de-emphasis. The input equalizer removes
ISI jitter—typically caused by PCB trace losses—by
opening the input data eye in applications where long PCB
traces are used. There are four settings available for the
input equalizer, allowing flexibility in adjusting the
equalization level on a per-input basis.
Output de-emphasis capability provides a boost of the
high-frequency content of the output signal, such that the
data eye remains open after passing through a long
interconnect of PCB traces and connectors. There are four
de-emphasis settings that can be enabled on a per-output
basis.
Two integrated programmable pattern generators, and two
pattern checkers are provided to assist in system test and
configuration.
The pattern generators can each be routed to any output of
the device without impacting the normal operation of any
other channel. Any input can be routed to each of the
pattern checkers.
The chip features eight independent strobe inputs,
UPDATE_EN[7:0], which are used to determine the timing
of the output updates. Any output can be linked to any
strobe.
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-053317 March 2013
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GX3290 Functional Block Diagram
Input 0
De-Emp
Output 0
Output 287
Input 287
Trace
EQ
Parallel/Serial Interfaces and General Registers
Active
Configuration Latch
Input
Configuration Latch
JTAG and
Boundary
Scan
Reference Clock/Crystal Buffer
Programmable
Pattern Generator 1
MON0/MON0
UPDATE_EN[7:0]
P_DAT
[15:0]
P_ADD
[11:0]
SCLK
SDIN
SDOUT
REF_CLK_IN REF_CLK_OUT
SDI[0]/SDI[0]
SDI[287]/SDI[287]
Programmable
Pattern Generator 0
SDO[0]/SDO[0]
SDO[287]/SDO[287]
Trace
EQ
P_R/W
De-Emp
Pattern Checker
& Status Monitor 0
Pattern Checker
& Status Monitor 1
MON1/MON1
EXT_PG0/EXT_PG0
EXT_PG1/EXT_PG1
RESET
HOST_S/P
S_CS P_CS
P_ADS
TCK
TDI
TDO
TMS
Input 288
Trace
EQ
Input 289
Output 288
Output 289
De-Emp
290 x 290
Differential
Cross-point
Switch Matrix
De-Emp
Trace
EQ
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-053317 March 2013
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Revision History
Version ECO PCN Date Changes and/or Modifications
2 011719 – March 2013 Corrected second bullet in Section 4.7.1, and added a note to
Section 4.4.
1 158372 – October 2012
Included ESD Voltage Sensitivity in Table 2-1. Modifications to
Table 4-18 and Section 4.12.2 to include Auto-Increment Timing
and functionality. Updates to Appendix - Relevant
Documentation with clear reference to correct documents.
Converted document to Final Data Sheet.
0 157403 – February 2012 Converted document to Preliminary Data Sheet. Updates
throughout.
F 157275 – November 2011 Minor updates through entire document.
E 156342 – July 2011
Updates throughout entire document. Removed Configuration
and Status Registers (transferred to document Crosspoint
(GX3290 and family) Reference Manual (for CSRs)).
D 154735 – September 2010
Changed maximum data rate to 3.5Gb/s. Updates to Figure 4-10
and Figure 4-11, 4.12.2 Serial Host Interface Specifications,
Package Dimensions and Marking Diagram.
C154303 – July 2010
Updates throughout entire document. Changes to GX3290 Ball
Assignment Overview (Top View). Addition of multiple sections
in Section 4. Detailed Description. Addition of Ball Descriptions.
Changes to Input/Output Equivalent Circuits and Application
Information.
B 153176 – January 2010
Updates to Table 2-3: DC Electrical Characteristics. Updates to
Section 4.12 Host Interface. Updates to Figure 1-1: GX3290 Ball
Assignment Overview (Top View). Addition of Section 3.
Input/Output Equivalent Circuits.
A 152552 – October 2009 New document.
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-053317 March 2013
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Contents
Key Features ........................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
Revision History .................................................................................................................................................3
1. Ball Out .............................................................................................................................................................5
1.1 Ball Assignment ................................................................................................................................5
1.2 Ball Descriptions ...............................................................................................................................6
2. Electrical Characteristics ............................................................................................................................9
2.1 Absolute Maximum Ratings ..........................................................................................................9
2.2 Recommended Operating Conditions .................................................................................... 10
2.3 DC Electrical Characteristics ..................................................................................................... 11
2.4 AC Electrical Characteristics ..................................................................................................... 15
3. Input/Output Equivalent Circuits......................................................................................................... 17
4. Detailed Description.................................................................................................................................. 20
4.1 Serial Data Input ............................................................................................................................ 20
4.2 Serial Data Output ......................................................................................................................... 21
4.3 Crosspoint Switch Matrix Operation ...................................................................................... 23
4.4 Propagation Delay ......................................................................................................................... 24
4.5 Using Multiple Strobes ................................................................................................................. 24
4.6 Pattern Generator and Pattern Checker ................................................................................ 25
4.6.1 Pattern Generator.............................................................................................................. 25
4.6.2 Pattern Checker.................................................................................................................. 26
4.7 Horizontal Eye Measurement .................................................................................................... 30
4.7.1 Configuration for Horizontal Eye Measurement .................................................... 30
4.8 Temperature Sensors .................................................................................................................... 30
4.9 27MHz Reference Clock .............................................................................................................. 33
4.10 Device Power-Up ........................................................................................................................ 33
4.11 Device Reset .................................................................................................................................. 34
4.12 Host Interface ............................................................................................................................... 34
4.12.1 Parallel Host Interface Specifications ...................................................................... 34
4.12.2 Serial Host Interface Specifications .......................................................................... 39
5. Application Information .......................................................................................................................... 41
5.1 Power Supply Filtering and Recommendations .................................................................. 41
5.2 Estimated Worst-Case Load Current Steps ........................................................................... 42
5.2.1 VCC_25_A Supply ............................................................................................................. 42
5.2.2 VCC_OUT1, VCC_OUT2 Supplies ................................................................................ 42
5.2.3 VCC_IN1, VCC_IN2 Supplies......................................................................................... 43
6. Package and Ordering Information...................................................................................................... 44
6.1 Package Dimensions ..................................................................................................................... 44
6.2 Package Thermal Data and Information ................................................................................ 45
6.3 Marking Diagram ........................................................................................................................... 45
6.4 Solder Reflow Profile .................................................................................................................... 46
6.5 Ordering Information ................................................................................................................... 46
Appendix - Relevant Documentation...................................................................................................... 46
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
GENDOC-053317 March 2013
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1. Ball Out
1.1 Ball Assignment
Figure 1-1: GX3290 Ball Assignment Overview (Top View)
SDI_
17
SDI_
39
SDI_
17
SDI_
5
SDI_
1
12 34 567 8 9 101112131415 1617 18 19 20 21 22 23 24 25 2627 28 29 3130 32 33 34 35 3637 38 39 40 41 42 43 44 45 4647 48 49
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AU
AV
AW
1234567 8 9 1011 121314151617 18 19 20 21
GND
GNDGNDGND
GND
GNDGNDGNDGNDGNDGND
GND
GNDGNDGNDGNDGNDGNDGND
GND
GNDGNDGND
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GNDGND
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GND
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GNDGNDGND
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GNDGND
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GND
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GNDGNDGNDGNDGNDGNDGND
GNDGND
GNDGNDGNDGNDGNDGND
GND
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GND
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GND
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GNDGND
GND
GNDGNDGNDGNDGND
GND
GND
GND
GNDGNDGNDGNDGNDGNDGND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GNDGND
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GNDGNDGNDGNDGND
GND
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GNDGNDGNDGNDGNDGNDGNDGNDGND
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GND
GNDGNDGNDGNDGNDGNDGNDGND
GND
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GND
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GNDGNDGNDGNDGNDGNDGND
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GND
GND
GNDGND
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GND
GNDGNDGNDGND
GND
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GNDGND
GNDGND
GNDGND
GND
GNDGND
GND
GNDGND
GNDGNDGNDGNDGNDGNDGND
GND
GND
GND
GND
GND
GNDGND
GNDGNDGNDGNDGNDGNDGNDGNDGND
GNDGND
GNDGNDGNDGND
GND
GNDGNDGNDGNDGND
GND
GNDGNDGNDGNDGND
GNDGNDGNDGND
GND
GNDGNDGNDGND
GND
GND
GND
GNDGNDGNDGND
GND
GNDGNDGNDGNDGNDGNDGND
GNDGNDGND
GND
GNDGND
GNDGND
GND
GNDGNDGNDGND
GND
GNDGNDGNDGNDGND
GND
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GND
GNDGNDGNDGNDGNDGNDGNDGNDGND
GND
GND
GND
GNDGNDGND
GND
GND
VCC_
25_A
GNDGND
GND
GND
GND
GND
GND
GND
GNDGNDGND
GNDGNDGND
GNDGNDGND
GNDGND
GND
GND
GND
GND
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GND
GND
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GND
GNDGND
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GND
VCC_
25_A
GND
GND GND
GND
GND
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GNDGND
GND
GND
GND
GND
GND GND GND GND GND GND GND
GND
GND
GND
GND
GND
VDD
_25
VDD
_25
VDD
_25
VDD
_25
VCC_
25_A
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT1
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VDD
_18
VDD
_18
VDD
_18
VDD
_18
VDD
_18
VDD
_18
VDD
_18
VDD
_18
VDD
_18
VDD
_18
VDDIO
_D
LDO0
LDO_
DIGITAL
LDO1
LDO2
POR_
DFT
RSV
_DNC RESET
REF_
CLK_
IN
REF_
CLK_
OUT
GND GND GND GND GND GND
TDO TDITCK
SDOUTSCLK
P_R/W
S_CS
RSV
_DNC
RSV
_DNC
RSV
_DNC
RSV
_DNC
HOST_
S/P
P_ADS
P_ADD
0
P_ADD
1
P_ADD
10
P_ADD
11
P_ADD
2
P_ADD
3
P_ADD
4
P_ADD
5
P_ADD
6
P_ADD
7
P_ADD
8
P_ADD
9
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0
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1
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10
P_DAT
11
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2
P_DAT
3
P_DAT
4
P_DAT
5
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6
P_DAT
7
P_DAT
8
P_DAT
9
P_CS
P_DAT
12
P_DAT
13
P_DAT
14
P_DAT
15
TMS
UPDATE
_EN0
UPDATE
_EN1
UPDATE
_EN2
UPDATE
_EN3
UPDATE
_EN4
UPDATE
_EN5
UPDATE
_EN6
UPDATE
_EN7
SDIN
SDI
_0
SDI_
10
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100
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101
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103
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105
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107
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109
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102
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104
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106
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11
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111
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113
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115
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117
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119
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110
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112
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114
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116
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SDI_
12
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120
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130
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134
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136
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14
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140
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144
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146
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148
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150
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152
SDI_
154
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121
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123
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125
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127
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129
SDI_
13
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131
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133
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135
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137
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141
SDI_
143
SDI_
145
SDI_
147
SDI_
149
SDI_
139
SDI_
151
SDI_
153
SDI_
155
SDI_
157
SDI_
15
SDI_
156
SDI_
158
SDI_
16
SDI_
160
SDI_
162
SDI_
161
SDI_
159
SDI_
163
SDI_
165
SDI_
167
SDI_
169
SDI_
7
SDI_
171
SDI_
173
SDI_
175
SDI_
177
SDI_
179
SDI_
164
SDI_
166
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168
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170
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172
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174
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176
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178
SDI_
18
SDI_
180
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181
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183
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185
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187
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189
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19
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191
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193
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195
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197
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199
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201
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203
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205
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182
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184
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186
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188
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190
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192
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194
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196
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198
SDI_
2
SDI_
20
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200
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202
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204
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207
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209
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21
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213
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215
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23
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238
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24
SDI_
240
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242
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244
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246
SDI_
248
SDI_
22
SDI_
25
SDI_
251
SDI_
253
SDI_
257
SDI_
259
SDI_
261
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263
SDI_
265
SDI_
267
SDI_
269
SDI_
250
SDI_
252
SDI_
254
SDI_
256
SDI_
258
SDI_
260
SDI_
262
SDI_
264
SDI_
266
SDI_
268
SDI_
26
SDI_
270
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272
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274
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276
SDI_
278
SDI_
27
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271
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273
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275
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277
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279
SDI_
281
SDI_
285
SDI_
28
SDI_
280
SDI_
282
SDI_
284
SDI_
286
SDI_
30
SDI_
32
SDI_
34
SDI_
36
SDI_
38
SDI_
40
SDI_
42
SDI_
44
SDI_
46
SDI_
48
SDI_
50
SDI_
52
SDI_
54
SDI_
56
SDI_
58
SDI_
60
SDI_
62
SDI_
64
SDI_
66
SDI_
68
SDI_
70
SDI_
72
SDI_
74
SDI_
76
SDI_
78
SDI_
80
SDI_
82
SDI_
84
SDI_
86
SDI_
88
SDI_
90
SDI_
92
SDI_
94
SDI_
96
SDI_
98
SDI_
29
SDI_
3
SDI_
31
SDI_
33
SDI_
35
SDI_
37
SDI_
39
SDI_
41
SDI_
43
SDI_
45
SDI_
47
SDI_
49
SDI_
51
SDI_
53
SDI_
55
SDI_
57
SDI_
59
SDI_
61
SDI_
63
SDI_
65
SDI_
67
SDI_
69
SDI_
71
SDI_
73
SDI_
75
SDI_
77
SDI_
79
SDI_
81
SDI_
83
SDI_
85
SDI_
87
SDI_
89
SDI_
91
SDI_
93
SDI_
95
SDI_
97
SDI_
99
SDI_
4
SDI_
6
GND
DIGITAL
_CL_SEL
GND RSV
_DNC
RSV
_DNC
RSV
_DNC
RSV
_DNC
DTHERMA
0
DTHERMK
0
DTHERMK
3
DTHERMA
2
DTHERMK
2
DTHERMA
3
DTHERMA
1
DTHERMK
1
LF_
DIGITAL
LF1
VCC
_25_
VCO0
VCC_
VCO_
DIGITAL
VCC_
25_
VCO1
VCC
_25_
VCO2
NC NC
NC
NC
NC
NC
NC
NC
NC
NC
NCNC
NC
NC NC
NC NC NC
NCNC
NC
NC NC
NC
EXT_
CLK0
EXT
_CLK2
EXT_
CLK_
DIGITAL
EXT
_CLK1
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN1
VCC
_IN1
VCC
_IN1
VCC
_IN1
VCC
_IN1
VCC
_IN1
VCC
_IN1
VCC
_IN1
VCC
_IN1
MON1
SDO_
0
SDO_
10
SDO_
100
SDO_
110
SDO_
102
SDO_
104
SDO_
106
SDO_
112
SDO_
1
SDO_
105
SDO_
107
SDO_
109
SDO_
11
SDO_
101
SDO_
103
SDO_
111
SDO_
113
SDO_
115
SDO_
117
SDO_
119
SDO_
121
SDO_
123
SDO_
125
SDO_
127
SDO_
129
SDO_
13
SDO_
131
SDO_
133
SDO_
135
SDO_
137
SDO_
139
SDO_
141
SDO_
143
SDO_
145
SDO_
147
SDO_
149
SDO_
15
SDO_
151
SDO_
153
SDO_
155
SDO_
157
SDO_
159
SDO_
161
SDO_
108
SDO_
114
SDO_
116
SDO_
118
SDO_
120
SDO_
12
SDO_
122
SDO_
124
SDO_
126
SDO_
128
SDO_
130
SDO_
132
SDO_
134
SDO_
136
SDO_
154
SDO_
144
SDO_
14
SDO_
142
SDO_
140
SDO_
138
SDO_
148
SDO_
146
SDO_
152
SDO_
170
SDO_
160
SDO_
158
SDO_
156
SDO_
16
SDO_
162
SDO_
164
SDO_
166
SDO_
168
SDO_
150
SDO_
176
SDO_
174
SDO_
172
SDO_
194
SDO_
180
SDO_
182
SDO_
184
SDO_
202
SDO_
192
SDO_
222
SDO_
188
SDO_
178
SDO_
196
SDO_
198
SDO_
200
SDO_
218
SDO_
220
SDO_
206
SDO_
208
SDO_
226
SDO_
212
SDO_
230
SDO_
216
SDO_
186
SDO_
224
SDO_
190
SDO_
256
SDO_
214
SDO_
228
SDO_
18
SDO_
2
SDO_
20
SDO_
22
SDO_
163
SDO_
165
SDO_
167
SDO_
169
SDO_
171
SDO_
173
SDO_
175
SDO_
177
SDO_
179
SDO_
181
SDO_
183
SDO_
185
SDO_
187
SDO_
189
SDO_
191
SDO_
193
SDO_
195
SDO_
197
SDO_
199
SDO_
201
SDO_
203
SDO_
205
SDO_
207
SDO_
209
SDO_
211
SDO_
213
SDO_
215
SDO_
217
SDO_
219
SDO_
221
SDO_
223
SDO_
225
SDO_
227
SDO_
23
SDO_
17
SDO_
19
SDO_
21
SDO_
229
SDO_
231
SDO_
233
SDO_
235
SDO_
237
SDO_
239
SDO_
241
SDO_
243
SDO_
245
SDO_
247
SDO_
249
SDO_
251
SDO_
253
SDO_
255
SDO_
257
SDO_
259
SDO_
261
SDO_
263
SDO_
265
SDO_
267
SDO_
269
SDO_
271
SDO_
273
SDO_
275
SDO_
277
SDO_
279
SDO_
281
SDO_
283
SDO_
285
SDO_
287
SDO_
25
SDO_
27
SDO_
232
SDO_
266
SDO_
204
SDO_
238
SDO_
252
SDO_
210
SDO_
276
SDO_
242
SDO_
248
SDO_
250
SDO_
240
SDO_
254
SDO_
272
SDO_
262
SDO_
260
SDO_
258
SDO_
264
SDO_
234
SDO_
236
SDO_
270
SDO_
284
SDO_
278
SDO_
244
SDO_
274
SDO_
280
SDO_
286
SDO_
268
SDO_
282
SDO_
24
SDO_
26
SDO_
28
SDO_
34
SDO_
32
SDO_
30
SDO_
36
SDO_
38
SDO_
40
SDO_
42
SDO_
44
SDO_
46
SDO_
48
SDO_
50
SDO_
52
SDO_
54
SDO_
56
SDO_
58
SDO_
60
SDO_
4
SDO_
6
SDO_
8
SDO_
70
SDO_
76
SDO_
90
SDO_
62
SDO_
64
SDO_
66
SDO_
68
SDO_
72
SDO_
74
SDO_
80
SDO_
78
SDO_
82
SDO_
84
SDO_
86
SDO_
88
SDO_
96
SDO_
94
SDO_
92
SDO_
98
SDO_
3
SDO_
31
SDO_
33
SDO_
35
SDO_
37
SDO_
39
SDO_
41
SDO_
43
SDO_
45
SDO_
47
SDO_
49
SDO_
51
SDO_
53
SDO_
55
SDO_
57
SDO_
59
SDO_
5
SDO_
7
SDO_
9
SDO_
61
SDO_
63
SDO_
65
SDO_
67
SDO_
69
SDO_
71
SDO_
73
SDO_
75
SDO_
77
SDO_
79
SDO_
81
SDO_
83
SDO_
85
SDO_
87
SDO_
89
SDO_
91
SDO_
93
SDO_
95
SDO_
97
SDO_
99
SDO_
0
SDO_
1
SDO_
10
SDO_
100
SDI_
0
SDI_
10
SDI_
100
SDI_
102
SDI_
104
SDI_
106
SDI_
108
SDI_
110
SDI_
112
SDI_
114
SDI_
116
SDI_
118
SDI_
120
SDI_
122
SDI_
124
SDI_
126
SDI_
128
SDI_
130
SDI_
101
SDI_
103
SDI_
105
SDI_
107
SDI_
109
SDI_
11
SDI_
111
SDI_
113
SDI_
115
SDI_
117
SDI_
119
SDI_
12
SDI_
121
SDI_
123
SDI_
125
SDI_
127
SDI_
129
SDI_
13
SDI_
132
SDI_
134
SDI_
136
SDI_
138
SDI_
14
SDI_
140
SDI_
142
SDI_
144
SDI_
146
SDI_
148
SDI_
150
SDI_
131
SDI_
133
SDI_
135
SDI_
137
SDI_
139
SDI_
141
SDI_
143
SDI_
145
SDI_
147
SDI_
149
SDI_
15
SDI_
152
SDI_
154
SDI_
156
SDI_
158
SDI_
160
SDI_
162
SDI_
164
SDI_
166
SDI_
168
SDI_
170
SDI_
172
SDI_
174
SDI_
176
SDI_
178
SDI_
180
SDI_
18
SDI_
16
SDI_
182
SDI_
184
SDI_
186
SDI_
188
SDI_
190
SDI_
192
SDI_
194
SDI_
196
SDI_
198
SDI_
200
SDI_
151
SDI_
153
SDI_
155
SDI_
157
SDI_
159
SDI_
161
SDI_
163
SDI_
165
SDI_
167
SDI_
169
SDI_
7
SDI_
171
SDI_
173
SDI_
175
SDI_
177
SDI_
179
SDI_
181
SDI_
183
SDI_
185
SDI_
187
SDI_
189
SDI_
19
SDI_
191
SDI_
193
SDI_
195
SDI_
197
SDI_
199
SDI_
2
SDI_
20
SDI_
202
SDI_
204
SDI_
206
SDI_
208
SDI_
210
SDI_
212
SDI_
214
SDI_
216
SDI_
218
SDI_
220
SDI_
222
SDI_
224
SDI_
226
SDI_
228
SDI_
230
SDI_
232
SDI_
234
SDI_
236
SDI_
238
SDI_
240
SDI_
22
SDI_
201
SDI_
21
SDI_
203
SDI_
205
SDI_
207
SDI_
209
SDI_
213
SDI_
215
SDI_
217
SDI_
219
SDI_
221
SDI_
223
SDI_
225
SDI_
227
SDI_
229
SDI_
231
SDI_
233
SDI_
235
SDI_
237
SDI_
239
SDI_
23
SDI_
24
SDI_
242
SDI_
244
SDI_
246
SDI_
248
SDI_
250
SDI_
252
SDI_
254
SDI_
256
SDI_
258
SDI_
260
SDI_
262
SDI_
264
SDI_
266
SDI_
268
SDI_
270
SDI_
272
SDI_
274
SDI_
276
SDI_
278
SDI_
280
SDI_
282
SDI_
284
SDI_
286
SDI_
25
SDI_
26
SDI_
28
SDI_
241
SDI_
243
SDI_
245
SDI_
247
SDI_
249
SDI_
251
SDI_
253
SDI_
257
SDI_
259
SDI_
261
SDI_
263
SDI_
265
SDI_
267
SDI_
269
SDI_
271
SDI_
273
SDI_
275
SDI_
277
SDI_
279
SDI_
281
SDI_
285
SDI_
287
SDI_
27
SDI_
29
SDI_
3
SDI_
9
SDI_
31
SDI_
33
SDI_
35
SDI_
37
SDI_
41
SDI_
43
SDI_
45
SDI_
47
SDI_
49
SDI_
51
SDI_
53
SDI_
55
SDI_
57
SDI_
59
SDI_
61
SDI_
63
SDI_
65
SDI_
67
SDI_
69
SDI_
71
SDI_
73
SDI_
75
SDI_
77
SDI_
79
SDI_
81
SDI_
83
SDI_
85
SDI_
87
SDI_
89
SDI_
91
SDI_
93
SDI_
95
SDI_
97
SDI_
99
SDI_
30
SDI_
4
SDI_
6
SDI_
8
SDI_
32
SDI_
34
SDI_
36
SDI_
38
SDI_
50
SDI_
60
SDI_
70
SDI_
80
SDI_
90
SDI_
42
SDI_
44
SDI_
46
SDI_
48
SDI_
40
SDI_
52
SDI_
54
SDI_
56
SDI_
58
SDI_
62
SDI_
64
SDI_
66
SDI_
68
SDI_
72
SDI_
74
SDI_
76
SDI_
78
SDI_
82
SDI_
84
SDI_
86
SDI_
88
SDI_
92
SDI_
94
SDI_
96
SDI_
98
SDO_
105
SDO_
101
SDO_
102
SDO_
103
SDO_
104
SDO_
106
SDO_
107
SDO_
112
SDO_
109
SDO_
11
SDO_
110
SDO_
111
SDO_
108
SDO_
113
SDO_
114
SDO_
115
SDO_
116
SDO_
117
SDO_
118
SDO_
119
SDO_
12
SDO_
120
SDO_
121
SDO_
122
SDO_
123
SDO_
124
SDO_
125
SDO_
126
SDO_
127
SDO_
128
SDO_
129
SDO_
13
SDO_
130
SDO_
131
SDO_
132
SDO_
133
SDO_
134
SDO_
135
SDO_
136
SDO_
137
SDO_
154
SDO_
139
SDO_
14
SDO_
144
SDO_
141
SDO_
142
SDO_
143
SDO_
140
SDO_
138
SDO_
148
SDO_
145
SDO_
147
SDO_
149
SDO_
15
SDO_
151
SDO_
153
SDO_
155
SDO_
157
SDO_
159
SDO_
146
SDO_
152
SDO_
170
SDO_
160
SDO_
158
SDO_
17
SDO_
19
SDO_
21
SDO_
23
SDO_
25
SDO_
27
SDO_
161
SDO_
163
SDO_
165
SDO_
167
SDO_
169
SDO_
171
SDO_
173
SDO_
175
SDO_
177
SDO_
179
SDO_
156
SDO_
162
SDO_
164
SDO_
166
SDO_
168
SDO_
150
SDO_
176
SDO_
174
SDO_
172
SDO_
194
SDO_
16
SDO_
18
SDO_
181
SDO_
183
SDO_
185
SDO_
187
SDO_
189
SDO_
191
SDO_
193
SDO_
195
SDO_
197
SDO_
199
SDO_
180
SDO_
182
SDO_
184
SDO_
202
SDO_
192
SDO_
222
SDO_
188
SDO_
178
SDO_
196
SDO_
198
SDO_
3
SDO_
5
SDO_
7
SDO_
9
SDO_
2
SDO_
20
SDO_
200
SDO_
201
SDO_
203
SDO_
205
SDO_
207
SDO_
209
SDO_
211
SDO_
213
SDO_
215
SDO_
217
SDO_
219
SDO_
221
SDO_
223
SDO_
225
SDO_
227
SDO_
229
SDO_
218
SDO_
220
SDO_
206
SDO_
208
SDO_
226
SDO_
212
SDO_
230
SDO_
216
SDO_
186
SDO_
224
SDO_
190
SDO_
256
SDO_
214
SDO_
228
SDO_
22
SDO_
231
SDO_
233
SDO_
235
SDO_
237
SDO_
239
SDO_
241
SDO_
243
SDO_
245
SDO_
247
SDO_
249
SDO_
251
SDO_
253
SDO_
255
SDO_
257
SDO_
259
SDO_
246
SDO_
232
SDO_
266
SDO_
204
SDO_
238
SDO_
252
SDO_
210
SDO_
276
SDO_
242
SDO_
248
SDO_
250
SDO_
240
SDO_
254
SDO_
272
SDO_
262
SDO_
24
SDO_
26
SDO_
261
SDO_
263
SDO_
265
SDO_
267
SDO_
269
SDO_
271
SDO_
273
SDO_
275
SDO_
277
SDO_
279
SDO_
281
SDO_
283
SDO_
285
SDO_
287
SDO_
260
SDO_
258
SDO_
264
SDO_
234
SDO_
236
SDO_
270
SDO_
284
SDO_
278
SDO_
244
SDO_
274
SDO_
280
SDO_
286
SDO_
268
SDO_
282
SDO_
28
SDO_
31
SDO_
33
SDO_
35
SDO_
37
SDO_
39
SDO_
41
SDO_
43
SDO_
45
SDO_
47
SDO_
49
SDO_
51
SDO_
53
SDO_
55
SDO_
57
SDO_
59
SDO_
61
SDO_
63
SDO_
65
SDO_
67
SDO_
69
SDO_
71
SDO_
73
SDO_
75
SDO_
77
SDO_
79
SDO_
81
SDO_
83
SDO_
85
SDO_
87
SDO_
89
SDO_
91
SDO_
93
SDO_
95
SDO_
97
SDO_
99
SDO_
34
SDO_
32
SDO_
30
SDO_
36
SDO_
38
SDO_
40
SDO_
42
SDO_
44
SDO_
46
SDO_
48
SDO_
50
SDO_
52
SDO_
54
SDO_
56
SDO_
58
SDO_
60
SDO_
62
SDO_
64
SDO_
66
SDO_
68
SDO_
70
SDO_
72
SDO_
74
SDO_
80
SDO_
78
SDO_
76
SDO_
82
SDO_
84
SDO_
86
SDO_
88
SDO_
90
SDO_
96
SDO_
94
SDO_
92
SDO_
98
SDO_
4
SDO_
6
SDO_
8
AY
BA
BB
BC
BD
BE
BF
BG
BH
BJ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AU
AV
AW
AY
BA
BB
BC
BD
BE
BF
BG
BH
BJ
EXT
_PG1
EXT
_PG1
SDI_
8
EXT
_PG0
SDI_
1
SDI_
5
SDI_
9
SDI_
211
SDI_
211
GND
SDI_
255
SDI_
255
SDI_
287
SDI_
283
SDI_
283
VCC_
25_A
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
VCC_
OUT2
SDO_
29
SDO_
29
VCC_
25_A
VDDIO
_D
VDDIO
_D
VDD
_18
VDDIO
_D
VDDIO
_D
VDDIO
_D
VDDIO
_D
VDDIO
_D
VDDIO
_D
VDDIO
_D
VDDIO
_D
VDDIO
_D
VDDIO
_D
VDD
_18
VDD
_18
VDD
_18
VCC
_IN1
VCC
_IN1
VCC
_IN1
GND
GND
VDDIO
_D
VDD
_18
VCC
_IN1
VCC
_IN1
VCC
_IN1
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
GND
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
GND
VDD
_18
VDD
_18
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VDD
_18
VDD
_18
VCC
_IN1
VCC
_IN1
VCC
_IN1
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A GND
VCC_
25_
REF_
CLK
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC
_IN1
VCC
_IN1
VCC
_IN1
VCC
_IN1
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC
_IN1
VCC
_IN1
VCC
_IN1
VCC
_IN1
VDD
_18
VDD
_18
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VDD
_18
VDD
_18
VCC
_IN2
VCC
_IN2
VCC
_IN2
VCC
_IN2
LF2
GND VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
LF0
GND
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
VCC_
25_A
SDO_
246
EXT
_PG0
RSV
_DNC
MON1
GND GND GND
MON0 MON0
RSV
_DNC
RSV
_DNC
RSV
_DNC
RSV
_DNC
RSV
_DNC
RSV
_DNC
RSV
_DNC
EXT
_CLK1
EXT_
CLK_
DIGITAL
EXT
_CLK2
EXT_
CLK0
Power
Ground
Input
Output
Digital
Control
Legend:
Reserved
22 23 24 25 2627 28 29 3130 32 33 34 35 3637 38 39 40 41 42 43 44 45 4647 48 49
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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1.2 Ball Descriptions
Table 1-1 shows the descriptions for selected GX3290 balls. For a comprehensive list of
balls from the GX3290 Crosspoint family, please refer to GX3290 (and family) Crosspoint
Ball Guide.
Table 1-1: Ball Descriptions
Ball # Ball Name I/O Description
Serial Interface I/O
AN16 SCLK I Serial Host Interface Clock. If unused, tie to ground.
AN17 SDIN I Serial Host Interface Data Input. If unused, tie to ground.
AN18 SDOUT O Serial Host Interface Data Output. Leave NC if not used.
AN19 S_CS ISerial Host Interface Chip Select. Active-LOW. Must be tied LOW when HOST_S/P is
set LOW.
Parallel Interface I/O
AL23 P_CS IParallel host interface chip select. Active-LOW. Must be tied LOW when HOST_S/P is
set HIGH.
AL24 P_R/W ISelects between read and write operations on the parallel host interface.
HIGH = Read, LOW = Write. If unused, tie to ground.
AL25 P_ADSIAddress and Data Strobe. Strobe signal for latching the address and data into the
chip. See Section 4.12.1 for timing information. If unused, tie to ground.
AM27 - AM16 P_ADD[11:0] I Address bus for the parallel interface. If unused, tie to ground.
AN35 - AN20 P_DAT[15:0] I/O Bi-directional data bus for the parallel interface. If P_CS is HIGH, these pins are
configured as inputs. If unused, tie to ground.
General I/O
AN15 HOST_S/P I
Host Interface Select pin. Selects between serial and parallel host interfaces. Serial
host interface is enabled when HIGH, parallel host interface is enabled when LOW.
Must assert RESET after changing this pin.
AM35 - AM28 UPDATE_EN
[7:0] IUpdate Strobes used to update the switch matrix configuration (see Section 4.5). If
unused, weak pull-down to ground.
AR33 POR_DFT I This pin disables the Power On Reset circuitry when HIGH. Weak internal pull-down.
Leave NC if not used.
AR35 RESET IActive-LOW reset for entire chip (see Section 4.11 for timing details). Weak internal
pull-up. Leave NC if not used.
Test Interface
AL17 TCKIJTAG test clock. Weak pull-up if not used.
AL18 TMSIJTAG test mode start. Weak pull-up if not used.
AL19 TDO O JTAG test data out. Leave NC if not used.
AL20 TDI I JTAG test data in. Weak pull-up if not used.
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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Filtering
R17 LDO2 — LDO filter capacitor for VCO_2. Connect through a 220nF capacitor to ground.
See Figure 3-4 for configuration.
R33 LDO0 — LDO filter capacitor for VCO_0. Connect through a 220nF capacitor to ground.
See Figure 3-4 for configuration.
T17 LF2 — PLL loop filter capacitor for VCO_2. See Figure 3-4 for configuration. Leave NC if not
used.
T33 LF0 — PLL loop filter capacitor for VCO_0. See Figure 3-4 for configuration. Leave NC if not
used.
AH17 LF1 — PLL loop filter capacitor for VCO_1. See Figure 3-4 for configuration. Leave NC if not
used.
AH33 LF_DIGITAL — PLL loop filter capacitor for VCO_DIGITAL. Connect through a 47nF capacitor to
ground. See Figure 3-4 for configuration.
AJ17 LDO1 — LDO filter capacitor for VCO_1. Connect through a 220nF capacitor to ground. See
Figure 3-4 for configuration.
AJ33 LDO_DIGITAL — LDO filter capacitor for VCO_DIGITAL. Connect through a 220nF capacitor to
ground. See Figure 3-4 for configuration.
Crystal Oscillator
AE35 REF_CLK_IN — Connect a 27MHz crystal between this ball and REF_CLK_OUT (or connect to a
27MHz clock source). See Section 4.9 and Figure 3-6.
AF35 REF_CLK_OUT — Connect a 27MHz crystal between this ball and REF_CLK_IN (if a clock source is used,
leave floating). See Section 4.9 and Figure 3-6. Leave NC if not used.
External Clocks
R15 EXT_CLK2 I External CML clock for Pattern Generator 1 (true). Leave NC if not used.
R35 EXT_CLK0 I External CML clock for Pattern Checker 0 (true). Leave NC if not used.
T15 EXT_CLK2 IExternal CML clock for Pattern Generator 1 (complement). Leave NC if not used.
T35 EXT_CLK0 IExternal CML clock for Pattern Checker 0 (complement). Leave NC if not used.
AH15 EXT_CLK1 IExternal CML clock for Pattern Checker 1 (complement). Leave NC if not used.
AH35 EXT_CLK
_DIGITAL IExternal CML clock for Pattern Transmitter 0/Digital Core (complement). Leave NC if
not used.
AJ15 EXT_CLK1 I External CML clock for Pattern Checker 1 (true). Leave NC if not used.
AJ35 EXT_CLK
_DIGITAL IExternal CML clock for Pattern Transmitter 0/Digital Core (true). Leave NC if not
used.
BH45 DIGITAL_CL_SEL I
Clock select between external clock source (EXT_CLK_DIGITAL) and internal VCO
(VCO_DIGITAL). This pin has a weak internal pull-up, and should be pulled LOW to
use an external clock.
Table 1-1: Ball Descriptions (Continued)
Ball # Ball Name I/O Description
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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Temperature Sensors
E8 DTHERMA3 — Thermometer 3 diode terminals. See Section 4.8. Leave NC if not used.
F9 DTHERMK3 — Thermometer 3 diode terminals. See Section 4.8. Leave NC if not used.
H45 DTHERMA0 — Thermometer 0 diode terminals. See Section 4.8. Leave NC if not used.
J44 DTHERMK0 — Thermometer 0 diode terminals. See Section 4.8. Leave NC if not used.
BA6 DTHERMK2 — Thermometer 2 diode terminals. See Section 4.8. Leave NC if not used.
BB5 DTHERMA2 — Thermometer 2 diode terminals. See Section 4.8. Leave NC if not used.
BD41 DTHERMK1 — Thermometer 1 diode terminals. See Section 4.8. Leave NC if not used.
BE42 DTHERMA1 — Thermometer 1 diode terminals. See Section 4.8. Leave NC if not used.
Monitors
A44 MON0 OSerial monitoring output 0 (complement). Leave NC if not used.
A45 MON0 O Serial monitoring output 0 (true). Leave NC if not used.
BJ5MON1OSerial monitoring output 1 (true). Leave NC if not used.
BJ6MON1
OSerial monitoring output 1 (complement). Leave NC if not used.
External Pattern Generators
E1 EXT_PG1 I Serial pattern generator input 1 (complement). Leave NC if not used.
F1 EXT_PG1ISerial pattern generator input 1 (true). Leave NC if not used.
BD49 EXT_PG0ISerial pattern generator input 0 (true). Leave NC if not used.
BE49 EXT_PG0ISerial pattern generator input 0 (complement). Leave NC if not used.
Reserved - Do Not Connect
B45, C44, D7,
E2, F3, G46,
AL32, AL33,
AL34, AL35,
AR34, BC4,
BD47, BE48,
BF43, BG6, BH5,
RSV_DNC— Reserved. Do not connect.
SDI/SDO
Refer to the GX3290 (and family) Crosspoint Ball Guide for a detailed list of SDI and SDO balls.
Power
Refer to the GX3290 (and family) Crosspoint Ball Guide for a detailed list of power supply balls.
Ground
Refer to the GX3290 (and family) Crosspoint Ball Guide for a detailed list of ground balls.
Table 1-1: Ball Descriptions (Continued)
Ball # Ball Name I/O Description
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter Value
Supply Voltage (VDD_18) -0.3V to +2.1V
Supply Voltage (VCC_IN1, VCC_IN2, VCC_25_A,
VDD_25, VDDIO_D, VCC_OUT1, VCC_OUT2,
VCC_25_REF_CLK, VCC_25_VCO0, VCC_25_VCO1,
VCC_25_VCO2)
-0.3V to +2.8V
Input Voltage Range
-0.3 to (0.3 + min[VCC_IN1,
VCC_25_A])V
for even numbered SDI inputs and
EXT_PG0
-0.3 to (0.3 + min[VCC_IN2,
VCC_25_A])V
for odd numbered SDI inputs and
EXT_PG1
ESD Voltage (HBM; all balls) 1kV
ESD Voltage (CDM; all balls) 100V
Storage Temperature Range -50ºC to +125ºC
Operating Temperature Range0ºC to +85ºC
Solder Reflow Temperature 245ºC
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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2.2 Recommended Operating Conditions
Table 2-2: Recommended Operating Conditions
Parameter Symbol Min Ty p Max Units Notes
Operating Power Supply
VCC_25_A,
VCC_25_REF_CLK 2.375 2.5 2.625 V 1
VCC_IN1, VCC_IN2
1.14 1.2 1.26 V 2
1.71 1.8 1.89 V 3
2.375 2.5 2.625 V 1
VCC_OUT1,
VCC_OUT2
1.14 1.2 1.26 V 2
1.71 1.8 1.89 V 3
2.375 2.5 2.625 V 1
VDD_18 1.71 1.8 1.89 V 3
VDDIO_D
1.71 1.8 1.89 V 3
2.375 2.5 2.625 V 1
VDD_25 2.375 2.5 2.625 V 1
Operating Temperature Range (case) TOP 02585°C—
Start-up Temperature RangeTSU-40 — 85 °C—
Notes:
1. 2.5V supply.
2. 1.2V supply.
3. 1.8V supply.
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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2.3 DC Electrical Characteristics
Table 2-3: DC Electrical Characteristics
Parameter Symbol Conditions Min Ty p Max Units Notes
System
Power P
All channels active,
VCC_IN[1,2] =
VCC_OUT[1,2] =
1.2V±5%,
ΔVOD = 200mV,
ΔVSDI = 800mVppd,
de-emphasis=6, without
Pattern
Generator/Checker,
AC-coupled
— 34.25 43 W 1
All channels active,
VCC_IN[1,2] =
VCC_OUT[1,2] =
1.2V±5%,
ΔVOD = 400mV,
ΔVSDI = 800mVppd,
de-emphasis=6, without
Pattern
Generator/Checker,
AC-coupled
— 37.66 — W 1
All channels active,
VCC_IN[1,2] =
VCC_OUT[1,2] =
2.5V±5%,
ΔVOD = 800mV,
ΔVSDI = 800mVppd,
de-emphasis=6, without
Pattern
Generator/Checker,
AC-coupled
— 44.39 54 W 1
All channels active,
VCC_IN[1,2] =
VCC_OUT[1,2] =
2.5V±5%,
ΔVOD = 1200mV,
ΔVSDI = 800mVppd,
de-emphasis=6, without
Pattern
Generator/Checker,
AC-coupled
— 49.02 60 W 1
PRBS Generator/Checker — 1.86 — W —
Power in Reset ModePRESET = 0 — 0.5 — W —
Current - VCC_25_A ICC_25_A
With de-emphasis,
without Pattern
Generator/Checker
— 13.8 16.7 A —
Without de-emphasis,
without Pattern
Generator/Checker
—13—A—
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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Current - VCC_IN1 ICC_IN1
All inputs active,
ΔVSDI = 1.2Vppd,
DC-coupled
—1.75— A2
All inputs active,
ΔVSDI = 1.2Vppd,
AC-coupled
-0.2 — 0 A 3
Current - VCC_IN2 ICC_IN2
All inputs active,
ΔVSDI = 1.2Vppd,
DC-coupled
—1.75— A2
All inputs active,
ΔVSDI = 1.2Vppd,
AC-coupled
-0.2 — 0 A 3
Current - VCC_OUT1 ICC_OUT1
VCC_OUT1 = 1.2V ±5%,
all outputs active,
ΔVOD = 200mV, with
De-emphasis
— 0.30 0.38 A 4
VCC_OUT1 = 1.2V ±5%,
all outputs active,
ΔVOD = 400mV, with
De-emphasis
—0.60— A4
VCC_OUT1 = 1.2V ±5%,
all outputs active,
ΔVOD = 800mV, with
De-emphasis
—1.12— A4, 5
VCC_OUT1 = 2.5V ±5%,
all outputs active,
ΔVOD = 200mV, with
De-emphasis
—0.34— A4
VCC_OUT1 = 2.5V ±5%,
all outputs active,
ΔVOD = 400mV, with
De-emphasis
—0.60— A4
VCC_OUT1 = 2.5V ±5%,
all outputs active,
ΔVOD = 800mV, with
De-emphasis
— 1.23 1.55 A 4
VCC_OUT1 = 2.5V ±5%,
all outputs active,
ΔVOD = 1200mV, with
De-emphasis
— 1.64 2.13 A 4
Table 2-3: DC Electrical Characteristics (Continued)
Parameter Symbol Conditions Min Ty p Max Units Notes
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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Current - VCC_OUT2 ICC_OUT2
VCC_OUT2 = 1.2V ±5%,
all outputs active,
ΔVOD = 200mV, with
De-emphasis
— 0.30 0.38 A 4
VCC_OUT2 = 1.2V ±5%,
all outputs active,
ΔVOD = 400mV, with
De-emphasis
—0.60— A4
VCC_OUT2 = 1.2V ±5%,
all outputs active,
ΔVOD = 800mV, with
De-emphasis
—1.12— A4, 5
VCC_OUT2 = 2.5V ±5%,
all outputs active,
ΔVOD = 200mV, with
De-emphasis
—0.34— A4
VCC_OUT2 = 2.5V ±5%,
all outputs active,
ΔVOD = 400mV, with
De-emphasis
—0.60— A4
VCC_OUT2 = 2.5V ±5%,
all outputs active,
ΔVOD = 800mV, with
De-emphasis
— 1.23 1.55 A 4
VCC_OUT2 = 2.5V ±5%,
all outputs active,
ΔVOD = 1200mV, with
De-emphasis
— 1.64 2.13 A 4
Current - VCC_25_REF_CLK ICC_25
_REF_CLK —2040mA—
Current - VCC_VCO_DIGITAL ICC_VCO
_DIGITAL —610mA—
Current - VCC_25_VCO0 ICC_25
_VCO0 —610mA—
Current - VCC_25_VCO1 ICC_25
_VCO1 —610mA—
Current - VCC_25_VCO2 ICC_25
_VCO2 —610mA—
Current - VDD_18 IDD_18 VDD_18 = 1.8V±5% — 260 750 mA —
Current - VDD_25 IDD_25 VDD_25 = 2.5V±5% — 20 40 mA —
Current - VDDIO_D IDDIO_D
VDDIO_D = 1.8V±5%,
all inputs active
(15pF load)
—50100mA—
VDDIO_D = 2.5V±5%,
all inputs active
(15pF load)
—70140mA—
Table 2-3: DC Electrical Characteristics (Continued)
Parameter Symbol Conditions Min Ty p Max Units Notes
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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High-speed Inputs/Outputs
Serial Input Termination
Differential — 100 — Ω
6
Single-ended—50—Ω
Serial Output Termination Differential — 100 — Ω—
Serial Input Common Mode
VoltageVICM
VCC_IN[1,2] = 1.2V±5%,
VCC_IN[1,2] = 1.8V±5%,
VCC_IN[1,2] = 2.5V±5%,
terminated to
VCC_IN[1,2]
VCC_IN
[1,2] -
(ΔVSDI
_max/4)
—
VCC_IN
[1,2] -
(ΔVSDI
_min/4)
V7, 8, 9,
10
Serial Output Common Mode
VoltageVOCM
VCC_OUT[1,2] = 1.2V±5%,
VCC_OUT[1,2] = 1.8V±5%,
VCC_OUT[1,2] = 2.5V±5%
VCC_OUT
[1,2] -
(ΔVOD_
max/4)
—
VCC_OUT
[1,2] -
(ΔVOD_
min/4)
V—
Host Interface
Logic HIGH voltage on digital
input pins VIH 0.7 x
VDDIO_D —VDDIO_D
+ 0.3 V11
Logic LOW voltage on digital
input pins VIL -0.3 — 0.3 x
VDDIO_D V11
Output Logic LOW VOL
IOL = 2mA,
2.5V operation ——0.7V11
IOL = 2mA,
1.8V operation — — 0.45 V 11
Output Logic HIGHVOH
IOH = -2mA,
2.5V operation 1.7 — — V 11
IOH = -2mA,
1.8 operation 1.35 — — V 11
Notes:
1. Total Maximum Power is lower than individual maximum currents multiplied by individual maximum supply voltages because the individual
maximum currents can not occur simultaneously (they occur at different conditions).
2. The ICC_IN1 and ICC_IN2 current flows out of the GX3290 and into the input signal source, and is subject to variability in that source. Some
variability in input signal source current draw should be assumed, and up to ±15% is possible.
3. When the common mode termination points for AC-coupled inputs are connected to VCC_IN1, VCC_IN2, the GX3290 equalizer input bias
currents can lead to current flowing out of the VCC_IN1, VCC_IN2 supply pins.
4. Currents apply for output DC-coupled applications. When AC-coupled, the current draw may be increased by up to 2x.
5. For DC-coupled applications only.
6. Input termination is selectable between 100Ω differential and 50Ω single-ended. See Section 3. Input/Output Equivalent Circuits.
7. DC common mode current into/out of each EQ input differential pair should not exceed 14mA, and the current into/out of each half of the
differential pair should not exceed 14mA.
8. No more than VCC_IN[1,2] - ΔVSDI_actual/4.
9. Where it is understood that VCC_IN[1,2] have a ±5% tolerance.
10.In no case should either side of the input differential pair be allowed to rise above VCC_25_A + 0.3V or fall below -0.3V.
11.Specifications relate to all host interface pins.
Table 2-3: DC Electrical Characteristics (Continued)
Parameter Symbol Conditions Min Ty p Max Units Notes
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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2.4 AC Electrical Characteristics
Table 2-4: AC Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Units Notes
System
Serial Input Data Rate DRSDO ———3.5Gb/s —
Propagation Delay tP———6ns1
Propagation Delay DifferenceΔtPBetween any two
channels ——5.5ns 1
High-speed Inputs/Outputs
Output Switch Time using Update
Enable Strobes 0.9 — 1.8 μs2
Input Voltage SwingΔVSDI — 100 — 1200 mVppd—
Output Voltage SwingΔVOD
VCC_OUT[1,2] = 1.2V±5%,
Output = 200mVppd150 225 300 mVppd—
VCC_OUT[1,2] = 1.2V±5%,
Output = 400mVppd300 450 600 mVppd—
VCC_OUT[1,2] = 1.2V±5%,
Output = 800mVppd600 900 1200 mVppd3
VCC_OUT[1,2] = 1.8V±5%,
Output = 200mVppd150 225 300 mVppd—
VCC_OUT[1,2] = 1.8V±5%,
Output = 400mVppd300 450 600 mVppd—
VCC_OUT[1,2] = 1.8V±5%,
Output = 800mVppd600 900 1200 mVppd—
VCC_OUT[1,2] = 2.5V±5%,
Output = 200mVppd150 225 300 mVppd—
VCC_OUT[1,2] = 2.5V±5%,
Output = 400mVppd300 450 600 mVppd—
VCC_OUT[1,2] = 2.5V±5%,
Output = 800mVppd600 900 1200 mVppd—
VCC_OUT[1,2] = 2.5V±5%,
Output = 1200mVppd1000 1350 1700 mVppd—
Output Rise/Fall Time tr/tfAll output swings.
20% to 80%. — — 150 ps —
Duty Cycle Distortion All data rates, all output
swings. -50 — +50 ps —
Additive Jitter All inputs active,
peak-to-peak (PRBS 31) ——60
psp-p —
Input Trace Equalization 0 — 12 dB4
Output De-Emphasis Setting
Range 0 — 11.2 dB
4
Maximum Setting9——dB
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Host Interface
Parallel Rate of Operation 0.1 — 112.5 Mop/s 5, 6, 7
Serial Interface Operating Speed0.1 — 25 MHz 5, 8
Notes:
1. See Section 4.4 for more details.
2. This parameter is the time it takes for the outputs to change to a new switch matrix configuration when the corresponding strobe signal
assigned to that output is asserted.
3. DC-coupled.
4. Selectable, maximum gain occurs at 3Gb/s (or 1.5GHz).
5. Specifications relate to all host interface pins.
6. Millions of operations per second.
7. For detailed timing specifications, see Section 4.12.1.
8. For detailed timing specifications, see Section 4.12.2.
Table 2-4: AC Electrical Characteristics (Continued)
Parameter Symbol Conditions Min Typ Max Units Notes
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3. Input/Output Equivalent Circuits
Note: Please refer to the following supplementary documents: Crosspoint Design Guide
and EB-GX3290 Schematics, PCB Layout and Bill of Materials.
Figure 3-1: Equalizer Input Equivalent Circuit
Figure 3-2: Trace Driver Output Equivalent Circuit
Note: the MON0 and MON1 outputs are terminated to the VCC_25_A supply.
VCC_IN[1,2]
VCC_25_A
SDI[0:287]
50Ω
50Ω
EQ_TERMINATION[287:0]
HIZ_ACCM
HIZ_ACCM
SDI[0:287]
VCC_25_A
VCC_OUT[1,2]50Ω50Ω
VCC_OUT[1,2]
VCC_OUT[1,2]
MainDelayed
SDO[0:287]
SDO[0:287]
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Figure 3-3: External Clock Input Equivalent Circuit
Figure 3-4: Required connections for VCC_VCO_DIGITAL, VCC_25_VCO0, VCC_25_VCO1, VCC_25_VCO2,
LF_DIGITAL, LF0, LF1, LF2, LDO_DIGITAL, LDO0, LDO1 and LDO2
VCC_25_A
ext_ref_clk
50Ω
50Ω
ext_ref_clk
VCC_25_A
VCC_25_A
VCC_VCO_DIGITAL
10nF 1µF 10µF
267Ω
VCC_25_A
10nF 1µF 10µF
267Ω
VCC_VCO_DIGITAL
VCC_25_VCO0
VCC_25_VCO1
VCC_25_VCO2
47nF
LF_DIGITAL
0Ω
220nF
LDO_DIGITAL
47nF
LF0
LF1
220nF
LDO_DIGITAL
LDO0
LDO1
LDO2
47nF
LF_DIGITAL
LF2
0Ω
VCC_25_VCO0
VCC_25_VCO1
VCC_25_VCO2
LF0
LF1
LF2
220nF
LDO0
LDO1
LDO2
Note 1: Each of the VCC_VCO_DIGITAL, VCC_VCO0, VCC_VCO1, and VCC_VCO2 pins require an independent RC network.
Note 2: The LF_DIGITAL and LF2 pins each require an independent RC network.
Note 3: The LF0 and LF1 pins each require an independent capacitor to ground.
Note 4: Each of the LDO_DIGITAL, LDO0, LDO1, and LDO2 pins require an independent capacitor to ground.
Note 5: VCC_VCO_DIGITAL, LF_DIGITAL and LDO_DIGITAL used for pattern generator TX0, digital communication (GSPI and APPI), and the internal
temperature ADC for JNCTN_TEMP_1. VCC_VCO_DIGITAL, LF_DIGITAL and LDO_DIGITAL must always be connected.
Note 6: VCC_25_VCO0, LF0, LDO0 used for pattern checker RX0 and the internal temperature ADC for JNCTN_TEMP_0.
If VCC_25_VCO0, LF0, and LDO0 are not connected, pattern checker RX0 and the internal temperature ADC for JNCTN_TEMP_0 will not operate.
Note 7: VCC_25_VCO1, LF1, LDO1 used for pattern checker RX1 and the internal temperature ADC for JNCTN_TEMP_2.
If VCC_25_VCO1, LF1, and LDO1 are not connected, pattern checker RX1 and the internal temperature ADC for JNCTN_TEMP_2 will not operate.
Note 8: VCC_25_VCO2, LF2, LDO2 used for pattern generator TX1 and the internal temperature ADC for JNCTN_TEMP_3.
If VCC_25_VCO2, LF2, and LDO2 are not connected, pattern generator TX1 and the internal temperature ADC for JNCTN_TEMP_3 will not operate.
If the internal temperature ADCs, pattern generators, and
checkers are used, these connections are required.
If the internal temperature ADCs, pattern generators, and
checkers are not used, only these connections are required.
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Figure 3-5: PRBS Generator/Checker Clock Selection
Figure 3-6: Crystal Oscillator
REF_CLK_IN
REF_CLK_OUT
XTAL
OSC. CMU
/2
EXT_CLK_DIGITAL
EXT_CLK_DIGITAL
DIGITAL_CL_SEL
0
1
Pattern
TX0
REF_CLK_IN
REF_CLK_OUT
CMU
/2
EXT_CLK0
EXT_CLK0
0
1
Pattern
RX0
CMU
/2 0
1
CMU
/2 0
1
Note: The clock used to drive Pattern Generator TX0 is also used to derive
the clock timing for the digital core. Therefore, GSPI/APPI interface timing
and update timing will track the external clock frequency if one is selected
from the EXT_CLK_DIGITAL/EXT_CLK_DIGITAL pins for Pattern Generator TX0.
XTAL
OSC.
REF_CLK_IN
REF_CLK_OUT
EXT_CLK1
EXT_CLK1
REF_CLK_IN
REF_CLK_OUT
EXT_CLK2
EXT_CLK2
XTAL
OSC.
XTAL
OSC.
Pattern
RX1
Pattern
TX1
BIST_RX_5 0x83C b4
BIST_RX_5 0x83C b6
BIST_TX_0 0x823 b0
REF_CLK_IN
REF_CLK_OUT
1MΩ27MHz
C2
C1
REF_CLK_IN
REF_CLK_OUT
27MHz Oscillator
Using a crystal Using a single-ended 27MHz oscillator
Note: The value of the C1 and C2 load capacitors are
dependent on the chosen crystal.
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4. Detailed Description
4.1 Serial Data Input
Each of the GX3290 SDI inputs provide on-chip 100Ω differential terminations (or 50Ω
single-ended). Each is compatible with input differential amplitudes from 100mVppd to
1200mVppd, and input signal sources having CML outputs referred to DC supplies of
1.2V, 1.8V or 2.5V. Note that for AC-coupled inputs, the recommended supply voltage
for VCC_IN1 and VCC_IN2 is 1.8V.
Each of the 290 SDI input channels include frequency domain equalization,
independently-programmable to one of four levels, to compensate from 0 to 47 inches
(119 cm) of FR4 trace at 3Gb/s. The boost at the 1.5GHz Nyquist frequency, and
recommended trace length range, are shown under EQ_BOOST[287:0],
EXT_PG0_EQ_BOOST, EXT_PG1_EQ_BOOST in Table 4-1. See Figure 3-1.
Each input can be powered-down independently using the corresponding
EQ_POWERDOWN[287:0] or EXT_PG0_EQ_POWERDOWN or
EXT_PG1_EQ_POWERDOWN bit.
To accommodate input signal sources with 1.2V supplies and 1200mVppd signal
amplitudes, the input common mode point should be terminated to the respective
VCC_IN1 or VCC_IN2 supply.
The common mode termination connection to the respective VCC_IN1 or VCC_IN2
supply of each input can be independently controlled using the
EQ_TERMINATION[287:0] or EXT_PG0_EQ_TERMINATION or
EXT_PG1_EQ_TERMINATION bit (see Figure 3-1 and Table 4-1).
Note 1: When the HIZ_ACCM bit is set (register address 0x400h bit 0), inputs with their
common mode termination not connected to VCC_IN1 or VCC_IN2 are connected to an
internal common mode bias.
When an input EQ is powered-down, its common mode termination is automatically
disconnected from the corresponding VCC_IN1 or VCC_IN2.
For each of the inputs, there are control parameters (register address 0x401h to
0x522h). See Table 4-1 below.
Note 2: The EXT_PG01_SOURCE_PIN_PRBSB and EXT_PG1_SOURCE_PIN_PRBSB
bits in the TEST_SETUP register must be set to connect the EXT_PG0 and EXT_PG1 pins
to the matrix.
Table 4-1: Serial Data Input
EQ_BOOST[287:0],
EXT_PG0_EQ_BOOST and
EXT_PG1_EQ_BOOST bits 1:0
(binary)
Boost Applied (@ nominal 1.5GHz)
00 0dB boost 0” to 6” (15 cm) trace
01 3.5dB boost 6” (15 cm) to 16”
(40 cm) trace
10 7.6dB boost 16” (40 cm) to 35”
(89 cm) trace
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4.2 Serial Data Output
Each of the GX3290 SDI outputs have two on-chip 50Ω single-ended terminations, and
can be programmed to output differential amplitudes of 200mVppd, 400mVppd or
800mVppd when the corresponding VCC_OUT1 or VCC_OUT2 is connected to either
1.2V or 1.8V, or 200mVppd, 400mVppd, 800mVppd, or 1200mVppd when the
corresponding VCC_OUT1 or VCC_OUT2 is connected to 2.5V. The selection of the
output swing is made using the corresponding OUTPUT_SWING_SET[287:0],
MON0_OUTPUT_SWING_SET or MON1_OUTPUT_SWING_SET bits, shown in
Table 4-3.
If the HIGH_OP_V bit is set when either the VCC_OUT1 or VCC_OUT2 supplies are 1.2V
or 1.8V, the 800mVppd swing setting is no longer valid for that output bank. Swing
settings for an output bank connected to a 2.5V supply are unaffected.
11 12dB boost 35” (89 cm) to 47”
(119 cm) trace
EQ_TERMINATION[287:0],
EXT_PG0_EQ_TERMINATION
and
EXT_PG1_EQ_TERMINATION
bits 3:3
Input Termination Common Mode Point Switch to
VCC_IN_1, VCC_IN_2
0Open (see Figure 3-1)
1Closed (see Figure 3-1)
EQ_POWERDOWN[287:0],
EXT_PG0_EQ_POWERDOWN
and
EXT_PG1_EQ_POWERDOWN
bits 4:4
Equalizer Power
0On
1Off
Table 4-1: Serial Data Input (Continued)
EQ_BOOST[287:0],
EXT_PG0_EQ_BOOST and
EXT_PG1_EQ_BOOST bits 1:0
(binary)
Boost Applied (@ nominal 1.5GHz)
Table 4-2: HIGH_OP_V Swing Selection
HIGH_OP_V = 0 HIGH_OP_V = 1
Note
VCC_OUTx
Supply Voltage
(V)
Valid Output Swing
Selection
(mVppd)
Valid Output Swing
Selection
(mVppd)
1.2 200, 400, 800 200, 400 1
1.8 200, 400, 800 200, 400 —
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Each of the 290 SDI output channels provide independently programmable
de-emphasis, to compensate from 0 to 47 inches (119 cm) of FR4 trace at 3Gb/s. The
selection of the amount of output de-emphasis is made using the corresponding
OUTPUT_DEEMPHASIS[287:0], MON0_OUTPUT_DEEMPHASIS or
MON1_OUTPUT_DEEMPHASIS bits, shown in Table 4-3.
Each output can be independently powered-down by the setting of the corresponding
bit: ACTIVE_POWER_DOWN[287:0], DYNAMIC_POWER_DOWN[287:0] together
with the assigned strobe, MON0_POWER_DOWN, or MON1_POWER_DOWN.
The polarity of the signal at each output can be independently inverted by setting the
corresponding bit: ACTIVE_SIGNAL_INVERT[287:0],
DYNAMIC_SIGNAL_INVERT[287:0] together with the assigned strobe,
MON0_SIGNAL_INVERT, or MON1_SIGNAL_INVERT.
2.5 200, 400, 800 200, 400, 800, 1200 2
Notes:
1. For an 800mVppd output swing when the corresponding VCC_OUT1 or VCC_OUT2 is connected to 1.2V, the
output must be DC-coupled to a receiving device terminated to 1.2V.
2. When VCC_OUT1 or VCC_OUT2 is set to 2.5V, the HIGH_OP_V bit must be set to enable 1200mVppd swing
selection.
Table 4-2: HIGH_OP_V Swing Selection (Continued)
HIGH_OP_V = 0 HIGH_OP_V = 1
Note
VCC_OUTx
Supply Voltage
(V)
Valid Output Swing
Selection
(mVppd)
Valid Output Swing
Selection
(mVppd)
Table 4-3: Serial Data Output
OUTPUT_SWING_SET[287:0],
MON0_OUTPUT_SWING_SET and
MON1_OUTPUT_SWING_SET bits 2:0 (binary)
Output Swing
000 200mVppd
001 400mVppd
011 800mVppd
110 1200mVppd
111 Reserved. Do not use.
OUTPUT_DEEMPHASIS[287:0],
MON0_OUTPUT_DEEMPHASIS and
MON1_OUTPUT_DEEMPHASIS bits 5:3 (binary)
Level of De-emphasis
000 Off
100 12” (30 cm) nominal
101 24” (60 cm) nominal
110 36” (90 cm) nominal
111 48” (120 cm) nominal
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4.3 Crosspoint Switch Matrix Operation
The crosspoint switch matrix routes the serial digital input signals
(SDI[0:287]/SDI[0:287], EXT_PG0/EXT_PG0 or EXT_PG1/EXT_PG1) to one or more serial
digital outputs (SDO[0:287]/SDO[0:287], MON0/MON0 or MON1/MON1). The matrix is
configured on a per output basis. Each serial digital output can be configured to accept
a signal from one serial digital input. Multiple serial digital outputs can accept input
from the same serial digital input.
Updates to the switch matrix take place as soon as they are written to the host interface
when controlling the device through the ACTIVE Configuration and Status Registers.
These registers are the ACTIVE[287:0], MON0, and MON1 registers found in Section 2
of the Crosspoint (GX3290 and family) Reference Manual (for CSRs) document.
Before the ACTIVE[287:0], MON0, and MON1 registers at addresses 0x200h through
0x321h can be directly used to update the crosspoint switch matrix, an initialization
procedure is required. One of the UPDATE_EN[7:0] pins needs be toggled from a low
state to a high state, and back to a low state again.
Alternatively, set the SOFTWARE_UPDATE_ENABLE bit in the CONTROL_SETUP
register at address 0xA00h to a value of 1, and then toggle one of the
SOFT_UPDATE_EN[7:0] bits in the SOFT_UPDATE_CONTROL register at address
0xA01h from a value of 0 to a value of 1, and then back to a value of 0.
If the ACTIVE[287:0], MON0, and MON1 registers are not being directly written by the
system controller, this procedure is not required. Reading from the ACTIVE[287:0],
MON0, and MON1 registers will work regardless of whether or not the above
procedure is executed.
Updating the crosspoint switch matrix using the DYNAMIC[287:0] registers (discussed
below) does not require the initialization procedure described above.
The switch matrix can also be updated using double-buffering when controlling the
device through the DYNAMIC Configuration and Status Registers. These registers are
DYNAMIC[287:0] in Section 1 of the Crosspoint (GX3290 and family) Reference
Manual (for CSRs) document.
ACTIVE_SIGNAL_INVERT[287:0],
DYNAMIC_SIGNAL_INVERT[287:0],
MON0_SIGNAL_INVERT or MON1_SIGNAL_INVERT
Status
0 Not inverted
1 Inverted
ACTIVE_POWER_DOWN[287:0],
DYNAMIC_POWER_DOWN[287:0], MON0_POWER_DOWN
or MON1_POWER_DOWN
Status
0On
1Off
Table 4-3: Serial Data Output (Continued)
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When using dynamic configuration, updates to the switch matrix are first written to the
DYNAMIC[287:0] registers where they are held until the corresponding update strobe
signal, selected using the UPDATE_SELECT[287:0] bits in the DYNAMIC[287:0]
registers, changes state from LOW-to-HIGH.
The source for the update strobes can either be via external pins (UPDATE_EN[7:0]) or
register bits (SOFT_UPDATE_EN[7:0]) as selected by the setting of the
SOFTWARE_UPDATE_ENABLE bit in the CONTROL_SETUP register. Setting the
SOFTWARE_UPDATE_ENABLE bit LOW causes the device to use the external
UPDATE_EN[7:0] pins as update strobes for the switch matrix. Setting the
SOFTWARE_UPDATE_ENABLE bit HIGH causes the device to use the
SOFT_UPDATE_EN[7:0] bits as update strobes for the switch matrix. See Section 6 of
the Crosspoint (GX3290 and family) Reference Manual (for CSRs) document.
When the selected update strobe signal (or bit) transitions from LOW-to-HIGH, the state
of all the outputs configured to respond to that update strobe signal (or bit) are updated
at that time.
Regardless of which register set is used to configure the switch matrix, the current
configuration of the matrix is always available by reading back the ACTIVE[287:0]
registers.
Note: The MON0 and MON1 outputs can not be powered up/down, switched, or
polarity inverted dynamically (Dynamic Configuration). They can only be configured in
the Active Configuration mode described above using the settings in registers 0x320h
and 0x321h, respectively. Also, the MON0 and MON1 outputs are terminated to the
VCC_25_A supply.
4.4 Propagation Delay
The propagation delay is dependent on the path that the signal takes through the device.
Although the delay difference from the shortest path to the longest path could be up to
5.5ns, this difference is at a minimum for connections from inputs numerically close
together and on the same side of the device to outputs that are numerically close
together and on the same side of the device. Propagation delay differences of less than
750ps can be expected when the inputs are adjacent in the ballout and the outputs are
also adjacent in the ballout.
Note: The 750ps propagation delay difference (skew) between physically adjacent
channels is guaranteed by simulation.
4.5 Using Multiple Strobes
The GX3290 has eight fully-independent update strobes.
Outputs 287 to 0 can be assigned to one of the eight strobes through the setting of the
UPDATE_SELECT bits in the corresponding DYNAMIC[287:0] register. The input
signal selection, output power switching and signal inversion will take effect on the
LOW-to-HIGH edge of its assigned strobe signal or bit. This allows different portions of
the crosspoint to be switched at different points in time. This is particularly useful in
systems supporting multiple data or video formats, where the switch point/time varies
from format to format.
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4.6 Pattern Generator and Pattern Checker
4.6.1 Pattern Generator
Note 1: There are two pattern generator “Tx” blocks in the GX3290. In the following,
wherever only TX0 is mentioned, the corresponding is also true for TX1.
Note 2: When the PRBS Generator is disabled, the generated signal does not completely
terminate. The PRBS polynomial bits must be re-written in order to terminate the signal.
The two pattern generator “Tx” blocks in the GX3290 can each independently generate
PRBS 27-1, PRBS 215-1, and PRBS 223-1 data patterns, or alternating 1's and 0's. The
built-in clock multiplier PLLs independently synthesize rates of 270Mb/s and 2.97Gb/s
from the required, external 27MHz reference clock (see Section 4.9). Other rates up to
3Gb/s can be generated by providing an external clock signal at 2x, 4x, or 22x the
desired bit rate to TX1, with a maximum external clock frequency of 6GHz.
While this facility exists for both TX0 and TX1, the user is cautioned that the digital core
clock is derived from the TX0 data clock, and therefore interface and update timing will
track the external clock frequency if one is provided to TX0.
The pattern generators are enabled by the TX0_PRBS_GEN_ENABLE and
TX1_PRBS_GEN_ENABLE bits (register address 0x802h, bits [1:0] respectively).
The PRBS generating polynomials used are:
1. PRBS7: x7 + x6 + 1
2. PRBS15: x15 + x14 + 1
3. PRBS23: x23 + x18 + 1
The pattern generated is selected via the TX0_PRBS_POLYNOMIAL and
TX1_PRBS_POLYNOMIAL bits (register address 0x800h and 0x801h respectively).
Table 4-4: Tx External Clocks
TX0 TX1
EXT_CLK_DIGITAL (AJ35) EXT_CLK2 (R15)
EXT_CLK_DIGITAL (AH35) EXT_CLK2 (T15)
Table 4-5: Generated Patterns
TX0_PRBS_POLYNOMIAL[1:0] (binary) Pattern Generated
00 PRBS7
01 PRBS15
10 PRBS23
11 Square Wave
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4.6.2 Pattern Checker
The pattern checkers de-serialize incoming serial data before checking for errors in the
parallel domain. Three comparison modes are supported:
1. Neutral Phase Comparison Mode. The incoming data is re-timed in a CDR, and
sampled at the neutral (eye center) phase recovered by the CDR before
de-serialization. Errors with respect to the supported PRBS sequences can be
counted.
2. Offset Phase Comparison Mode. The phase at which the incoming data is
sampled with respect to the recovered clock is adjustable over a full UI. Errors with
respect to the supported PRBS sequences can be counted. By sweeping the
sampling phase and counting errors at each phase, an error rate “bathtub curve”
can be recorded, and the horizontal eye opening evaluated.
3. Arbitrary Data Comparison Mode. This mode can operate on arbitrary data
patterns. The incoming serial data is sampled at both the neutral phase and the
adjustable phase, and each of the two sampled data streams is de-serialized and the
two streams are compared in the parallel domain.
The pattern checker allows a true measurement of bit error rate for the supported PRBS
sequences in the first two modes above. The third, arbitrary data comparison mode,
gives an indication of the degree of eye closure at a given sampling phase offset, but
cannot detect bit errors in the incident data. See Figure 4-1 and Figure 4-2 below.
Figure 4-1: Simplified Pattern Generator/Checker Zero Block Diagram
/2 /11
CMU
xtal osc.
Serializer/
Pattern
Generator
Neutral
Phase
Deserializer
CDR
Variable
Phase
Deserializer
Pattern Checker
27MHz
Crosspoint Core
(290 x 290)
EXT_CLK_DIGITAL
REF_CLK_IN
Pattern
Generator 0 Pattern
Checker 0
/2 /2
REF_CLK_OUT
EXT_CLK0
MON0/MON0
EXT_PG0/EXT_PG0
EXT_CLK_DIGITAL
EXT_CLK0
Input 288 Output 288
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Figure 4-2: Simplified Pattern Generator/Checker One Block Diagram
Note 1: There are two pattern checker “Rx” blocks in the GX3290. In the following,
wherever only RX0 is mentioned, the corresponding is also true for RX1.
The CDR integrated in each Rx block can independently lock to data at rates of 270Mb/s,
1.485Gb/s and 2.97Gb/s. Other rates up to 3Gb/s can be analyzed by providing an
external clock signal of 2x, 4x, or 22x the desired bit rate, with a maximum external
clock frequency of 6GHz. Note that retiming is not possible when using an external
clock signal for the Rx block. The external clock must be synchronous with any data to
be checked and the RX0_PRBS_CHK_MODE bits must be set to a value of '01'. The two
pattern checker “Rx” blocks in the GX3290 can each independently check PRBS 27-1,
PRBS 215-1, and PRBS 223-1 data patterns.
The error checking modes are selected by the RX0_PRBS_CHK_MODE bits and the
RX1_PRBS_CHK_MODE bits (addresses 0x804h and 0x810h respectively).
Table 4-6: Rx External Clocks
RX0 RX1
EXT_CLK0 (R35) EXT_CLK1 (AJ15)
EXT_CLK0 (T35) EXT_CLK1 (AH15)
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The pattern checker will check for the PRBS pattern specified by the
RX0_PRBS_POLYNOMIAL and RX1_PRBS_POLYNOMIAL bits (addresses 0x803h
and 0x811h respectively).
The PRBS checkers are enabled by the RX0_PRBS_ENABLE and RX1_PRBS_ENABLE
bits (register address 0x81Dh[1:0]).
The incident data can be inverted before checking by setting the corresponding
RX0_INVERT_PRBS_IN or RX1_INVERT_PRBS_IN bit (address 0x803h[2:2] and
0x811h[2:2]) to '1'.
The number of words to be compared is selectable via the corresponding
RX0_PRBS_BER_TIME and RX1_PRBS_BER_TIME bits (registers 0x80Ah and
0x817h).
Table 4-7: Checking Modes
RX0_PRBS_CHK_MODE[1:0] (binary) Input Mode
00 Check data sampled at neutral phase
01 Check data sampled at adjustable phase
10 or 11
Compare nominally sampled data with phase
offset data (allows eye monitoring of
arbitrary patterns)
Table 4-8: Checked Patterns
RX0_PRBS_POLYNOMIAL[1:0] (binary) Pattern Checked
00 PRBS7
01 PRBS15
10 PRBS23
Table 4-9: Compared Words
RX0_PRBS_BER_TIME[3:0] (binary) Number of words* compared (decimal)
0000 Infinite
0001 13
0010 26
0011 3277
0100 6554
0101 838861
0110 1677722
*Note: Each word is comprised of 10 bits, therefore the actual number of samples compared is
10 times the number of words compared.
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The status of the two pattern checking blocks is available in the RX0_PRBS_LOCK and
RX1_PRBS_LOCK, RX0_PRBS_PASS and RX1_PRBS_PASS, RX0_PRBS_FAIL and
RX1_PRBS_FAIL, and RX0_PRBS_ERROR_COUNT and RX1_PRBS_ERROR_COUNT
read-only bits (see register addresses 0x81Eh to 0x821h).
•RX0_PRBS_LOCK [0] - When HIGH, indicates that the pattern checker has
acquired the pattern
•RX0_PRBS_PASS [1] - When HIGH, indicates that the pattern was locked, and the
specified number of words have been compared with fewer detected errors than
specified by the RX0_PRBS_BER_THRESH parameter
•RX0_PRBS_FAIL [2] - Indicates that the test terminated in a failure condition.
There are three possible failure conditions:
1. The pattern generator failed to lock in the number of attempts specified by
RX0_PRBS_LOCK_ATTEMPTS (in which case RX0_PRBS_LOCK would still be
'0').
2. The pattern generator locked, but over the period of time indicated by the
RX0_PRBS_LOL_TIME bits, a greater number of errors were detected than
allowed by the RX0_PRBS_LOL_THRESH setting. In this error condition, the
device determines that it has “lost lock“, and terminates the test. This error
condition is detectable if both RX0_PRBS_LOCK and RX0_PRBS_FAIL bits are
HIGH, and the value of RX0_PRBS_ERROR_COUNT is less than
RX0_PRBS_BER_THRESH (the same applies for RX1_PRBS_LOCK,
RX1_PRBS_FAIL and RX1_PRBS_ERROR_COUNT).
3. The pattern generator locked, but the number of errors observed exceeded the
value indicated by the RX0_PRBS_BER_THRESH bits. This error is detectable if
RX0_PRBS_LOCK and RX0_PRBS_FAIL are both HIGH, and the value of
RX0_PRBS_ERROR_COUNT is equal or greater than the value in
RX0_PRBS_BER_THRESH.
Note that the values of RX0_PRBS_LOCK and RX1_PRBS_LOCK, RX0_PRBS_PASS
and RX1_PRBS_PASS, RX0_PRBS_FAIL and RX1_PRBS_FAIL,
RX0_PRBS_ERROR_COUNT and RX1_PRBS_ERROR_COUNT are reset whenever
any of the corresponding test parameters for the RX0 and RX1 pattern checkers are
updated as well as whenever the corresponding RX0_PRBS_ENABLE or
RX1_PRBS_ENABLE bits are set to '1' when previously set to '0'. To start a new PRBS test
when the previous one has already been run, either re-write
RX0_PRBS_BER_TIME/RX1_PRBS_BER_TIME or toggle
RX0_PRBS_ENABLE/RX1_PRBS_ENABLE.
Note 2: The pattern checkers will count zero errors if the incident data is simply a static
zero.
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4.7 Horizontal Eye Measurement
As explained above, the GX3290 enables the measurement of bit error “bathtub” curves
at the video rates of 1485Mb/s and 2970Mb/s to assist in evaluating how much margin
there is in the system.
See Using the Monitoring Features of the GX3290 Application Note for more
information.
4.7.1 Configuration for Horizontal Eye Measurement
• Route the input signal of interest to the MON0 or MON1 of the matrix
• Route the monitor output of matrix to pattern checker Rx, (RX0 in the notes below)
by changing the RX0_CHECK_KEY_D2A word from its default value of 512
(decimal) to 288 (decimal)
• For a PRBS pattern, select a pattern length with a value of the
RX0_PRBS_POLYNOMIAL bits set to match the source pattern, and set the
RX0_PRBS_CHK_MODE bits to 1 to select the phase interpolator path
• For an arbitrary pattern, set the RX0_PRBS_CHK_MODE bits to 2 to select the
direct data comparison mode
• Set initial sampling phase with the
RX0_PHASE_INTERPOLATOR_PHASE_SEL_D2A bits (in the BIST_RX_4 register)
• Initiate error counting as described in Section 4.6.2 above
• Increment the sampling phase
•Count errors
• Repeat last two steps to cover one UI
4.8 Temperature Sensors
The GX3290 has twelve on-chip temperature sensors comprised of four junction diode
temperature sensors and four ADCs, each with two selectable temperature sensors.
Analog output voltages can be used to determine the temperature of the chip at the
junction diode temperature sensors in four different locations. An external test current
is applied to each sensor, and the voltage across the sensor is measured.
Note that the “A” and “K” of the pin names indicate the preferred direction of the test
current, but other junctions are present internally. Test currents should be limited to
10mA or less.
Figure 4-3: Temperature Sensors
DTHERMA[3:0]
DTHERMK[3:0]
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In addition to the diode temperature sensors, four ADCs, each with two selectable
temperature sensors, are also provided. Digitized temperatures can be read through the
device’s host interface.
Figure 4-4: Map of Thermometer ADC Positions on Die
Digitized 10-bit temperature values can be read through the host interface from
registers JNCTN_TEMP_0 (register 0xA08h[9:0]) through JNCTN_TEMP_3 (register
0xA0Bh[9:0]). The temperature word in each register will be updated every 213 clock
cycles, provided the value of the respective COUNT_PD_[3:0] bit remains LOW. When
a COUNT_PD_[3:0] bit goes HIGH, the ADC is reset and the corresponding
JNCTN_TEMP_[3:0] register retains its last updated value. The clock rate can be
selected between 211kHz or 844kHz through the corresponding
ADC_CTRL_CLK_SEL_[3:0] bits (registers 0xA04h, 0xA05h, 0xA06h and 0xA07h).
The junction temperature at each temperature sensor in terms of the ADC output code
is given by:
Where δ3 is the temperature uncertainty. The accuracy of the temperature sensors can
be improved by calibrating the GX3290 at a known junction temperature. Without
calibration, the temperature uncertainty, due to process variations and component
mismatch, can be as high as ±27°C. After calibration, the uncertainty can be reduced to
about ±2°C.
Crosspoint Core
Even Outputs 0 to 288
Odd Outputs 1 to 289
Odd Inputs 1 to 289
Package Top-view of Die
thermo
ADC 1
Even Inputs 0 to 288
Legend:
“remote” temperature sensors
ADC and “local” temperature sensors
thermo
ADC 2
thermo
ADC 0
thermo
ADC 3
Table 4-10: Junction Temperature Registers
Thermometer ADC Sensor Location Select
Register Result Register
0ADC_IN_0 JNCTN_TEMP_0
1ADC_IN_1 JNCTN_TEMP_1
2ADC_IN_2 JNCTN_TEMP_2
3ADC_IN_3 JNCTN_TEMP_3
Tj0.5489 JNCTN_TEMP_[3:0]×263–δ3
+=
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See Using the Monitoring Features of the GX3290 Application Note for more
information.
Table 4-11: Nominal Temperature-to-Code Conversion
Tj (°C) JNCTN_TEMP_
[3:0] Tj (°C) JNCTN_TEMP_
[3:0] Tj (°C) JNCTN_TEMP_
[3:0] Tj (°C) JNCTN_TEMP_
[3:0]
-40 406 2 483 44 559 86 636
-38 410 4 486 46 563 88 639
-36 414 6 490 48 567 90 643
-34 417 8 494 50 570 92 647
-32 421 10 497 52 574 94 650
-30 424 12 501 54 578 96 654
-28 428 14 505 56 581 98 658
-26 432 16 508 58 585 100 661
-24 435 18 512 60 588 102 665
-22 439 20 516 62 592 104 669
-20 443 22 519 64 596 106 672
-18 446 24 523 66 599 108 676
-16 450 26 527 68 603 110 680
-14 454 28 530 70 607 112 683
-12 457 30 534 72 610 114 687
-10 461 32 538 74 614 116 690
-8 465 34 541 76 618 118 694
-6 468 36 545 78 621 120 698
-4 472 38 548 80 625 122 701
-2 475 40 552 82 629 124 705
0 479 42 556 84 632 126 709
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4.9 27MHz Reference Clock
The GX3290 requires an external 27MHz reference clock for correct operation. This
clock is multiplied to generate the digital core and interface clocks, and is also used to
synthesize video rate clocks in the pattern generation blocks, and to acquire video rate
signals in the pattern checker blocks. The reference clock has no impact on the jitter
measurement performance when the pattern checker blocks are locked to external data
sources, but has a direct impact on jitter performance within the loop bandwidth of the
CMU PLL in the pattern generation blocks.
The 27MHz reference clock can be generated by connecting a crystal between the
REF_CLK_IN and REF_CLK_OUT balls, along with appropriate loading capacitors and a
feedback resistor (see Figure 3-6). Alternatively, an LVCMOS 27MHz external clock
source can be connected to the REF_CLK_IN ball with the REF_CLK_OUT ball left
floating. The frequency variation of the crystal (including aging, supply and
temperature variation) should be less than +/-100ppm if the PRBS checking and
generation features are to be used in video applications.
4.10 Device Power-Up
Note 1: No power supply sequencing is required (see Section 4.11).
There is a 50μs delay (tidle) between the power supplies reaching their nominal value
and the device becoming operational. During this time, there should be no host interface
activity, and the UPDATE_EN[7:0] pins must be held LOW.
The RC filter, shown in Figure 3-4, on each of the four VCO supplies—VCC_25_VCO0,
VCC_25_VCO1, VCC_25_VCO2 and VCC_VCO_DIGITAL—is required to minimize the
phase noise of the PLLs in pattern generation/detection modes, but the rise time of the
filter on VCC_VCO_DIGITAL in particular can impact the start-up time of the device
internal clock.
Note 2: In applications where power supplies reach their final voltage in under 1ms (the
time for the internal clock to start), approximately two time constants of the RC filter on
VCC_VCO_DIGITAL, can dominate the time for the GX3290 to emerge from reset upon
power-up. In such cases, the time for VCC_VCO_DIGITAL can be traded-off against
supply filtering and hence low-frequency jitter of patterns generated by Pattern
Generator Zero.
Note 3: RESET must be held LOW until all power supplies have stabilized.
Figure 4-5: Power-Up Timing Diagram
Nominal voltage
95% Nominal voltage
Supply voltage
t
idle
{
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4.11 Device Reset
The RESET pin is an active-LOW asynchronous reset for the device. Assertion of the
RESET pin sets the device in its minimum power state. The minimum pulse width of the
RESET signal is 10ms (treset). There is a 50μs delay (tidle) between the RESET signal going
HIGH (inactive) and the device becoming operational. During this time (all of treset +
tidle), there should be no host interface activity and the UPDATE_EN[7:0] pins must be
held LOW.
Note 1: RESET must be held LOW until all power supplies have stabilized.
Note 2: Upon emerging from reset, all SDI inputs and SDO outputs are powered-down,
pattern generation and checking is inactive, and all registers assume their reset values
as noted in the Semtech Crosspoint (GX3290 and family) Reference Manual (for CSRs).
Reset Timing Diagram
4.12 Host Interface
4.12.1 Parallel Host Interface Specifications
The Asynchronous Parallel Peripheral Interface (APPI) on the GX3290 device allows an
external host to access internal registers using parallel read and write operations.
The GX3290 APPI is selected by setting the HOST_S/P pin LOW.
Note: The S_CS pin must be pulled LOW when HOST_S/P is set LOW for parallel port
communication.
The host interface communicates with the Control and Status Registers (CSR) over an
APPI bridge. It is possible to write one register every 10ns (100MHz write update rate). It
is also possible to read one register every 20ns (50MHz read update rate).
The parallel interface is asynchronous. During writes, an active-LOW P_CS (Chip Select)
enables the interface and ADS (Address/Data Strobe) latches 12-bit write address and
16-bit write data into the device. During reads, the same P_CS signal is used, and the
ADS signal latches the 12-bit read address and then clocks out the 16-bit read data. The
P_R/W signal is used to differentiate between the two access types.
An auto-increment mode exists for both reads and writes. This mode is configured by
way of the APPI_AUTO_INCREMENT bit in the HOST_SETUP register. See Section 6 in
the Semtech Crosspoint (GX3290 and family) Reference Manual (for CSRs).
t
reset
t
idle
RESET
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4.12.1.1 APPI External Timing for Normal Write
Figure 4-6: External Timing for Normal Write Cycle
Table 4-12: APPI Inputs/Outputs
Signal Name I/O Description
P_CS IChip Select from the host.
P_ADSI
Address/Data Strobe from the host; used to “clock” address
and write data into the chip, and to “clock” read data out of
the chip.
P_R/W IRead/Write indication from the host; HIGH for read, LOW for
write.
P_ADD[11:0] I Address from the host.
P_DAT[15:0] I/O Write data from the host, or read data to the host.
P_R/W
D[15:0]
P_ADD
[11:0]
P_DAT
[15:0]
P_ADS
A[11:0]
tSRW_w
tSA_w
tSD_w
tPW_w
tHD_w
tHRW_w
tHA_w
tCSH_w
P_CS
tSCS_w
tHCS_w
Table 4-13: APPI External Timing Specifications for Normal Write
Parameter Symbol Equiv.
Cycles Min Ty p Max Units
P_CS LOW before P_ADS positive edgetSCS_w — 10.0 — — ns
P_CS hold time after P_ADS positive edgetHCS_w 2 14.8 — — ns
P_R/W low before P_CS negative edgetSRW_w —1.5——ns
P_R/W hold time after P_ADS positive edgetHRW_w 2 14.8 — — ns
P_ADD[11:0] setup before P_ADS positive edgetSA_w — 10.0 — — ns
P_ADD[11:0] hold after P_ADS positive edgetHA_w —5.0——ns
P_DAT[15:0] setup before P_ADS positive edgetSD_w —5.0——ns
P_DAT[15:0] hold after P_ADS positive edgetHD_w —5.0——ns
P_ADS LOW pulse width tPW_w 0.64.4——ns
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4.12.1.2 APPI External Timing for Auto-Increment Write
Figure 4-7: External Timing for Auto-Increment Write Cycle
P_CS HIGH before next read/write cycle tCSH_w 5 37.0 — — ns
Frequency for back-to-back single writes — — — — 16.17 MHz
Table 4-13: APPI External Timing Specifications for Normal Write (Continued)
Parameter Symbol Equiv.
Cycles Min Ty p Max Units
Dn
An
tSRW_w
tSA_w
tSD_w
t
HA_w
tHRW_w
Dn+1[15:0]
tCSH_w
tSCS_w tHCS_w
[15:0]
[11:0]
tHD_w tHD_w
tSD_w
tPW_w tADSH_w tPW_w
P_R/W
P_ADD
[11:0]
P_DAT
[15:0]
P_ADS
P_CS
Table 4-14: APPI External Timing Specifications for Auto-Increment Write
Parameter Symbol Equiv.
Cycles Min Typ Max Units
P_CS LOW before P_ADS positive edgetSCS_w —10.0——ns
P_CS hold time after last P_ADS positive edgetHCS_w 214.8——ns
P_R/W LOW before P_CS negative edgetSRW_w — 1.5——ns
P_R/W hold time after P_ADS positive edgetHRW_w 214.8——ns
P_ADD[11:0] setup before P_ADS positive edgetSA_w —10.0——ns
P_ADD[11:0] hold after P_ADS positive edgetHA_w — 5.0——ns
P_DAT[15:0] setup before P_ADS positive edgetSD_w — 4.0——ns
P_DAT[15:0] hold after P_ADS positive edgetHD_w — 4.0——ns
P_ADS LOW pulse width tPW_w 0.64.4——ns
P_ADS HIGH before next pulse tADSH_w 0.64.4——ns
P_CS HIGH before next read/write cycle tCSH_w 537.0——ns
Frequency during auto-increment write — — — — 112.5 MHz
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4.12.1.3 APPI External Timing for Normal Read
Figure 4-8: External Timing for Normal Read Cycle
D[15:0]
A[11:0]
t
CSH_r
t
HCS_r
t
SCS_r
t
SRW_r
t
HRW_r
t
RDZ
t
CDZ
t
SA_r
t
DNZ
t
DO
t
HA_r
t
PW_r
P_R/W
P_ADD
[11:0]
P_DAT
[15:0]
P_ADS
P_CS
Table 4-15: APPI External Timing Specifications for Normal Read
Parameter Symbol Equiv.
Cycles Min Typ Max Units
Internal read pipeline delay (0 if one-cycle read) — 1 ————
P_CS LOW before P_ADS negative edgetSCS_r —5.0——ns
P_CS hold time after P_ADS positive edgetHCS_r —5.0——ns
P_R/W HIGH before P_CS negative edgetSRW_r —1.5——ns
P_R/W hold time after P_ADS positive edgetHRW_r —5.0——ns
P_ADD[11:0] setup before P_ADS negative edgetSA_r —0.0——ns
P_ADD[11:0] hold after P_ADS positive edgetHA_r —0.0——ns
P_DAT[15:0] out of tristate after P_ADS negative edgetDNZ 214.8——ns
P_DAT[15:0] becomes valid after P_ADS negative edgetDO ———65.0ns
P_DAT[15:0] goes tristate after P_CS positive edgetDZ ———45.0ns
P_DAT[15:0] goes tristate after P_ADS positive edgetDZ ———45.0ns
P_ADS LOW pulse width tPW —65.0——ns
P_CS HIGH before next read/write cycle tCSH_r 322.2——ns
Frequency for back-to-back single reads————10.29MHz
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4.12.1.4 APPI External Timing for Auto-Increment Read
Figure 4-9: External Timing for Auto-Increment Read Cycle
A
n
[11:0]
D
n
[15:0]
D
n+1
[15:0] D
n+2
[15:0]
t
SCS_r
t
SRW_r
t
CSH_r
t
HCS_r
t
CDZ
t
HRW_r
t
RDZ
t
PW2_r
t
ADSH_r
t
PW2_r
t
ADSH_r
t
PW1_r
t
DO1
t
DO2
t
DX
t
DO2
t
DX
t
DX
t
SA_r
t
DNZ
t
HA_r
P_R/W
P_ADD
[11:0]
P_DAT
[15:0]
P_ADS
P_CS
Table 4-16: APPI External Timing Specifications for Auto-Increment Read
Parameter Symbol Equiv.
Cycles Min Ty p Max Units
Internal read pipeline delay (0 if one-cycle read) — 1 ————
P_CS LOW before first P_ADS positive edgetSCS_r —5.0——ns
P_CS hold time after last P_ADS positive edgetHCS_r —5.0——ns
P_R/W HIGH before P_CS negative edgetSRW_r —1.5——ns
P_R/W hold time after last P_ADS positive edgetHRW_r —5.0——ns
P_ADD[11:0] setup before P_ADS negative edgetSA_r —0.0——ns
P_ADD[11:0] hold after P_ADS positive edgetHA_r —0.0——ns
P_DAT[15:0] out of tristate after P_ADS negative edgetDNZ 214.8——ns
P_DAT[15:0] becomes valid after first P_ADS negative edgetDO1 ———70.0ns
P_DAT[15:0] becomes valid after P_ADS positive edgetDO2 ———13.0ns
P_DAT[15:0] becomes invalid after P_ADS positive edgetDX —3.0——ns
P_DAT[15:0] goes tristate after P_CS positive edgetDZ — 12.0 — 45.0 ns
P_DAT[15:0] goes tristate after P_ADS positive edgetDZ — 12.0 — 45.0 ns
P_ADS first LOW pulse width tPW1_r —70.0— — ns
P_ADS subsequent LOW pulse widths tPW2_r 1.2 8.9 — — ns
P_ADS HIGH between pulses tADSH_r 1.2 8.9 — — ns
P_CS HIGH before next read/write cycle tCSH_r 537.0——ns
Frequency during auto-increment read————56.25MHz
Frequency for back-to-back single reads in auto-increment mode————8.54MHz
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4.12.2 Serial Host Interface Specifications
The Gennum Serial Peripheral Interface (GSPI) handles the communication with an
external host over the SPI port. It allows configuration of the Control and Status
Registers (CSR) using serial read and write operations.
The GX3290 GSPI is selected by setting the HOST_S/P pin HIGH.
Note 1: The P_CS pin must be pulled LOW when HOST_S/P is set HIGH for serial port
communication.
The GX3290 uses a four-wire protocol, with serial communication via the input SDIN
pin, the output SDOUT pin, clock input signal (SCLK), and the chip select signal (S_CS).
The signalling rate can be up to 25Mb/s. The interface uses 16-bit data and a 16-bit
address/control. The 16-bit address and control consists of a 12-bit address, one
read/write bit (‘1’ for read, ‘0’ for write), one bit for auto-increment and two unused bits.
The four-wire protocol is implemented as shown in Figure 4-10 and Figure 4-11.
When the Auto-Increment bit is set LOW, each Command Word must be followed by
only one Data Word to ensure proper operation.
If the Auto-Increment bit is set HIGH, the following Data Word is written into the
address specified in the Command Word, and subsequent Data Words are written into
incremental addresses from the first Data Word. This facilitates multiple address reads
or writes without sending a Command Word for each Data Word.
Figure 4-10: Serial Host Interface Timing Diagram - Write Mode
Table 4-17: GSPI Inputs/Outputs
Signal Name I/O Reference
Clock
Description
SCLK I — GSPI clock
SDIN I SCLK GSPI serial data input
SDOUT O SCLK GSPI serial data output (on the negative edge of
SCLK)
S_CS I—GSPI Chip Select
SDIN signal is looped out on SDOUT
RRSVRSV Auto_Inc A11 A10 A9 A8 A7 A6A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6D5 D4 D3 D2 D1 D0
t0
t8
t2
t3
t1t7
t4
R/W RSV RSV Auto_Inc A11 A10 A9 A8 A7 A6A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6D5 D4 D3 D2 D1 D0
SCLK
SDOUT
SDIN
S_CS
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Figure 4-11: Serial Host Interface Timing Diagram - Read Mode
70ns (t5) = 5 clock cycles at 135MHz plus SCLK and SDO signal propagation.
18.5ns (t9) = 2.5 clock cycles at 135MHz.
Max t6 (16ns) represents the latest time by which the SDO will be stable after the SCLK negative edge. As SDO
must be sampled on the SCLK positive edge, this determines the minimum SCLK period, and therefore the
maximum SCLK frequency.
SDO maximum transition time with 15pF load: 2ns.
SDO maximum transition time with 50pF load: 5ns.
Note 2: The GSPI and APPI are mutually exclusive (they can not both be used at the
same time).
SCLK
SDIN signal is looped out on SDOUT
SDOUT
Read Data is output on SDOUT
SDIN
t9
t6
t5
R/W RSV RSV Auto_Inc A11 A10 A9 A8 A7 A6A5 A4 A3 A2 A1 A0
R/W RSV RSV Auto_Inc A11 A10 A9 A8 A7 A6A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6D5 D4 D3 D2 D1 D0
S_CS
Table 4-18: Serial Host Interface Timing
Parameter Symbol Conditions Equiv.
Cycles Min Ty p Max Units
S_CS LOW before SCLK positive edget0
50% levels;
3.3V or 1.8V
operation
—7.0——ns
SCLK frequency——0.1—25.0MHz
SCLK periodt1 — 40.0 — 10,000 ns
SCLK duty cycle t2 — 40.0 50.0 60.0 %
Input data setup time t3 — 7.0 — — ns
Time between end of Command Word
(or previous data word in
Auto-Increment mode) and the first
SCLK of the following Data Word - write
cycle
t4 — 40.0 — — ns
Time between end of Command Word
(or previous data word in
Auto-Increment mode) and the first
SCLK of the following Data Word - read
cycle
t5 — 70.0 — — ns
SDO hold time after SCLK negative edge t6 — 5.0 — 16.0 ns
S_CS HIGH after last SCLK negative edget7 1.2 9.0 — — ns
Input data hold time t8 — 5.0 — — ns
S_CS HIGH time t9 2.5 18.5 — — ns
GX3290 290 x 290 3.5Gb/s Crosspoint
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5. Application Information
Note: Please refer to the following supplementary documents:
•Crosspoint Design Guide
•EB-GX3290 Schematics, PCB Layout and Bill of Materials
5.1 Power Supply Filtering and Recommendations
One of the most important steps that PCB designers can take to ensure power supply
integrity for the GX3290 device is to design the PCB layer stack-up to minimize power
plane pair inductance. Locating supply planes adjacent to ground planes, and separated
by minimum thickness dielectrics in the stack-up, will minimize plane-pair inductance,
and incidentally maximize the plane pair capacitance. Holes and cuts in the planes
should be avoided as much as possible. While such closely spaced plane pairs allow the
lowest inductance connections to supply pins of the GX3290 when they are closest to
the device mounting surface of the PCB, the need to balance PCB stack-ups will lead to
closely spaced layers on the far side of the PCB.
The supply currents drawn from the VDD_18 and VDDIO_D supplies are noisy and
activity dependent, and the corresponding supply/ground plane pairs should be treated
as for FPGA or CPU devices. Supply currents drawn from the VCC_25_A, VCC_IN1,
VCC_IN2, VCC_OUT1 and VCC_OUT2 supplies are continuous except under changes of
the high speed signal path configuration. The VCC_OUT1 and VCC_OUT2 supplies in
particular are subject to rapid steps in current under some configuration changes: the
maximum combined current draw of the VCC_OUT1 and VCC_OUT2 supplies, 8.52A,
can be switched in as little as 10ns. This current step may be reduced by appropriate
programming of the device.
Locating point of use voltage regulators close to the GX3290 device on the PCB will
maximize the regulation roll-off frequency. At the highest frequencies, the GX3290
package and mounting parasitics will limit the effectiveness of any measures on the PCB
to suppress voltage ripple on the device supplies. In between the voltage regulator roll
off frequencies and the frequencies where parasitics on each supply domain within the
GX3290 isolate the die from the PCB, decoupling capacitors on the PCB are effective.
PCB layout effort should be spent on details of the decoupling capacitor mounting
layout. Some simple layout measures can help to reduce the inductance of capacitor
mounting.
See the Crosspoint Design Guide for more detailed recommendations.
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5.2 Estimated Worst-Case Load Current Steps
Under normal operation, the power supply networks need to minimize voltage
transients due to configuration change related load current steps. When the device reset
is asserted while the device is drawing significant current, the load on power supplies
could be shed fast enough to raise concerns about the board level voltage regulator
dynamics, and the impact of any power supply network inductance.
5.2.1 VCC_25_A Supply
The tail currents of CML blocks (the high-speed signal paths) in the matrix switch
relatively slowly, with worst case switching times of 30ns and typical times ~50ns. The
matrix supply current of ~9.4A could in principle switch in 30ns, but in practice the
propagation delay of UPDATE_EN[7:0] signals across the matrix will increase the
switching time somewhat.
The VCC_25_A supply current drawn by individual EQs takes more than 10ns to rise
upon application of control signals. The VCC_25_A supply current drops in as little as
5ns upon assertion of reset, though, and the reset signal arrival times at EQs in a bank
are roughly uniformly distributed over an interval of 0.8ns. This means that the
VCC_25_A current drawn by all EQs together, ~3.2A, could be shed in 5.8ns.
The trace drivers draw significant current from the VCC_25_A supply, up to ~4.1A total
for all trace drivers together, and this current can rise in as little as 20ns upon the
de-assertion of power-down signals, or fall in as little as 1ns upon the assertion of
power-down or reset signals. The arrival times of power-down or reset signals within
the bottom trace driver bank are nearly uniformly distributed over an interval of 0.8ns,
while the arrival time of power-down or reset signals within the top trace driver bank
are nearly uniformly distributed over an interval of 4.4ns.
The worst case total load current slew rate on the VCC_25_A supply is estimated from
the above to be ~2.2GA/s.
5.2.2 VCC_OUT1, VCC_OUT2 Supplies
In simulation, the tail currents of trace driver output stages turn on in as little as 10ns.
Should all outputs be configured for maximum swing and enabled simultaneously, the
load current step on each of VCC_OUT1, VCC_OUT2 would be as high as 4.26A (for
AC-coupled applications) in ~14ns, 11ns respectively (including the propagation delay
spread noted above). That large dI/dt can be reduced by appropriate programming of
updates. The VCC_OUT1 and VCC_OUT2 supply current drawn by each trace driver
drops in as little as 1ns upon the assertion of device reset. The greater spread of signal
arrival times in the top bank leads to a significantly smaller magnitude of dI/dt on the
VCC_OUT1 supply than on the VCC_OUT2 supply.
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Final Data Sheet Rev. 2
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5.2.3 VCC_IN1, VCC_IN2 Supplies
The controls for the equalizers are serialized, and hence power switching of the
equalizers in mission mode is staggered in time. Assertion of reset will however lead to
more nearly synchronous shedding of load. The typical current drawn from the
VCC_IN1 and VCC_IN2 supplies is 1.75A each, and this can be shed in 1ns, including the
reset signal propagation delay.
Table 5-1: Summary
Supply Maximum
Current (A) Maximum Positive dI/dt
Maximum Negative dI/dt
(reset/simultaneous
power-down)
VCC_25_A 16.7 0.81GA/s -2.2GA/s
VCC_OUT1 4.26 0.42GA/s -1.4GA/s
VCC_OUT2 4.26 0.54GA/s -3.6GA/s
VCC_IN1 1.75(typ) <0.1GA/s -1.8GA/s
VCC_IN2 1.75(typ) <0.1GA/s -1.8GA/s
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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6. Package and Ordering Information
6.1 Package Dimensions
50mm x 50mm FCBGA (1mm pitch)
Figure 6-1: Package Dimensions
Side View
Top View Bottom View
50.00
38.00
50.00
38.00
A1 Ball Pad Corner
0.20
B
A
A
A
4X (6.00)
4X (6.00)
(4X)
Φ1.35±0.25
Section A–A
36.00
0.50±0.05
3.69±0.12
Φ0.60+0.06
–0.14
Φ0.25
Φ0.10 C
AC B
M
M
CC0.20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2931
3032
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
AB
CD
EF
GH
JK
LM
NP
RT
UV
WY
AA AB
AC AD
AE AF
AG AH
AJ AK
AL AM
AN AP
AR AT
AU AV
AW AY
BA BB
BC BD
BE BF
BG BH
BJ
1.00
1.00
(4.00)
(4.00)
A1 Ball Pad Corner
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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6.2 Package Thermal Data and Information
6.3 Marking Diagram
Figure 6-2: Marking Diagram
Table 6-1: Package Thermal Data and Information
Parameter Value
Package Type 50mm x 50mm HFC BGA
Moisture Sensitivity Level 3
Junction to Case Thermal Resistance, θj-c0.31°C/W
Junction to Air Thermal Resistance, θj-a (at zero
airflow)
N/A. This device requires a heat
sink. See Semtech’s Crosspoint
Design Guide.
Junction to Board Thermal Resistance, θj-b2.1°C/W
Pb-free and RoHS Compliant Yes
Instructions:
GX3290 Package Mark
ZZZZZZ Marking batch work order
information
E3 Pb-free & Green indicator
YYWW Date Code
Pin 1
Indicator
GX3290
ZZZZZZE3
XXXXXX-YYWW
XXXXXX Assembly batch work order
information
GX3290 290 x 290 3.5Gb/s Crosspoint
Final Data Sheet Rev. 2
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6.4 Solder Reflow Profile
The GX3290 is available in a Pb-free package. It is recommended that the Pb-free
package be soldered with Pb-free paste using the reflow profile shown in Figure 6-3.
Figure 6-3: Maximum Pb-free Solder Reflow Profile
6.5 Ordering Information
Appendix - Relevant Documentation
250
200
150
100
50
150°C
180°C
60 - 120s
Pre Heating Zone
Soldering
Zone
230°C
1.0 - 2.0°C/s
1.5 - 2.0°C/s
1.0 - 2.0°C/s
10 - 15s
Heating Time
Device Surface Temperature (°C)
Peak 245°C
Table 6-2: Ordering Information
Part Number Package Temperature Range
GX3290-CBE3 50x50mm HFC-BGA0°C to 85°C
Table 6-3: Relevant Documentation
Document Description Document Identification
EB-GX3290 Schematics, PCB Layout and Bill of Materials GENDOC-056057
GX3290 Host Control Software User Manual GENDOC-055970
Using the Monitoring Features of the GX3290 Application Note GENDOC-058329
GX3290 (and family) Crosspoint Ball GuideGENDOC-056697
Crosspoint Design GuideGENDOC-056004
Crosspoint (GX3290 and family) Reference Manual (for CSRs) GENDOC-056832
© Semtech 2012
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DOCUMENT IDENTIFICATION
FINAL DATA SHEET
Information relating to this product and the application or design described
herein is believed to be reliable, however such information is provided as a
guide only and Semtech assumes no liability for any errors in this document, or
for the application or design described herein. Semtech reserves the right to
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