○Product structure:Sillicon monolithic integrated circuit ○This product is not designed protection against radio active rays
1/35 TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・14・001
Power LSI series for Digital Camera and Digital Video Camera
4CH Internal Power MOSFET
System Switching Regulator
BD9866GUL
●Outline
BD9866GUL is a 4ch DC/DC converter IC c omposed of
Buck converter 3-channels and Buck-Boost converter
1-channel.Including power MOSFET of all channels
reduces the number of peripheral devices. Each
channel is controlled in dividuall y, that enables to reduce
power consumption of not working channel.
●Features
1) Includes Buck converter (CH1, 2 and 4), and
Buck-Boost converter (CH3), total 4 channels
included.
2) Includes Power MOSFET for all channels.
3) Includes Over Current Protection (OCP) for all
channels.
4) Includes Short Circuit Protection (SCP.)
5) Includes Undervoltage Lock Out (UVLO.)
6) Includes Thermal Shut Down (TSD.)
7) Includes Power Good(PG)
8) External synchrono us oscillation
9) Each channel can be turn on/off individually.
10) Contains internal compensation for all channels.
11) Operation frequency of 1MHz.
●Package
WLCSP(3.75mm×3.75mm)
●Use
For digital single-lens reflex camera, digital video
camera.
●Key specifications
・Input voltage range :
・Output voltage
CH1 reference voltage:
CH2 reference voltage:
CH3 reference voltage:
CH4 reference voltage:
・Load current
CH1 load current:
CH2 load current:
CH3 load current:
CH4 load current:
・Frequency:
4.0V to 14.0V
0.6V±1.67% (typ.)
0.8V±1.25% (typ.)
0.8V±1.25% (typ.)
0.8V±1.25% (typ.)
3.0A(max)
2.0A(max)
1.5A(max)
3.0A(max)
1MHz(typ.)
●Function block diagram
Step Down
DC/DC 1 FET
FET
Step Down
DC/DC 2 FET
FET
Step Down
DC/DC 4 FET
FET
1.1V
1.5V
5.0V
3.3V
Buck Boost
DC/DC 3 FET
FET
FET
FET
Figure. 1 Function block diagram
2/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Pin assignment(Bottom View)
G PVCC1 PVCC1 VREGD PVCC GND VCC PVCC4
F Lx1 CH1G INV1 VREGB VREGA RT PVCC4
E Lx1 CH2G SYNC INV3 INV4 Lx4 Lx4
D PGND1 PGND1 CTL2 INV2 RTSS PGND4 PGND4
CPGND2PGND2
1pin
POST
CTL1 CTL4 CTL3 SEL
B Lx2 Lx2 PGND SCP PG Lx32 VO3
A PVCC2 PVCC2 PVCC3 Lx31 PGND3 PGND3 Lx32
1234567
Figure.2 Pin assignment
●Pin description
PINno Symbol I/O
Description
G6 VCC -
Input supply voltage
G4 PVCC -
Input supply voltage of internal regulator for driver
B3 PGND -
Ground terminal
G1,G2,A1,A2,
A3,F7,G7 PVCC1,2,3,4 -
Driver input supply voltage terminal.
D1,D2,C1,C2,
A5,A6,D6,D7 PGND1,2,3,4 -
Ground for internal FET
G5 GND -
Ground
G3 VREGD O
Output terminal of 3.5V regulator for lowside driver
F5 VREGA O
Output terminal of 3.5V regulator for internal reference voltage
F4 VREGB O
Output terminal of PVCC – 3.5V regulator for highside dr iver
B7 Vo3 O
Output voltage terminal for CH3
E1,F1,B1,B2,
E6,E7 Lx1,2,4 O
Inductor connecting terminal
A4 Lx31 O
CH3 input side inductor connecting terminal
A7,B6 Lx32 O
CH3 output side inductor connecting termin al
F3,D4,E4,E5 INV1,2,3,4 I
Error amplifier inverted input terminal
E3 SYNC I
External oscillator input terminal
F6 RT -
Oscillator frequency adjustment terminal with external resistor
B4 SCP -
SCP delay time setting terminal with external capacitor
C4,D3,C6,C5 CTL1,2,3,4 I
ON/OFF control terminal
B5 PG O
Power good signal output terminal at SCP
F2,E2 CH1,2G O
CH1,2 power good signal output terminal
D5 RTSS O
RT voltage setting terminal
C7 SEL I
CH2,4 mode select terminal
3/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●block diagram
Figure. 3 block diagram
4/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Absolute Maximum Ratings
Parameter Symbol Limits Units
Maximum Power Supply Voltage VCC, PVCC, PVCC1,2,3,4 -0.3 to 15 V
Maximum Input Current IPVCC1,4 3.5 A
IPVCC2,3 2.5 A
Maximum Input Voltage
VREGA, VREGD, PVCC1,2,3,4-VREGB -0.3 to 7 V
Lx1, Lx2, Lx31, Lx4 -0.3 to 15 V
Lx32, Vo3 -0.3 to 10.5 V
PG -0.3 to 15 V
CH1,2G -0.3 to 7 V
CTL1,2,3,4 -0.3 to 15 V
SEL -0.3 to 15 V
SYNC -0.3 to 15 V
Power Dissipation Pd 1.25(*1) W
Operating Temperature Topr -25 to +85 ℃
Storage Temperature Tstg -55 to +125 ℃
Junction Temperature Tjmax 125 ℃
(1*)when mounted on a 50mm×50mm×1.75mm glass epoxy 8layer PCB at Ta=25℃(Derate by 12.5mW /℃ above 25℃)
●Recommended Operating Conditions
Parameter Symbol
Limits Units Conditions
Min Typ Max
Power Supply Voltage VCC,PVCC 4.0 6.0 14 V
VREGA,VREGD Output Capacitor CVREGA,D 0.47 1.0 2.2 µF
VREGB Output Capacitor CVREGB 0.47 1.0 2.2 µF Connect to PVCC
Capacitor Connected to SCP CSCP 0.001 － 2.2 µF
Oscillator Frequency FOSC 0.6 1.0 1.5 MHz
OSC T iming Resistor RT 47 82 120 kΩ 1MHz by connecting 82kΩ
Capacitor Connected to RTSS CRTSS 1000 10000 － pF
H Level of SYNC Input voltage VSYNCH 3.0 - VCC V
L Level of SYNC Input voltage VSYNCL -0.3 - 0.5 V
Duty of SYNC Input DSYNC 40 50 60 %
Output voltage range of CH3 VVOUT3 4.0 － 10 V
Output Current of CH1 IOUTCH1 － － 3
(*3) A 1.1V Output
Output Current of CH2 IOUTCH2 － － 2
(*3) A 1.5V Output
Output Current of CH3 IOUTCH3 － － 1.5(*3) A 5.0V Output
Output Current of CH4 IOUTCH4 － － 3
(*3) A 3.3V Output
(*) Please connect capacitor to I/O(VCC, PVCC, VREG) so that IC can be operated safety.
(*3) Please make a power design total loss of IC not to exceed the power dissipation.
●Over Current Protection
Parameter Symbol Limits Units Conditions
Min Typ Max
CH1 PVCC1 OCP Current IOCP1 3.2 - - A
CH2 PVCC2 OCP Current IOCP2 2.2 - - A
CH3 PVCC3 OCP Curernt IOCP3 3.0 - - A
CH4 PVCC4 OCP Current IOCP4 3.2 - - A
5/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Electrical Characteristics(Ta=25℃, VCC=PVCC=6V, RT=82kΩ, CTL1-4=3V, unless otherwise noted)
Parameter Symbol Limits Units Conditions
Min Typ Max
【Internal Regulator】
Regulator output voltage for internal
analog circuit VREGA 3.3 3.5 3.7 V IVREGA=-1mA
Regulator output voltage for bias
voltage of Highside FET VREGB VCC-3.7 VCC-3.5 VCC-3.3 V IVREGB=+1mA
Regulator output voltage for bias
voltage of Lowside FET VREGD 3.3 3.5 3.7 V IVREGD=-1mA
【Under Voltage Lock Out】
Threshold voltage of VCC
undervoltage lock out VSTD1 3.2 3.4 3.6 V
VCC terminal voltage
monitor
Hysteresis voltage of VCC
undervoltage lock out VHYS1 － 0.1 0.2 V
VCC terminal voltage
monitor
Threshold voltage of VREG
undervoltage lock out VSTD2 2.8 3.0 3.2 V
VREGA,VREGD
terminals voltage
monitor
Hysteresis voltage of VREG
undervoltage lock out VHYS2 － 0.1 0.2 V
VREGA,VREGD
terminals voltage
monitor
【Short Circuit Protection】
SCP terminal output current ISCP 2.5 5.0 7.5 µA VSCP=0.1V
SCP terminal detect voltage VTSC 0.45 0.50 0.55 V
SCP terminal stand-by voltage VSSC － 10 100 mV
【Oscillator】
Oscillator frequency of DC/DC
converter FOSC 0.9 1.0 1.1 MHz RT=82kΩ
Max duty Lx1,Lx2,Lx4 DMAX1,2,4 - - 100 % VSCP=0V (*4),
Lx1,Lx2,Lx4 High Duty
Max duty Lx31 DMAX31 - - 100 % Lx31 High Duty
Max duty Lx32 DMAX32 74 80 86 % Lx32 Low Duty
RTSS terminal stand-by voltage RTSSF - 1 20 mV CTL1-4=0V
RTSS terminal input current IRTSSI -7 -5 -3 µA
RTSS terminal output current IRTSSO 3 5 7 µA
【Error Amplifier】
INV1-4 terminal input bias current IINV1,2,3,4 -50 0 50 nA INV=2.0V
INV1 terminal threshold voltage VINV1 0.590 0.600 0.610 V
INV2-4 terminal threshold voltage VINV2,3,4 0.790 0.800 0.810 V
【Soft Start】
CH1 Soft start time TSS1 0.7 1.4 2.1 msec
CH2,3,4 Soft start time TSS2,3,4 0.95 1.9 2.85 msec
(*4) SCP circuit starts to charge when operated 100% Duty, therefore it is possible to use 100% Duty only while SCP voltage doesn’t reach to 0.5V.
6/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Electrical Characteristics(Ta=25℃, VCC=PVCC=6V, RT=82kΩ, CTL1-4=3V, unless otherwise noted)
Parameter Symbol Limits Units Conditions
Min Typ Max
【Driver】
Lx1 Highside SW on resistance RON1P - 180 300 mΩ ILx1=-50mA
Lx1 Lowside SW on resistane RON1N - 75 130 mΩ ILx1=+50mA
Lx2 Highside SW on resistance RON2P - 190 305 mΩ ILx2=-50mA
Lx2 Lowside SW on resistance RON2N - 100 160 mΩ ILx2=+50mA
Lx31 Highside SW on resistance RON31P - 190 305 mΩ ILx31=-50mA
Lx31 Lowside SW on resistance RON31N - 115 185 mΩ ILx31=+50mA
Lx32 Highside SW on resistance RON32P - 230 370 mΩ Vo3=5.0V, ILx32=-50mA
Lx32 Lowside SW on resistance RON32N - 115 185 mΩ ILx32=+50mA
Lx4 Highside SW on resistance RON4P - 170 290 mΩ ILx4=-50mA
Lx4 Lowside SW on resistance RON4N - 140 230 mΩ ILx4=+50mA
Lx1,Lx2,Lx4 terminal discharge
resistance RDISLX,2,4 40 100 160 Ω CTL1,2,4=0V
VO3 terminal discharge resistance RDISVO3 40 100 160 Ω CTL3=0V
【Power Good】
PG terminal on resistance RONPG - 350 600 Ω PG=1V
PG terminal leak current ILKPG - 0 1.0 µA PG=15V
CH1G,CH2G terminals high voltage CH1,2GH VREGA
-0.5 - - V ICTL1,2G=-100uA
CH1G,CH2G terminals low voltage CH1,2GL - - 0.5 V ICTL1,2G=+100uA
【Control】
CTL terminal active voltage VCTLH 2.5 - VCC V CTL1,2,3,4
CTL terminal stand-by voltage VCTLL -0.3 - 0.8 V CTL1,2,3,4
CTL terminal pull-down resistance RCTL 250 400 700 kΩ CTL1,2,3,4
SEL terminal high voltage VSELH 2.5 - VCC V
SEL terminal low voltage VSELL -0.3 - 0.8 V
SEL terminal pull-d own resistance RSEL 250 400 700 kΩ
【Circuit Current】
Stand-by current(IC OFF) ISTB - 0 5 µA CTL1-4=0V
Active current(SCP detect state) ICCST - 5 10 mA INV1,2,3,4=0V
Circuit current of analog
Active current(DC/DC converter
active) ICCAPP - 35 45 mA
All channels operate
with recommended
external parts
7/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Applic at ion c ircuit1
PVCC4
VCC
Lx1
PGND1
PVCC1
Lx2
PVCC2
PVCC3
Lx31
PGND3
Lx32
Vo3
Lx4
VREGB
PGND2
PVCC
A
B
D
C
C
B
A
D
+
-
+
ERRORAMP1
PWMCOMP1
INV1
+
-
+
ERRORAMP2
INV2
+
-
+
ERRORAMP3
INV3
ERRORAMP4
INV4
+
-
SCP TIMER
PROTECTION
TSD
UVLO
OSC
CH CTL
VREG
A
PGND
CTL1 CTL2 CTL3 CTL4 RT VREGA GNDSYNC
CH2
Step Down
(Current mode)
CH1
Step Down
(Current mode)
CH3
Cross Converter
(Voltage mode)
-
-
-
-
+
RTSS
VREG
DVREG
B
VREGD
SCP
CH4
Step Down
(Current mode)
PWMCOMP2
PWMCOMP3
PG
SCP
TIMEROUT
Substrate
VCC
VREGA
VREGD
OCP
OCP
OCP
PWMCOMP4 OCP
VREGA
VREGA
VREGA
VREGA
RTSS
enable
SS Counter reset
CLK
shutdown
SCP
TIMEROUT
Limit input current for PVCC
Limit input current for PVCC
Limit input current for PVCC
Limit input current for PVCC
+
PGND4
Light Load
mode
Light Load
mode
CH1G
VREGA
VREGA
CH2G
SEL
SEL
SEL
150kΩ
180kΩ
100kΩ
120kΩ
200kΩ
39kΩ
24pF
75kΩ
24kΩ
0.01μF
0.01μF82kΩ1.0μF1.0μF
1.0μF
100kΩ
10μF
4.7μH
4.7μF
10μF
4.7μF
4.7μH
10μF
4.7μH
4.7μF
10μF
4.7μH
4.7μF
Vo1
1.1V
Vo2
1.5V
Vo3
5.0V
Vo4
3.3V
(47pF)
(8.2kΩ)
()
()
(*1)
Figure. 4 Application circuit 1
8/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
PVCC4
VCC
Lx1
PGND1
PVCC1
Lx2
PVCC2
PVCC3
Lx31
PGND3
Lx32
Vo3
Lx4
VREGB
PGND2
PVCC
A
B
D
C
C
B
A
D
+
-
+
ERRORAMP1
PWMCOMP1
INV1
+
-
+
ERRORAMP2
INV2
+
-
+
ERRORAMP3
INV3
ERRORAMP4
INV4
+
-
SCP TIMER
PROTECTION
TSD
UVLO
OSC
CH CTL
VREG
A
PGND
CTL1 CTL2 CTL3 CTL4 RT VREGA GNDSYNC
CH2
Step Down
(Current mode)
CH1
Step Down
(Current mode)
CH3
Cross Converter
(Voltage mode)
-
-
-
-
+
RTSS
VREG
DVREG
B
VREGD
SCP
CH4
Step Down
(Current mode)
PWMCOMP2
PWMCOMP3
PG
SCP
TIMEROUT
Substrate
VCC
VREGA
VREGD
OCP
OCP
OCP
PWMCOMP4 OCP
VREGA
VREGA
VREGA
VREGA
RTSS
enable
SS Counter reset
CLK
shutdown
SCP
TIMEROUT
Limit input current for PVCC
Limit input current for PVCC
Limit input current for PVCC
Limit input current for PVCC
+
PGND4
Light Load
mode
Light Load
mode
CH1G
VREGA
VREGA
CH2G
SEL
SEL
SEL
150kΩ
180kΩ
100kΩ
120kΩ
200kΩ
39kΩ
24pF
75kΩ
24kΩ
0.01μF
0.01μF82kΩ
1.0μF
1.0μF
1.0μF
100kΩ
10μF
4.7μH
4.7μF
10μF
4.7μF
4.7μH
10μF
4.7μH
4.7μF
10μF
4.7μH
4.7μF
Vo1
1.1V
Vo2
1.5V
Vo3
5.0V
Vo4
3.3V
(47pF)
(8.2kΩ)
()
()
(*1)
Figure. 5 Application circuit 2
(*1) Add to improve transient characteristics optio nally.
We are confident that above applied circuit diagram should be recommended, but please thoroughly conf irm its
characteristics when using it. In addition, when using it with external circuit’s constants changed, please make a
decision that allows a sufficient margin in light of the fluctuations of external compon ents and ROHM’s IC in terms of
not only static characteristics but also transient characteristi cs..
9/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Timing Chart of startup
Constant
output
0.6V(typ.)
Soft Start by internal counter
0.35V(typ.)
RTSS Charge Current
60μA@RTSS < 0.35V
5μA@RTSS > 0.35V
RTSS constant point
no external synchronization: 0.5V
external synchronization:
a stable point between 0.5 to 0.83V
UVLO (VREG) rele ase=3.0V
Start up VREGA,VREGD,VREGB and part of controller
VCC
CTL
VREGA
VREGD
Internal
triangular
waveform
RTSS
SS1
(internal node)
Vo1
Constant
output
0.8V(typ.)
Soft Start by internal counter
SS2-4
(internal node)
Vo2-4
CH1 Stop Delay
Toff1=50usec
Tss2,3,4 = 1.9ms
Tss1 = 1.4ms
Figure.6 Timing chart of Startup
10/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Timing chart of UVLO operation
Figure. 7 Timing chart of UVLO operation
(UVLO detect and after release from UVLO, restart with softstart)
11/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Timing chart of SCP detection after startup
INV
EOUT
(internal node)
SCP
PG
Output stops with SCP latch
SCP latch is detected when SCP > 0.5V
(Latch state is released at UVLO)
3.0V(typ.)
Charge the capacitor
connected SCP terminal by
charge current of 5μA 0.5V(typ.)
0.8V(setting voltage)
Open drain terminal becomes Low by SCP latch
Latch detect time when capacitor connected
to SCP terminal is 0.01μF
=(C×V)/I
=(0.01μ×0.5)/5μ=1msec
Figure. 8 Timing chart of SCP detection after startup
(abnormal output in operating)
12/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Timing chart of startup with output shorted to GND
Figure. 9 Timing chart of startup with output shorted to GND
13/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Typical Operating Characteristics
0.0
1.0
2.0
3.0
4.0
5.0
02468101214
VCC [ V]
ICC [uA]
0.0
1.0
2.0
3.0
4.0
5.0
-50-25 0 25 50 75100
Temperature [℃]
ICC [uA]
Figure.10 ICC(OFF) - VCC Figure.11 ICC(OFF) - Ta
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
02468101214
VCC [ V]
ICC [mA]
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
-50 -25 0 25 50 75 100
Temperature [℃]
ICC [mA]
Figure.12 ICC(SCP state) - VCC Figure.13 ICC(SCP state) - Ta
VCC=0→14V
Ta=25℃
VCC=14V
Ta=-25 to 85℃
VCC=0→14V
Ta=25℃ VCC=7V
Ta=-25 to85℃
14/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Typical Operating Characteristics(continued)
0.0
1.0
2.0
3.0
4.0
5.0
0 2 4 6 8 10 12 14
VCC [V]
VREGA[V]
3.300
3.340
3.380
3.420
3.460
3.500
3.540
3.580
3.620
3.660
3.700
-50 -25 0 25 50 75 100
Temperature [℃]
VREGD[V]
Figure.15 VREGA – Ta
Figure.14 VREGA - VCC
Figure.16 VREGD- VCC
0.0
1.0
2.0
3.0
4.0
5.0
02468101214
VCC[V]
VREGD[V]
3.300
3.340
3.380
3.420
3.460
3.500
3.540
3.580
3.620
3.660
3.700
-50 -25 0 25 50 75 100
Temperature [℃]
VREGA [V]
Figure.17 VREGD
–
Ta
VCC=0→14V
Ta=25℃ VCC=7V
Ta=-25 to 85℃
VCC=0→14V
Ta=25℃ VCC=7V
Ta=-25 to 85℃
15/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Typical Operating Characteristics(continued)
0.0
1.0
2.0
3.0
4.0
5.0
02468101214
VCC [ V]
PVCC-VREGB[V]
3.300
3.340
3.380
3.420
3.460
3.500
3.540
3.580
3.620
3.660
3.700
-50 -25 0 25 50 75 100
Temperature [℃]
VREGD[V]
Figure.18 (PVCC
–
VREGB)- VCC Figure.19 (PVCC
–
VREGB)
–
Ta
0.500
0.520
0.540
0.560
0.580
0.600
0.620
0.640
0.660
0.680
0.700
4 6 8 10 12 14
VCC [ V]
INV1 threshold voltage[V]
0.500
0.520
0.540
0.560
0.580
0.600
0.620
0.640
0.660
0.680
0.700
-50 -25 0 25 50 75 100
Temperature [℃]
INV1 threshold voltage[V]
Figure.21
INV1 threshold voltage – Ta
Figure.20
INV1 threshold voltage – VCC
VCC=7V
Ta=-25 to 85℃
VCC=7V
Ta=-25 to 85℃
VCC=0→14V
Ta=25℃
VCC=4→14V
Ta=25℃
16/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Typical Operating Characteristics(continued)
0.700
0.720
0.740
0.760
0.780
0.800
0.820
0.840
0.860
0.880
0.900
4 6 8 10 12 14
VCC [ V]
INV2,3,4 threshold voltage[V]
0.700
0.720
0.740
0.760
0.780
0.800
0.820
0.840
0.860
0.880
0.900
-50 -25 0 25 50 75 100
Temperature [℃]
INV2,3,4 threshold voltage[V]
Figure.23
INV2,3,4 threshold voltage– Ta
Figure.22
INV2,3,4 threshold voltage– VCC
800
850
900
950
1000
1050
1100
1150
1200
4 6 8 10 12 14
VCC [ V]
fosc [ KHz]
800
850
900
950
1000
1050
1100
1150
1200
-50 -25 0 25 50 75 100
Temperature [℃]
f osc [kHz]
Figure.25 fosc - Ta
Figure.24 fosc - VCC
VCC=4→14V
Ta=25℃
VCC=4→14V
Ta=25℃
VCC=7V
Ta=-25 to 85℃
VCC=7V
Ta=-25 to 85℃
17/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Typical Operating Characteristics(continued)
0.0
1.0
2.0
3.0
4.0
5.0
3.30 3.40 3.50 3.60 3.70 3.80
VCC [V]
CH1G[V]
0.0
1.0
2.0
3.0
4.0
5.0
3.30 3.40 3.50 3.60 3.70 3.80
VCC [V]
CH1G[V]
Figure.26 UVLO VCC
detect threshold voltage Figure.27 UVLO VCC
reset threshold voltage
0.0
1.0
2.0
3.0
4.0
5.0
2.90 2.95 3.00 3.05 3.10 3.15 3.20
VREGA [V]
CH1G[V]
0.0
1.0
2.0
3.0
4.0
5.0
2.90 2.95 3.00 3.05 3.10 3.15 3.20
VREGA [V]
CH1G[V]
Figure.28 UVLO VREGA
detect threshold voltage Figure.29 UVLO VREGA
reset threshold voltage
VCC=3.8→3.3V
Ta=25℃ VCC=3.3→3.8V
Ta=25℃
VREGA=3.2→2.9V
Ta=25℃
VREGA=2.9→3.2V
Ta=25℃
18/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Typical Operating Characteristics(continued)
0.0
1.0
2.0
3.0
4.0
5.0
2.90 2.95 3.00 3.05 3.10 3.15 3.20
VREGD [V]
CH1G[V]
0.0
1.0
2.0
3.0
4.0
5.0
2.90 2.95 3.00 3.05 3.10 3.15 3.20
VREGD[V]
CH1G[V]
Figure.30 UVLO VREGD
detect threshold voltage Figure.31 UVLO VREGD
reset threshold voltage
0.0
1.0
2.0
3.0
4.0
5.0
1.00 1.40 1.80 2.20 2.60 3.00
CTL1,2,3,4 [V ]
VREGA[V]
0.0
1.0
2.0
3.0
4.0
5.0
1.00 1.40 1.80 2.20 2.60 3.00
CTL1,2,3,4 [V]
VREGA[V]
Figure.32 CTL OFF threshold voltage Figure.33 CTL ON threshold voltage
VREGD=3.2→2.9V
Ta=25℃
VREGD=2.9→3.2V
Ta=25℃
VCC=7V
CTL=3.0→1.0V
Ta=25℃
VCC=7V
CTL=1.0→3.0V
Ta=25℃
19/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Typical Operating Characteristics(continued)
0.0
25.0
50.0
75.0
100.0
125.0
150.0
175.0
200.0
0 1020304050
ILx1 [mA ]
ON RESI ST ANCE[mohm]
0.0
25.0
50.0
75.0
100.0
125.0
150.0
175.0
200.0
0 1020304050
ILx2 [mA]
O N RESI ST ANCE[mohm]
Figure.36 Lx2 High side FET RON
(Ta=-30℃, 25℃, 85℃)
Figure.34 Lx1 High side FET RON
(Ta=-30℃, 25℃, 85℃)
0.0
25.0
50.0
75.0
100.0
125.0
150.0
175.0
200.0
0 1020304050
ILx1 [mA ]
ON RESI ST ANCE[mohm]
0.0
25.0
50.0
75.0
100.0
125.0
150.0
175.0
200.0
0 1020304050
ILx2 [mA ]
ON RESI ST ANCE[mohm]
Figure.37 Lx2 Low side FET RON
(Ta=-30℃, 25℃, 85℃)
Figure.35 Lx1 Low side FET RON
(Ta=-30℃, 25℃, 85℃)
VCC=7V
ILx1=-1→-50mA
85℃
25℃
-30℃
85℃ 25℃
-30℃
VCC=7V
ILx1=1→50mA
VCC=7V
ILx2=-1→-50mA
85℃
25℃ -30℃
VCC=7V
ILx2=1→50mA
85℃ 25℃
-30℃
20/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Typical Operating Characteristics(continued)
0.0
25.0
50.0
75.0
100.0
125.0
150.0
175.0
200.0
225.0
250.0
0 1020304050
I Lx32 [mA]
O N RESI ST ANCE[mohm]
Figure.38 Lx31 High side FET RON
(Ta=-30℃, 25℃, 85℃)
0.0
25.0
50.0
75.0
100.0
125.0
150.0
175.0
200.0
0 1020304050
ILx31[mA]
O N RESI STANCE[ mohm]
Figure.40 Lx32 High side FET RON
(Ta=-30℃, 25℃, 85℃)
0.0
25.0
50.0
75.0
100.0
125.0
150.0
175.0
200.0
0 1020304050
ILx31[mA]
ON RESI STA NCE[mohm]
0.0
25.0
50.0
75.0
100.0
125.0
150.0
175.0
200.0
0 1020304050
ILx32 [mA]
ON RESI STA NCE[mohm]
Figure.41 Lx32 Low side FET RON
(Ta=-30℃, 25℃, 85℃)
Figure.39 Lx31 Low side FET RON
(Ta=-30℃, 25℃, 85℃)
VCC=7V
ILx31=-1→-50mA
85℃
25℃ -30℃
VCC=7V
ILx31=1→50mA
85℃ 25℃
-30℃
VCC=7V
ILx32=-1→-50mA
85℃
25℃
-30℃
VCC=7V
ILx32=1→50mA
85℃ 25℃
-30℃
21/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Typical Operating Characteristics(continued)
0.0
25.0
50.0
75.0
100.0
125.0
150.0
175.0
200.0
0 1020304050
ILx4[mA]
O N RESI ST ANCE[mohm]
Figure.42 Lx4 High side FET RON
(Ta=-30℃, 25℃, 85℃)
0.0
25.0
50.0
75.0
100.0
125.0
150.0
175.0
200.0
0 1020304050
ILX 4 [mA ]
O N RESIST ANCE[ mohm]
Figure.43 Lx4 Low side FET RON
(Ta=-30℃, 25℃, 85℃)
0
50
100
150
200
250
300
4 6 8 101214
VCC [ V]
RESISTANCE[ohm]
0
50
100
150
200
250
300
4 6 8 101214
VCC [V]
RESISTANCE[ohm]
Figure.44 Lx1 discharge SW RON
(Ta=-30℃, 25℃, 85℃) Figure.45 Lx2 discharge SW RON
(Ta=-30℃, 25℃, 85℃)
VCC=7V
ILx4=-1→-50mA
85℃
25℃
-30℃
VCC=7V
ILx4=1→50mA
-30℃
25℃
85℃
85℃
25℃
-30℃
85℃
25℃
-30℃
22/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Typical Operating Characteristics(continued)
0
50
100
150
200
250
300
4 6 8 101214
VCC [ V]
RESISTANCE[mohm]
0
50
100
150
200
250
300
4 6 8 101214
VCC [ V]
RESISTANCE[ohm]
Figure.46 Vo3 dischar ge SW RON
(Ta=-30℃, 25℃, 85℃) Figure.47 Lx4 discharge SW RON
(Ta=-30℃, 25℃, 85℃)
85℃
25℃
-30℃
85℃
25℃
-30℃
23/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
0
10
20
30
40
50
60
70
80
90
100
10 100 1000 10000
efficiency[%]
load current [ m A ]
VCC=4V
VCC=7V
VCC=10V
VCC=14V
･fosc=1000kHz(RT=82kΩ)
・VCC=4,7,10,14V
･Vo1=1.1V
･L:4.7uH C5- K3LGA (MITSUM I)
0
10
20
30
40
50
60
70
80
90
100
10 100 1000 10000
efficiency[%]
load current[mA]
VCC=4V
VCC=7V
VCC=10V
VCC=14V
･fosc=1000kHz(RT=82kΩ)
・VCC=4,7,10,14V
･Vo2=1.5V
･L:4.7uH C5-K3LGA(MITS UMI)
0
10
20
30
40
50
60
70
80
90
100
10 100 1000 10000
efficiency[%]
load current [ m A ]
VCC=4V
VCC=7V
VCC=10V
VCC=14V
･fosc=1000kHz(RT=82kΩ)
・VCC=4,7,10,14V
･Vo3=5.0V
･L:4.7uH C5-K3LGA(MITS UMI)
0
10
20
30
40
50
60
70
80
90
100
10 100 1000 10000
efficiency[%]
load current [m A]
VCC=4V
VCC=7V
VCC=10V
VCC=14V
･fosc=1000kHz(RT=82kΩ)
・VCC=4,7,10,14V
･Vo4=3.3V
･L:4.7uH C5-K3LGA(MITSUM I)
●Efficiency
Figure.48 Efficiency – load current
CH1 Vo1=1.1V Figure.49 Efficiency – load current
CH2 Vo2=1.5V
Figure.50 Efficiency – load current
CH3 Vo3=5.0V Figure.51 Efficiency – load current
CH4 Vo4=3.3V
24/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Block explanation
・DCDC Block(4channe ls)
Followings is specification of each channel of this IC.
CH1 CH2 CH3 CH4
Type Buck Buck Buck-Boost Buck
Mode Current Current Voltage Current
Synchronous
rectifier ○ ○ ○ ○
FET constitution Internal P/N Internal P/N Internal P/N Internal P/N
Softstart Internal counter Internal counter Internal counter Internal counter
ON/OFF control Independent Independent Independent Independent
Table.1 speci f ication of each channel
・VREGA,VREGD,VREGB Block
VREGA is an internal regulator of 3.5V output. VREGD supply 3.5V gate bias voltage of Low side internal FET, VREGB
supply PVCC – 3.5V gate bias voltage of High side inter nal FET. Bypass these regulators to GND(VREGB to PVCC) with
a capacitor between 0.47μF and 2.2μF. We recommend capacitor of 1.0μF.
・Oscillator Block
OSC generates triangular waveform (slope waveform) with a resistor connected to RT terminal for setting frequency and
inputs into PWM comparator of each CH. Swithing frequency is set to 1.0MHz at RT = 82kΩ. Refer to the way of detailed
setting on p.26.
When CTL is turned ON with SYNC terminal input external clock, DC/DC converter switches at the frequenc y of the clock
input to SYNC terminal. Refer to p.29 for details of external synchronizati on.
・ERRORAMP Block
Error amplifiers monitor output voltage at INV terminals and output amplified error voltage at internal EOUT node.
Reference voltage of CH1 is 0.6V and accuracy is ±1. 67 %, and 0.8V for CH2-4 and accurac y is ±1.25%. Refer to p.26
for setting of output voltage.
・PWM Comparator Block
PWM comparators control switching duty of output FET by comparing SLOPE waveform from OSC and output voltage of
error amplifier.
・Current Mode Control Block
CH1, 2 and 4 operate with current mode PWM. In current mode DC/DC converter, main FET of synchronous rectifier
turns on at the edge of main clock, and turn off after detection of peak current in current comparator.
・Buck-Boost control Block
a block for controlling the switching duty of buck-boost DC/DC of CH3. This block consists of PWM comparator to
compare 1.0MHz SLOPE waveform and output of error amplifier, and Logic circuit to convert the output of PWM
comparator to ON/OFF signal of 4 internal output FETs.
・Softstart Block(SS)
Softstart block prevents the inrush current to charge the output capacitor at DC/DC start-up by softly starting up the
reference voltage of error amplifier. CH1 is 1.4msec(typ. at fosc=1MHz) and CH2-4 are 1.9msec(typ. at fosc=1MHz.)
Only CH1 has 50usec of delay time at stop. As in Figure .6, output is turned off after 50usec has passed from CTL1 is
turned to L.
25/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
・Channel Control Block(CH_CTL)
CTL1-4 terminals enable output of each channels to turn ON/OFF individually. When voltage of each terminal is over
2.5V and less than VCC voltage each channel turns ON, and when the terminals are open or voltage of them is over
-0.3V and less than 0.8V, it turns OFF. When all channels are turned OFF, IC becomes stand-by state. Each terminal
contains pull-down resistor of 400kΩ (t yp.) N ote that the o utput voltage of CH3 ma y s wing when CH4 is turned OFF while
CH3 is operating, so use this IC after confirming with much care that does not cause any problems in th at situation.
CTL LX VREGA VREGD VREGB OSC
1 2 3 4 1 2 31 32 4
L L L L L L Z L L N N N N
H L L L A L Z L L A A A A
L H L L L A Z L L A A A A
L L H L L L A A L A A A A
L L L H L L Z L A A A A A
H H H H A A A A A A A A A
Table.2 CTL table
・Short Circuit Protection Circuit(SCP)
Output short protect circuit with timer latch. When output of any channels drop, output of error amplifier rises. And after it
reaches to 3.0V (typ.), SCP block start to charge the output capacitor at SCP terminal with current of 5uA output of all
channels stop when the terminal voltage of SCP reaches to 0.5V. To release short circuit protection latch state, turn CTL
terminal to “L” level and return to “H”, or restart power supply. When you don’t use short circuit protection, connect SCP
terminal to GND. Refer to p.11, 12 about timing chart of SCP operation.
・Undervoltage Lock Out(UVLO)
Undervoltage lock out prevents IC malfunctions that could otherwise occur due to power supply fluctuation at power on
or abrupt power off. This system turns off output of each channel and fix the output voltage of error amplifier to “L” when
the VCC voltage becomes lower than 3.4V(typ.), or anyone of VREGA, VREGD voltage becomes lower than 3.0V(typ.)
Threshold voltage of each UVLO has hysteresis of 0.1V to prevent malfunct ions in transie nt swing of power supply
around threshold voltage. Refer to p.10 about timing chart of UVLO operation.
・Thermal Shut Down(TSD)
The thermal shutdown circuit is protection the IC against thermal runaway and heat damage. When the temperature
reaches to TSD threshold (typ. 175℃), the output of a ll channels, VREGA, VREGD, VREGB are turned off. Threshold of
TSD has hysteresis of 25℃ to prevent malfunctions in transient swing of temperature around threshold. Notice is written
in p.34.
・Power Good Circuit(PG)
PG is a NMOS open drain form terminal and when SCP is detected, inner NMOS FET turns on and pull-down with
350Ω(typ.) Refer to p.11,12 about PG operation.
・CH1,2 Softstart Good Circuit(CH1G,CH2G)
CH1G, CH2G is inverter output form terminals power supply of them is V REGA and th ey detect finish of softstart of CH1
and CH2. When CTL terminal of each channel is L or while output voltage is lower than 90% of setting output voltage
after CTL terminals are turned on, the output of these terminals is L. And at the end of softstart, when output voltage
becomes greater than 90% of setting output voltage, the output voltage of CH1,2G terminal turns to H.( As shown in
Figure. 57, CH1G output turns to L when CTL1 is turned off, but while CH1 is in the stop delay time, output of CH1
continues.) Note that the output of CH1,2G terminals is kept H when output voltage drops below 90% of setting output
voltage after softstart finished. Startup sequence of each channel can be controlled by connecting CH1,2G terminals to
CTL terminals of other channels. Refer to p.30 about timing chart of CH1,2 softstart good function.
・Light Load Mode Control Circuit(SEL)
Control mode of CH2 and 4 is selected between PWM mode and lig ht load mode by S EL terminal. W hen voltage of SEL
terminal is over 2.5V and less than VCC voltage, light load mode is enabled. And when the terminal is open or voltage of
that is over -0.3V and less than 0.8V, it is disabled. SEL terminal contains pull-down resistor of 400kΩ (typ.) When you
use this function, we recommend to short SEL terminal to VREGA.
・Over Current Protection Circuit(OCP)
OCP prevents destruction of IC from over current flow through internal FET in overload situation or output shorted to
GND by detecting input curre nt. When OCP is detected, output switching duty is down to minimum duty, and thus, input
current is limited and output voltage decrease. Finally, SCP operates and all DC/DC output stops safely. Refer to p.4
about detect current limit. About CH3, OCP is detected when output current becomes greater than 1.8A under the
conditions of VO3 output voltage setting is 5.0V.
.
26/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●peripheral components setting
・Setting the switching frequency
The switching frequency FOSC is set by the resistor connected to RT terminal. Connect 82kΩ to set to 1.0MHz.
Switching frequency is calculated as below. Confirm the frequency with IC after select RT value with this equation.
Fosc = × 1000[kHz]
82
RRT
・Setting output voltages
Figure.52 Setting output voltages
Output voltages of each channel are determined b y feedback resistor R1 and R2 as equation (1) for CH1 and (2) for CH2
to 4.
This IC contains phase compensation, so choose sum of R1 and R2 value between 90kΩ to 1MΩ for CH1 and CH2,
100kΩ to 500kΩ for CH3 and 70kΩ to 300kΩ for CH4, and sufficiently confirm there is no abnormal oscillations.
・Terminal manipulate method for not used channel
Set each terminal of the channel as below when you don’t use.
Figure.53 Terminal manipulate method for not used channel
27/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
・Setting of SCP timer
Monitoring the output voltages of error amplifier (EOUT voltage), if the voltages become over 3.0V(typ.), the output of
SCPCOMP turns to L, and transistor Q1 will turn off. Thus the current of 5uA is supplied to Cscp. DC/DC outputs stop
when voltage of Cscp reaches to the thresho ld voltage (Vtsc ≒0.5V). The time from short circuit detection to outputs stop
is determined as below.
To reset from SCP latch state, turn CTL to L.
Refer to p.11, 12 about SCP operating timing chart.
EOUT1－
＋
INV1
EOUT2
－
＋
INV2
EOUT3－
＋
INV3
EOUT4－
＋
INV4
SCP CSCP
5uA
3.0V
－
＋
Vo1
Vo2
Vo3
Vo4 Q1
－
－
－
Figure.54 Short Circuit Protection
・About output voltage setting of CH1,2 and 4
The switching duty of CH1, 2 and 4 can reach to 100% but they have maxi mum duty cycle between 90 to 95%. Thus,
when voltage difference between input and output is small or load current is large under the condition of SCP is enabled,
SCP may operate. Normally, switching ON Duty of buck converter is calculated as VOUT / VIN, but in fact, it is VOUT /
(VIN-Io×Ron) with there is load current. When switching duty become above maximum duty, the output switching turns
to 100% duty, but the state of 100% duty output is only allowed transiently before SCP operates. So, set output duty not
to exceed the maximum duty cycle.
28/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
・Selection of inductor
We recommend the ones of those current rating is sufficiently larger than
the peak current value Ipeak written as below and DCR is small and
shield type.
The inductor value has much influence to the ripple current.
As shown in the equation below, the larger the inductor value is or higher
the switching frequency is, the smaller ripple current becomes
Generally, choose inductance value as that the ripple current is within 20% to 50% of the output maximum current.
If the inductor current exceeds the maximum rating current of the inductor, a saturation of inductor occur s and may cause
an abnormal degradatio n of efficienc y or oscillation. So, choose inductor value with sufficient margin not to peak current
exceeds maximum rating current of the inductor.
・Selection of output capacitor
We recommend a low ESR ceramic capacitor as output capacitor to reduce output ripple voltage. And , under
consideration of its DC bias characteristics, choose the ones of those maximum rating voltage is sufficiently higher than
output voltage.
The output ripple voltage is calculated as in the equation below with a ceramic capacitor.
Confirm the ripple voltage with IC after choose the capacitor with this equation to the output ripple voltage is within
allowed value.
ΔIL
Figure.55 ripple current of inductor
29/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
・Setting of external synchronization
When you use external synchronization function, stop external clock after IC stops. If it is stopped before IC stops,
discharge of triangle waveform (slope waveform) is interrupted and the internal oscillator stops, thus, DC/DC stops.
Additionally, force power supply voltage of IC before start to input the external clock to SYNC terminal. There is an
anti-ESD diode bet ween SYNC terminal and VCC terminal, so, before supply voltage is forced, current flows from SYNC
terminal to VCC terminal through the diode.
The external synchronization function, the switching frequency of DC/DC is synchronized with any external clock, works
by turning on CTL under the condition of inputting external clock pulse to SYNC terminal.
This IC controls to increase RTSS voltage in order to maintain the top voltage of the internal triangle waveform when
external synchronizati on is used. If the frequency of input clock is out of the possible RTSS voltage range, the IC cannot
maintain the height of internal slope waveform, so, set the frequency of in put clock within 20% higher than the freque ncy
that is determined by the resistor connected to RT terminal as below..
frequency set by resistor at RT ＜ frequency input to SYNC ＜ (frequency set by resistor at RT x 1.2)
The block of RTSS terminal start with the time constant determined by the capacitor connected to RTSS terminal. To
prevent malfunction in startup, internal SS nodes are discha rged b efore RTSS voltage reaches to 0.35V. And also, before
RTSS voltage reaches to 0.35V, RTSS output current increase to about 60uA to speed up the startup. The time RTSS
voltage reaches to 0.35V is calculated as following equation.
(ex. TRTSS1≒60µsec @ CRTSS=10000pF)
After RTSS voltage reaches to 0.35V, RTSS output current decrease to 5.0uA, and the time RTSS voltage reached to
0.5V is calculated as following equation..
(ex. TRTSS2≒300µsec @ CRTSS=10000pF)
RTSS voltage is maintained by turning current sink and source repeat edly, and switch of current flow is controlled by rise
edge of external clock, so, if the ca pacitor value connected to RTSS terminal is too small,(especiall y switching fre quency
is low) the range of voltage swing from one clock to the next may increase. And that may cause inaccuracy of, for
example, maximum duty. We recommend around 10000pF when switching frequency is around 1MHz. Note that if you
select a larger value than that , stability will in crease but the time before o utput softstart lengthens.
30/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
・CH1, 2 Softstart Good function
CH1 and CH2 have softstart good function that detects the finish of softstart of each channel, and CH1G terminal and
CH2G terminal are output terminal of each. When CTL terminal of each channel is off or while output voltage is lower than
90% of setting output voltage after CTL terminals are turned on, the output of these terminals is L. And at the end of
softstart, when output volta ge becom es greater than 90% of setting output voltage, the output voltage of CH1,2G terminal
turns to H. As shown in Figure. 56 below, we can control the start up order of each channel by connecting CH1G or CH2G
terminal to CTL terminal of other channels. If you connect CH1G terminal to CTL2 and CTL4, after softstart of CH1 finish,
CTL2 and CTL4 turn to H and CH2 and 4 start. After that, CH2 finish its softstart, and thus, CTL3 it is connected to CH2G
become H and CH3 start operating. In the off sequence, if you turn CTL1 off, all channels will stop (Figure.57)
When you don’t use CH1,2 softstart good function, make CH1G, CH2G terminal opened.
Figure.56 example of startup sequence control
CTL1
Vo1
CH1G
=CTL2/CTL4
90%
Vo2/Vo4 90%
CH2G
=CTL3
Vo3
When Vo1 reaches to
90% of setting voltage,
CH1G turn L to H and
CH2,4 turn ON.
When Vo2, 4 reach to
90% of setting voltage,
CH2G turns L to H and
CH3 turns ON.
CH1G turns H to L by
CTL1 OFF and CH2,4 turn
OFF. And that, CH2G
turns H to L , so CH3 turns
OFF
CH1 stop
50usec after
CTL1 OFF.
Figure.57 timing chart of startup sequence control
31/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●PCB layout considerations
・Connect input capacitor(bypass capacitor : Cin_bp) to PVCC and PGND through shortest line.
→Its aim is to shorten the current loop and reduce parasitic impedanc e. Switching current is supplied from power supply
Vin(Cin), but there are parasitic impedance or inductance in capacitors or boards, so current suppl y from bypass
capacitor put near the IC when current flow is rapidly changed.
It is a desirable constitution that a large capacitance electrolytic capacitor is used as Cin and a ceramic capacitor is
used as a bypass capacitor.
・Layout GND and PGND line wide and short as possible.
→In this IC, subcontact is connected GND and PGND. Because of this, if you separate GND and PGND, and connect
them at one point, GND and PGND are connected inside of IC through subcontact. And if inner impedance is lower
than impedance of outer connection, the current of PGND terminal flows down to GND terminal. This may have an
effect on internal bandgap voltage or oscillator and so on. So,it is needed to reduce outer impedance of PGND line
lower than inner impedance of GND line and layout ,GND and PGND line wide an d short.
・To avoid interf erence, layout between feedback resistor a nd feedback terminals short as possible. An interference of noise
to feedback terminals(INV1-4) may cause output abnormal oscillation.
→An interference of noise to feedback terminals(INV1-4) may cause output abnormal oscillation.
・Terminal voltage of VCC and PVCC not exceed a bsolute maximum ratings.
→If input capacitor are placed far from IC, parasitic inductance of PCB may cause ringing and the terminal voltage
exceed the absolute maximum ratings. For reference, place input capacitor within 5.0mm from IC under the condition
of that, thickness of PCB pattern is 35um, width of it is 1.0mm.
Figure.58 effect of input capacitor
Figure.59 effect of common impedance
32/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Pin equivalent circuit
Name Pin equivalent circuit Name Pin equivalent circuit
G6
G5
G4
B3
VCC
GND
PVCC
PGND
VCC PVCC
PGND
GND
C4
D3
C6
C5
C7
CTL1
CTL2
CTL3
CTL4
SEL
SEL
CTL1-4
VCC
GND
F3
D4
E4
E5
INV1
INV2
INV3
INV4
INV1-4
GND
VREGA
E3 SYNC
B4 SCP
SCP
GND
VREGA VREGA
B5 PG
D5 RTSS
RTSS
GND
VREGA VREGA
F6 RT RT
GND
VREGA VREGA
F5
G3 VREGA
VREGD
VREGA
VREGD
※VCC
※VCC※VCC
※PVCC for VREGD PVCC
VCC
GND
F4 VREGB
Figure.60 Pin equivalent circuit 1
33/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
0
0.5
1
1.5
2
0 25 50 75 100 125 150
PowerDissipation:Pd[W]
AmbientTemperature：Ta[℃]
Name Pin equivalent circuit Name Pin equivalent circuit
G1,G2
A1,A2
F7,G7
F4
E1,F1
B1,B2
E6,E7
D1,D2
C1,C2
D6,D7
PVCC1
PVCC2
PVCC4
VREGB
Lx1
Lx2
Lx4
PGND1
PGND2
PGND4
A3
F4
A4
A5,A6
PVCC3
VREGB
Lx31
PGND3
B7
A7,B6
A5,A6
VO3
Lx32
PGND3
Lx32
VO3
PGND3
GND
F2
E2 CH1G
CH2G
VREGA
CH1G
CH2G
GND
●Thermal Derating Curves
When mounted on a 50mm × 50mm × 1.75mm glass
epoxy 8layers PCB.
Should be derated b y 12.5mW/℃ Ta=25℃ or more.
Heat design should consider tolerance dissipation during
actual use and margins which should be set plenty of room.
Figure.61 Pin equivalent circuit 2
Figure.62 Power dissipation
34/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
●Usage Notes
1.) Absolute maximum ratings
This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute
maximum ratings. If the device is d estroyed by exceeding t he recommen ded maximum r atings, the failu re mode will be
difficult to determine. (E.g. short mode, open mode.) Therefore, physical protection counter-measures (like fuse) should
be implemented when operating conditions beyond the absolute maximum ratings anticipated.
2.) GND potential
Make sure GND is connected at lowest potential. All pins must not have voltage below GND.
3.) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating
conditions.
4.) Pin shorts and mounting errors
Use caution direction and position the IC for mounting on printed circuit boards. Improper mounting may result in
damage the IC. In addition, Output-output short and output-power supply/ground short co ndition may destroy the IC.
5.) Actions in strong magnetic field
Exposing the IC within a strong magnet ic field are may cause malfunction.
6.) Common impedance
Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize
ripple as much as possible. (by making wiring as short and wide as possible or rejecting ripple by incorporating
inductance and capacitance.)
7.) Thermal shutdown circuit (TSD circuit)
This IC incorporates a built-in thermal shutdown circuit (T SD circuit.) The TSD circuit is designed o nly to shut the IC off
to prevent from thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not continue to use
the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed.
8.) Rush current at the time of power supply injection
An IC which has plural power supplies, or CMOS IC could have momentary rush current at the time of power supply
injection. Please take care about power supply coupling ca pacity and width of power supply and GND pattern wiring.
9) Influence by strong light
When large amount of light like strobe is come in, IC can act under wrong operation. Please make light removal
system and check operations adequately.
10) IC terminal input
. This IC is a monolithic IC, and between each element there is a P+ isol ation and P substrate for element separation.
There is a P-N junction formed between this P-layer and each element’s N-layer, which makes up various parasitic
elements.
For example, when a resistor and a transistor are connected with a terminal as in Figure. 63:
○When GND＞(terminal A) at the res istor, or GND＞(terminal B) at the transistor (NPN) , the P-N junction operat es as
a parasitic diode.
○Also, when GND＞(terminal B) at the transistor, a parasitic NPN transistor operates b y the N-layer of other elem ents
close to the aforementioned parasitic diode.
With the IC’s configuration, the production of parasitic elements by the relationships of the electrical potentials is
inevitable. The operation of the parasitic elements can also interfere with the circuit operation, leading to malfunction
and even destruction.
Therefore, uses which caus e the parasitic elements to operate, such as appl ying voltage to the input terminal which is
lower than the GND (P-substrate), should be avoided.
Figure. 63 Simplified structure of bipolar IC
P substrate
N
P
N N
P＋
P＋
（Terminal A）
Parasitic
element
resistor
Parasitic element
transistor(NPN)
～
～
GND
P substrate
NP
ＮN
P＋
P＋
（Terminal B）B
N
E
C
GND
～
～
（Terminal Ａ）
GND
Parasitic element
35/35
Datasheet
Datasheet
BD9866GUL
TSZ02201-0B2B0A400010-1-2
17.APR.2013 Rev.001
© 2013 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
Tape
Quantity
Direction
of feed
Embossed carrier tape （熱圧着方式）
2,500pcs / R eel
E2
Reel Direction of feed
1 Pin
1234 1234 1234 1234 1234 1234
●Ordering Information
B D 9 8 6 6 G U L E 2
Part Number
Package
GUL:VCSP50L3
Packaging and forming specific ation
E2:Embossed tape and reel
●Marking Diagram
Figure. 64 Package dimens ions
Figure. 65 Direction of feed
Figure. 65 Marking diagram
Datasheet
Datasheet
Notice - GE Rev.002
© 2014 ROHM Co., Ltd. All rights reserved.
Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN USA EU CHINA
CLASSⅢ CLASSⅢ CLASSⅡb CLASSⅢ
CLASSⅣ CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Datasheet
Datasheet
Notice - GE Rev.002
© 2014 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
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When disposing Products please dispose them properly using an authorized industry waste company.
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Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
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1. All information and data including but not limited to application example contained in this document is for reference
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third parties with respect to the information contained in this document.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
DatasheetDatasheet
Notice – WE Rev.001
© 2014 ROHM Co., Ltd. All rights reserved.
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Datasheet
Part Number bd9866gul
Package VCSP50L3
Unit Quantity 2500
Minimum Package Quantity 2500
Packing Type Taping
Constitution Materials List inquiry
RoHS Yes
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