FEATURES Dual-channel, 256-position resolution 10 k, 50 k, and 100 k nominal terminal resistance Nonvolatile memory maintenance of wiper settings Predefined linear increment/decrement instructions Predefined 6 dB step log taper increment/decrement instructions SPI-compatible serial interface Wiper settings and EEMEM readback 3 V to 5 V single-supply operation 2.5 V dual-supply operation 14 bytes of general-purpose user EEMEM Permanent memory write protection 100-year typical data retention (TA = 55C) FUNCTIONAL BLOCK DIAGRAM VDD CS AD5232 ADDR DECODE RDAC1 REGISTER CLK SDI W1 SDO PR EEMEM1 RDAC1 RDAC2 REGISTER POWER-ON RESET B1 A2 W2 WP RDY EEMEM CONTROL EEMEM2 RDAC2 B2 14 BYTES USER EEMEM APPLICATIONS Mechanical potentiometer replacement Instrumentation: gain and offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, and time constants Programmable power supply Low resolution DAC replacement Sensor calibration A1 SERIAL INTERFACE GND VSS 02618-001 Data Sheet Nonvolatile Memory, Dual 256-Position Digital Potentiometer AD5232 Figure 1. GENERAL DESCRIPTION The AD5232 device provides a nonvolatile, dual-channel, digitally controlled variable resistor (VR) with 256-position resolution. This device performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. The versatile programming of the AD5232, perormed via a microcontroller, allows multiple modes of operation and adjustment. In the direct program mode, a predetermined setting of the RDAC registers (RDAC1 and RDAC2) can be loaded directly from the microcontroller. Another important mode of operation allows the RDACx register to be refreshed with the setting previously stored in the corresponding EEMEM register (EEMEM1 and EEMEM2). When changes are made to the RDACx register to establish a new wiper position, the value of the setting can be saved into the EEMEMx register by executing an EEMEM save operation. After the settings are saved in the EEMEMx register, these values are automatically transferred to the RDACx register to set the wiper position at system power-on. Such operation is enabled by the internal preset strobe. The preset strobe can also be accessed externally. All internal register contents can be read via the serial data output (SDO). This includes the RDAC1 and RDAC2 registers, the corresponding nonvolatile EEMEM1 and EEMEM2 registers, and the 14 spare USER EEMEM registers that are available for constant storage. The basic mode of adjustment is the increment and decrement command instructions that control the wiper position setting register (RDACx). An internal scratch pad RDACx register can be moved up or down one step of the nominal resistance between Terminal A and Terminal B. This step adjustment linearly changes the wiper to Terminal B resistance (RWB) by one position segment of the device's end-to-end resistance (RAB). For exponential/ logarithmic changes in wiper setting, a left/right shift command instruction adjusts the levels in 6 dB steps, which can be useful for audio and light alarm applications. The AD5232 is available in a thin, 16-lead TSSOP package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C. An evaluation board, the EVAL-AD5232-10EBZ, is available. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2001-2011 Analog Devices, Inc. All rights reserved. AD5232 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital Input/Output Configuration........................................ 14 Applications....................................................................................... 1 Serial Data Interface................................................................... 15 Functional Block Diagram .............................................................. 1 Daisy-Chaining Operation........................................................ 15 General Description ......................................................................... 1 Advanced Control Modes ......................................................... 17 Revision History ............................................................................... 2 Using Additional Internal, Nonvolatile EEMEM................... 18 Specifications..................................................................................... 3 Terminal Voltage Operating Range ......................................... 18 Electrical Characteristics--10 k, 50 k, 100 k Versions .. 3 Detailed Potentiometer Operation .......................................... 18 Interface Timing Characteristics................................................ 5 Programming the Variable Resistor......................................... 19 Absolute Maximum Ratings............................................................ 7 Programming the Potentiometer Divider............................... 20 Thermal Resistance ...................................................................... 7 Operation from Dual Supplies ................................................. 20 ESD Caution.................................................................................. 7 Application Programming Examples ...................................... 20 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Equipment Customer Start-up Sequence for a PCB Calibrated Unit with Protected Settings................ 21 Test Circuits..................................................................................... 12 Flash/EEMEM Reliability.......................................................... 21 Theory of Operation ...................................................................... 14 Evaluation Board ........................................................................ 21 Scratch Pad and EEMEM Programming................................. 14 Outline Dimensions ....................................................................... 22 Basic Operation .......................................................................... 14 Ordering Guide .......................................................................... 22 EEMEM Protection.................................................................... 14 REVISION HISTORY 09/11--Rev. A to Rev. B Change to Resistor Noise Voltage Parameter in Table 1.............. 4 10/09--Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Data Sheet Title ............................................................ 1 Changes to Features Section............................................................ 1 Changes to Applications Section .................................................... 1 Change to Wiper Resistance Parameter, Table 1 .......................... 3 Changes to CS Rise to RDY Fall Time Parameter, Table 2 ..........5 Changes to Figure 2 and Figure 3....................................................6 Changes to Figure 24...................................................................... 12 Added Figure 32 ............................................................................. 13 Changes to Serial Data Interface Section .................................... 15 Changes to Programming the Variable Resistor Section .......... 19 Changes to Ordering Guide .......................................................... 22 10/01--Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet AD5232 SPECIFICATIONS ELECTRICAL CHARACTERISTICS--10 k, 50 k, 100 k VERSIONS VDD = 3 V 10% or 5 V 10% and VSS = 0 V, VA = +VDD, VB = 0 V, -40C < TA < +85C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS, RHEOSTAT MODE Resistor Differential Nonlinearity 2 Resistor Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient Wiper Resistance POTENTIOMETER DIVIDER MODES Resolution Differential Nonlinearity 3 Integral Nonlinearity3 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range 4 Capacitance Ax, Bx5 Capacitance Wx 5 Common-Mode Leakage Current5, 6 DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High (SDO and RDY) Output Logic Low Input Current Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current 7 Negative Supply Current Power Dissipation 8 Power Supply Sensitivity5 Symbol Conditions Specifications apply to all VRs Min Typ 1 Max Unit R-DNL R-INL RAB RAB/T RW RWB, VA = NC RWB, VA = NC -1 -0.4 -40 1/2 +1 +0.4 +20 LSB % FS % ppm/C N DNL INL VW/T Code = half scale VWFSE VWZSE Code = full scale Code = zero scale VA, VB, VW CA, CB CW ICM f = 1 MHz, measured to GND, code = half-scale f = 1 MHz, measured to GND, code = half scale VW = VDD/2 8 -1 -0.4 1/2 With respect to GND, VDD = 5 V With respect to GND, VDD = 5 V With respect to GND, VDD= 3 V With respect to GND, VDD = 3 V With respect to GND, VDD = +2.5 V, VSS = -2.5 V With respect to GND, VDD = +2.5 V, VSS = -2.5 V RPULL-UP = 2.2 k to 5 V IOL = 1.6 mA, VLOGIC = 5 V VIN = 0 V or VDD VDD VDD/VSS IDD IDD(PG) IDD(XFR) ISS VSS = 0 V 100 +1 +0.4 Bits LSB % FS ppm/C 0 3 % FS % FS VDD V pF pF A 15 -3 0 VSS VIH VIL VIH VIL VIH VIL VOH VOL IIL CIL PDISS PSS 600 50 200 IW = 100 A, VDD = 5.5 V, code = 0x1E IW = 100 A, VDD = 3 V, code = 0x1E 45 60 0.01 1 2.4 0.8 2.1 0.6 2.0 0.5 4.9 0.4 2.5 4 2.7 2.25 VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND VDD = 5 V 10% Rev. B | Page 3 of 24 0.9 5.5 2.75 10 V V V V V V V V A pF 3.5 35 3 9 V V A mA mA 3.5 0.018 0.002 10 0.05 0.01 A mW %/% AD5232 Parameter DYNAMIC CHARACTERISTICS5, 9 Bandwidth Total Harmonic Distortion Data Sheet Symbol THDw VW Settling Time tS Resistor Noise Voltage Crosstalk (CW1/CW2) eN_WB CT Analog Crosstalk (CW1/CW2) CTA Conditions Min -3 dB, BW_10k, R = 10 k VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 50 k, 100 k VDD = 5 V, VSS = 0 V, VA = VDD, VB = 0 V, VW = 0.50% error band, Code 0x00 to Code 0x80 for RAB = 10 k/50 k/100 k RWB = 5 k, f= 1 kHz VA = VDD, VB = 0 V, measure VW with adjacent VR making full-scale code change VA1 = VDD, VB1 = 0 V, measure VW1 with VW2 = 5 V p-p @ f = 10 kHz; Code1 = 0x80; Code2 = 0xFF FLASH/EE MEMORY RELIABILITY Endurance 10 Data Retention 11 Typ 1 Unit 500 0.022 0.045 0.65/3/6 kHz % % s 9 -5 nV/Hz nV-sec -70 dB 100 kCycles Years 100 1 Max Typical parameters represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW ~ 50 A @ VDD = 2.7 V and IW ~ 400 A @ VDD = 5 V for the RAB = 10 k version, IW ~ 50 A for the RAB = 50 k version, and IW ~ 25 A for the RAB = 100 k version (see Figure 22). 3 INL and DNL are measured at VW with the RDACx configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = VSS. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions (see Figure 23). 4 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. Dual supply operation enables ground-referenced bipolar signal adjustment. 5 Guaranteed by design; not subject to production test. 6 Common-mode leakage current is a measure of the dc leakage from any A, B, or W terminal to a common-mode bias level of VDD/2. 7 Transfer (XFR) mode current is not continuous. Current is consumed while the EEMEMx locations are read and transferred to the RDACx register (see Figure 13). 8 PDISS is calculated from (IDD x VDD) + (ISS x VSS). 9 All dynamic characteristics use VDD = +2.5 V and VSS = -2.5 V, unless otherwise noted. 10 Endurance is qualified to 100,000 cycles per JEDEC Std. 22, Method A117 and measured at -40C, +25C, and +85C. Typical endurance at +25C is 700,000 cycles. 11 The retention lifetime equivalent at junction temperature (TJ) = 55C, as per JEDEC Std. 22, Method A117. Retention lifetime, based on an activation energy of 0.6 eV, derates with junction temperature as shown in Figure 44 in the Flash/EEMEM Reliability section. The AD5232 contains 9,646 transistors. Die size = 69 mil x 115 mil, 7,993 sq. mil. 2 Rev. B | Page 4 of 24 Data Sheet AD5232 INTERFACE TIMING CHARACTERISTICS All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V. Table 2. Parameter 1, 2 Clock Cycle Time (tCYC) CS Setup Time CLK Shutdown Time to CS Rise Input Clock Pulse Width Data Setup Time Data Hold Time CS to SDO-SPI Line Acquire CS to SDO-SPI Line Release CLK to SDO Propagation Delay 4 CLK to SDO Data Hold Time CS High Pulse Width 5 CS High to CS High5 RDY Rise to CS Fall CS Rise to RDY Fall Time Store/Read EEMEM Time 6 Symbol t1 t2 t3 t4, t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 CS Rise to Clock Rise/Fall Setup Preset Pulse Width (Asynchronous) Preset Response Time to RDY High t17 tPRW tPRESP Conditions Clock level high or low From positive CLK transition From positive CLK transition RP = 2.2 k, CL < 20 pF RP = 2.2 k, CL < 20 pF Min 20 10 1 10 5 5 Typ 3 40 50 50 0 10 4 0 0.15 Applies to Command Instruction 2, Command Instruction 3, and Command Instruction 9 Not shown in timing diagram PR pulsed low to refresh wiper positions 1 Max 10 50 70 0.3 25 Unit ns ns tCYC ns ns ns ns ns ns ns ns tCYC ns ms ms ns ns s Guaranteed by design; not subject to production test. See the Timing Diagrams section for the location of measured values. Typicals represent average readings at 25C and VDD = 5 V. 4 Propagation delay depends on the value of VDD, RPULL-UP, and CL. 5 Valid for commands that do not activate the RDY pin. 6 RDY pin low only for Command Instruction 2, Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and the PR hardware pulse: CMD_8 ~ 1 ms, CMD_9 = CMD_10 ~ 0.12 ms, and CMD_2 = CMD_3 ~ 20 ms. Device operation at TA = -40C and VDD < 3 V extends the save time to 35 ms. 2 3 Rev. B | Page 5 of 24 AD5232 Data Sheet Timing Diagrams CPHA = 1 t12 CS t13 t3 t1 t2 CLK CPOL = 1 t5 B15 B0 t17 t4 t7 t6 HIGH OR LOW SDI B15 (MSB) t8 t11 t10 t9 B15 (MSB) B16* SDO HIGH OR LOW B0 (LSB) B0 (LSB) t14 t15 t16 RDY 02618-002 NOTES 1. B24 IS AN EXTRA BIT THAT IS NOT DEFINED, BUT IT IS USUALLY THE LSB OF THE CHARACTER THAT WAS PREVIOUSLY TRANSMITTED. 2. THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. Figure 2. CPHA = 1 CPHA = 0 CS t12 B15 (MSB) t2 t1 t3 t5 B15 CLK CPOL = 0 B0 (LSB) t13 t17 B0 t4 t7 SDI t6 HIGH OR LOW B15 (MSB IN) t8 HIGH OR LOW B0 (LSB) t10 t11 t9 B15 (MSB OUT) SDO B0 (LSB) t14 * t15 t16 NOTES 1. THIS EXTRA BIT IS NOT DEFINED, BUT IT IS USUALLY THE MSB OF THE CHARACTER THAT WAS JUST RECEIVED. 2. THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. Figure 3. CPHA = 0 Rev. B | Page 6 of 24 02618-003 RDY Data Sheet AD5232 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter VDD to GND VSS to GND VDD to VSS VA, VB, VW to GND AX - BX, AX - WX, BX - WX Intermittent1 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range2 Maximum Junction Temperature (TJ max) Storage Temperature Range Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Package Power Dissipation Rating -0.3 V, +7 V +0.3 V, -7 V 7V VSS - 0.3 V, VDD + 0.3 V 20 mA 2 mA -0.3 V, VDD + 0.3 V -40C to +85C 150C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 16-Lead TSSOP (RU-16) 215C 220C (TJ max - TA)/JA ESD CAUTION 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Includes programming of nonvolatile memory. Rev. B | Page 7 of 24 JA 150 JC 28 Unit C/W AD5232 Data Sheet CLK 1 SDI 2 16 RDY 15 CS SDO 3 AD5232 14 PR GND 4 TOP VIEW (Not to Scale) 13 WP VSS 5 12 VDD A1 6 11 A2 W1 7 10 W2 B1 8 9 B2 02618-004 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 Mnemonic CLK SDI SDO 4 5 6 7 8 9 10 11 12 13 GND VSS A1 W1 B1 B2 W2 A2 VDD WP 14 PR 15 16 CS RDY Description Serial Input Register Clock. Shifts in one bit at a time on positive clock edges. Serial Data Input. The MSB is loaded first. Serial Data Output. This open-drain output requires an external pull-up resistor. Command Instruction 9 and Command Instruction 10 activate the SDO output (see Table 8). Other commands shift out the previously loaded SDI bit pattern delayed by 16 clock pulses, allowing daisy-chain operation of multiple packages. Ground, Logic Ground Reference. Negative Power Supply. Connect to 0 V for single-supply applications. Terminal A of RDAC1. Wiper Terminal W of RDAC1, ADDR (RDAC1) = 0x0. Terminal B of RDAC1. Terminal B of RDAC2. Wiper Terminal W of RDAC2, ADDR (RDAC2) = 0x1. Terminal A of RDAC2. Positive Power Supply. Write Protect. When active low, WP prevents any changes to the present register contents, except PR, Command Instruction 1, and Command Instruction 8, which refresh the RDACx register from EEMEM. Execute an NOP instruction (Command Instruction 0) before returning WP to logic high. Hardware Override Preset. Refreshes the scratch pad register with current contents of the EEMEMx register. Factory default loads Midscale 0x80 until EEMEMx is loaded with a new value by the user (PR is activated at the logic high transition). Serial Register Chip Select, Active Low. Serial register operation takes place when CS returns to logic high. Ready. This active-high, open-drain output requires a pull-up resistor. Identifies completion of Command Instruction 2, Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and PR. Rev. B | Page 8 of 24 Data Sheet AD5232 TYPICAL PERFORMANCE CHARACTERISTICS 2.00 2000 1.50 RHEOSTAT MODE TEMPCO (ppm/C) VDD = 2.7V VSS = 0V 1.75 1.25 INL ERROR (LSB) 1.00 INL TA = -40C 0.75 0.50 INL TA = +25C 0.25 0 -0.25 INL TA = +85C -0.50 -0.75 -1.00 -1.25 -1.50 VDD = 5V TA = -40C/+85C VA = NO CONNECT RWB MEASURED 1500 1000 500 0 64 128 DIGITAL CODE 192 256 0 02618-005 0 Figure 5. INL vs. Code; TA = -40C, +25C, +85C Overlay 96 128 160 CODE (Decimal) 192 224 256 70 1.50 POTENTIOMETER MODE TEMPCO (ppm/C) VDD = 2.7V VSS = 0V 1.75 1.25 1.00 DNL ERROR (LSB) 64 Figure 8. RWB/T vs. Code; RAB = 10 k, VDD = 5 V 2.00 DNL TA = -40C 0.75 0.50 DNL TA = +25C 0.25 0 -0.25 -0.50 DNL TA = +85C -0.75 -1.00 -1.25 -1.50 0 64 128 DIGITAL CODE 192 256 VDD = 5V TA = -40C/+85C VA = 2V VB = 0V 60 50 40 30 20 10 0 -10 02618-006 -1.75 -2.00 32 0 Figure 6. DNL vs. Code; TA = -40C, +25C, +85C Overlay 32 64 96 128 160 CODE (Decimal) 192 224 256 02618-009 -2.00 02618-008 -1.75 Figure 9. VWB/T vs. Code; RAB = 10 k, VDD = 5 V 0.20 1 VDD = 5.5V VSS = 0V TA = 25C 0.15 VDD = +2.5V VSS = -2.5V VCM = 0V 0.1 ICM (A) 0.05 0 -0.05 0.01 -0.10 -0.20 0 32 64 96 128 160 CODE (Decimal) 192 224 256 0.001 -50 -35 -20 -5 10 25 40 55 TEMPERATURE (C) Figure 10. ICM vs. Temperature (See Figure 30) Figure 7. R-DNL vs. Code; RAB = 10 k, 50 k, 100 k Overlay Rev. B | Page 9 of 24 70 85 02618-010 -0.15 02618-007 R-DNL (LSB) 0.10 AD5232 Data Sheet 4 12 6 VDD = 5.5V f-3dB = 500kHz, R = 10k 0 f-3dB = 45kHz, R = 100k GAIN (dB) IDD (A) -6 2 VDD = 2.7V f-3dB = 95kHz, R = 50k -12 -18 -24 -36 -35 -20 -5 10 25 40 55 70 85 TEMPERATURE (C) -42 1k 02618-011 0 -50 10k 100k FREQUENCY (Hz) 1M 02618-014 VIN = 100mV rms VDD = +2.5V VSS = -2.5V RL = 1M TA = +25C -30 Figure 14. -3 dB Bandwidth vs. Resistance Figure 11. IDD vs. Temperature 10 T VDD = 5V TA = 25C FILTER = 22kHz CS 1 THD + NOISE (%) 1 CLK 2 SDI 0.1 RAB = 10k 3 RAB = 50k, 100k 0.01 CH1 5.00V CH3 5.00V CH2 5.00V CH4 10.00V M 2.00ms 0.001 10 Figure 12. IDD vs. Time (Save) Program Mode 100 1k FREQUENCY (Hz) 10k 100k 02618-015 4 02618-012 IDD 2mA/DIV Figure 15. Total Harmonic Distortion + Noise vs. Frequency 110 T VDD = 2.7V TA = 25C 100 CS 90 1 80 70 RW () CLK 2 50 40 SDI 30 3 20 IDD* 2mA/DIV CH2 5.00V CH4 10.00V 10 0 M 2.00ms *SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION IF COMMAND INSTRUCTION 0 (NOP) IS EXECUTED IMMEDIATELY AFTER COMMAND INSTRUCTION 1 (READ EEMEM). Figure 13. IDD vs. Time Read Mode 0 32 64 96 128 160 CODE (Decimal) 192 Figure 16. Wiper On Resistance vs. Code Rev. B | Page 10 of 24 224 256 02618-016 CH1 5.00V CH3 5.00V 02618-013 4 60 Data Sheet AD5232 0 80 0x40 -12 RAB = 50k 60 PSRR REJECTION (dB) 0x20 -18 0x10 -24 0x08 -30 0x04 -36 0x02 -42 0x01 VDD = +2.7V -54 VSS = -2.7V VA = 100mV rms TA = 25C -60 1k 40 20 VA RAB = 10k 10k 100k FREQUENCY (Hz) 1M 0 1k 02618-017 -48 RAB = 10k Figure 17. Gain vs. Frequency vs. Code, RAB = 10 k 0x40 0x20 -18 0x10 -24 0x08 -30 0x04 -36 0x02 -42 0x01 VDD = +2.7V -54 VSS = -2.7V VA = 100mV rms TA = 25C -60 1k VA RAB = 50k 10k 100k FREQUENCY (Hz) 1M Figure 18. Gain vs. Frequency vs. Code, RAB = 50 k 0x80 0x40 -12 0x20 -18 0x10 -24 0x08 -30 0x04 -36 0x02 -42 0x01 VA RAB = 100k 10k 100k FREQUENCY (Hz) 1M 02618-019 VDD = +2.7V -54 VSS = -2.7V VA = 100mV rms T = 25C -60 A 1k RAB = 100k RAB = 50k 60 VDD = VA2 = +2.75V VSS = VB2 = -2.75V VIN = +5V P-P TA = 25C 40 1 10 FREQUENCY (kHz) Figure 21. Analog Crosstalk vs. Frequency (See Figure 31) 0 -6 RAB = 10k 80 20 02618-018 -48 100 Figure 19. Gain vs. Frequency vs. Code, RAB = 100 k Rev. B | Page 11 of 24 100 02618-021 CTA ANALOG CROSSTALK REJECTION (dB) -6 GAIN (dB) 1M 120 0x80 -12 GAIN (dB) 10k 100k FREQUENCY (Hz) Figure 20. PSRR vs. Frequency 0 -48 VDD = 5.5V 100mV AC VSS = 0V VB = 5V VA = 0V MEASURE AT VW WITH CODE = 0x80 TA = 25C 02618-020 -6 GAIN (dB) RAB = 100k 0x80 AD5232 Data Sheet TEST CIRCUITS Figure 22 to Figure 32 define the test conditions that are used in the Specifications section. NC A DUT B IW 5V W VIN VMS OFFSET BIAS 02618-022 NC = NO CONNECT VOUT OP279 OFFSET GND B 02618-026 DUT A W Figure 22. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 26. Inverting Gain 5V DUT W OP279 VIN VOUT W B VMS OFFSET GND A DUT B 02618-027 V+ V+ = VDD 1LSB = V+/2N 02618-023 A OFFSET BIAS Figure 23. Potentiometer Divider Nonlinearity Error (INL, DNL) IW = VDD/RNOMINAL W W VIN B 02618-024 VMS1 RW = [VMS1 - VMS2]/IW DUT Figure 24. Wiper Resistance 2.5V ~ A B PSRR (dB) = 20 LOG W VMS PSS (%/%) = ( VMS VDD ) A VMS% VDD% RSW = DUT A = NC Figure 25. Power Supply Sensitivity (PSS, PSRR) 0.1V ISW CODE = 0x00 W B 02618-025 V+ VDD -15V Figure 28. Gain vs. Frequency VA V+ = VDD 10% VOUT OP42 B OFFSET GND 02618-028 VMS2 +15V A VW + ISW - VSS TO VDD 0.1V 02618-029 DUT A Figure 27. Noninverting Gain Figure 29. Incremental On Resistance Rev. B | Page 12 of 24 Data Sheet AD5232 NC 200A A ICM VSS GND B TO OUTPUT PIN VCM NC NC = NO CONNECT VOH (MIN) OR VOL (MAX) CL 50pF 200A IOH NOTES 1. THE DIODE BRIDGE TEST CIRCUIT IS EQUIVALENT TO THE APPLICATION CIRCUIT WITH RPULL-UP OF 2.2k. Figure 32. Load Circuit for Measuring VOH and VOL Figure 30. Common-Mode Leakage Current VDD VIN NC W2 W1 B1 A2 RDAC2 VSS VOUT B2 CTA = 20 LOG [VOUT/VIN] NC = NO CONNECT 02618-031 A1 RDAC1 Figure 31. Analog Crosstalk Rev. B | Page 13 of 24 02618-032 W 02618-030 VDD DUT IOL AD5232 Data Sheet THEORY OF OPERATION The AD5232 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of VSS < VTERM < VDD. The basic voltage range is limited to a |VDD - VSS| < 5.5 V. The digital potentiometer wiper position is determined by the RDACx register contents. The RDACx register acts as a scratch pad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. The scratch pad register can be programmed with any position value using the standard SPI serial interface mode by loading the complete representative data-word. When a desirable position is found, this value can be saved into a corresponding EEMEMx register. Thereafter, the wiper position is always set at that position for any future on-off-on power supply sequence. The EEMEM save process takes approximately 25 ms. During this time, the shift register is locked, preventing any changes from taking place. The RDY pin indicates the completion of this EEMEM save. SCRATCH PAD AND EEMEM PROGRAMMING The scratch pad register (RDACx register) directly controls the position of the digital potentiometer wiper. When the scratch pad register is loaded with all 0s, the wiper is connected to Terminal B of the variable resistor. When the scratch pad register is loaded with midscale code (1/2 of full-scale position), the wiper is connected to the middle of the variable resistor. When the scratch pad is loaded with full-scale code, which is all 1s, the wiper connects to Terminal A. Because the scratch pad register is a standard logic register, there is no restriction on the number of changes allowed. The EEMEMx registers have a program erase/write cycle limitation that is described in the Flash/EEMEM Reliability section. BASIC OPERATION The basic mode of setting the variable resistor wiper position (by programming the scratch pad register) is accomplished by loading the serial data input register with Command Instruction 11, which includes the desired wiper position data. When the desired wiper position is found, the user loads the serial data input register with Command Instruction 2, which copies the desired wiper position data into the corresponding nonvolatile EEMEMx register. After 25 ms, the wiper position is permanently stored in the corresponding nonvolatile EEMEM location. Table 6 provides an application programming example listing the sequence of serial data input (SDI) words and the corresponding serial data output appearing at the serial data output (SDO) pin in hexadecimal format. At system power-on, the scratch pad register is refreshed with the last value saved in the EEMEMx register. The factory preset EEMEM value is midscale. The scratch pad (wiper) register can be refreshed with the current contents of the nonvolatile EEMEMx register under hardware control by pulsing the PR pin. The application programming example shown in Table 6 lists two digital potentiometers set to independent data values. The wiper positions are then saved in the corresponding nonvolatile EEMEMx registers. Table 6. Application Programming Example SDI 0xB040 SDO 0xXXXX1 0x20XX1 0xB040 0xB180 0x20XX1 0x21XX1 0xB180 1 Action Loads 0x40 data into the RDAC1 register; Wiper W1 moves to 1/4 full-scale position. Saves a copy of the RDAC1 register contents into the corresponding EEMEM1 register. Loads 0x80 data into the RDAC2 register; Wiper W2 moves to 1/2 full-scale position. Saves a copy of the RDAC2 register contents into the corresponding EEMEM2 register. X = don't care. Note that the PR pulse first sets the wiper at midscale when it is brought to Logic 0. Then, on the positive transition to logic high, it reloads the DAC wiper register with the contents of EEMEMx. Many additional advanced programming commands are available to simplify the variable resistor adjustment process. For example, the wiper position can be changed, one step at a time, by using the software controlled increment/decrement command instructions. The wiper position can be also be changed, 6 dB at a time, by using the shift left/right command instructions. After an increment, decrement, or shift command instruction is loaded into the shift register, subsequent CS strobes repeat this command instruction. This is useful for push-button control applications (see the Advanced Control Modes section). The SDO pin is available for daisy chaining and for readout of the internal register contents. The serial input data register uses a 16-bit instruction/address/data-word. EEMEM PROTECTION The write protect (WP) pin disables any changes of the scratch pad register contents, regardless of the software commands, except that the EEMEM setting can be refreshed using Instruction Command 8 and PR. Therefore, the WP pin provides a hardware EEMEM protection feature. Execute an NOP command (Command Instruction 0) before returning WP to logic high. DIGITAL INPUT/OUTPUT CONFIGURATION All digital inputs are ESD protected, high input impedance that can be driven directly from most digital sources. The PR and WP pins, which are active at logic low, must be biased to VDD if they are not being used. No internal pull-up resistors are present on any digital input pins. The SDO and RDY pins are open-drain, digital outputs when pullup resistors are needed, but only if these functions are in use. A resistor value in the range of 1 k to 10 k optimizes the power and switching speed trade-off. Rev. B | Page 14 of 24 Data Sheet AD5232 VDD SERIAL DATA INTERFACE The AD5232 contains a 4-wire SPI-compatible digital interface (SDI, SDO, CS, and CLK) and uses a 16-bit serial data-word that is loaded MSB first. The format of the SPI-compatible word is shown in Table 7. The chip select (CS) pin must be held low until the complete data-word is loaded into the SDI pin. When CS returns high, the serial data-word is decoded according to the instructions in Table 8. The command bits (Cx) control the operation of the digital potentiometer. The address bits (Ax) determine which register is activated. The data bits (Dx) are the values that are loaded into the decoded register. Table 9 provides an address map of the EEMEM locations. The last command instruction executed prior to a period of no programming activity should be the no operation (NOP) command instruction (Command Instruction 0). This instruction places the internal logic circuitry in a minimum power dissipation state. COUNTER 02618-034 VDD INPUTS 300 WP AD5232 GND COMMAND PROCESSOR AND ADDRESS DECODE 5V Figure 35. Equivalent WP Input Protection SERIAL REGISTER SDO CS GND AD5232 02618-033 SDI Figure 34. Equivalent ESD Digital Input Protection WP RPULL-UP CLK GND Figure 33. Equivalent Digital Input/Output Logic The AD5232 has an internal counter that counts a multiple of 16 bits (per frame) for proper operation. For example, the AD5232 works with a 16-bit or 32-bit word, but it cannot work properly with a 15-bit or 17-bit word. To prevent data from mislocking (due to noise, for example), the counter resets if the count is not a multiple of 4 when CS goes high, but the data remains in the register if the count is a multiple of 4. In addition, the AD5232 has a subtle feature whereby, if CS is pulsed without CLK and SDI, the part repeats the previous command (except during powerup). As a result, care must be taken to ensure that no excessive noise exists in the CLK or CS line that may alter the effective number of bits pattern. The equivalent serial data input and output logic is shown in Figure 33. The open-drain SDO is disabled whenever CS is logic high. The SPI interface can be used in two slave modes: CPHA = 1, CPOL = 1; and CPHA = 0, CPOL = 0. CPHA and CPOL refer to the control bits that dictate SPI timing in the following microprocessors and MicroConverter(R) devices: the ADuC812 and the ADuC824, the M68HC11, and the MC68HC16R1/916R1. ESD protection of the digital inputs is shown in Figure 34 and Figure 35. DAISY-CHAINING OPERATION The SDO pin serves two purposes: it can be used to read back the contents of the wiper setting and the EEMEM using Command Instruction 9 and Command Instruction 10 (see Table 8), or it can be used for daisy-chaining multiple devices.The remaining command instructions are valid for daisy-chaining multiple devices in simultaneous operations. Daisy chaining minimizes the number of port pins required from the controlling IC (see Figure 36). The SDO pin contains an open-drain N-channel FET that requires a pull-up resistor if this function is used. As shown in Figure 36, users must tie the SDO pin of one package to the SDI pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO-to-SDI interface may require additional time delay between subsequent packages. If two AD5232s are daisy-chained, 32 bits of data are required. The first 16 bits go to U2, and the second 16 bits with the same format go to U1. The 16 bits are formatted to contain the 4-bit instruction, followed by the 4-bit address, followed by the eight bits of data. The CS pin should be kept low until all 32 bits are locked into their respective serial registers. The CS pin is then pulled high to complete the operation. VDD AD5232 U1 SDI SDO RP 2.2k AD5232 U2 SDI SDO MicroConverter CS CLK CS CLK 02618-036 VALID COMMAND AD5232 02618-035 PR INPUTS 300 LOGIC PINS Figure 36. Daisy-Chain Configuration Using the SDO Rev. B | Page 15 of 24 AD5232 Data Sheet data-words to completely clock out the contents of the serial register. The RDACx register is a volatile scratch pad register that is refreshed at power-on from the corresponding nonvolatile EEMEMx register. The increment, decrement, and shift command instructions ignore the contents of Data Byte 0 in the shift register. Execution of the operation noted in Table 8 occurs when the CS strobe returns to logic high. Execution of an NOP instruction minimizes power dissipation. Command bits are identified as Cx, address bits are Ax, and data bits are Dx. The command instruction codes are defined in Table 8. The SDO output shifts out the last eight bits of data clocked into the serial register for daisy-chain operation, with the following exception: after Command Instruction 9 or Command Instruction 10, the selected internal register data is present in Data Byte 0. The command instructions following Command Instruction 9 and Command Instruction 10 must be full 16-bit Table 7. 16-Bit Serial Data Word MSB B15 C3 B14 C2 B13 C1 B12 C0 B11 A3 B10 A2 B9 A1 B8 A0 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 LSB B0 D0 Table 8. Instruction/Operation Truth Table Instruction Byte 1 Data Byte 0 Comm. Inst. No. 0 1 B15 C3 0 0 C2 0 0 C1 0 0 C0 0 1 A3 X 0 A2 X 0 2 0 0 1 0 0 0 3 0 0 1 1 4 0 1 0 0 0 0 0 5 0 1 0 1 X X 6 0 1 1 0 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 0 0 0 11 1 0 1 1 0 0 12 1 1 0 0 0 13 1 1 0 1 14 1 1 1 15 1 1 1 A1 X 0 B8 A0 X A0 B7 D7 X X D6 X X D5 X X D4 X X D3 X X D2 X X D1 X X B0 D0 X X 0 A0 X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 A0 X X X X X X X X X X X X X X X X X X 0 0 A0 X X X X X X X X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X A0 X X X X X X X X 0 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 A0 X X X X X X X X X X X X X X X X X X X X 0 0 0 0 A0 X X X X X X X X 1 X X X X X X X X X X X X ADDR ADDR Rev. B | Page 16 of 24 Operation No operation (NOP). Do nothing. Write contents of EEMEM (A0) to the RDAC (A0) register. This command leaves the device in the read program power state. To return the part to the idle state, perform Command Instruction 0 (NOP). Save wiper setting. Write contents of RDAC (ADDR) to EEMEM (A0). Write contents of Serial Register Data Byte 0 to EEMEM (ADDR). Decrement 6 dB right shift contents of RDAC (A0). Stops at all 0s. Decrement all 6 dB right shift contents of all RDAC registers. Stops at all 0s. Decrement contents of RDAC (A0) by 1. Stops at all 0s. Decrement contents of all RDAC registers by 1. Stops at all 0s. Reset. Load all RDACs with their corresponding, previously saved EEMEM values. Write contents of EEMEM(ADDR) to Serial Register Data Byte 0. Write contents of RDAC (A0) to Serial Register Data Byte 0. Write contents of Serial Register Data Byte 0 to RDAC (A0). Increment 6 dB left shift contents of RDAC (A0). Stops at all 1s. Increment all 6 dB left shift contents of all RDAC registers. Stops at all 1s. Increment contents of RDAC (A0) by 1. Stops at all 1s. Increment contents of all RDAC registers by 1. Stops at all 1s. Data Sheet AD5232 ADVANCED CONTROL MODES The AD5232 digital potentiometer contains a set of user programming features to address the wide variety of applications available to these universal adjustment devices. Key programming features include the following: * * * Increment and Decrement Commands The Right Shift 4 and Right Shift 5 command instructions are ideal only if the LSB is 0 (that is, ideal logarithmic, with no error). If the LSB is a 1, the right shift function generates a linear halfLSB error that translates to a code-dependent logarithmic error for odd codes only, as shown in Figure 38. The plot shows the errors of the odd codes. LEFT SHIFT RIGHT SHIFT The increment and decrement command instructions (Command Instruction 14, Command Instruction 15, Command Instruction 6, and Command Instruction 7) are useful for the basic servo adjustment application. These commands simplify microcontroller software coding by eliminating the need to perform a readback of the current wiper position and then add a 1 to the register contents using the microcontroller adder. The microcontroller sends an increment command instruction (Command Instruction 14) to the digital potentiometer, which automatically moves the wiper to the next resistance segment position. The master increment command instruction (Command Instruction 15) moves all potentiometer wipers by one position from their present position to the next resistor segment position. The direction of movement is referenced to Terminal B. Thus, each Command Instruction 15 moves the wiper tap position farther from Terminal B. Logarithmic Taper Mode Adjustment Programming instructions allow decrement and increment wiper position control by an individual potentiometer or in a ganged potentiometer arrangement, where both wiper positions are changed at the same time. These settings are activated by the 6 dB decrement and 6 dB increment command instructions (Command Instruction 4 and Command Instruction 5, and Command Instruction 12 and Command Instruction 13, respectively). For example, starting with the wiper connected to Terminal B, executing nine increment instructions (Command Instruction 12) moves the wiper in 6 dB steps from the 0% of the RBA (Terminal B) position to the 100% of the RBA position of the AD5232 8-bit potentiometer. The 6 dB increment instruction doubles the value of the RDACx register contents each time the command is executed. When the wiper position is greater than midscale, the last 6 dB increment command instruction causes the wiper to go to the full-scale 255 code position. Any addi- LEFT SHIFT (+6dB) 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 1111 1111 1111 1111 1111 1111 0111 1111 0011 1111 0001 1111 0000 0111 0000 0011 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 RIGHT SHIFT (-6dB) Figure 37. Detail Left and Right Shift Function Actual conformance to a logarithmic curve between the data contents in the RDACx register and the wiper position for each Right Shift 4 and Right Shift 5 command execution contains an error only for the odd codes. The even codes are ideal, with the exception of zero right shift or greater than half-scale left shift. Figure 38 shows plots of Log_Error, that is, 20 x log10 (error/code). For example, Code 3 Log_Error = 20 x log10 (0.5/3) = -15.56 dB, which is the worst case. The plot of Log_Error is more signifi-cant at the lower codes. 0 -10 -20 -30 LOG_ERROR (CODE) FOR 8-BIT -40 -50 -60 0 20 40 60 80 100 120 140 160 180 200 220 240 260 CODE, FROM 1 TO 255 BY 2 Figure 38. Plot of Log_Error Conformance for Odd Codes Only (Even Codes Are Ideal) Rev. B | Page 17 of 24 02618-038 * In addition, the left shift commands were modified so that if the data in the RDAC register is greater than or equal to midscale and is left shifted, the data is then set to full scale. This makes the left shift function as close to ideally logarithmic as possible. 02618-037 * Independently programmable read and write to all registers Simultaneous refresh of all RDAC wiper registers from corresponding internal EEMEM registers Increment and decrement command instructions for each RDAC wiper register Left and right bit shift of all RDAC wiper registers to achieve 6 dB level changes Nonvolatile storage of the present scratch pad RDACx register values into the corresponding EEMEMx register Fourteen extra bytes of user-addressable, electrical erasable memory Figure 37 illustrates the operation of the 6 dB shifting function on the individual RDACx register data bits for the 8-bit AD5232 example. Each line going down the table represents a successive shift operation. Note that the Left Shift 12 and Left Shift 13 command instructions were modified so that if the data in the RDACx register is equal to 0 and is left shifted, it is then set to Code 1. GAIN (dB) * tional 6 dB instruction does not change the wiper position from full scale (RDACx register code = 255). AD5232 Data Sheet VDD USING ADDITIONAL INTERNAL, NONVOLATILE EEMEM The AD5232 contains additional internal user storage registers (EEMEM) for saving constants and other 8-bit data. Table 9 provides an address map of the internal nonvolatile storage registers, which are shown in the functional block diagram as EEMEM1, EEMEM2, and bytes of USER EEMEM. A W Note the following about EEMEM function: * * * * RDAC data stored in EEMEM locations are transferred to their corresponding RDACx register at power-on or when Command Instruction 1 and Command Instruction 8 are executed. USERx refers to internal nonvolatile EEMEM registers that are available to store and retrieve constants by using Command Instruction 3 and Command Instruction 9, respectively. The EEMEM locations are one byte each (eight bits). Execution of Command Instruction 1 leaves the device in the read mode power consumption state. When the final Command Instruction 1 is executed, the user should perform an NOP (Command Instruction 0) to return the device to the low power idle state. Table 9. EEMEM Address Map EEMEM Address (ADDR) 0000 0001 0010 0011 0100 0101 *** 1111 EEMEM Contents of Each Device EEMEM (ADDR) RDAC1 RDAC2 USER 1 USER 2 USER 3 USER 4 *** USER 14 VSS 02618-039 B Figure 39. Maximum Terminal Voltages Set by VDD and VSS Table 10. RDAC and Digital Register Address Map Name of Register1 RDAC1 RDAC2 Register Address (ADDR) 0000 0001 1 The RDACx registers contain data that determines the position of the variable resistor wiper. DETAILED POTENTIOMETER OPERATION The actual structure of the RDACx is designed to emulate the performance of a mechanical potentiometer. The RDACx contains multiple strings of connected resistor segments, with an array of analog switches that act as the wiper connection to several points along the resistor array. The number of points is equal to the resolution of the device. For example, the AD5232 has 256 connection points, allowing it to provide better than 0.5% setability resolution. Figure 40 provides an equivalent diagram of the connections between the three terminals that make up one channel of the RDACx. The SWA and SWB switches are always on, whereas only one of the SW(0) to SW(2N-1) switches is on at a time, depending on the resistance step decoded from the data bits. The resistance contributed by RW must be accounted for in the output resistance. SWA A TERMINAL VOLTAGE OPERATING RANGE The ground pin of the AD5232 device is used primarily as a digital ground reference that needs to be tied to the common ground of the PCB. The digital input logic signals to the AD5232 must be referenced to the ground (GND) pin of the device and satisfy the minimum input logic high level and the maximum input logic low level that are defined in the Specifications section. An internal level shift circuit between the digital interface and the wiper switch control ensures that the common-mode voltage range of the three terminals, Terminal A, Terminal B, and Wiper Terminal W, extends from VSS to VDD. Rev. B | Page 18 of 24 SW(2N-1) RDAC WIPER REGISTER AND DECODER RS SW(2N-2) RS SW(1) RS SW(2) W RS = RAB/2N SWB B NOTES 1. DIGITAL CIRCUITRY OMITTED FOR CLARITY 02618-040 The positive VDD and negative VSS power supply of the digital potentiometer defines the boundary conditions for proper 3-terminal programmable resistance operations. Signals present on Terminal A, Terminal B, and Wiper Terminal W that exceed VDD or VSS are clamped by a forward biased diode (see Figure 39). Figure 40. Equivalent RDAC Structure Data Sheet AD5232 100 10 k Version 78.10 PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistances of the RDACx between Terminal A and Terminal B are available with values of 10 k, 50 k, and 100 k. The final digits of the part number determine the nominal resistance value; for example, 10 k = 10; 100 k = 100. The nominal resistance (RAB) of the AD5232 VR has 256 contact points accessed by Wiper Terminal W, plus the Terminal B contact. The 8-bit data-word in the RDACx latch is decoded to select one of the 256 possible settings. The general transfer equation, which determines the digitally programmed output resistance between Wx and Bx, is RWB (D) = D x R AB + RW 256 Table 12 lists the output resistance values that are set for the RDACx latch codes shown for 8-bit, 10 k potentiometers. 1 RWB (D) () 10011 5050 89 50 25 RWB 0 RWA 64 128 CODE (Decimal) 192 258 Figure 41. Symmetrical RDAC Operation When these terminals are used, Terminal B should be tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is RWA (D) = 256 - D x R AB + RW 256 (2) where: D is the decimal equivalent of the data contained in the RDAC register. RAB is the nominal resistance between Terminal A and Terminal B. RW is the wiper resistance. Table 13 lists the output resistance values that are set for the RDACx latch codes shown for 8-bit, 10 k potentiometers. Table 12. Nominal Resistance Value at Selected Codes for RAB = 10 k D (Dec) 255 128 1 0 50 0 (1) where: D is the decimal equivalent of the data contained in the RDACx register. RAB is the nominal resistance between Terminal A and Terminal B. RW is the wiper resistance. 75 02618-041 Device Resolution 8-Bit Segmented Resistor Size for RAB End-to-End Values 50 k 100 k Version Version 390.5 781.0 PERCENT OF NOMINAL END-TO-END RESISTANCE (% RAB) Table 11. Nominal Individual Segment Resistor Values () Output State Full scale Midscale 1 LSB Zero scale1 (wiper contact resistance) Note that in the zero-scale condition, a finite wiper resistance of 50 is present. Care should be taken to limit the current flow between Wx and Bx in this state to a maximum continuous value of 2 mA to avoid degradation or possible destruction of the internal switch metallization. Intermittent current operation to 20 mA is allowed. Like the mechanical potentiometer that the RDACx replaces, the AD5232 parts are totally symmetrical. The resistance between the Wiper Terminal W and Terminal A also produces a digitally controlled resistance, RWA. Figure 41 shows the symmetrical programmability of the various terminal connections. Table 13. Nominal Resistance Value at Selected Codes for RAB = 10 k D (Dec) 255 128 1 0 RWA (D) () 89 5050 10011 10050 Output State Full scale Midscale 1 LSB Zero scale The multichannel AD5232 has a 0.2% typical distribution of internal channel-to-channel RBA match. Device-to-device matching is dependent on process lot and exhibits a -40% to +20% variation. The change in RBA with temperature has a 600 ppm/C temperature coefficient. Rev. B | Page 19 of 24 AD5232 Data Sheet RDAC 10k A Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example, connecting Terminal A to 5 V and Terminal B to GND produces an output voltage at the wiper that can be any value from 0 V to 5 V. Each LSB of voltage is equal to the voltage applied across Terminal A to Terminal B, divided by the 2N position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to Terminal A to Terminal B is VW (D) = R (D ) RWB (D) x V A + WA xVB R AB R AB (3) where RWB(D) can be obtained from Equation 1 and RWA(D) can be obtained from Equation 2. Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the drift improves to 15 ppm/C. There is no voltage polarity restriction between Terminal A, Terminal B, and Wiper Terminal W as long as the terminal voltage (VTERM) stays within VSS < VTERM < VDD. CA 45pF B CW 60pF CB 45pF W 02618-043 PROGRAMMING THE POTENTIOMETER DIVIDER Figure 43. RDAC Circuit Simulation Model for RDACx = 10 k The following code provides a macro model net list for the 10 k RDAC: .PARAM DW=255, RDAC=10E3 * .SUBCKT DPOT (A,W,B) * CA A 0 {45E-12} RAW A W {(1-DW/256)*RDAC+50} CW W 0 60E-12 RBW W B {DW/256*RDAC+50} CB B 0 {45E-12} * .ENDS DPOT APPLICATION PROGRAMMING EXAMPLES The command sequence examples shown in Table 14 to Table 18 have been developed to illustrate a typical sequence of events for the various features of the AD5232 nonvolatile digital potentiometer. Table 14 illustrates setting two digital potentiometers to independent data values. OPERATION FROM DUAL SUPPLIES The AD5232 can be operated from dual supplies, enabling control of ground-referenced ac signals (see Figure 42 for a typical circuit connection). +2.5V VDD SS MicroConverter SCLK MOSI GND CS CLK SDI VDD Table 14. 2V p-p 1V p-p GND VSS -2.5V 02618-042 AD5232 SDI 0xB140 SDO 0xXXXX 0xB080 0xB140 Action Loads 0x40 data into the RDAC2 register; Wiper W2 moves to 1/4 full-scale position. Loads 0x80 data into the RDAC1 register; Wiper W1 moves to 1/2 full-scale position. Table 15 illustrates the active trimming of one potentiometer, followed by a save to nonvolatile memory (PCB calibrate). Table 15. Figure 42. Operation from Dual Supplies The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. When configured as a potentiometer divider, the -3 dB bandwidth of the AD5232BRU10 (10 k resistor) measures 500 kHz at half scale. Figure 14 provides the large signal BODE plot characteristics of the three resistor versions: 10 k, 50 k, and 100 k (see Figure 43 for a parasitic simulation model of the RDAC circuit). SDI 0xB040 SDO 0xXXXX 0xE0XX 0xB040 0xE0XX 0xE0XX 0x20XX 0xE0XX Rev. B | Page 20 of 24 Action Loads 0x40 data into the RDAC1 register; Wiper W1 moves to 1/4 full-scale position. Increments the RDAC1 register by 1, to 0x41; Wiper W1 moves one resistor segment away from Terminal B. Increments the RDAC1 register by 1, to 0x42; Wiper W1 moves one more resistor segment away from Terminal B. Continue until desired the wiper position is reached. Saves the RDAC1 register data into the corresponding nonvolatile EEMEM1 memory: ADDR = 0x0. Data Sheet AD5232 SDI 0xC1XX SDO 0xXXXX 0xC1XX 0xXXXX Action Moves Wiper W2 to double the present data value contained in the RDAC2 register in the direction of Terminal A. Moves Wiper W2 to double the present data value contained in the RDAC2 register in the direction of Terminal A. Table 17 illustrates storing additional data in nonvolatile memory. Table 17. SDI 0x3280 SDO 0xXXXX 0x3340 0xXXXX Action Stores 0x80 data in spare EEMEM location, USER1. Stores 0x40 data in spare EEMEM location, USER2. Table 18 illustrates reading back data from various memory locations. Table 18. SDI 0x94XX SDO 0xXXXX 0x00XX 0xXX80 Action Prepares data read from USER3 location. (USER3 is already loaded with 0x80.) Instruction 0 (NOP) sends 16-bit word out of SDO where the last eight bits contain the contents of USER3 location. The NOP command ensures that the device returns to the idle power dissipation state. EQUIPMENT CUSTOMER START-UP SEQUENCE FOR A PCB CALIBRATED UNIT WITH PROTECTED SETTINGS 1. 2. 3. For the PCB setting, tie WP to GND to prevent changes in the PCB wiper set position. Set power VDD and VSS with respect to GND. As an optional step, strobe the PR pin to ensure full poweron preset of the wiper register with EEMEM contents in unpredictable supply sequencing environments. FLASH/EEMEM RELIABILITY The Flash/EE memory array on the AD5232 is fully qualified for two key Flash/EE memory characteristics: namely, Flash/EE memory cycling endurance and Flash/EE memory data retention. As indicated in the Specifications section, the AD5232 Flash/EE memory endurance qualification has been carried out in accordance with JEDEC Std. 22, Method A117 over the industrial temperature range of -40C to +85C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25C. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the AD5232 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature of TJ = 55C. As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit, as described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash/EE memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 eV, derates with TJ, as shown in Figure 44. 300 250 ADI TYPICAL PERFORMANCE AT TJ = 55C 150 100 50 0 40 50 60 70 80 90 100 TJ JUNCTION TEMPERATURE (C) 110 Figure 44. Flash/EE Memory Data Retention EVALUATION BOARD Analog Devices, Inc., offers a user-friendly EVAL-AD5232-10EBZ evaluation kit that can be controlled by a personal computer through a printer port. The driving program is self-contained; no programming languages or skills are needed. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as follows: 1. 2. 3. 4. 200 02618-044 Table 16. During reliability qualification, Flash/EE memory is cycled from 0x00 to 0xFF until a first fail is recorded, signifying the endurance limit of the on-chip Flash/EE memory. RETENTION (Years) Table 16 illustrates using the left shift-by-one to change circuit gain in 6 dB steps. Initial page erase sequence Read/verify sequence Byte program sequence Second read/verify sequence Rev. B | Page 21 of 24 AD5232 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 0.20 0.09 SEATING PLANE 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 45. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5232BRU10 AD5232BRU10-REEL7 AD5232BRUZ10 AD5232BRUZ10-REEL7 AD5232BRU50 AD5232BRU50-REEL7 AD5232BRUZ50 AD5232BRUZ50-REEL7 AD5232BRU100 AD5232BRU100-REEL7 AD5232BRUZ100 AD5232BRUZ100-RL7 EVAL-AD5232-10EBZ 1 2 Number of Channels 2 2 2 2 2 2 2 2 2 2 2 2 End-to-End RAB (k) 10 10 10 10 50 50 50 50 100 100 100 100 10 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP Evaluation Board Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 Ordering Quantity 96 1,000 96 1,000 96 1,000 96 1,000 96 1,000 96 1,000 1 Branding 2 5232B10 5232B10 5232B10 5232B10 5232B50 5232B50 5232B50 5232B50 5232BC 5232BC 5232BC 5232BC Z = RoHS Compliant Part. Line 1 contains the Analog Devices logo, followed by the date code: YYWW. Line 2 contains the model number, followed by the end-to-end resistance value. (Note that C = 100 k). OR Line 1 contains the model number. Line 2 contains the Analog Devices logo, followed by the end-to-end resistance value. Line 3 contains the date code: YYWW. Rev. B | Page 22 of 24 Data Sheet AD5232 NOTES Rev. B | Page 23 of 24 AD5232 Data Sheet NOTES (c)2001-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02618-0-9/11(B) Rev. B | Page 24 of 24