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e2v semiconductors SAS 2007
TS8388B
ADC 8-bit 1 Gsps
Datasheet
1. Features
•
8-bit Resolution
•
ADC Gain Adjust
•
1.5 GHz Full Power Input Bandwidth (–3 dB)
•
1 Gsps (min.) Sampling Rate
•
SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc, at F
S
= 1 Gsps, F
IN
= 20 MHz
•
SINAD = 42.9 dB (7.0 Effective Bits), SFDR = 52 dBc, at F
S
= 1 Gsps, F
IN
= 500 MHz
•
SINAD = 40.3 dB (6.8 Effective Bits), SFDR = 50 dBc, at F
S
= 1 Gsps, F
IN
= 1000 MHz (–3 dBFS)
•
2-tone IMD: –52 dBc (489 MHz, 490 MHz) at 1 Gsps
•
DNL = 0.3 lsb, INL = 0.7 lsb
•
Low Bit Error Rate (10-
13
) at 1 Gsps
•
Very Low Input Capacitance: 3 pF
•
500 mVpp Differential or Single-ended Analog Inputs
•
Differential or Single-ended 50Ω ECL Compatible Clock Inputs
•
ECL or LVDS/HSTL Output Compatibility
•
Data Ready Output with Asynchronous Reset
•
Gray or Binary Selectable Output Data; NRZ Output Mode
•
Power Consumption: 3.4W at T
J
= 70°C Typical
•
Radiation Tolerance Oriented Design (150 Krad (Si) Measured)
•
Two Package Versions
•
Evaluation Board: TSEV8388B
•
Demultiplexer TS81102G0: Companion Device Available
2. Applications
•
Digital Sampling Oscilloscopes
•
Satellite Receiver
•
Electronic Countermeasures/Electronic Warfare
•
Direct RF Down-conversion
3. Description
The TS8388B is a monolithic 8-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very
high sampling rates of up to 1 Gsps.
The TS8388B uses an innovative architecture, including an on-chip Sample and Hold (S/H), and is fabricated with an
advanced high-speed bipolar process.
The on-chip S/H has a 1.5 GHz full power input bandwidth, providing excellent dynamic performance in undersampling
applications (high IF digitizing).
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4. Functional Description
4.1 Block Diagram
The following figure shows the simplified block diagram.
Figure 4-1. Simplified Block Diagram
4.2 Functional Description
The TS8388B is an 8-bit 1 Gsps ADC based on an advanced high-speed bipolar technology featuring a
cutoff frequency of 25 GHz.
The TS8388B includes a front-end master/slave Track and Hold stage (S/H), followed by an analog
encoding stage and interpolation circuitry.
Successive banks of latches regenerate the analog residues into logical data before entering an error
correction circuitry and a resynchronization stage followed by 75Ω differential output buffers.
The TS8388B works in fully differential mode from analog inputs up to digital outputs.
The TS8388B features a full-power input bandwidth of 1.5 GHz.
A control pin GORB is provided to select either Gray or Binary data output format.
A gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8388B.
The TS8388B uses only vertical isolated NPN transistors together with oxide isolated polysilicon resis-
tors, which allow enhanced radiation tolerance (no performance drift measured at 150 kRad total dose).
MASTER/SLAVE TRACK & HOLD AMPLIFIER
VIN, VINB
CLOCK
BUFFER
GAIN
GORB DATA, DATAB OR, ORB
DRRB DR, DRB
CLK, CLKB
4
45
45
8
8
G=2 T/H G=1 T/H G=1 RESISTOR
CHAIN
ANALOG
ENCODING
BLOCK
INTERPOLATION
STAGES
REGENERATION
LATCHES
ERROR CORRECTION &
DECODE LOGIC
OUTPUT LATCHES &
BUFFERS
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TS8388B
5. Specifications
5.1 Absolute Maximum Ratings
Note: Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat
sink is mandatory. See “The board set comes fully assembled and tested, with the TS8388B installed.” on page 43.
5.2 Recommended Operating Conditions
Table 5-1. Absolute Maximum Ratings
Parameter Symbol Comments Value Unit
Positive supply voltage V
CC
GND to 6 V
Digital negative supply voltage DV
EE
GND to –5.7 V
Digital positive supply voltage V
PLUSD
GND –0.3 to 2.8 V
Negative supply voltage V
EE
GND to –6V
Maximum difference between negative supply voltage DV
EE
to V
EE
0.3 V
Analog input voltages V
IN
or V
INB
–1 to +1 V
Maximum difference between V
IN
and V
INB
V
IN
- V
INB
–2 to +2 V
Digital input voltage V
D
GORB –0.3 to V
CC
+0.3 V
Digital input voltage V
D
DRRB V
EE
–0.3 to +0.9 V
Digital output voltage V
O
V
PLUSD
–3 to V
PLUSD
–0.5 V
Clock input voltage V
CLK
or V
CLKB
–3 to +1.5 V
Maximum difference between V
CLK
and V
CLKB
V
CLK
- V
CLKB
–2 to +2 V
Maximum junction temperature T
J
+135 °C
Storage temperature T
stg
–65 to +150 °C
Lead temperature (soldering 10s) T
leads
+300 °C
Table 5-2. Recommended Operating Conditions
Parameter Symbol Comments
Recommended Value
UnitMin Typ Max
Positive supply voltage V
CC
4.5 +5 5.25 V
Positive digital supply voltage V
PLUSD
ECL output compatibility – GND – V
Positive digital supply voltage V
PLUSD
LVDS output compatibility +1.4 +2.4 +2.6 V
Negative supply voltage V
EE,
DV
EE
–5.25 –5–4.75 V
Differential analog input voltage
(Full Scale)
V
IN,
V
INB
V
IN
- V
INB
50Ω differential or single-ended ±113
450
±125
500
±137
550
mV
mVpp
Clock input power level P
CLK,
P
CLKB
50Ω single-ended clock input 3 4 10 dBm
Operating temperature range T
J
Commercial grade: “C”
Industrial grade: “V”
Military grade: “M”
0 < Tc; T
J
< 90
–40 < Tc; T
J
< 110
–55 < Tc; T
J
< +125
°C
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5.3 Electrical Operating Characteristics
•V
EE
= DV
EE
=
–
5V; V
CC
= +5V; V
IN
- V
INB
= 500 mVpp Full Scale differential input
• Digital outputs 75 or 50Ω differentially terminated
•T
J
(typical) = 70°C. Full Temperature Range: up to
–
55°C < Tc; T
J
- < +125°C, depending on device
grade
Table 5-3. Electrical Specifications
Parameter Symbol
Test
Level
Value
Unit NoteMin Typ Max
Power Requirements (CBGA68 package)
Positive supply voltage
Analog
Digital (ECL)
Digital (LVDS)
V
CC
V
PLUSD
V
PLUSD
1
4
4
4.5
–
1.4
5
0
2.4
5.5
–
2.6
V
V
V
Positive supply current
Analog
Digital
I
CC
I
PLUSD
1
1
–
–
420
130
445
145
mA
mA
Negative supply voltage V
EE
1–5.5 –5–4.5 V
Negative supply current
Analog
Digital
AI
EE
DI
EE
1
1
–
–
185
160
200
180
mA
mA
Nominal power dissipation PD 1 – 3.9 4.1 W
Power supply rejection ratio PSRR 4 – 0.5 2 mV/V
Power Requirements
Power Requirements (CQFP68 packaged device)
Positive supply voltage
Analog
Digital (ECL)
Digital (LVDS)
V
CC
V
PLUSD
V
PLUSD
1, 2, 6
4
4
4.7
–
1.4
5
0
2.4
5.3
–
2.6
V
V
V
Positive supply current
Analog
Digital
I
CC
I
PLUSD
1, 2
6
1, 2
6
–
–
–
–
385
395
115
120
445
445
145
145
mA
mA
mA
mA
Negative supply voltage V
EE
1, 2, 6 –5.3 –5–4.7 V
Negative supply current
Analog
Digital
AI
EE
DI
EE
1, 2
6
1, 2
6
–
–
–
–
165
170
135
145
200
200
180
180
mA
mA
mA
mA
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TS8388B
Nominal power dissipation PD 1, 2
6
–
–
3.4
3.6
4.1
4.3
W
W
Power supply rejection ratio PSRR 4 – 0.5 2 mV/V
Resolution – – – 8 – bits
(2)
Analog Inputs
Full Scale Input Voltage range (differential mode)
(0V common mode voltage)
V
IN
V
INB
4
–
–125
–125
–
–
125
125
mV
mV
Full Scale Input Voltage range (single-ended input
option) (See Application Notes)
V
IN
V
INB
4
–
–250
–
–
0
250
–
mV
mV
Analog input capacitance C
IN
4– 33.5pF
Input bias current I
IN
4 – 10 20 µA
Input Resistance R
IN
40.5 1 – MΩ
Full Power input Bandwidth (–3dB)
CBGA68 package
CQFP68 package
FPBW
–
–
–
4
4
–
–
–
–
1.8
1.5
–
–
–
–
GHz
GHz
–
Small signal input Bandwidth (10% full scale) SSBW 4 1.5 1.7 – GHz
Clock Inputs
Logic compatibility for clock inputs
(See Application Notes) ––
ECL or specified clock input
power level in dBm –
(10)
ECL Clock inputs voltages (V
CLK
or V
CLKB
): – 4––––
Logic “0” voltage V
IL
–– ––1.5 V
Logic “1” voltage V
IH
––1.1 – – V
Logic “0” current I
IL
–– 5 50µA
Logic “1” current I
IH
–– 5 50µA
Clock input power level into 50Ω termination – – dBm into 50Ω–
Clock input power level – 4 –2410dBm
Clock input capacitance C
CLK
4– 33.5pF
Digital Outputs
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,
T
J
(typical) = 70
°
C.
(1)(6)
Logic compatibility for digital outputs
(Depending on the value of V
PLUSD
)
(See Application Notes)
–– ECL or LVDS –
Differential output voltage swings
(assuming V
PLUSD
= 0V): – 4––––
75Ω open transmission lines (ECL levels) – – 1.5 1.620 – V
75Ω differentially terminated – – 0.70 0.825 – V
Table 5-3. Electrical Specifications (Continued)
Parameter Symbol
Test
Level
Value
Unit NoteMin Typ Max
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50Ω differentially terminated – – 0.54 0.660 – V
Output levels (assuming V
PLUSD
= 0V)
75Ω open transmission lines: – 4––––
(6)
Logic “0” voltage V
OL
–––1.62 –1.54 V
Logic “1” voltage V
OH
––0.88 –0.8 – V
Output levels (assuming V
PLUSD
= 0V)
75Ω differentially terminated: – 4––––
(6)
Logic “0” voltage V
OL
–––1.41 –1.34 V
Logic “1” voltage V
OH
––1.07 –1– V
Output levels (assuming V
PLUSD
= 0V)
50Ω differentially terminated: – –––––
(6)
Logic “0” voltage V
OL
1, 2
6
–
–
–1.40
–1.40
–1.32
–1.25
V
V
Logic “1” voltage V
OH
1, 2
6
–1.16
–1.25
–1.10
–1.10
–
–
V
V
Differential Output Swing DOS 4 270 300 – mV
Output level drift with temperature – 4 – – 1.6 mV/
°
C
DC Accuracy (CBGA68 package)
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
T
J
(typical) = 70
°
C
Differential nonlinearity DNL- 1 –0.6 –0.4 – lsb
(2)(3)
Differential nonlinearity DNL+ 1 – 0.4 0.6 lsb
Integral nonlinearity INL- 1 –1.2 –0.7 – lsb
(2)(3)
Integral nonlinearity INL+ 1 – 0.7 1.2 lsb
No missing codes – Guaranteed over specified temperature range
(3)
Gain – 1, 2 90 98 110 %
Input offset voltage – 1, 2 –26 –526mV
Gain error drift
Offset error drift
–
–
4
4
100
40
125
50
150
60
ppm/
°
C
ppm/
°
C
DC Accuracy (CQFP68 package)
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
T
J
(typical) = 70
°
C.
Differential nonlinearity DNL- 1, 2
6
–0.5
–0.6
–0.25
–0.35
–
–
lsb
lsb
(2)(3)
Differential nonlinearity DNL+ 1, 2
6
–
–
0.3
0.4
0.6
0.7
lsb
lsb
Table 5-3. Electrical Specifications (Continued)
Parameter Symbol
Test
Level
Value
Unit NoteMin Typ Max
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TS8388B
Integral nonlinearity INL- 1, 2
6
–1.0
–1.2
0.7
0.9
–
–
lsb
lsb
(2)(3)
Integral nonlinearity INL+ 1, 2
6
–
–
0.7
0.9
1.0
1.2
lsb
lsb
No missing code – Guaranteed over specified temperature range
(3)
Gain error – 1, 2
6
–10
–11
–2
–2
10
11
% F
S
% F
S
Input offset voltage – 1, 2
6
–26
–30
–5
–5
26
30
mV
mV
Gain error drift
Offset error drift
–
–
4
4
100
40
125
50
150
60
ppm/
°
C
ppm/
°
C
Transient Performance
Bit Error Rate
F
S
= 1 Gsps F
IN
= 62.5 MHz BER 4 – – 1E-12 Error/
sample
(2)(4)
ADC settling time
V
IN
-V
INB
= 400 mVpp TS 4 – 0.5 1 ns
(2)
Overvoltage recovery time TOR 4 – 0.5 1 ns
(2)
AC Performance
Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,
T
J
= 70
°
C, unless otherwise specified.
Signal to Noise and Distortion ratio
SINAD
–––––
(2)
F
S
= 1 Gsps, F
IN
= 20 MHz 4 42 44 – dB
F
S
= 1 Gsps, F
IN
= 500 MHz 4 41 43 – dB
F
S
= 1 Gsps, F
IN
= 1000 MHz (-1 dBFs) 4 38 40 – dB
F
S
= 50 Msps, F
IN
= 25 MHz 1, 2, 6 40 44 – dB
Effective Number of Bits
ENOB
–––––
F
S
= 1 Gsps, F
IN
= 20 MHz 4 7.0 7.2 – Bits
F
S
= 1 Gsps, F
IN
= 500 MHz 4 6.6 6.8 – Bits
F
S
= 1 Gsps, F
IN
= 1000 MHz (–1 dBFs) 4 6.2 6.4 – Bits
F
S
= 50 Msps, F
IN
= 25 MHz 1, 2, 6 7.0 7.2 – Bits
Signal to Noise Ratio
SNR
–––––
(2)
F
S
= 1 Gsps, F
IN
= 20 MHz 4 42 45 – dB
F
S
= 1 Gsps, F
IN
= 500 MHz 4 41 44 – dB
F
S
= 1 Gsps, F
IN
= 1000 MHz (–1 dBFs) 4 41 44 – dB
F
S
= 50 Msps, F
IN
= 25 MHz 1, 2, 6 44 45 – dB
Table 5-3. Electrical Specifications (Continued)
Parameter Symbol
Test
Level
Value
Unit NoteMin Typ Max
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TS8388B
e2v semiconductors SAS 2007
Notes: 1. Differential output buffers are internally loaded by 75Ω resistors. Buffer bias current = 11 mA.
Total Harmonic Distortion
THD
–––––
(2)
F
S
= 1 Gsps, F
IN
= 20 MHz 4 50 54 – dB
F
S
= 1 Gsps, F
IN
= 500 MHz 4 46 50 – dB
F
S
= 1 Gsps, F
IN
= 1000 MHz (–1 dBFs) 4 42 46 – dB
F
S
= 50 Msps, F
IN
= 25 MHz 1, 2, 6 46 45 – dB
Spurious Free Dynamic Range
SFDR
–––––
(2)
F
S
= 1 Gsps, F
IN
= 20 MHz 4 52 57 – dBc
F
S
= 1 Gsps, F
IN
= 500 MHz 4 47 52 – dBc
F
S
= 1 Gsps, F
IN
= 1000 MHz (–1 dBFs) 4 42 47 – dBc
F
S
= 1 Gsps, F
IN
= 1000 MHz (–3 dBFs) 4 45 50 – dBc
F
S
= 50 Msps, F
IN
= 25 MHz 1, 2, 6 40 54 – dBc
Two-tone Intermodulation Distortion
IMD
4––––
(2)
F
IN1
= 489 MHz at F
S
= 1 Gsps
F
IN2
= 490 MHz at F
S
= 1 Gsps ––47 –52 – dBc
Switching Performance and Characteristics – See Figure 5-1 and Figure 5-2 on page 10
Maximum clock frequency F
S
–1 –1.4Gsps
(14)
Minimum clock frequency F
S
410–50Msps
(15)
Minimum Clock pulse width (high) TC1 4 0.280 0.500 50 ns
Minimum Clock pulse width (low) TC2 4 0.350 0.500 50 ns
Aperture delay T
A
4 100 +250 400 ps
(2)
Aperture uncertainty Jitter 4 – 0.4 0.6 ps (rms)
(2)(5)
Data output delay TDO 4 1150 1360 1660 ps
(2)(10)
(11)(12
)
Output rise/fall time for DATA (20% to 80%) TR/TF 4 250 350 550 ps
(11)
Output rise/fall time for DATA READY (20% to 80%) TR/TF 4 250 350 550 ps
(11)
Data ready output delay TDR 4 1110 1320 1620 ps
(2)(10)
(11)(12
)
Data ready reset delay TRDR 4 – 720 1000 ps
Data to data ready – Clock low pulse width
(See “Timing Diagrams” on page 10.)TOD-TDR 4 0 40 80 ps
(9)(13)
(14)
Data to data ready output delay (50% duty cycle) at
1 Gsps (See “Timing Diagrams” on page 10.)TD1 4 420 460 500 ps
(2)(15)
Data pipeline delay TPD 4 4 clock
cycles
Table 5-3. Electrical Specifications (Continued)
Parameter Symbol
Test
Level
Value
Unit NoteMin Typ Max
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TS8388B
2. See “Definition of Terms” on page 49.
3. Histogram testing based on sampling of a 10 MHz sinewave at 50 Msps.
4. Output error amplitude < ± 4 lsb around correct code (including gain and offset error).
5. Maximum jitter value obtained for single-ended clock input on the JTS8388B die (chip on board): 200 fs. (500 fs expected on
TS8388BG)
6. Digital output back termination options depicted in Application Notes.
7. With a typical value of TD = 465 ps, at 1 Gsps, the timing safety margin for the data storing using the ECLinPS 10E452 out-
put registers from Freescale
®
is of ± 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR,
DRB).
8. The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level
into the 50Ω termination resistor of the inphase clock input. (4 dBm into 50Ω clock input correspond to 10 dBm power level
for the clock generator.)
9. At 1 Gsps, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = –100 ps (typ) does not depend on the sampling rate.
10. Specified loading conditions for digital outputs:
- 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated, or unterminated 75Ω controlled impedance traces.
- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Freescale. (that is: 10E452) (Typical
input parasitic capacitance of 1.5 pF including package and ESD protections.)
11. Termination load parasitic capacitance derating values:
- 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated: 60 ps/pF or 75 ps per additional ECLinPS load.
- Unterminated (source terminated) 75Ω controlled impedance lines: 100 ps/pF or 150 ps per additional ECLinPS termina-
tion load.
12. Apply proper 50/75Ω impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation
Board.
13. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100
°
C temperature variation).
Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between
each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are
never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes
about “TOD-TDR Variation Over Temperature” on page 28).
14. Min value guarantees performance. Max value guarantees functionality.
15. Min value guarantees functionality. Max value guarantees performance.
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5.4 Timing Diagrams
Figure 5-1. TS8388B Timing Diagram (1 Gsps Clock Rate), Data Ready Reset, Clock Held at Low Level
Figure 5-2. TS8388B Timing Diagram (1 Gsps Clock Rate), Data Ready Reset, Clock Held at High Level
TC1 TC2
TA = 250 ps TBC
X
X
N+1
X
N+2
XN+3
N
DIGITAL
OUTPUTS
(VIN, VINB)
Data Ready
(DR, DRB)
(CLK, CLKB)
XN+5
N-4 N-3 N
N-2 N-1
TC = 1000 ps
XX
N+4
TOD = 1360 ps
1360 ps
DRRB
1 ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
1000 ps
TRDR = 720 ps
N-1
TD2 = TC2+TOD-TDR
= TC2+40 ps = 540 ps
TDR = 1320 ps
DATA DATA DATA DATA DATADATA
N-5 N+1
TD1 = TC1+TDR-TOD
= TC1-40 ps = 460 ps
TC1 TC2
TA = 250 ps TBC
N+1 N+2
N
DIGITAL
OUTPUTS
(VIN, VINB)
Data Ready
(DR, DRB)
(CLK, CLKB)
N+5
N-4 N-3 N
N-1N-2
TC = 1000 ps
N+4
TOD = 1360 ps
1360 ps
DRRB
1 ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
TRDR = 720 ps
N-1
TD2 = TC2+TOD-TDR
= TC2+40 ps = 540 ps
TDR = 1320 ps
DATA DATA DATA DATA DATADATA DATA
N-5 N+1
1000 ps
X
X
X
X
XXX
TD1 = TC1+TDR-TOD
= TC1-40 ps = 460 ps
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5.5 Explanation of Test Levels
Notes: 1. Unless otherwise specified, all tests are pulsed tests: therefore T
J
= Tc = T
amb
, where T
J
, Tc and T
A
are
junction, case and ambient temperature respectively.
2. Refer to “Ordering Information” on page 52.
3. Only MIN and MAX values are guaranteed (typical values are issuing from characterization results).
5.6 Functions Description
Table 5-4. Explanation of Test Levels
No. Characteristics
1 100% production tested at +25
°
C
(1)
(for “C” Temperature range
(2)
).
2100% production tested at +25
°
C
(1)
, and sample tested at specified temperatures
(for “V” and “M” Temperature range
(2)
).
3 Sample tested only at specified temperatures.
4Parameter is guaranteed by design and characterization testing (thermal steady-state
conditions at specified temperature).
5 Parameter is a typical value only.
6100% production tested over specified temperature range
(for “B/Q” Temperature range
(2)
).
Table 5-5. Functions Description
Name Function
V
CC
Positive power supply
V
EE
Analog negative power supply
V
PLUSD
Digital positive power supply
GND Ground
V
IN
, V
INB
Differential analog inputs
CLK, CLKB Differential clock inputs
<D0:D7>
<D0B:D7B> Differential output data port
DR, DRB Differential data ready outputs
OR, ORB Out of range outputs
GAIN ADC gain adjust
GORB Gray or Binary digital output select
DIOD/DRRB Die junction temperature measurement/
asynchronous data ready reset
VIN
VINB
CLK
CLKB D0 D7
D0B D7B
16
DVEE = -5V
VCC = +5V VPLUSD = +0V (ECL)
VPLUSD = +2.4V (LVDS)
TS8388B
VEE = -5V GND
GAIN
GORG
DIOD/
DRRB
OR
ORB
DR
DRB
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5.7 Digital Output Coding
NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity voltage errors.
6. Package Description
6.1 Pin Description
Table 5-6. Digital Output Coding
Differential
Analog Input Voltage Level
Digital Output
Out-of
Range
Binary
GORB = VCC or Floating
Gray
GORB = GND
> +251 mV > Positive full scale + 1/2 lsb 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1
+251 mV
+249 mV
Positive full scale + 1/2 lsb
Positive full scale – 1/2 lsb
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 1
0
0
+126 mV
+124 mV
Positive 1/2 scale + 1/2 lsb
Positive 1/2 scale – 1/2 lsb
1 1 0 0 0 0 0 0
1 0 1 1 1 1 1 1
1 0 1 0 0 0 0 0
1 1 1 0 0 0 0 0
0
0
+1 mV
–1 mV
Bipolar zero + 1/2 lsb
Bipolar zero – 1/2 lsb
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
1 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0
0
0
–124 mV
–126 mV
Negative 1/2 scale + 1/2 lsb
Negative 1/2 scale – 1/2 lsb
0 1 0 0 0 0 0 0
0 0 1 1 1 1 1 1
0 1 1 0 0 0 0 0
0 0 1 0 0 0 0 0
0
0
–249 mV
–251 mV
Negative full scale + 1/2 lsb
Negative full scale – 1/2 lsb
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
0
0
< –251 mV < Negative full scale – 1/2 lsb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 6-1. TS8388BGL Pin Description (CBGA68 Package)
Symbol Pin number Function
GND A2, A5, B1, B5, B10, C2, D2, E1, E2, E11,
F1, F2, G11, K2, K3, K4, K5, K10, L2, L5
Ground pins.
To be connected to external ground plane.
V
CC
A4, A6, B2, B4, B6, H1, H2, L6, L7 +5V positive supply.
V
EE
A3, B3, G1, G2, J1, J2 5V analog negative supply.
DV
EE
F10, F11 –5V digital negative supply.
V
IN
L3 In phase (+) analog input signal of the Sample and Hold
differential preamplifier.
V
INB
L4 Inverted phase (-) of ECL clock input signal (CLK).
CLK C1 In phase (+) ECL clock input signal. The analog input is
sampled and held on the rising edge of the CLK signal.
CLKB D1 Inverted phase (-) of ECL clock input signal (CLK).
B0, B1, B2, B3, B4,
B5, B6, B7 A8, A9, A10, D10, H11, J11, K9, K8 In phase (+) digital outputs.
B0 is the LSB. B7 is the MSB.
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Note: 1. The common mode level of the output buffers is 1.2V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0V (ground).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.
If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive
digital supply level in the same proportion in order to spare power dissipation.
B0B, B1B, B2B, B3B,
B4B, B5B, B6B, B7B B7, B8, B9, C11, G10, H10, L10, L9 Inverted phase (-) digital outputs.
B0B is the inverted LSB. B7B is the inverted MSB.
OR K7 In phase (+) Out of Range Bit. Out of Range is high on the
leading edge of code 0 and code 256.
ORB L8 Inverted phase (+) Out of Range Bit (OR).
DR E10 In phase (+) output of Data Ready Signal.
DRB D11 Inverted phase (-) output of Data Ready Signal (DR).
GORB A7
Gray or Binary select output format control pin.
- Binary output format if GORB is floating or V
CC
.
- Gray output format if GORB is connected at ground (0V).
GAIN K6 ADC gain adjust pin. The gain pin is by default grounded, the
ADC gain transfer function is nominally close to one.
DIOD/DRRB K1
Die function temperature measurement pin and
asynchronous data ready reset active low, single-ended ECL
input.
V
PLUSD
B11, C10, J10, K11 +2.4V for LVDS output levels otherwise to GND
(2)
.
NC A1, A11, L1, L11 Not connected.
Table 6-1. TS8388BGL Pin Description (CBGA68 Package)
Symbol Pin number Function
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6.2 TS8388BGL Pinout
Figure 6-1. TS8388BGL Pinout of CBGA 68 Package
1
2
3
4
5
6
7
8
9
10
11
VPLUSD VPLUSD
NC B3b DRb GND GND B4 B5 NCDVEE
GND GNDB2
VPLUSD
B3 DR B4b B5b
VPLUSD
B6b
B2b B6B1 B7b
B1b B7B0 ORb
B0b ORGorb VCC
VCC GAINVCC VCC
GND GNDGND GND
VCC GNDVCC VINB
VEE GNDVEE VIN
DVEE
VCC GNDGND GND GND GND VEE VCC VEE GNDGND
GND DiodeNC
Ball
A1 Index
other side
Bottom View
CLK CLKB GND VEE VCC VEE NCGND
ABCDEFGH JKL
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Notes: 1. Following pin numbers 37 (CLK), 40 (CLKB), 54 (V
IN
) and 57 (V
INB
) have to be connected to GND through a 50Ω resistor as
close as possible to the package (50Ω termination preferred option).
2. The common mode level of the output buffers is 1.2V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0V (ground).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.
If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive
digital supply level in the same proportion in order to spare power dissipation.
Table 6-2. TS8388BF/TS8388BFS Pin Description (CQFP68 Package)
Symbol Pin number Function
GND 5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51,
52, 53, 58, 59
Ground pins.
To be connected to external ground plane.
V
PLUSD
1, 2, 16, 17, 18, 68 Digital positive supply (0V for ECL compatibility, 2.4V for
LVDS compatibility).
(2)
V
CC
26, 29, 32, 33, 46, 47, 61 +5V positive supply.
V
EE
30, 31, 44, 45, 48 –5V analog negative supply.
DV
EE
8, 9, 10 –5V digital negative supply.
V
IN
54
(1)
, 55 In phase (+) analog input signal of the Sample and Hold
differential preamplifier.
V
INB
56, 57
(1)
Inverted phase (-) of analog input signal (V
IN
).
CLK 37
(1)
, 38 In phase (+) ECL clock input signal. The analog input is
sampled and held on the rising edge of the CLK signal.
CLKB 39, 40
(1)
Inverted phase (-) of ECL clock input signal (CLK).
D0, D1, D2, D3, D4,
D5, D6, D7 23, 21, 19, 14, 6, 3, 66, 64 In phase (+) digital outputs.
B0 is the LSB. B7 is the MSB.
D0B, D1B, D2B, D3B,
D4B, D5B, D6B, D7B 24, 22, 20, 15, 7, 4, 67, 65 Inverted phase (-) digital outputs.
B0B is the inverted LSB. B7B is the inverted MSB.
OR 62 In phase (+) Out of Range Bit. Out of Range is high on the
leading edge of code 0 and code 256.
ORB 63 Inverted phase (+) Out of Range Bit (OR).
DR 11 In phase (+) output of Data Ready Signal.
DRB 12 Inverted phase (-) output of Data Ready Signal (DR).
GORB 25
Gray or Binary select output format control pin.
- Binary output format if GORB is floating or V
CC
.
- Gray output format if GORB is connected at ground (0V).
GAIN 60 ADC gain adjust pin.
DIOD/DRRB 49
This pin has a double function (can be left open or grounded
if not used):
- DIOD: die junction temperature monitoring pin.
- DRRB: asynchronous data ready reset function.
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6.3 TS8388BF/TS8388BFS Pinout
Figure 6-2. TS8388BF/TS8388BFS Pinout of CQFP68 Package
Top View
TS8388BF/TS8388BFS
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VPLUSD
VPLUSD
VPLUSD
VPLUSD
D3B
D3
GND
DRB
DR
DVEE
DVEE
DVEE
D4B
D4
GND
D5B
D5
GND
GND
CLK
CLK
CLKb
GND
GND
CLKb
GND
GND
GND
VEE
VEE
VCC
VCC
VEE
Diode
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
GND
VCC
D2B
D1
D1B
VPLUSD
D2
D0
D0B
GORB
VCC
GND
GND
VCC
VEE
VEE
VCC
GND
GND
D6
D7B
D7
VPLUSD
Pin 1 index
D6B
ORB
OR
VCC
Gain
GND
GND
VINb
VINb
VIN
VIN
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
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7. Typical Characterization Results
7.1 Static Linearity
F
S
= 50 Msps/F
IN
= 10 MHz
Figure 7-1. Integral Non-Linearity
Note: Clock Frequency = 50 Msps; Signal Frequency = 10 MHz.
Positive peak: 0.78 lsb; Negative peak: –0.73 lsb.
Figure 7-2. Differential Non-Linearity
Note: Clock Frequency = 50 Msps; Signal Frequency = 10 MHz.
Positive peak: 0.3 lsb; Negative peak: –0.39 lsb.
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7.2 Effective Number of Bits vs. Power Supplies Variation
Figure 7-3. Effective Number of Bits = f (V
EEA
); F
S
= 500 Msps; F
IN
= 100 MHz
Figure 7-4. Effective Number of Bits = f (V
CC
); F
S
= 500 Msps; F
IN
= 100 MHz
0
1
2
3
4
5
6
7
8
-7 -6.5 -6 -5.5 -5 -4.5 -4
VEEA (V)
ENOB (bits)
0
1
2
3
4
5
6
7
8
3 3.5 4 4.5 5 5.5 6 6.5 7
VCC (V)
ENOB (bits)
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Figure 7-5. Effective Number of Bits = f (V
EED
); F
S
= 500 Msps; F
IN
= 100 MHz
7.3 Typical FFT Results
Figure 7-6. F
S
= 1 Gsps; F
IN
= 20 MHz
Figure 7-7. F
S
= 1 Gsps; F
IN
= 495 MHz
0
1
2
3
4
5
6
7
8
-6 -5.5 -5 -4.5 -4 -3.5 -3
VEED (V)
ENOB (bits)
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Figure 7-8. F
S
= 1 Gsps; F
IN
= 995 MHz (
–
3 dB Full Scale Input)
7.4 Spurious Free Dynamic Range vs. Input Amplitude
Figure 7-9. Sampling Frequency: F
S
= 1 Gsps; Input Frequency F
IN
= 995 MHz; Full Scale; ENOB = 6.4;
SINAD = 40 dB; SNR = 44 dB; THD =
–
46 dBc; SFDR =
–
47 dBc; Gray or Binary Output Coding
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Figure 7-10. Sampling Frequency: F
S
= 1 Gsps; Input Frequency F
IN
= 995 MHz;
–
3 dB Full Scale; ENOB = 6.6;
SINAD = 40.8 dB; SNR = 44 dB; THD =
–
48 dBc; SFDR =
–
50 dBc; Gray or Binary Output Coding
7.5 Dynamic Performance vs. Analog Input Frequency
F
S
= 1 Gsps, F
IN
= 0 up to 1600 MHz, Full Scale input (F
S
), F
S
–
3 dB
Clock duty cycle 50/50, Binary/Gray output coding, fully differential or single-ended analog and clock
inputs.
Figure 7-11. ENOB (dB)
3
4
5
6
7
8
0 200 400 600 800 1000 1200 1400 1600 1800
ENOB (dB)
FS
Input Frequency (MHz)
-3 dB FS
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Figure 7-12. SNR (dB)
Figure 7-13. SFDR (dBc)
30
32
34
36
38
40
42
44
46
48
50
0 200 400 600 800 1000 1200 1400 1600 1800
SNR (dB)
FS
Input Frequency (MHz)
-3 dB FS
-60
-55
-50
-45
-40
-35
-30
-25
-20
0 200 400 600 800 1000 1200 1400 1600 1800
SFDR (dBc)
FS
Input Frequency (MHz)
-3 dB FS
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7.6 Effective Number of Bits (ENOB) vs. Sampling Frequency
Analog Input Frequency: F
IN
= 495 MHz and Nyquist conditions (F
IN
= F
S
/2)
Clock duty cycle 50/50, Binary output coding
Figure 7-14. ENOB (dB)
7.7 SFDR vs. Sampling Frequency
Analog Input Frequency: F
IN
= 495 MHz and Nyquist conditions (F
IN
= F
S
/2)
Clock duty cycle 50/50, Binary output coding
Figure 7-15. SFDR (dBc)
2
3
4
5
6
7
8
0 200 400 600 800 1000 1200 1400 1600
ENOB (dB)
Sampling Frequency (MSPS)
FIN = FS/2
FIN = 500 MHz
-60
-55
-50
-45
-40
-35
-30
-25
0 200 400 600 800 1000 1200 1400 1600
SFDR (dBc)
Sampling Frequency (Msps)
FIN = FS/2
FIN = 500 MHz
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7.8 TS8388B ADC Performances vs. Junction Temperature
Figure 7-16. Effective Number of Bits vs. Junction Temperature
F
S
= 1 Gsps; F
IN
= 500 MHz; Duty Cycle = 50%
Figure 7-17. Signal to Noise Ratio vs. Junction Temperature
F
S
= 1 Gsps; F
IN
= 507 MHz; Differential Clock; Single-ended Analog Input (V
IN
=
–
1 dBFs)
Figure 7-18. Total Harmonic Distortion vs. Junction Temperature
F
S
= 1 Gsps; F
IN
= 507 MHz; Differential Clock; Single-ended Analog Input (V
IN
=
–
1 dBFs)
3
4
5
6
7
8
-40 -20 0 20 40 60 80 100 120 140 160
Temperature (°C)
ENOB (bits)
Temperature (°C)
42
43
44
45
46
-60 -40 -20 0 20 40 60 80 100 120
SNR (dB)
Temperature (°C)
43
45
47
49
51
53
-60 -40 -20 0 20 40 60 80 100 120
THD (dB)
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Figure 7-19. Power Consumption vs. Junction Temperature, F
S
= 1 Gsps; F
IN
= 500 MHz; Duty Cycle = 50%
7.9 Typical Full Power Input Bandwidth
Figure 7-20. 1.8 GHz at
–
3 dB (
–
2 dBm Full Power Input) – CBGA68 Package
0
1
2
3
4
5
-40 -20 0 20 40 60 80 100 120 140 160
Power consumption (W)
Temperature (°C)
-6
-5
-4
-3
-2
-1
0
400 600 800 1000 1200 1400 1600 1800 2000
Magnitude (dB)
Frequency (MHz)
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Figure 7-21. 1.5 GHz at
–
3 dB (
–
2 dBm Full Power Input) – CQFP68 Package
7.10 ADC Step Response
Test pulse input characteristics: 20% to 80% input full scale and rise time ~ 200 ps.
Note: This step response was obtained with the TSEV8388B chip on-board (device in die form).
Figure 7-22. Test Pulse Digitized with 20 GHz DSO
-6
-5
-4
-3
-2
-1
0
100 300 500 700 900 1100 1300 1500 1700
Magnitude (dB)
Frequency (MHz)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.00
Time (ns)
Tr ~ 240 ps
50 mV/div
Vpp ~ 260 mV
500 ps/div
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Figure 7-23. Same Test Pulse Digitized with TS8388B ADC
Note: Ripples are due to the test setup (they are present on both measurements).
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.00
200
150
100
50
0
ADC code
Time (ns)
Tr ~ 280 ps
50 codes/div (Vpp ~ 260 mV)
500 ps/div
ADC calculated rise time: between 150 and 200 ps
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8. TS8388B Main Features
8.1 Timing Information
8.1.1 Timing Value for TS8388B
Timing values as defined in Table 5-3 on page 4 are advanced data, issued from electric simulations and
first characterizations results fitted with measurements.
Timing values are given at package inputs/outputs, taking into account package internal controlled
impedance traces propagation delays, gullwing pin model, and specified termination loads.
Propagation delays in 50/75Ω impedance traces are not taken into account for TOD and TDR.
Apply proper derating values corresponding to termination topology.
The min/max timing values are valid over the full temperature range in the following conditions:
• Specified Termination Load (Differential output Data and Data Ready):
50Ω resistor in parallel with 1 standard ECLinPS register from Freescale (that is: 10E452)
Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD
protections).
If addressing an output DMUX, take care if some Digital outputs do not have the same termination
load and apply corresponding derating value given below.
• Output Termination Load derating values for TOD and TDR:
~ 35 ps/pF or 50 ps per additional ECLinPS load.
• Propagation time delay derating values have also to be applied for TOD and TDR:
~ 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation Board.
Apply proper time delay derating value if a different dielectric layer is used.
8.1.2 Propagation Time Considerations
TOD and TDR Timing values are given from pin to pin and do not include the additional propagation
times between device pins and input/output termination loads. For the TSEV8388B Evaluation Board,
the propagation time delay is 6 ps/mm (155 ps/inch) corresponding to 3.4 (at 10 GHz) dielectric constant
of the RO4003 used for the board.
If a different dielectric layer is used (for instance Teflon), please use appropriate propagation time
values.
TD does not depend on propagation times because it is a differential data (TD is the time difference
between data ready output delay and digital data output delay).
TD is also the most straightforward data to measure, again because it is differential: TD can be mea-
sured directly onto termination loads, with matched oscilloscopes probes.
8.1.3 TOD-TDR Variation Over Temperature
Values for TOD and TDR track each other over temperature (1% variation for TOD-TDR per 100°C tem-
perature variation).
Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and pack-
age skews between each Data TODs and TDR effect can be considered as negligible.
Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true
for the TOD and TDR maximum values.
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In other terms:
– If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR).
– If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR). However,
external TOD-TDR values may be dictated by total digital data skews between every TODs
(each digital data) and TDR: MCM Board, bonding wires and output lines lengths
differences, and output termination impedance mismatches.
The external (on board) skew effect has NOT been taken into account for the specification of the mini-
mum and maximum values for TOD-TDR.
8.1.4 Principle of Operation
The Analog input is sampled on the rising edge of external clock input (CLK, CLKB) after TA (aperture
delay) of typically 250 ps. The digitized data is available after 4 clock periods latency (pipeline delay
(TPD)), on clock rising edge, after 1360 ps typical propagation delay TOD.
The Data Ready differential output signal frequency (DR, DRB) is half the external clock frequency, that
is it switches at the same rate as the digital outputs.
The Data Ready output signal (DR, DRB) switches on external clock falling edge after a propagation
delay TDR of typically 1320 ps.
A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is available
for initializing the differential Data Ready output signal (DR, DRB). This feature is mandatory in certain
applications using interleaved ADCs or using a single ADC with demultiplexed outputs. Actually, without
Data Ready signal initialization, it is impossible to store the output digital data in a defined order.
8.2 Principle of Data Ready Signal Control by DRRB Input Command
8.2.1 Data Ready Output Signal Reset
The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low level
(–1.8V). DRRB may also be tied to V
EE
= -5V for Data Ready output signal Master Reset. So long DRRB
remains at logical low level, (or tied to V
EE
= -5V), the Data Ready output remains at logical zero and is
independent of the external free running encoding clock.
The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 920 ps typical.
TRDR is measured between the -1.3V point of the falling edge of DRRB input command and the zero
crossing point of the differential Data Ready output signal (DR, DRB).
The Data Ready Reset command may be a pulse of 1 ns minimum time width.
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8.2.2 Data Ready Output Signal Restart
The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels (-0.8V).
DRRB may also be Grounded, or is allowed to float, for normal free running Data Ready output signal.
The Data Ready signal restart sequence depends on the logical level of the external encoding clock, at
DRRB rising edge instant:
• The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is LOW: The Data
Ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay
time TDR = 1320 ps already defined here above.
• The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is HIGH: The Data
Ready output first rising edge occurs after one clock period on the clock falling edge, and a delay
TDR = 1320 ps.
Consequently, as the analog input is sampled on clock rising edge, the first digitized data corresponding
to the first acquisition (N) after Data Ready signal restart (rising edge) is always strobed by the third ris-
ing edge of the data ready signal.
The time delay (TD1) is specified between the last point of a change in the differential output data (zero
crossing point) to the rising or falling edge of the differential Data Ready signal (DR, DRB) (zero crossing
point).
For normal initialization of Data Ready output signal, the external encoding clock signal frequency and
level must be controlled. It is reminded that the minimum encoding clock sampling rate for the ADC is 10
Msps and consequently the clock cannot be stopped.
One single pin is used for both DRRB input command and die junction temperature monitoring. Pin
denomination will be DRRB/DIOD. On the former version denomination was DIOD. Temperature moni-
toring and Data Ready control by DRRB is not possible simultaneously.
8.3 Analog Inputs (V
IN
) (V
INB
)
The analog input Full Scale range is 0.5V peak to peak (Vpp), or
–
2 dBm into the 50Ω termination
resistor.
In differential mode input configuration, that means 0.25V on each input, or
±
125 mV around 0V. The
input common mode is ground.
The typical input capacitance is 3 pF for TS8388B in CQFP and CBGA packages.
The input capacitance is mainly due to the package.
8.3.1 Differential Inputs Voltage Span
Figure 8-1. Differential Inputs Voltage Span
-125
125
[mV]
-250 mV
VIN
(VIN, VINB) = ±250 mV = 500 mV diff
500 mV
Full Scale
analog input
t
VINB
0V
250 mV
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8.3.2 Differential vs. Single-ended Analog Input Operation
The TS8388B can operate at full speed in either differential or single-ended configuration.
This is explained by the fact the ADC uses a high input impedance differential preamplifier stage, (pre-
ceeding the sample and hold stage), which has been designed in order to be entered either in differential
mode or single-ended mode.
This is true so long as the out-of-phase analog input pin V
INB
is 50Ω terminated very closely to one of the
neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground reference for the
inphase analog input pin (V
IN
).
Thus the differential analog input preamplifier will fully reject the local ground noise (and any capacitively
and inductively coupled noise) as common mode effects.
In typical single-ended configuration, enter on the (V
IN
) input pin, with the inverted phase input pin (V
INB
)
grounded through the 50Ω termination resistor.
In single-ended input configuration, the in-phase input amplitude is 0.5V peak to peak, centered on 0V
(or -2 dBm into 50Ω). The inverted phase input is at ground potential through a 50Ω termination resistor.
However, dynamic performances can be somewhat improved by entering either analog or clock inputs in
differential mode.
8.3.3 Typical Single-ended Analog Input Configuration
Figure 8-2. Typical Single-ended Analog Input Configuration
Note: Since VIN and VINB have a double pad architecture, a 50Ω reverse termination is needed. For the CBGA
package, this reverse termination is already on package.
8.4 Clock Inputs (CLK) (CLKB)
The TS8388B can be clocked at full speed without noticeable performance degradation in either differen-
tial or single-ended configuration.
This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has
been designed in order to be entered either in differential or single-ended mode.
Recommended sinewave generator characteristics are typically
–
120 dBc/Hz phase noise floor spectral
density, at 1 kHz from carrier, assuming a single tone 4 dBm input for the clock signal.
8.4.1 Single-ended Clock Input (Ground Common Mode)
Although the clock inputs were intended to be driven differentially with nominal
–
0.8V/
–
1.8V ECL levels,
the TS8388B clock buffer can manage a single-ended sinewave clock signal centered around 0V. This is
the most convenient clock input configuration as it does not require the use of a power splitter.
50Ω
(external or
on package)
1 MΩ3 pF
-250
250
500 mV
t
[mV]
VIN
VIN = ±250 mV = 500 mV diff
VIN or VINB double pad (pins 54, 55 or 56, 57)
VIN or VINB
50Ω reverse termination
500 mV
Full Scale
analog input
VINB = 0V
VINB
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No performance degradation (that is: due to timing jitter) is observed in this particular single-ended con-
figuration up to 1.2 Gsps Nyquist conditions (F
IN
= 600 MHz).
This is true so long as the inverted phase clock input pin is 50Ω terminated very closely to one of the
neighboring shield ground pins, which constitutes the local Ground reference for the inphase clock input.
Thus the TS8388B differential clock input buffer will fully reject the local ground noise (and any capaci-
tively and inductively coupled noise) as common mode effects. Moreover, a very low phase noise
sinewave generator must be used for enhanced jitter performance.
The typical inphase clock input amplitude is 1V peak to peak, centered on 0V (ground) common mode.
This corresponds to a typical clock input power level of 4 dBm into the 50Ω termination resistor. Do not
exceed 10 dBm to avoid saturation of the preamplifier input transistors.
The inverted phase clock input is grounded through the 50Ω termination resistor.
Figure 8-3. Single-ended Clock Input (Ground common mode):
VCLK Common Mode = 0V; VCLKB = 0V; 4 dBm Typical Clock Input Power Level (into 50Ω termination
resistor)
Note: Do not exceed 10 dBm into the 50Ω termination resistor for single clock input power level.
8.4.2 Differential ECL Clock Input
The clock inputs can be driven differentially with nominal
–
0.8V/
–
1.8V ECL levels.
In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, followed by a
power splitter (hybrid junction) in order to obtain 180 degrees out of phase sinewave signals. Biasing
tees can be used for offseting the common mode voltage to ECL levels.
Note: As the biasing tees propagation times are not matching, a tunable delay line is required in order to
ensure the signals to be 180 degrees out of phase especially at fast clock rates in the Gsps range.
Figure 8-4. Differential Clock Inputs (ECL Levels)
50Ω
(external or
on package)
1 MΩ0.4 pF
-0.5V
+0.5V
t
[V]
VCLK
CLK or CLKB double pad (pins 37, 38 or 39, 40)
CLK or CLKB
50Ω reverse termination
VCLK = 0V
VCLK
50Ω
(external or
on package)
1 MΩ0.4 pF
CLK or CLKB double pad (pins 37, 38 or 39, 40)
CLK or CLKB
-2V
50Ω reverse termination
-1.8V
-0.8V
[mV]
VCLK
t
VCLKB
Common mode = -1.3V
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8.4.3 Single-ended ECL Clock Input
In single-ended configuration enter on CLK (resp. CLKB) pin, with the inverted phase clock input pin
CLKB (respectively CLK) connected to
–
1.3V through the 50Ω termination resistor.
The inphase input amplitude is 1V peak to peak, centered on
–
1.3V common mode.
Figure 8-5. Single-ended Clock Input (ECL):
VCLK Common Mode =
–
1.3V; VCLKB =
–
1.3V
8.5 Noise Immunity Information
Circuit noise immunity performance begins at design level.
Efforts have been made on the design in order to make the device as insensitive as possible to chip
environment perturbations resulting from the circuit itself or induced by external circuitry (Cascode
stages isolation, internal damping resistors, clamps, internal (on-chip) decoupling capacitors).
Furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced
noise immunity by common mode noise rejection.
Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by
these balanced differential amplifiers.
Moreover, proper active signals shielding has been provided on the chip to reduce the amount of cou-
pled noise on the active inputs.
The analog inputs and clock inputs of the TS8388B device have been surrounded by ground pins, which
must be directly connected to the external ground plane.
8.6 Digital Outputs
The TS8388B differential output buffers are internally 75Ω loaded. The 75Ω resistors are connected to
the digital ground pins through a
–
0.8V level shift diode (see Figure 8-6, Figure 8-7, Figure 8-8 on page
36).
The TS8388B output buffers are designed for driving 75Ω (default) or 50Ω properly terminated imped-
ance lines or coaxial cables. An 11 mA bias current flowing alternately into one of the 75Ω resistors
when switching ensures a 0.825V voltage drop across the resistor (unterminated outputs).
The V
PLUSD
positive supply voltage allows the adjustment of the output common mode level from
–
1.2V
(V
PLUSD
= 0V for ECL output compatibility) to +1.2V (V
PLUSD
= 2.4V for LVDS output compatibility).
Therefore, the single-ended output voltages vary approximately between
–
0.8V and
–
1.625V, (outputs
unterminated), around
–
1.2V common mode voltage.
Three possible line driving and back-termination scenarios are proposed (assuming V
PLUSD
= 0V):
-1.8V
-0.8V
t
[V]
VCLK
VCLKB = -1.3V
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1. 75Ω impedance transmission lines, 75Ω differentially terminated (Figure 8-6):
Each output voltage varies between
–
1V and
–
1.42V (respectively +1.4V and +1V), leading to
±
0.41V = 0.825V in differential, around
–
1.21V (respectively +1.21V) common mode for V
PLUSD
= 0V
(respectively 2.4V).
2. 50Ω impedance transmission lines, 50Ω differentially termination (Figure 8-7):
Each output voltage varies between
–
1.02V and
–
1.35V (respectively +1.38V and +1.05V), leading
to
±
0.33V = 660 mV in differential, around
–
1.18V (respectively +1.21V) common mode for V
PLUSD
=
0V (respectively 2.4V).
3. 75Ω impedance open transmission lines (Figure 8-8):
Each output voltage varies between
–
1.6V and
–
0.8V (respectively +0.8V and +1.6V), which are true
ECL levels, leading to
±
0.8V = 1.6V in differential, around
–
1.2V (respectively +1.2V) common mode
for V
PLUSD
= 0V (respectively 2.4V). Therefore, it is possible to drive directly high input impedance
storing registers, without terminating the 75Ω transmission lines. In time domain, that means that the
incident wave will reflect at the 75Ω transmission line output and travel back to the generator (that is:
the 75Ω data output buffer). As the buffer output impedance is 75Ω, no back reflection will occur.
Note: This is no longer true if a 50Ω transmission line is used, as the latter is not matching the buffer 75Ω
output impedance.
Each differential output termination length must be kept identical. It is recommended to decouple the
midpoint of the differential termination with a 10 nF capacitor to avoid common mode perturbation in
case of slight mismatch in the differential output line lengths.
Too large mismatches (keep < a few mm) in the differential line lengths will lead to switching currents
flowing into the decoupling capacitor leading to switching ground noise.
The differential output voltage levels (75Ω or 50Ω termination) are not ECL standard voltage levels, how-
ever it is possible to drive standard logic ECL circuitry like the ECLinPS logic line from
Freescale
®
.
At sampling rates exceeding 1 Gsps, it may be difficult to trigger any Acquisition System with digital out-
puts. It becomes necessary to regenerate digital data and Data Ready by means of external amplifiers,
in order to be able to test the TS8388B at its optimum performance conditions.
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8.6.1 Differential Output Loading Configurations (Levels for ECL Compatibility)
Figure 8-6. Differential Output: 75Ω Terminated
Figure 8-7. Differential Output: 50Ω Terminated
-0.8V
75Ω75Ω
-+
11 mA
DVEE
75Ω
75Ω
impedance
Out
OutB
75Ω
75Ω
-1V/-1.41V
10 nF
Differential output:
+0.41V = 0.825V
-1.41V/-1V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 0V
-0.8V
75Ω75Ω
-+
11 mA
DVEE
50Ω
50Ω
impedance
Out
OutB
50Ω
50Ω
-1.02V/-1.35V
10 nF
Differential output:
+0.33V = 0.660V
-1.35V/-1.02V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 0V
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Figure 8-8. Differential Output: Open Loaded
8.6.2 Differential Output Loading Configurations (Levels for LVDS Compatibility)
Figure 8-9. Differential Output: 75Ω Terminated
-0.8V
75Ω75Ω
-+
11 mA
DVEE
75Ω
75Ω
impedance
Out
OutB
-0.8V/-1.6V
Differential output:
+0.8V = 1.6V
-1.6V/-0.8V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 0V
1.6V
75Ω75Ω
-+
11 mA
DVEE
75Ω
75Ω
impedance
Out
OutB
75Ω
75Ω
1.4V/0.99V
10 nF
Differential output:
+0.41V = 0.825V
0.99V/1.4V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 2.4V
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Figure 8-10. Differential Output: 50Ω Terminated
Figure 8-11. Differential Output: Open Loaded
8.7 Out of Range Bit
An Out of Range (OR, ORB) bit is provided that goes to logical high state when the input exceeds the
positive full scale or falls below the negative full scale.
When the analog input exceeds the positive full scale, the digital output data remain at high logical state,
with (OR, ORB) at logical one.
When the analog input falls below the negative full scale, the digital outputs remain at logical low state,
with (OR, ORB) at logical one again.
8.8 Gray or Binary Output Data Format Select
The TS8388B internal regeneration latches indecision (for inputs very close to latches threshold) may
produce errors in the logic encoding circuitry and leading to large amplitude output errors.
This is due to the fact that the latches are regenerating the internal analog residues into logical states
with a finite voltage gain value (Av) within a given positive amount of time ∆(t):
Av = exp(∆(t)/τ), with τ the positive feedback regeneration time constant.
1.6V
75Ω75Ω
-+
11 mA
DVEE
50Ω
50Ω
impedance
Out
OutB
50Ω
50Ω
1.38V/1.05V
10 nF
Differential output:
+0.33V = 0.660V
1.05V/1.38V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 2.4V
1.6V
75Ω75Ω
-+
11 mA
DVEE
75Ω
75Ω
impedance
Out
OutB
1.6V/0.8V
Differential output:
+0.8V = 1.6V
0.8V/1.6V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 2.4V
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The TS8388B has been designed for reducing the probability of occurrence of such errors to approxi-
mately 10
-13
(targeted for the TS8388B at 1 Gsps).
A standard technique for reducing the amplitude of such errors down to
±
1 lsb consists of outputting the
digital data in Gray code format. Though the TS8388B has been designed for featuring a Bit Error Rate
of 10
-13
with a binary output format, it is possible for the user to select between the Binary or Gray output
data format, in order to reduce the amplitude of such errors when occurring, by storing Gray output
codes.
Digital data format selection:
• Binary output format if GORB is floating or V
CC
• Gray output format if GORB is connected to ground (0V)
8.9 Diode Pin 49
One single pin is used for both DRRB input command and die junction monitoring. The pin denomination
is DRRB/DIOD. Temperature monitoring and Data Ready control by DRRB is not possible
simultaneously.
(See “Principle of Data Ready Signal Control by DRRB Input Command” on page 29 for Data Ready
Reset input command).
The operating die junction temperature must be kept below 145°C, therefore an adequate cooling sys-
tem has to be set up. The diode mounted transistor measured Vbe value vs. junction temperature is
given below.
Figure 8-12. Diode Pin 49
600
640
680
720
760
800
840
880
920
960
1000
-55 -35 -15 5 25 45 65 85 105 125
VBE (mV)
Junction temperature (°C)
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8.10 ADC Gain Control Pin 60
The ADC gain is adjustable by the means of the pin 60 (input impedance is 1 MΩ in parallel with 2 pF).
The gain adjust transfer function is given below.
Figure 8-13. ADC Gain Control Pin 60
Note: For more information, please refer to the document "DEMUX and ADCs Application Notes".
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
-500 -400 -300 -200 -100 0 100 200 300 400 500
ADC Gain
Vgain (command voltage) (mV)
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9. Equivalent Input/Output Schematics
Figure 9-1. Equivalent Analog Input Circuit and ESD Protections
Note: The ESD protection equivalent capacitance is 150 fF.
Figure 9-2. Equivalent Analog Clock Input Circuit and ESD Protections
Note: The ESD protection equivalent capacitance is 150 fF.
VEE VEE
5.8V
0.8V
200Ω200Ω
50Ω50Ω
E21V
E21G E21G
E21V
VIN
GND = 0V
VINB
Pad
capacitance
340 fF
Pad
capacitance
340 fF
VCC = +5V
-0.8V
-5.8V
5.8V
0.8V
-0.8V
-5.8V
VCLAMP = +2.4V
+1.65V
-1.55V
VEE = -5V
GND
VCC
VEE VEE
5.8V
0.8V
150Ω150Ω
E31V
E21GE21G
E31V
CLK CLKB
Pad
capacitance
340 fF
Pad
capacitance
340 fF
VCC = +5V
-5.8V
-5.8V
-5.8V
5.8V
0.8V
-0.8V
-5.8V
-5.8V
+0.8V
GND = 0V
380 µA
VEE = -5V
VCC
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Figure 9-3. Equivalent Data Output Buffer Circuit and ESD Protections
Note: The ESD protection equivalent capacitance is 150 fF.
Figure 9-4. ADC Gain Adjust Equivalent Analog Input Circuit and ESD Protections
Note: The ESD protection equivalent capacitance is 150 fF.
5.8V
0.8V
0.8V
VEE VEE
-5.8V
E21GA
E01V E01V
-5.8V
OUT
Pad
capacitance
180 fF
DVEE = -5V
VPLUSD = 0V to 2.4V
VEE = -5V VEE = -5V
5.8V
0.8V
0.8V
OUTB
Pad
capacitance
180 fF
VEE
1 kΩ
GA
Pad
capacitance
180 fF 2 pF
NP1032C2
+0.8V
500 µA 500 µA
VEE = -5V
E22V
VCC = +5V
GND
GND
-0.8V
-5.8V
0.8V
0.8V
5.8V
E22GA
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Figure 9-5. GORB Equivalent Input Schematic and ESD Protections
GORB: Gray or Binary Select Input, Floating or Tied to V
CC
-> Binary
Note: The ESD protection equivalent capacitance is 150 fF.
Figure 9-6. DRRB Equivalent Input Schematic and ESD Protections
(Actual protection range: 6.6V above V
EE
, in fact stress above GND are clipped by the CB diode used for
T
J
monitoring)
Note: The ESD protection equivalent capacitance is 150 fF.
5.8V
5.8V
5.8V
VEE
E21VA
-0.8V
-0.8V
-5.8V
E31G
1 kΩ
5 kΩ
1 kΩ
1 kΩ
GORB
Pad
capacitance
180 fF
VCC = +5V
250 µA 250 µA
GND = 0V
VEE = -5V
5.8V
-2.6V
-1.3V
0.8V
200Ω
10 kΩ
E21G
DRRB
VEE
GND=0V
VCC = +5V
VEE = -5V
Pad
capacitance
180 fF
NP1032C2
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10. TSEV8388B: Device Evaluation Board
For complete specification, see separate TSEV8388B document.
10.1 General Description
The TSEV8388B Evaluation Board (EB) is a board which has been designed in order to facilitate the
evaluation and the characterization of the TS8388B device up to its 1.5 GHz full power bandwidth at up
to 1 Gsps in the military temperature range.
The high speed of the TS8388B requires careful attention to circuit design and layout to achieve optimal
performance.
This four metal layer board with internal ground plane has the adequate functions in order to allow a
quick and simple evaluation of the TS8388B ADC performances over the temperature range.
The TSEV8388B Evaluation Board is very straightforward as it only implements the TS8388B ADC, SMA
connectors for input/output accesses and a 2.54 mm pitch connector compatible with high speed acqui-
sition system probes.
The board also implements a de-embedding fixture in order to facilitate the evaluation of the high fre-
quency insertion loss of the input microstrip lines, and a die junction temperature measurement setting.
The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and enhanced
thermal characteristics for operation in the high frequency domain and extended temperature range.
The board dimensions are 130 mm x 130 mm.
The board set comes fully assembled and tested, with the TS8388B installed.
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10.2 CBGA68 Thermal and Moisture Characteristics
10.2.1 Thermal Resistance from Junction to Ambient: RTHJA
The following table lists the converter thermal performance parameters of the device itself, with no exter-
nal heatsink added.
Figure 10-1. Thermal Resistance from Junction to Ambient: RTHJA
Table 10-1. Thermal Resistance
Air flow (m/s) Estimated JA thermal resistance (
°
C/W)
045
0.5 35.8
130.8
1.5 27.4
224.9
2.5 23
321.5
419.3
517.7
RTHJA (°C/W)
Air flow (m/s)
0
0
10
20
30
40
50
12 345
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10.2.2 Thermal Resistance from Junction to Case: RTHJC
Typical value for Rthjc is given to 6.7
°
C/W (8
°
C/W max).
This value does not include thermal contact resistance between package and external component (heat-
sink or PCBoard).
As an example, 2.0°C/W can be taken for 50 µm of thermal grease.
10.2.3 CBGA68 Board Assembly with External Heatsink
It is recommended to use an external heatsink or PCBoard special design.
Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated in the
device.
Figure 10-2. CBGA68 Board Assembly
10.2.4 Moisture Characteristics
This device is sensitive to the moisture (MSL3 according to JEDEC standard):
Shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH).
After this bag is opened, devices that will be subjected to infrared reflow, vapor-phase reflow, or equiva-
lent processing (peak package body temperature 220°C) must be:
• Mounted within 198 hours at factory conditions of ≤30°C/60% RH, or
• Stored at ≤20% RH.
Devices require baking, before mounting, if Humidity Indicator Card is >20% when read at 23°C ±5°C.
If baking is required, devices may be baked for:
• 192 hours at 40°C +5°C/
–
0°C and <5% RH for low-temperature device containers, or
• 24 hours at 125°C ±5°C for high temperature device containers.
31
32.5
Board
50.5
20.224.2
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10.3 Nominal CQFP68 Thermal Characteristics
Although the power dissipation is low for this performance, the use of a heat sink is mandatory.
The user will find some advice on this topics below.
10.3.1 Thermal Resistance from Junction to Ambient: RTHJA
The following table lists the converter thermal performance parameters, with or without heatsink.
For the following measurements, a 50 x 50 x 16 mm heatsink has been used (see Figure 10-4 on page
47).
Note: 1. Heatsink is glued to backside of package or screwed and pressed with thermal grease.
Figure 10-3. Thermal Resistance from Junction to Ambient: RTHJA
Table 10-2. Thermal Resistance
Air Flow
(m/s)
Estimated JA Thermal Resistance (
°
C/W)
CQFP68 on Board
Estimated – without Heatsink Targeted – with Heatsink
(1)
050 10
0.5 40 8.9
135 7.9
1.5 32 7.3
230 6.8
2.5 28 6.5
326 6.2
424 5.8
523.5 5.6
RTHJA (°C/W)
Air Flow (m/s)
0
0
10
20
30
40
50
60
123 45
Without heatsink
With heatsink
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10.3.2 Thermal Resistance from Junction to Case: RTHJC
Typical value for Rthjc is given to 4.75°C/W.
10.3.3 CQFP68 Board Assembly
Figure 10-4. CQFP68 Board Assembly with a 50 x 50 x 16 mm External Heatsink
24.13
28.96
15.0
1.3 3.2
50.0
1.4 4.0
2.5
16.0
Printed circuit
Interface: Af-filled epoxy or thermal
conductive grease - 100 µm max.
Aluminum heatsink
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10.4 Enhanced CQFP68 Thermal Characteristics
10.4.1 Enhanced CQFP68
The CQFP68 has been modified, in order to improve the thermal characteristics:
• A CuW heatspreader has been added at the bottom of the package.
• The die has been electrically isolated with the ALN substrate.
10.4.2 Thermal Resistance from Junction to Case: RTHJC
Typical value for Rthjc is given to 1.56°C/W.
This value does not include thermal contact resistance between package and external component (heat-
sink or PCBoard).
As an example, 2.0°C/W can be taken for 50 µm of thermal grease.
10.4.3 Heatsink
It is recommended to use an external heatsink, or PCBoard special design.
The stand off has been calculated to permit the simultaneous soldering of the leads and of the
heatspreader with the solder paste.
Figure 10-5. Enhanced CQFP68 Suggested Assembly
Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated in the
device.
Printed
circuit board
CuW heatspreader
28.78
Thermal via Solid ground plane
24.13
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10.5 Definitions
10.5.1 Definition of Terms
10.5.1.1 (BER) Bit Error Rate
Probability to exceed a specified error threshold for a sample. An error code is a code that differs by
more than
±
4 lsb from the correct code.
10.5.1.2 (FPBW) Full Power Input Bandwidth
Analog input frequency at which the fundamental component in the digitally reconstructed output has
fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at Full Scale.
10.5.1.3 (SINAD) Signal to Noise and Distortion Ratio
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS sum of all
other spectral components, including the harmonics except DC.
10.5.1.4 (SNR) Signal to Noise Ratio
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS sum of all
other spectral components excluding the five first harmonics.
10.5.1.5 (THD) Total Harmonic Distortion
Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS value of the
measured fundamental spectral component.
10.5.1.6 (SFDR) Spurious Free Dynamic Range
Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below Full Scale, to the RMS value of the
next highest spectral component (peak spurious spectral component). SFDR is the key parameter for
selecting a converter to be used in a frequency domain application (Radar systems, digital receiver, net-
work analyzer, etc.). It may be reported in dBc (that is: degrades as signal levels is lowered), or in dBFS
(that is: always related back to converter full scale).
10.5.1.7 (ENOB) Effective Number of Bits
Where A is the actual input amplitude and V is the full scale range of the ADC under test.
10.5.1.8 (DNL) Differential Non Linearity
The Differential Non Linearity for an output code i is the difference between the measured step size of
code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL
(i). DNL error specification of less than 1 lsb guarantees that there are no missing output codes and that
the transfer function is monotonic.
10.5.1.9 (INL) Integral Nonlinearity
The Integral Non Linearity for an output code i is the difference between the measured input voltage at
which the transition occurs and the ideal value of this transition.
INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.
SINAD - 1.76 + 20 log (A/V/2)
6.02
ENOB =
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10.5.1.10 (DG) Differential Gain
The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full Scale peak to
peak amplitude. F
IN
= 5 MHz (TBC).
10.5.1.11 (DP) Differential Phase
Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full Scale peak to
peak amplitude. F
IN
= 5 MHz (TBC).
10.5.1.12 (TA) Aperture Delay
Delay between the rising edge of the differential clock inputs (CLK, CLKB) (zero crossing point), and the
time at which (V
IN
, V
INB
) is sampled.
10.5.1.13 (JITTER) Aperture Uncertainty
Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of
the signal at the sampling point.
10.5.1.14 (TS) Settling Time
Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step function is
applied to the differential analog input.
10.5.1.15 (ORT) Overvoltage Recovery Time
Time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input is reduced
to midscale.
10.5.1.16 (TOD) Digital Data Output Delay
Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to the next
point of change in the differential output data (zero crossing) with specified load.
10.5.1.17 (TD1) Time Delay from Data to Data Ready
Time delay from Data transition to Data ready.
10.5.1.18 (TD2) Time Delay from Data Ready to Data
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock period.
10.5.1.19 (TC) Encoding Clock Period
TC1 = Minimum clock pulse width (high) TC = TC1 + TC2
TC2 = Minimum clock pulse width (low)
10.5.1.20 (TPD) Pipeline Delay
Number of clock cycles between the sampling edge of an input data and the associated output data
being made available, (not taking in account the TOD). For the TS8388B the TPD is 4 clock periods.
10.5.1.21 (TRDR) Data Ready Reset Delay
Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB) and the
reset to digital zero transition of the Data Ready output signal (DR).
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10.5.1.22 (TR) Rise Time
Time delay for the output DATA signals to rise from 20% to 80% of delta between low level and high
level.
10.5.1.23 (TF) Fall Time
Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and high level.
10.5.1.24 (PSRR) Power Supply Rejection Ratio
Ratio of input offset variation to a change in power supply voltage.
10.5.1.25 (NRZ) Non Return to Zero
When the input signal is larger than the upper bound of the ADC input range, the output code is identical
to the maximum code and the Out of Range bit is set to logic one. When the input signal is smaller than
the lower bound of the ADC input range, the output code is identical to the minimum code, and the Out of
range bit is set to logic one. (It is assumed that the input signal amplitude remains within the absolute
maximum ratings).
10.5.1.26 (IMD) Intermodulation Distortion
The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the worst third
order intermodulation products. The input tones levels are at
–
7 dB Full Scale.
10.5.1.27 (NPR) Noise Power Ratio
The NPR is measured to characterize the ADC performance in response to broad bandwidth signals.
When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the
Noise Power Ratio is defined as the ratio of the average out-of-notch to the average in-notch power
spectral density magnitudes for the FFT spectrum of the ADC output sample test.
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11. Ordering Information
Table 11-1. Ordering Information
Part Number Package Temperature Range Screening Comments
JTS8388B-1V1B Die Ambient Visual inspection ON REQUEST ONLY
(Please contact Marketing)
JTS8388B-1V2B Die Ambient and High
temperature (T
J
= 125°C) Visual inspection ON REQUEST ONLY
(Please contact Marketing)
TS8388BCF CQFP 68 C" grade
0°C < Tc; T
J
< 90°CStandard
TS8388BVF CQFP 68 "V" grade
–40°C < Tc; T
J
< 110°CStandard
TS8388BMF CQFP 68 "M" grade
–55°C < Tc; T
J
< 125°CStandard
TS8388BMF B/Q CQFP 68 "M" grade
–55°C < Tc; T
J
< 125°C
Mil-PRF-38535,
QML level Q DSCC 5962-0050401QYC
TS8388BMF B/T CQFP 68 "M" grade
–55°C < Tc; T
J
< 125°C
Standard + 3 temperatures
test (min, ambient, max)
TS8388BCFS CQFP 68 with
heatspreader
"C" grade
0°C < Tc; T
J
< 90°CStandard
TS8388BVFS CQFP 68 with
heatspreader
"V" grade
–40°C < Tc; T
J
< 110°CStandard
TS8388BMFS CQFP 68 with
heatspreader
"M" grade
–55°C < Tc; T
J
< 125°CStandard
TS8388BMFS B/Q CQFP 68 with
heatspreader
"M" grade
–55°C < Tc; T
J
< 125°C
Mil-PRF-38535,
QML level Q DSCC 5962-0050401QXC
TS8388BMFS B/T CQFP 68 with
heatspreader
"M" grade
–55°C < Tc; T
J
< 125°C
Standard + 3 temperatures
test (min, ambient, max)
TS8388BMFS9NB2 CQFP 68 with
heatspreader
"M" grade
–55°C < Tc; T
J
< 125°C
. ESA/SCC9000 Screening
. Non ESA/SCC qualified
. Level B selection
. Lot Acceptance Test 2
TS8388BMFS9NB3 CQFP 68 with
heatspreader
"M" grade
–55°C < Tc; T
J
< 125°C
. ESA/SCC9000 Screening
. Non ESA/SCC qualified
. Level B selection
. Lot Acceptance Test 3
TS8388BMFS9NC2 CQFP 68 with
heatspreader
"M" grade
–55°C < Tc; T
J
< 125°C
. ESA/SCC9000 Screening
. Non ESA/SCC qualified
. Level C selection
. Lot Acceptance Test 2
TS8388BMFS9NC3 CQFP 68 with
heatspreader
"M" grade
–55°C < Tc; T
J
< 125°C
. ESA/SCC9000 Screening
. Non ESA/SCC qualified
. Level C selection
. Lot Acceptance Test 3
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TS8388B
TS8388BCGL CBGA 68 "C" grade
0°C < Tc; T
J
< 90°CStandard
TS8388BVGL CBGA 68 "V" grade
–40°C < Tc; T
J
< 110°CStandard
TSEV8388BF CQFP 68 Ambient Prototype Evaluation board (delivered
with heatsink)
TSEV8388BFZA2 CQFP 68 Ambient Prototype
Evaluation board with digital
receivers (delivered with
heatsink)
TSEV8388BGL CBGA 68 Ambient Prototype Evaluation board (delivered
with heatsink)
TSEV8388BGLZA2 CBGA 68 Ambient Prototype
Evaluation board with digital
receivers (delivered with
heatsink)
Table 11-1. Ordering Information (Continued)
Part Number Package Temperature Range Screening Comments
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11.1 CBGA68 Capacitors and Resistors Implant
Figure 11-1. TS8388BGL Capacitors and Resistors Implant
Note: R and C are discrete components of 0603 size (1.6 x 0.8 mm).
GND
100 pF
DVEE
CLK
50Ω
GND
CLKB
50Ω
GND
VEE
100 pF
GND
VCC
100 pF
GND
VEE
100 pF
GND
GND
100 pF
GORB
VCC
100 pF
GND
VCC
100 pF
GND
VEE
100 pF
GND
VCC
100 pF
GND
GND
100 pF
GAIN
GND
50Ω
VINB
GND
50Ω
VIN
VCC
100 pF
GND
Only on-package marking
Electrically isolated
0.9 mm
0.9 mm
0.9 mm
∅ 7.0 mm
0.9 mm
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11.2 Outline Descriptions
Figure 11-2. Package Dimension – 68 Pins CBGA
CBGA 68 package.
AL203 substrate.
Package design.
Corner balls (x4) are not connected (mechanical ball).
Balls : 1.27 mm pitch on 11x11 grid.
View balls side
Top side with
soldered R, C
devices
(using solder
Sn/Pb 63/37) Balls side
Balls
Sn/Pb 63/37
AI203 substrate
AI203 Ceramic
Cap.
Glued and embedded
in substrate
0.63 ± 0.10
All units in mm
1.45 ± 0.12
15.00 ± 0.15 mm
72x∅ D = 0.80 ± 0.10 mm
ABCDEFGHJKL
1
2
3
4
5
6
7
8
9
10
11
Ball
A1 Index
other side
1.27 ref
1.27
15.00 ± 0.15 mm
7.84
7.84
- B -
Detail of
ball x2
0.40
0.15
TAB
T
(Position of array of balls / edges A and B)
(Position of balls within array)
- A -
0.15
0.95 max
100 pF
0.20 T
- T -
50 Ω
1.00
D
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11.3 Outline Dimensions
Figure 11-3. Package Dimension – 68-lead Ceramic Quad Flat Pack (CQFP)
CQFP 68
TOP VIEW
0.8 BCS
20.32 BSC
0.050 BCS
1.27 BSC
Pin N° 1 index
0.023 ± 0.002
0.58 ± 0.05
24.13 ± 0.152
0.950 ± 0.006
28.78 - 29.13
1.133 - 1.147
0.13 - 0.25
0.005 - 0.010
0.70 - 0.95
0° - 8°
0.027 - 0.037
0.950 ± 0.006
24.13 ± 0.152
1.133 - 1.147
28.78 - 29.13
0.075 ± 0.008
1.9 ± 0.20
0.135 Max
3.43 Max
0.018 - 0.035
0.46 - 0.88
M∅
0.005ZXY
0.004
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Figure 11-4. Package Dimension – 68-lead Enhanced CQFP with Heatspreder
CQFP 68
TOP VIEW
0.8 BCS
20.32 BSC
0.050 BCS
1.27 BSC
Pin N° 1 index
0.023 ± 0.002
0.58 ± 0.05
24.13 ± 0.152
0.950 ± 0.006
28.78 - 29.13
1.133 - 1.147
0.13 - 0.25
0.005 - 0.010
0.70 - 0.95
0° - 8°
0.027 - 0.037
0.950 ± 0.006
24.13 ± 0.152
1.133 - 1.147
28.78 - 29.13
0.0310
0.787
0.0385
0.978
0.007 ± 0.005
0.18 ± 0.13
M∅
0.005ZX
Y
0.020 ± 0.005
0.51 ± 0.13
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12. Datasheet Status Description
12.1 Life Support Applications
These products are not designed for use in life support appliances, devices or systems where malfunc-
tion of these products can reasonably be expected to result in personal injury. e2v customers using or
selling these products for use in such applications do so at their own risk and agree to fully indemnify e2v
for any damages resulting from such improper use or sale.
Table 12-1. Datasheet Status
Datasheet Status Validity
Objective specification
This datasheet contains target and
goal specifications for discussion with
customer and application validation.
Before design phase
Target specification
This datasheet contains target or
goal specifications for product
development.
Valid during the design phase
Preliminary specification
α-site
This datasheet contains preliminary
data. Additional data may be
published later; could include
simulation results.
Valid before characterization
phase
Preliminary specification
β-site
This datasheet contains also
characterization results.
Valid before the
industrialization phase
Product specification This datasheet contains final product
specification. Valid for production purposes
Limiting Values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress
above one or more of the limiting values may cause permanent damage to the device. These are
stress ratings only and operation of the device at these or at any other conditions above those given in
the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application Information
Where application information is given, it is advisory and does not form part of the specification.
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1 Features .................................................................................................... 1
2 Applications ............................................................................................. 1
3 Description ............................................................................................... 1
4 Functional Description ............................................................................ 2
4.1 Block Diagram ......................................................................................................2
4.2 Functional Description ..........................................................................................2
5 Specifications .......................................................................................... 3
5.1 Absolute Maximum Ratings .................................................................................. 3
5.2 Recommended Operating Conditions ...................................................................3
5.3 Electrical Operating Characteristics ......................................................................4
5.4 Timing Diagrams ................................................................................................. 10
5.5 Explanation of Test Levels ..................................................................................11
5.6 Functions Description .........................................................................................11
5.7 Digital Output Coding ..........................................................................................12
6 Package Description ............................................................................. 12
6.1 Pin Description .................................................................................................... 12
6.2 TS8388BGL Pinout ............................................................................................. 14
6.3 TS8388BF/TS8388BFS Pinout ...........................................................................16
7 Typical Characterization Results ......................................................... 17
7.1 Static Linearity ....................................................................................................17
7.2 Effective Number of Bits vs. Power Supplies Variation ......................................18
7.3 Typical FFT Results ............................................................................................19
7.4 Spurious Free Dynamic Range vs. Input Amplitude ........................................... 20
7.5 Dynamic Performance vs. Analog Input Frequency ...........................................21
7.6 Effective Number of Bits (ENOB) vs. Sampling Frequency ................................23
7.7 SFDR vs. Sampling Frequency ..........................................................................23
7.8 TS8388B ADC Performances vs. Junction Temperature ...................................24
7.9 Typical Full Power Input Bandwidth .................................................................... 25
7.10 ADC Step Response ...........................................................................................26
8 TS8388B Main Features ........................................................................ 28
8.1 Timing Information ..............................................................................................28
8.2 Principle of Data Ready Signal Control by DRRB Input Command ....................29
8.3 Analog Inputs (V
IN
) (V
INB
) ...................................................................................30
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8.4 Clock Inputs (CLK) (CLKB) .................................................................................31
8.5 Noise Immunity Information ................................................................................ 33
8.6 Digital Outputs ....................................................................................................33
8.7 Out of Range Bit ................................................................................................. 37
8.8 Gray or Binary Output Data Format Select .........................................................37
8.9 Diode Pin 49 .......................................................................................................38
8.10 ADC Gain Control Pin 60 ....................................................................................39
9 Equivalent Input/Output Schematics ................................................... 40
10 TSEV8388B: Device Evaluation Board ................................................ 43
10.1 General Description ............................................................................................43
10.2 CBGA68 Thermal and Moisture Characteristics .................................................44
10.3 Nominal CQFP68 Thermal Characteristics .........................................................46
10.4 Enhanced CQFP68 Thermal Characteristics ......................................................48
10.5 Definitions ...........................................................................................................49
11 Ordering Information ............................................................................. 52
11.1 CBGA68 Capacitors and Resistors Implant ........................................................ 54
11.2 Outline Descriptions ............................................................................................55
11.3 Outline Dimensions .............................................................................................56
12 Datasheet Status Description ............................................................... 58
12.1 Life Support Applications .................................................................................... 58
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0860E–BDC–04/07
e2v semiconductors SAS 2007
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