MF967-02 CMOS 8-BIT SINGLE CHIP MICROCOMPUTER S1C88409 Technical Manual S1C88409 Technical Hardware NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001 All rights reserved. The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 88104 F 0A01 00 Packing specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Development tools C 88348 S5U1 D1 1 00 Packing specification Version (1: Version 1 2) Tool type (D1: Development Tool 1) Corresponding model number (88348: for S1C88348) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products) 1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) 2: Actual versions are not written in the manuals. Comparison table between new and previous number S1C88 Family processors Previous No. New No. Previous No. New No. E0C88104 E0C88112 E0C88308 E0C88316 E0C88317 E0C88348 E0C88P348 E0C88349 S1C88104 S1C88112 S1C88308 S1C88316 S1C88317 S1C88348 S1C8P348 S1C88349 E0C88365 E0C88F360 E0C88408 E0C88409 E0C88816 E0C88832 E0C88862 E0C88F816 S1C88365 S1C8F360 S1C88408 S1C88409 S1C88816 S1C88832 S1C88862 S1C8F816 Comparison table between new and previous number of development tools Development tools for the S1C88 Family Previous No. New No. Previous No. New No. 88ISAIF ADP88348 ADP88360 DEV88104 DEV88112 DEV88308 DEV88316 DEV88317 DEV88348 DEV88365 DEV88408 DEV88409 S5U1C88000H4 S5U1C88348X S5U1C88360X S5U1C88104D S5U1C88112D S5U1C88308D S5U1C88316D S5U1C88317D S5U1C88348D S5U1C88365D S5U1C88408D S5U1C88409D DEV88816 DEV88832 DEV88862 DMT88348-DB ICE88UR PRC88316 PRC88348 PRC88365 PRC88409 PRC88816 SAP88 URS88348 S5U1C88816D S5U1C88832D S5U1C88862D S5U1C88348T S5U1C88000H5 S5U1C88316P S5U1C88348P S5U1C88365P S5U1C88409P S5U1C88816P S5U1C88000S S5U1C88348Y Development tools for the S1C63/88 Family Previous No. New No. ADS00002 GWH00002 URM00002 S5U1C88000X1 S5U1C88000W2 S5U1C88000W1 CONTENTS CONTENTS CHAPTER 1 OUTLINE ________________________________________________ 1 1.1 1.2 1.3 Features ......................................................................................................... 2 Block Diagram .............................................................................................. 3 System Configuration .................................................................................... 4 1.3.1 Single-chip system ...................................................................................... 4 1.3.2 Multi-chip system ....................................................................................... 4 1.4 1.5 CHAPTER 2 POWER SUPPLY ___________________________________________ 12 2.1 2.2 2.3 CHAPTER Pin Layout Diagram ..................................................................................... 5 Mask Option ................................................................................................. 11 Operating Voltage ........................................................................................ 12 Internal Power Supply Circuit ..................................................................... 12 Heavy Load Protection Mode ...................................................................... 12 3 CPU AND MEMORY ________________________________________ 13 3.1 3.2 CPU .............................................................................................................. 13 Internal Memory .......................................................................................... 13 3.2.1 ROM ........................................................................................................... 13 3.2.2 RAM (Data Memory, Display Memory) .................................................... 13 3.2.3 I/O memory ................................................................................................ 13 3.3 3.4 3.5 Exception Processing Vectors ...................................................................... 14 CC (Customized Condition Flag) ................................................................ 14 Chip Mode .................................................................................................... 14 3.5.1 MCU mode and MPU mode ...................................................................... 14 3.5.2 Bus mode ................................................................................................... 15 3.6 External Bus ................................................................................................. 17 3.6.1 Data bus ..................................................................................................... 17 3.6.2 Address bus ................................................................................................ 18 3.6.3 Read (RD)/write (WR) signals .................................................................. 18 3.6.4 Chip enable (CE) signal ............................................................................ 18 3.6.5 WAIT control .............................................................................................. 20 CHAPTER 4 INITIAL RESET ____________________________________________ 21 4.1 Initial Reset Factors ..................................................................................... 21 4.1.1 RESET terminal ......................................................................................... 21 4.1.2 Simultaneous LOW level input at input port terminals K00-K03 ........... 22 4.2 4.3 CHAPTER Initial Reset Sequence .................................................................................. 22 Initial Settings at Initial Reset ..................................................................... 23 5 PERIPHERAL CIRCUITS AND OPERATION __________________________ 24 5.1 5.2 I/O Memory Map ......................................................................................... 24 System Controller and Bus Control ............................................................. 46 5.2.1 Bus mode settings ...................................................................................... 46 5.2.2 Address decoder (CE output) settings ...................................................... 48 5.2.3 WAIT state settings .................................................................................... 48 5.2.4 I/O memory of system controller ............................................................... 49 5.2.5 Programming note ..................................................................................... 50 S1C88409 TECHNICAL MANUAL EPSON i CONTENTS 5.3 Watchdog Timer ........................................................................................... 51 5.3.1 Configuration of watchdog timer .............................................................. 51 5.3.2 Control of watchdog timer ........................................................................ 51 5.3.3 Interrupt function ...................................................................................... 52 5.3.4 I/O memory of watchdog timer ................................................................. 52 5.3.5 Programming notes ................................................................................... 53 5.4 Oscillation Circuit ....................................................................................... 54 5.4.1 Configuration of oscillation circuit .......................................................... 54 5.4.2 Mask option ............................................................................................... 54 5.4.3 OSC1 oscillation circuit ............................................................................ 54 5.4.4 OSC3 oscillation circuit ............................................................................ 55 5.4.5 Switching of CPU clock and operating voltage VD1 ................................ 56 5.4.6 I/O memory of oscillation circuit .............................................................. 58 5.4.7 Programming notes ................................................................................... 59 5.5 Prescaler and Clock Control Circuit for Peripheral Circuits ..................... 60 5.5.1 Configuration of prescaler ........................................................................ 60 5.5.2 Setting of source clock .............................................................................. 60 5.5.3 Prescaler division ratio selection and output control .............................. 61 5.5.4 Control of external clock for event counter .............................................. 62 5.5.5 I/O memory of prescaler ........................................................................... 63 5.5.6 Programming note ..................................................................................... 67 5.6 Input Ports (K ports) .................................................................................... 68 5.6.1 Configuration of input ports ..................................................................... 68 5.6.2 Mask option ............................................................................................... 68 5.6.3 Interrupt function ...................................................................................... 69 5.6.4 I/O memory of input ports ......................................................................... 72 5.6.5 Programming note ..................................................................................... 74 5.7 Output Ports (R ports) ................................................................................. 75 5.7.1 Configuration of output ports ................................................................... 75 5.7.2 High impedance control ............................................................................ 75 5.7.3 DC output .................................................................................................. 75 5.7.4 Special output ............................................................................................ 75 5.7.5 I/O memory of output ports ....................................................................... 76 5.8 I/O Ports (P ports) ....................................................................................... 78 5.8.1 Configuration of I/O ports ........................................................................ 78 5.8.2 Terminal configuration of I/O port and change of function ..................... 78 5.8.3 Mask option ............................................................................................... 80 5.8.4 I/O control registers and I/O mode ........................................................... 80 5.8.5 I/O memory of I/O ports ............................................................................ 81 5.8.6 Programming note ..................................................................................... 82 5.9 Clock Output ................................................................................................ 83 5.9.1 Configuration of clock output control circuit ........................................... 83 5.9.2 Clock output control .................................................................................. 84 5.9.3 I/O memory of clock output ....................................................................... 85 5.9.4 Programming notes ................................................................................... 87 5.10 LCD Controller ............................................................................................ 88 5.10.1 Configuration of LCD controller ............................................................ 88 5.10.2 Output signals ......................................................................................... 89 5.10.3 Display control ........................................................................................ 90 5.10.4 B&W and gray-scale mode setting ......................................................... 90 5.10.5 Display memory ....................................................................................... 91 5.10.6 LCD panel ............................................................................................... 91 5.10.7 Vertical scroll function ............................................................................ 93 5.10.8 Virtual screen function ............................................................................ 93 5.10.9 Data transfer ........................................................................................... 94 5.10.10 Interrupt function .................................................................................. 97 ii EPSON S1C88409 TECHNICAL MANUAL CONTENTS 5.10.11 I/O memory of LCD controller .............................................................. 98 5.10.12 Programming notes .............................................................................. 103 5.11 Clock Timer ................................................................................................. 104 5.11.1 Configuration of clock timer .................................................................. 104 5.11.2 Interrupt function ................................................................................... 104 5.11.3 I/O memory of clock timer ..................................................................... 106 5.11.4 Programming notes ................................................................................ 108 5.12 16-bit Programmable Timer ....................................................................... 109 5.12.1 Configuration of 16-bit programmable timer ........................................ 109 5.12.2 Operation mode ...................................................................................... 110 5.12.3 Setting of input clock .............................................................................. 111 5.12.4 Operation and control of timer .............................................................. 111 5.12.5 Interrupt function ................................................................................... 113 5.12.6 Setting of TOUT output .......................................................................... 114 5.12.7 I/O memory of 16-bit programmable timer ........................................... 115 5.12.8 Programming notes ................................................................................ 122 5.13 8-bit Programmable Timer ......................................................................... 123 5.13.1 Configuration of 8-bit programmable timer .......................................... 123 5.13.2 Setting of input clock .............................................................................. 123 5.13.3 Operation and control of timer .............................................................. 124 5.13.4 Interrupt function ................................................................................... 125 5.13.5 Transfer rate setting for serial interface ............................................... 125 5.13.6 I/O memory of 8-bit programmable timer ............................................. 126 5.13.7 Programming notes ................................................................................ 129 5.14 Serial Interface ........................................................................................... 130 5.14.1 Configuration of serial interface ........................................................... 130 5.14.2 Transfer mode and input/output terminals ............................................ 131 5.14.3 Mask option ............................................................................................ 133 5.14.4 Clock source ........................................................................................... 133 5.14.5 Control procedure to transmit/receive ................................................... 135 5.14.6 Receive error .......................................................................................... 136 5.14.7 Interrupt function ................................................................................... 137 5.14.8 IR (Infrared-ray) interface ..................................................................... 139 5.14.9 Timing charts .......................................................................................... 141 5.14.10 I/O memory of serial interface ............................................................. 144 5.14.11 Programming notes .............................................................................. 149 5.15 Sound Generator ......................................................................................... 150 5.15.1 Configuration of sound generator ......................................................... 150 5.15.2 Control of buzzer output ......................................................................... 150 5.15.3 Setting of buzzer frequency and sound level .......................................... 151 5.15.4 Digital envelope ..................................................................................... 151 5.15.5 One-shot output ...................................................................................... 152 5.15.6 I/O memory of sound generator ............................................................. 153 5.15.7 Programming notes ................................................................................ 155 5.16 SVD (Supply Voltage Detection) Circuit ..................................................... 156 5.16.1 Configuration of SVD circuit ................................................................. 156 5.16.2 SVD operation ........................................................................................ 156 5.16.3 I/O memory of SVD circuit ..................................................................... 157 5.16.4 Programming notes ................................................................................ 157 5.17 Touch Panel Controller ............................................................................... 158 5.17.1 Configuration of touch panel controller ................................................ 158 5.17.2 Terminal configuration ........................................................................... 158 5.17.3 Operation of touch panel controller ...................................................... 159 5.17.4 Interrupt function ................................................................................... 164 5.17.5 Touch panel controller control flow ....................................................... 165 5.17.6 I/O memory of touch panel controller ................................................... 167 5.17.7 Programming notes ................................................................................ 175 S1C88409 TECHNICAL MANUAL EPSON iii CONTENTS 5.18 A/D Converter ............................................................................................. 176 5.18.1 Characteristics and configuration of A/D converter ............................. 176 5.18.2 Terminal configuration of A/D converter ............................................... 176 5.18.3 Mask option ............................................................................................ 177 5.18.4 Control of A/D converter ........................................................................ 177 5.18.5 Interrupt function ................................................................................... 179 5.18.6 I/O memory of A/D converter ................................................................. 180 5.18.7 Programming notes ................................................................................ 183 5.19 D/A Converter ............................................................................................. 184 5.19.1 Characteristics and configuration of D/A converter ............................. 184 5.19.2 Terminal configuration of D/A converter .............................................. 184 5.19.3 Mask option ............................................................................................ 184 5.19.4 Control of D/A converter ........................................................................ 185 5.19.5 I/O memory of D/A converter ................................................................. 186 5.19.6 Programming note .................................................................................. 187 5.20 Interrupt and Standby Mode ....................................................................... 188 5.20.1 Types of interrupts .................................................................................. 188 5.20.2 Standby mode ......................................................................................... 190 5.20.3 Interrupt generation conditions ............................................................. 190 5.20.4 Interrupt factor flag ............................................................................... 192 5.20.5 Interrupt enable register ........................................................................ 192 5.20.6 Interrupt priority register and interrupt priority level .......................... 192 5.20.7 Exception processing vectors ................................................................. 193 5.20.8 I/O memory of interrupt ......................................................................... 194 5.20.9 Programming notes ................................................................................ 196 CHAPTER 6 SUMMARY OF NOTES ______________________________________ 197 6.1 6.2 6.3 Notes for Low Current Consumption .......................................................... 197 Summary of Notes by Function ................................................................... 197 Precautions on Mounting ........................................................................... 202 CHAPTER 7 BASIC EXTERNAL WIRING DIAGRAM ___________________________ 204 CHAPTER 8 ELECTRICAL CHARACTERISTICS _______________________________ 205 8.1 8.2 8.3 8.4 8.5 Absolute Maximum Rating .......................................................................... 205 Recommended Operating Conditions ......................................................... 205 DC Characteristics ..................................................................................... 206 Analog Circuit Characteristics and Current Consumption ....................... 207 AC Characteristics ...................................................................................... 208 8.5.1 External memory access ........................................................................... 208 8.5.2 Serial interface ......................................................................................... 210 8.5.3 Input clock ................................................................................................ 212 8.5.4 LCD controller ......................................................................................... 213 8.5.5 Power-on reset .......................................................................................... 214 8.5.6 Switching operating mode ........................................................................ 214 8.6 8.7 8.8 CHAPTER 9 PACKAGE _______________________________________________ 218 9.1 9.2 iv Oscillation Characteristics ......................................................................... 215 A/D Converter Characteristics ................................................................... 217 D/A Converter Characteristics ................................................................... 217 Plastic Package ........................................................................................... 218 Ceramic Package for Test Samples ............................................................. 219 EPSON S1C88409 TECHNICAL MANUAL CONTENTS CHAPTER 10 PAD LAYOUT ____________________________________________ 220 10.1 Diagram of Pad Layout ............................................................................... 220 10.2 Pad Coordinates .......................................................................................... 221 APPENDIX CONTROLLING THE TOUCH PANEL CONTROLLER __________________ 222 A.1 I/O Map ....................................................................................................... 222 A.2 Description .................................................................................................. 227 A.2.1 Circuit connection .................................................................................... 227 A.2.2 Mask option configuration ....................................................................... 227 A.2.3 Reducing power consumption and improving response ......................... 227 A.2.4 Reading coordinate data from the TPC ................................................... 227 A.2.5 Calculating the LCD dot position ........................................................... 228 A.3 Precautions ................................................................................................. 228 A.3.1 Interrupt processing ................................................................................. 228 A.3.2 Others ....................................................................................................... 228 A.4 Reference Flowchart ................................................................................... 229 A.4.1 Initializing the TPC .................................................................................. 229 A.4.2 TPC data update interrupt processing .................................................... 229 A.4.3 TP initial data configuration ................................................................... 230 A.4.4 Coordinate data calculation .................................................................... 231 A.5 Reference Program ..................................................................................... 232 A.5.1 Setting constants and macros (include file) ............................................ 232 A.5.2 TPC initialization ..................................................................................... 232 A.5.3 TPC data update interrupt processing .................................................... 233 A.5.4 TP initial data setting .............................................................................. 234 A.5.5 Coordinate data calculation .................................................................... 236 S1C88409 TECHNICAL MANUAL EPSON v CHAPTER 1: OUTLINE CHAPTER 1 S1C88409 TECHNICAL MANUAL OUTLINE The S1C88409 is a single chip microcomputer which consists of a CMOS 8-bit core CPU S1C88 (MODEL3), 8KB ROM, 3.75KB RAM, dot-matrix LCD controller, 3 types of timers/counters, serial interface (IR input/output function is available), touch panel controller, A/D converter and D/A converter. The S1C88409 operates faster even with low supply voltage, and is most suitable for various application equipment such as information terminals needing low power operation. Furthermore, the S1C88409 can control up to 4M x 3 bytes of memory with the 22-bit outside address bus and 3-bit chip enable signals, therefore it can also be applied to systems such as electronic dictionaries and organizers. EPSON 1 CHAPTER 1: OUTLINE 1.1 Features Table 1.1.1 Features Core CPU OSC1 oscillation circuit OSC3 oscillation circuit Instruction set Min. instruction execution time Internal ROM capacity Internal RAM capacity Bus line Input port Output port I/O port Serial interface 16-bit programmable timer 8-bit programmable timer Clock timer LCD controller Touch panel controller A/D converter D/A converter Sound generator Supply voltage detection (SVD) Watchdog timer Interrupt Supply voltage SLEEP Current consumption HALT (32 kHz) Run (32 kHz) Run (4 MHz) Run (8 MHz) Supply form 2 CMOS 8-bit core CPU S1C88 (MODEL3) Crystal oscillation circuit/CR oscillation circuit/external clock input 32.768 kHz (Typ.) Crystal oscillation circuit/ceramic oscillation circuit/CR oscillation circuit/external clock input 8 MHz (Max.) Basic instruction: 54 types, Total: 608 types (multiplication/division instructions are usable) Addressing mode: 12 types 0.25 sec/8 MHz (2 clocks) 8K bytes 3.75K bytes (display memory is included; data/display memory size can be set by mask option) Address bus: 22 bits Data bus: 8 bits (usable as general output port or I/O port when it is not used as a bus signal) CE signal: 3 bits WR signal: 1 bit RD signal: 1 bit 12 bits * 2 bits are usable for event counter input 30 bits * They are used as address bus and bus control signals when external bus is set * Usable for clock output and buzzer output 28 bits * 8 bits are used as data bus when external bus is set * Usable for serial interface input/output, A/D converter input, D/A converter output and touch panel output 1 channel * Clock synchronous mode/asynchronous mode selectable * Usable as IrDA interface 1 channel * Usable for 16 bits x 1 channel or 8 bits x 2 channels * Usable as event counter 1 channel * Usable as baud rate generator for serial interface 1 channel * Generating 1 sec signal with 32 kHz oscillation * 60S counter available Dot-matrix type * B&W or 4 gray scale display * A 240 x 100 dot LCD panel can be driven with external drivers (S1D16305 or S1D16700, S1D16006 or S1D15700) * Scroll function available Supports pressure sensitive and resistive membrane type analog touch panels Resolution 10 bits (input: 8 channels) Resolution 8 bits (output: 2 channels) Equipped with envelope and volume control functions Possible to detect 3 voltage levels Possible to generate NMI External: Input interrupt 2 systems (5 types) Internal: 16-bit programmable timer interrupt 2 systems (4 types) 8-bit programmable timer interrupt 1 system (1 type) Clock timer interrupt 1 system (5 types) Watchdog timer interrupt 1 system (1 type) Serial interface interrupt 1 system (3 types) LCD controller interrupt 1 system (1 type) Touch panel interrupt 1 system (2 types) A/D converter interrupt 1 system (1 type) 1.8 V to 5.5 V (operating frequency Max. 1.1 MHz) 2.6 V to 5.5 V (operating frequency Max. 4.4 MHz) 3.5 V to 5.5 V (operating frequency Max. 6.6 MHz) 4.5 V to 5.5 V (operating frequency Max. 8.8 MHz) 0.6 A Typ. (at 3.0 V) (Normal mode) 3.0 A Typ. (at 3.0 V) (Normal mode) 15 A Typ. (at 3.0 V) (Normal mode) 2 mA Typ. (at 3.0 V) (Normal mode) 9 mA Typ. (at 5.0 V) (High speed mode) QFP15-100pin or chip EPSON S1C88409 TECHNICAL MANUAL CHAPTER 1: OUTLINE 1.2 Block Diagram VDD VSS Core CPU S1C88 OSC1, OSC3 OSC2, OSC4 Oscillator (FOUT3) (FOUT1) Prescaler Interrupt Controller Serial Interface (Synchronous/Asynchronous/IrDA) (SIN/IRI, SOUT/IRO) (SCLK, SRDY) LCDEN, DOFF XSCL, LP, YD, FR SD0-SD7 VD1 Voltage Regulator LCD Controller MCU/MPU System Controller Supply Voltage Detector Reset/Test External Memory Interface 16-bit Programmable Timer Input Port K00-K07 K10-K13 Output Port R00-R07 R10-R17 R20-R27 R30-R32 R40-R42 I/O Port P00-P07 P10-P17 P20-P23 P30-P37 RESET TEST (TOUT0) (TOUT1) 8-bit Programmable Timer (A0-A21) (D0-D7) (RD, WR, CE0-CE2) Clock Timer Watchdog Timer (BZ) (BYH, BYL) (BXH, BXL) Sound Generator A/D Converter Touch Panel Controller D/A Converter RAM 3.75K-byte (AD0-AD7) AVDD AGND AVSS AVREF (DA0, DA1) ROM 8K-byte (Data RAM, Display RAM) Fig. 1.2.1 S1C88409 block diagram The terminals that are shown in ( ) are shared with Pxx or Rxx terminals. S1C88409 TECHNICAL MANUAL EPSON 3 CHAPTER 1: OUTLINE 1.3 System Configuration 1.3.2 Multi-chip system System configuration of the S1C88409 is classified in 2 types according to use. With the S1C88409 as the CPU, the multi-chip system has expanded memory as well as other expanded devices. It covers a wide range of applications. Memory and devices are connected to the external bus of the S1C88409 and are all controlled by the S1C88409. The bus mode of the S1C88409 can be set to the expanded mode (see Section 3.5) according to scale of the system. 1) Single-chip system 2) Multi-chip system To construct these systems, the S1C88409 has been designed to switch the bus mode (configuration of the external bus) by software and/or mask option. 1.3.1 Single-chip system The single-chip system has the smallest configuration that uses the S1C88409 as the CPU of the system and does not expand any memory and devices outside. It is suitable for various controller systems. Since it does not use an external bus, the bus mode of the S1C88409 should be set to the MCU/ singlechip mode (see Section 3.5). (Initial setting) The memory that can be used is limited to the built-in area. ROM ...8KB RAM ...3.75KB (display memory is included) The I/O ports shared with the external bus can be used entirely as general-purpose I/O ports. MCU or MPU*/Expanded 64K mode For systems with 64KB or less expanded memory MCU or MPU*/Expanded 4M minimum mode For systems with 64KB to 12MB (4M x 3) expanded memory (However, program memory is 64KB or less) MCU or MPU*/Expanded 4M maximum mode For systems with 64KB to 12MB (4M x 3) expanded memory (For systems that require 64KB or more program memory) The MCU mode is set when the internal ROM is used, and the MPU mode is set when the internal ROM is not used. Refer to Section 3.6, "External Bus", for the bus configuration. I/O Address bus (A0-A21) IN S1C88409 Data bus (D0-D7) OUT I/O S1C88409 External Device Fig. 1.3.1.1 Configuration of single-chip system External Device External Device RD WR CE0 CE1 CE2 Fig. 1.3.2.1 Configuration of multi-chip system 4 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 1: OUTLINE 1.4 Pin Layout Diagram 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R02 R01 R00 P07 P06 P05 P04 P03 P02 P01 P00 RESET K13 K12 K11 (EXCL11) K10 (EXCL00) K07 K06 K05 K04 K03 K02 K01 K00 MCU/MPU * Pin layout for single chip mode (initial setting) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 S1C88409 INDEX 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS OSC1 OSC2 VD1 OSC3 OSC4 VDD LCDEN DOFF YD FR XSCL LP SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 N.C. N.C. AGND AVREF (TOUT1/FOUT1) R41 (BZ) R42 (SIN) P10 (SOUT) P11 (SCLK) P12 (SRDY) P13 (SIN/IRI) P14 (SOUT/IRO) P15 (SCLK) P16 (SRDY) P17 (BYH) P20 (BYL) P21 (BXH) P22 (BXL) P23 TEST (AD7/DA1) P37 (AD6/DA0) P36 (AD5) P35 (AD4) P34 (AD3) P33 (AD2) P32 (AD1) P31 (AD0) P30 AVDD AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 R03 R04 R05 R06 R07 R10 R11 R12 R13 R14 R15 R16 R17 R20 R21 R22 R23 R24 R25 R26 R27 R30 R31 R32 (TOUT0/FOUT3) R40 Fig. 1.4.1 S1C88409 pin layout (single chip mode) S1C88409 TECHNICAL MANUAL EPSON 5 CHAPTER 1: OUTLINE Table 1.4.1 S1C88409 pin description (single chip mode) Pin name VDD VSS VD1 AVDD AGND AVSS AVREF OSC1 OSC2 OSC3 OSC4 MCU/MPU K00~K07 K10 (EXCL00) K11 (EXCL01) K12~K13 R00~R07 R10~R17 R20~R27 R30~R32 R40 (TOUT0/FOUT3) R41 (TOUT1/FOUT1) R42 (BZ) P00~P07 P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P14 (SIN/IRI) P15 (SOUT/IRO) P16 (SCLK) P17 (SRDY) P20 (BYH) P21 (BYL) P22 (BXH) P23 (BXL) P30~P35 (AD0~AD5) P36, P37 (AD6/DA0, AD7/DA1) LCDEN DOFF YD FR XSCL LP SD0~SD7 RESET TEST Pin No. 44 50 47 24 27 25 26 49 48 46 45 51 52~59 60 61 62~63 73~80 81~88 89~96 97~99 100 1 2 65~72 3 4 5 6 7 8 9 10 11 12 13 14 23~18 17,16 I/O - - O - - - I I O I O I I I I I O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 43 42 41 40 39 38 37~30 64 15 O O O O O O O I I Function Power supply (+) pin Power supply (GND) pin Voltage regulator output pin Power supply (+) pin for analog circuit system GND pin for analog circuit system Power supply (GND) pin for analog circuit system Reference voltage input pin for analog circuit system OSC1 oscillation input pin (32 kHz crystal, CR oscillation, external clock input) OSC1 oscillation output pin OSC3 oscillation input pin (crystal/ceramic, CR oscillation, external clock input) OSC3 oscillation output pin MCU/MPU mode stting pin*1 Input port pin Input port pin or external clock input pin for event counter (Timer 0) Input port pin or external clock input pin for event counter (Timer 1) Input port pin Output port pin Output port pin Output port pin Output port pin Output port pin or TOUT0/FOUT3 clock output pin Output port pin or TOUT1/FOUT1 clock output pin Output port pin or buzzer signal output pin I/O port pin I/O port pin or serial I/F data input pin I/O port pin or serial I/F data output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin, serial I/F data input or IR receiver input pin I/O port pin, serial I/F data output or IR transmitter output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin or touch panel controller BYH signal output pin I/O port pin or touch panel controller BYL signal output pin I/O port pin or touch panel controller BXH signal output pin I/O port pin or touch panel controller BXL signal output pin I/O port pin or A/D converter analog signal input pin I/O port pin, A/D converter analog signal input pin or D/A converter analog signal output pin LCD controller enable signal output pin LCD controller forced blank signal output pin LCD controller scan start pulse output pin LCD controller frame signal output pin LCD controller shift clock output pin LCD controller latch pulse output pin LCD controller data output pin Initial reset input pin Test input pin*2 1 The MCU/MPU terminal should be connected to VDD. 2 TEST is the terminal used for factory inspection of the IC. For normal operation, be sure to connect the TEST terminal to VDD. 6 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 1: OUTLINE 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 RESET K13 K12 K11 (EXCL11) K10 (EXCL00) K07 K06 K05 K04 K03 K02 K01 K00 MCU/MPU * Pin layout for expanded 64K mode (for multi-chip system) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 S1C88409 INDEX 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS OSC1 OSC2 VD1 OSC3 OSC4 VDD LCDEN DOFF YD FR XSCL LP SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 N.C. N.C. AGND AVREF (TOUT1/FOUT1) R41 (BZ) R42 (SIN) P10 (SOUT) P11 (SCLK) P12 (SRDY) P13 (SIN/IRI) P14 (SOUT/IRO) P15 (SCLK) P16 (SRDY) P17 (BYH) P20 (BYL) P21 (BXH) P22 (BXL) P23 TEST (AD7/DA1) P37 (AD6/DA0) P36 (AD5) P35 (AD4) P34 (AD3) P33 (AD2) P32 (AD1) P31 (AD0) P30 AVDD AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 R20 R21 R22 R23 R24 R25 RD WR CE0 (CE1) R31 (CE2) R32 (TOUT0/FOUT3) R40 Fig. 1.4.2 S1C88409 pin layout (expanded 64K mode) S1C88409 TECHNICAL MANUAL EPSON 7 CHAPTER 1: OUTLINE Table 1.4.2 S1C88409 pin description (expanded 64K mode) Pin name VDD VSS VD1 AVDD AGND AVSS AVREF OSC1 OSC2 OSC3 OSC4 MCU/MPU K00~K07 K10 (EXCL00) K11 (EXCL01) K12~K13 A00~A15 R20~R25 RD WR CE0 CE1 (R31) CE2 (R32) R40 (TOUT0/FOUT3) R41 (TOUT1/FOUT1) R42 (BZ) D0~D7 P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P14 (SIN/IRI) P15 (SOUT/IRO) P16 (SCLK) P17 (SRDY) P20 (BYH) P21 (BYL) P22 (BXH) P23 (BXL) P30~P35 (AD0~AD5) P36, P37 (AD6/DA0, AD7/DA1) LCDEN DOFF YD FR XSCL LP SD0~SD7 RESET TEST Pin No. 44 50 47 24 27 25 26 49 48 46 45 51 52~59 60 61 62~63 73~88 89~94 95 96 97 98 99 100 1 2 65~72 3 4 5 6 7 8 9 10 11 12 13 14 23~18 17,16 I/O - - O - - - I I O I O I I I I I O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 43 42 41 40 39 38 37~30 64 15 O O O O O O O I I Function Power supply (+) pin Power supply (GND) pin Voltage regulator output pin Power supply (+) pin for analog circuit system GND pin for analog circuit system Power supply (GND) pin for analog circuit system Reference voltage input pin for analog circuit system OSC1 oscillation input pin (32 kHz crystal, CR oscillation, external clock input) OSC1 oscillation output pin OSC3 oscillation input pin (crystal/ceramic, CR oscillation, external clock input) OSC3 oscillation output pin MCU/MPU mode stting pin Input port pin Input port pin or external clock input pin for event counter (Timer 0) Input port pin or external clock input pin for event counter (Timer 1) Input port pin Address bus Output port pin Read signal output pin Write signal output pin Chip enable signal output pin Chip enable signal output pin or output port pin Chip enable signal output pin or output port pin Output port pin or TOUT0/FOUT3 clock output pin Output port pin or TOUT1/FOUT1 clock output pin Output port pin or buzzer signal output pin Data bus I/O port pin or serial I/F data input pin I/O port pin or serial I/F data output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin, serial I/F data input or IR receiver input pin I/O port pin, serial I/F data output or IR transmitter output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin or touch panel controller BYH signal output pin I/O port pin or touch panel controller BYL signal output pin I/O port pin or touch panel controller BXH signal output pin I/O port pin or touch panel controller BXL signal output pin I/O port pin or A/D converter analog signal input pin I/O port pin, A/D converter analog signal input pin or D/A converter analog signal output pin LCD controller enable signal output pin LCD controller forced blank signal output pin LCD controller scan start pulse output pin LCD controller frame signal output pin LCD controller shift clock output pin LCD controller latch pulse output pin LCD controller data output pin Initial reset input pin Test input pin*1 1 TEST is the terminal used for factory inspection of the IC. For normal operation, be sure to connect the TEST terminal to VDD. 8 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 1: OUTLINE 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 RESET K13 K12 K11 (EXCL11) K10 (EXCL00) K07 K06 K05 K04 K03 K02 K01 K00 MCU/MPU * Pin layout for expanded 4M mode (for multi-chip system) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 S1C88409 INDEX 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS OSC1 OSC2 VD1 OSC3 OSC4 VDD LCDEN DOFF YD FR XSCL LP SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 N.C. N.C. AGND AVREF (TOUT1/FOUT1) R41 (BZ) R42 (SIN) P10 (SOUT) P11 (SCLK) P12 (SRDY) P13 (SIN/IRI) P14 (SOUT/IRO) P15 (SCLK) P16 (SRDY) P17 (BYH) P20 (BYL) P21 (BXH) P22 (BXL) P23 TEST (AD7/DA1) P37 (AD6/DA0) P36 (AD5) P35 (AD4) P34 (AD3) P33 (AD2) P32 (AD1) P31 (AD0) P30 AVDD AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 RD WR CE0 (CE1) R31 (CE2) R32 (TOUT0/FOUT3) R40 Fig. 1.4.3 S1C88409 pin layout (expanded 4M mode) S1C88409 TECHNICAL MANUAL EPSON 9 CHAPTER 1: OUTLINE Table 1.4.3 S1C88409 pin description (expanded 4M mode) Pin name VDD VSS VD1 AVDD AGND AVSS AVREF OSC1 OSC2 OSC3 OSC4 MCU/MPU K00~K07 K10 (EXCL00) K11 (EXCL01) K12~K13 A00~A21 RD WR CE0 CE1 (R31) CE2 (R32) R40 (TOUT0/FOUT3) R41 (TOUT1/FOUT1) R42 (BZ) D0~D7 P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P14 (SIN/IRI) P15 (SOUT/IRO) P16 (SCLK) P17 (SRDY) P20 (BYH) P21 (BYL) P22 (BXH) P23 (BXL) P30~P35 (AD0~AD5) P36, P37 (AD6/DA0, AD7/DA1) LCDEN DOFF YD FR XSCL LP SD0~SD7 RESET TEST Pin No. 44 50 47 24 27 25 26 49 48 46 45 51 52~59 60 61 62~63 73~94 95 96 97 98 99 100 1 2 65~72 3 4 5 6 7 8 9 10 11 12 13 14 23~18 17,16 I/O - - O - - - I I O I O I I I I I O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 43 42 41 40 39 38 37~30 64 15 O O O O O O O I I Function Power supply (+) pin Power supply (GND) pin Voltage regulator output pin Power supply (+) pin for analog circuit system GND pin for analog circuit system Power supply (GND) pin for analog circuit system Reference voltage input pin for analog circuit system OSC1 oscillation input pin (32 kHz crystal, CR oscillation, external clock input) OSC1 oscillation output pin OSC3 oscillation input pin (crystal/ceramic, CR oscillation, external clock input) OSC3 oscillation output pin MCU/MPU mode stting pin Input port pin Input port pin or external clock input pin for event counter (Timer 0) Input port pin or external clock input pin for event counter (Timer 1) Input port pin Address bus Read signal output pin Write signal output pin Chip enable signal output pin Chip enable signal output pin or output port pin Chip enable signal output pin or output port pin Output port pin or TOUT0/FOUT3 clock output pin Output port pin or TOUT1/FOUT1 clock output pin Output port pin or buzzer signal output pin Data bus I/O port pin or serial I/F data input pin I/O port pin or serial I/F data output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin, serial I/F data input or IR receiver input pin I/O port pin, serial I/F data output or IR transmitter output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin or touch panel controller BYH signal output pin I/O port pin or touch panel controller BYL signal output pin I/O port pin or touch panel controller BXH signal output pin I/O port pin or touch panel controller BXL signal output pin I/O port pin or A/D converter analog signal input pin I/O port pin, A/D converter analog signal input pin or D/A converter analog signal output pin LCD controller enable signal output pin LCD controller forced blank signal output pin LCD controller scan start pulse output pin LCD controller frame signal output pin LCD controller shift clock output pin LCD controller latch pulse output pin LCD controller data output pin Initial reset input pin Test input pin*1 1 TEST is the terminal used for factory inspection of the IC. For normal operation, be sure to connect the TEST terminal to VDD. 10 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 1: OUTLINE (7) I/O port pull-up resistor 1.5 Mask Option Mask options shown below are provided for the S1C88409. Several hardware specifications are prepared in each mask option, and one of them can be selected according to the application. The function option generator FOG88409, that has been prepared as the development software tool of the S1C88409, is used for this selection. Mask pattern of the IC is finally generated based on the data created by the FOG88409. Refer to the "S5U1C88409D Manual" for details on the FOG88409. This mask option can select whether the pullup resistor for the I/O port terminal (it works during input mode) is used or not. It is possible to select for each bit of the input ports. Refer to Section 5.8.3, "Mask option", for details. (8) Data RAM, Display RAM capacity The S1C88409 has built-in 3.75KB RAM. The data memory/display memory size can be selected from seven types (256/3584, 512/3328, 768/3072, 1024/2816, 1280/2560, 1536/2304, 1792/2048 bytes) according to the LCD panel to be used. Refer to Section 3.2.2, "RAM (Data Memory, Display Memory)", for details. <Functions selectable with S1C88409 mask options> (1) Bus mode The bus mode that is set at initial reset can be selected. It is necessary to select it when using the S1C88409 in the MPU mode. Refer to Section 5.2, "System Controller and Bus Control", for details. (9) Touch panel control terminal The control signal output terminals of the touch panel controller are shared with the I/O port terminals P20 to P23. The P20-P23 terminals can be set for either the touch panel controller or the I/O port. Refer to Section 5.17.2, "Terminal configuration", for details. (2) OSC1 oscillation circuit The specification of the OSC1 oscillation circuit can be selected from among four types: "Crystal oscillation", "CR oscillation", "Crystal oscillation (gate capacitor built-in)" and "External clock input". Refer to Section 5.4.3, "OSC1 oscillation circuit", for details. (10) Touch panel controller input terminal Two terminals can be selected from the I/O port terminals P30-P35 for inputting the X and Y coordinate detection signals of the touch panel to the A/D converter. Refer to Section 5.17.2, "Terminal configuration", for details. (3) OSC3 oscillation circuit The specification of the OSC3 oscillation circuit can be selected from among four types: "Crystal oscillation", "Ceramic oscillation", "CR oscillation" and "External clock input". Refer to Section 5.4.4, "OSC3 oscillation circuit", for details. (4) MCU/MPU terminal pull-up resistor This mask option can select whether the pullup resistor for the MCU/MPU terminal is used or not. (5) RESET terminal pull-up resistor This mask option can select whether the pullup resistor for the RESET terminal is used or not. (6) Input port pull-up resistor This mask option can select whether the pullup resistor for the input port terminal is used or not. It is possible to select for each bit of the input ports. Refer to Section 5.6.2, "Mask option", for details. S1C88409 TECHNICAL MANUAL EPSON 11 CHAPTER 2: POWER SUPPLY CHAPTER 2 POWER SUPPLY This section explains the operating voltage and the configuration of the internal power supply circuit of the S1C88409. 2.1 Operating Voltage 2.3 Heavy Load Protection Mode Table 2.1.1 shows the operating voltage of the S1C88409. Using a low voltage for VDD according to operating speed needs can reduce power consumption. The S1C88409 has a heavy load protection function for stable operation even when the supply voltage fluctuates by driving a heavy load. The heavy load protection mode becomes valid when the peripheral circuits are in the following status: Table 2.1.1 Correspondence between operating voltage and operating frequency Operatable voltage range (VDD) Max. clock frequency (OSC3) 1.8 V to 5.5 V 2.6 V to 5.5 V 1.1 MHz 4.4 MHz 3.5 V to 5.5 V 4.5 V to 5.5 V 6.6 MHz 8.8 MHz (1) The OSC3 oscillation circuit is switched ON (OSCC = "1" and not in SLEEP) (2) The buzzer output is switched ON (BZON = "1" or BZSHT = "1") SLEEP status OSCC Note: I/O signal levels (high and low) that are described in this manual show the following voltage level if not otherwise noted. High level = VDD Low level = VSS Heavy load protection mode BZON BZSHT Fig. 2.3.1 Configuration of heavy load protection mode control circuit 2.2 Internal Power Supply Circuit The S1C88409 has the built-in power supply circuit shown in Figure 2.2.1. The power supply circuit generates the voltage VD1 for the internal circuits by supplying a voltage within the range mentioned above between the VDD (+) and VSS (GND) terminals. For details of the OSC3 oscillation circuit and buzzer output, refer to Section 5.4, "Oscillation Circuit" and Section 5.15, "Sound Generator", respectively. VD1 voltage can be selected from among four types: 4.2 V (Max. 8.8 MHz), 3.2 V (Max. 6.6 MHz), 2.4 V (Max. 4.4 MHz) and 1.6 V (Max. 1.1 MHz). It should be selected by a program to switch according to the supply voltage and oscillation frequency. Refer to Section 5.4, "Oscillation Circuit" for switching VD1. Note: Be sure not to use the VD1 terminal output for driving external circuits. External power supply Internal voltage setting circuit VDD VD1 Voltage regulator VD1 Oscillation circuit VSS OSC1-OSC4 Internal circuits Fig. 2.2.1 Configuration of power supply circuit 12 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 3: CPU AND MEMORY CHAPTER 3 CPU AND MEMORY This section explains the CPU, operating mode and bus configuration. 3.1 CPU 3.2.2 RAM (Data Memory, Display Memory) The S1C88409 employs the 8-bit core CPU S1C88 as the CPU, so that register configuration, instructions and so on are virtually identical to those in other family processors using the S1C88. The internal RAM has a capacity of 3.75KB. The data memory size and display memory size can be selected as shown in Table 3.2.2.1 by mask option. Table 3.2.2.1 RAM size setting by mask option Refer to the "S1C88 Core CPU Manual" for details of the S1C88. 1 The S1C88 CPU model used is Model 3 and has up to 4M x 3 address space that can be used for extended memory. 2 3 3.2 Internal Memory 4 The S1C88409 has built-in ROM and RAM as shown in Figure 3.2.1. Small-scale applications can be realized with only this chip. The internal memory can be used together with the external memory. Furthermore, the internal ROM can be disconnected from the bus so that the space is released to external memory. 00FFFFH RAM, I/O memory 00F000H 00EFFFH 00FFFFH 00FF00H 00FEFFH I/O memory RAM (Data memory) RAM 00F000H (Display memory) Unused area See Section 3.2.2, "RAM (Data Memory, Display Memory)", for the capacity and address of the RAM. 002000H 001FFFH ROM (8K-byte) 7 The internal RAM area is not released to external memory even when the external memory which overlaps the internal RAM area is expanded. Access to this area affects the internal RAM. Refer to Section 5.10, "LCD Controller", for details of the display memory. 3.2.3 I/O memory 000000H Fig. 3.2.1 Internal memory map 3.2.1 ROM The internal ROM has a capacity of 8KB. Depending on the setting of the MCU/MPU terminal, the internal ROM area can be released to external memory. (See Section 3.5, "Chip Mode".) S1C88409 TECHNICAL MANUAL 6 Display memory 2048 bytes 00F000H-00F7FFH 2304 bytes 00F000H-00F8FFH 2560 bytes 00F000H-00F9FFH 2816 bytes 00F000H-00FAFFH 3072 bytes 00F000H-00FBFFH 3328 bytes 00F000H-00FCFFH 3584 bytes 00F000H-00FDFFH Note: The display memory area configured by mask option may be used as data memory. However, the stack area cannot be assigned there. : 5 Data memory 1792 bytes 00F800H-00FEFFH 1536 bytes 00F900H-00FEFFH 1280 bytes 00FA00H-00FEFFH 1024 bytes 00FB00H-00FEFFH 768 bytes 00FC00H-00FEFFH 512 bytes 00FD00H-00FEFFH 256 bytes 00FE00H-00FEFFH A memory mapped I/O method is adopted in the S1C88409 for interface with internal peripheral circuits. The control bits and data registers of the peripheral circuits are arranged in the data memory space. Control and data transfer can be done with normal memory access instructions. I/O memory area is arranged in 00FF00H- 00FFFFH. Refer to Section 5.1, "I/O Memory Map", for details of the I/O memory. The I/O memory area is not released to the external memory even when the external memory which overlaps the I/O memory area is expanded. Access to this area affects the I/O memory. EPSON 13 CHAPTER 3: CPU AND MEMORY 3.3 Exception Processing Vectors In the S1C88409, 000000H-000029H in the program area are assigned as exception processing vectors. Furthermore, from 000034H to 0000FFH, software interrupt vectors are assignable to any two bytes which begin with an even address. Table 3.3.1 shows the correspondence between the vector addresses and the exception processing factors. The start address of the exception processing routine should be written to the respective vector address and the next address in order of low and high-order start address. When an exception processing factor is generated, the exception processing routine which starts from the recorded address is executed. When multiple exception processing factors are generated at the same time, the exception processing is executed according to priority. The priority of interrupts shown in Table 3.3.1 assumes that the interrupt priority levels are all the same. The interrupt priority levels can be set by software in each interrupt system. (See Section 5.20, "Interrupt and Standby Mode".) Note: The exception processing not including reset saves the SC (system condition flag) and PC (program counter) to the stack before branching to the exception processing routine. Consequently, when returning to the main routine from exception processing routines, use the RETE instruction. Refer to the "S1C88 Core CPU Manual" for CPU operation when an exception processing factor is generated. Table 3.3.1 Correspondence between vector addresses and exception processing factors Vector address 000000H 000002H 000004H 000006H 000008H 00000AH 00000CH 00000EH 000010H 000012H 000014H 000016H 000018H 00001AH 00001CH 00001EH 000020H 000022H 000024H 000026H 000028H 000032H 000034H 0000FEH Symbol RESET ZDIV NMI IRK10 IRK11 IRK12 IRK13 IRK0 IRTU0 IRTC0 IRTU1 IRTC1 IRTU2 IRSER IRSRX IRSTX IRTP1 IRTP2 IRLCD IRAD IRRTC - - Exception processing factor Reset Zero division NMI (Watchdog timer) Input port K1 K10 input interrupt K11 input interrup K12 input interrup K13 input interrup Input port K0 K00-K07 input interrup 16-bit programmable timer 0 Underflow interrupt Compare match interrupt 16-bit programmable timer 1 Underflow interrupt Compare match interrupt 8-bit programmable timer Underflow interrupt Serial interface Receive error interrupt Receive completion interrupt Receive error interrupt Touch panel controller Pen-down interrupt Converted data update interrupt LCD controller Data transfer completion interrupt A/D converter A/D conversion completion interrupt Clock timer 32Hz/8Hz/2Hz/1Hz/60S interrupt System reserved (cannot be used) Software interrupt 3.4 CC (Customized Condition Flag) The S1C88409 does not use the customized condition flag (CC) in the core CPU. Accordingly, it cannot be used as a branching condition for the conditional branching instruction (JRS, CARS). 14 Priority High Low No Priority rating 3.5 Chip Mode 3.5.1 MCU mode and MPU mode The S1C88409 is set in two chip operating mode by the MCU/MPU terminal. EPSON S1C88409 TECHNICAL MANUAL CHAPTER 3: CPU AND MEMORY * MCU mode...Set the MCU/MPU terminal to HIGH (VDD) When setting this mode, the exception processing vectors and the initial routine must be assigned within the common area (000000H- 007FFFH). The MCU mode should be set when using the internal ROM. External memory can be expanded to the addressable space except for the internal memory area. Refer to Section 3.5.2, "Bus mode", for the memory map. In the MCU mode, an initial reset activates the S1C88409 as a system with the internal memory only. The internal ROM is allocated to the top of the common area (logical space 0000H-7FFFH) in the program memory. Exception processing vectors are assigned in the internal ROM. Furthermore, the application initial routine that starts with reset exception processing must likewise be written to the internal ROM. Bus and other settings corresponding to the expanded memory can be done by software. This processing is executed in the initial routine written in the internal ROM. The external memory can be accessed after the bus mode setting. The MCU/MPU terminal has a built-in pull-up resistor, and it can be selected for use or not by the mask option. Note: The MCU/MPU terminal status is latched at the rising edge of the RESET input signal. Therefore, apply a low pulse to the RESET terminal when switching the mode. 3.5.2 Bus mode The S1C88409 has four kind of bus modes in order to set the bus specification to match the configuration of expanded external memory. The four bus modes are as follows, and one of them can be selected with software. * Single chip mode The single chip mode should be set when using the S1C88409 as a single chip microcomputer without external memory expansion. This mode is available only in the MCU mode shown in the previous section because the internal ROM is used. In the MPU mode, the single chip mode cannot be set. In this mode, accessing the internal memory area does not output the chip enable (CE) or the read (RD)/write (WR) signals to the external memory, and it sets the data bus (D0- D7) to high impedance status (or pull-up status when the pull-up resistors for P00-P07 are available by setting the mask option). Consequently, the external memory addresses that overlap with the internal memory are invalid. The single chip mode does not need an external bus line. The terminals for the external bus can be used as general-purpose output ports or I/O ports. Accordingly, the output port consists of 30 bits and the I/O port consists of 28 bits. This mode is equivalent to the Model 3/ minimum mode of the S1C88 core CPU. Memory access is valid only for the internal memory area within the physical space 000000H to 00FFFFH. * MPU mode...Set the MCU/MPU terminal to LOW (VSS) The MPU mode releases the internal ROM area to an external memory, so the internal ROM cannot be used. When this area is accessed, a chip enable (CE) signal and a read (RD)/write (WR) signal are output to the external memory and the data bus (D0-D7) goes to active status. Accessing other internal memory (RAM, I/O memory) does not output these signals outside of the IC. In the MPU mode, the system is activated by the external memory. Therefore, the initial setting for the system configuration can be selected with mask option so that the bus is set according to the external memory at initial reset. (See Section 3.5.2, "Bus mode".) - MCU mode - 00FFFFH RAM, I/O memory 00F000H 00EFFFH 00FFFFH 00FF00H 00FEFFH I/O memory RAM (Data memory) : Unused area RAM 00F000H (Display memory) See Section 3.2.2, "RAM (Data Memory, Display Memory)", for the capacity and address of the RAM. 002000H 001FFFH ROM (8K-byte) 000000H Fig. 3.5.2.1 Memory map for single chip mode S1C88409 TECHNICAL MANUAL EPSON 15 CHAPTER 3: CPU AND MEMORY * Expanded 64K mode External memory can be assigned to the area from 400000H to FFFFFFH in the MCU/ expanded 4M minimum mode. In the MPU mode, the internal ROM area is released to the external memory. Thus, external memory can be assigned to the area from 000000H to BFFFFFH in the MPU/expanded 4M minimum mode. However, the area from 00F000H to 00FFFFH is assigned to the internal RAM and I/O memory, therefore the area cannot be accessed as an external memory. The expanded 64K mode should be set when 64KB or less of external memory is expanded to the S1C88409. This mode can be set regardless of the MCU/MPU mode setting. In the MCU mode, the internal ROM is used. Therefore, the external memory in that area cannot be accessed. External memory can be assigned to the area from 007000H to 00EFFFH in the MCU/expanded 64K mode. In the MPU mode, the internal ROM area is released to the external memory. Thus, external memory can be assigned to the area from 000000H to 00EFFFH in the MPU/expanded 64K mode. The area from 00F000H to 00FFFFH is assigned to the internal RAM and I/O memory, therefore the area cannot be accessed as an external memory. This mode is equivalent to the Model 3/ minimum mode of the S1C88 core CPU. Memory access is valid for the physical space 000000H to BFFFFFH in the MPU mode or 400000H to FFFFFFH + internal memory in the MCU mode. However, program memory expansion is limited to 64KB. In the MPU mode, program memory can be assigned to the common area (000000H to 007FFFH) and one optional bank (32K) area. In the MCU mode, since the internal ROM is assigned to the common area, external program memory can be assigned to one optional bank (32K) only. This mode is suitable for small- to mid-scale program memories and large-scale data memory systems. The expanded 64K mode is suitable for smallto mid-scale systems. This mode can output three (MCU mode) or four (MPU mode) kinds of chip enable (CE) signals for 8KB to 64KB memory chips. It can be selected by software according to the memory chip to be used. Refer to Section 3.6.4, "Chip enable (CE) signal", for details of the CE signal. This mode is equivalent to the Model 3/ minimum mode of the S1C88 core CPU. Memory access is valid only for the physical space 000000H to 00FFFFH. This mode outputs the chip enable (CE) signals for the 4MB memory chip. - MCU mode - 00FFFFH 00F000H 00EFFFH - MCU mode - - MPU mode - Internal mamory Internal memory - MPU mode - FFFFFFH BFFFFFH External memory area External memory area External memory area External memory area 400000H 3FFFFFH 002000H 001FFFH Unused area Internal memory 000000H 010000H 00FFFFH 00F000H 00EFFFH Fig. 3.5.2.2 Memory map for expanded 64K mode Internal memory Internal memory * Expanded 4M minimum mode Unused area The expanded 4M minimum mode should be set when 64KB-4MB x 3 of external memory is expanded to the S1C88409. This mode can be set regardless of the MCU/MPU mode setting. In the MCU mode, the internal ROM is used. 16 External memory area 002000H 001FFFH Internal memory 000000H Fig. 3.5.2.3 Memory map for expanded 4M minimum mode EPSON S1C88409 TECHNICAL MANUAL CHAPTER 3: CPU AND MEMORY * Expanded 4M maximum mode 3.6 External Bus The expanded 4M maximum mode should be set when 64KB-4MB x 3 of external memory is expanded to the S1C88409. This mode can be set regardless of the MCU/MPU mode setting. In the MCU mode, the internal ROM is used. External memory can be assigned to the area from 400000H to FFFFFFH in the MCU/ expanded 4M maximum mode. In the MPU mode, the internal ROM area is released to the external memory. Thus, external memory can be assigned to the area from 000000H to BFFFFFH in the MPU/expanded 4M maximum mode. However, the area from 00F000H to 00FFFFH is assigned to the internal RAM and I/O memory, therefore the area cannot be accessed as an external memory. This mode is equivalent to the Model 3/ maximum mode of the S1C88 core CPU. Memory access is valid for the physical space 000000H to BFFFFFH in the MPU mode or 400000H to FFFFFFH + internal memory in the MCU mode. Program memory and data memory can be assigned with an optional size (up to 4MB x 3 together), so this mode is suitable for systems with large-scale program and data capacity. This mode outputs the chip enable (CE) signals for the 4MB memory chip. - MCU mode - - MPU mode - FFFFFFH BFFFFFH External memory area External memory area 400000H 3FFFFFH Internal memory Address bus (A0-A21) Data bus (D0-D7) I/O External Device External Device RD CE0 CE1 CE2 Fig. 3.6.1 External bus lines The following explains the outline of the external bus terminals. Refer to Section 5.2, "System Controller and Bus Control", for controlling them. 3.6.1 Data bus The S1C88409 has an 8-bit external data bus (D0- D7). The terminals and I/O circuits of the data bus D0-D7 are shared with the I/O port P00-P07, and the function switches according to the bus mode setting. In the single chip mode, the 8-bit terminals are all set as the I/O port terminals P00-P07 and in the other expanded modes, they are set as the data bus (D0-D7). When the data bus is set, the data register and I/O control register of the I/O port P00-P07 are disconnected from the I/O circuit and can be used as general purpose data registers with the ability to read/write. Bus mode Internal memory Single chip External memory area Internal memory 000000H Fig. 3.5.2.4 Memory map for expanded 4M maximum mode Refer to Section 5.2, "System Controller and Bus Control", for setting the mode. S1C88409 TECHNICAL MANUAL External Device WR Unused area 002000H 001FFFH S1C88409 Each data bus line has a built-in pull-up resistor that is activated during the input mode, and it can be selected for use or not by the mask option. Unused area 010000H 00FFFFH 00F000H 00EFFFH The S1C88409 has bus terminals that can address a maximum 4MB x 3 external memory. Memory and other devices can be expanded outside according to the range of each bus mode shown in the previous section. EPSON I/O port Data bus P00 P01 P02 P03 P04 P05 P06 P07 D0 D1 D2 D3 D4 D5 D6 D7 Bus mode 64K 4M (min.) 4M (max.) Fig. 3.6.1.1 Correspondence between data bus and I/O port 17 CHAPTER 3: CPU AND MEMORY 3.6.2 Address bus 3.6.3 Read (RD)/write (WR) signals The S1C88409 has a 22-bit external address bus (A0-A21). The terminals and output circuits of the address bus A0-A21 are shared with the output ports R00-R07 (=A0-A7), R10-R17 (=A8-A15) and R20-R25 (=A16-A21), and the function switches according to the bus mode setting. In the single chip mode, the 22-bit terminals are all set as the output port terminals R00-R07, R10-R17 and R20-R25. In the expanded 64K mode, 16-bit terminals within the 22 bits are set as the address bus A0-A15, while the remaining 6 bits, A16-A21, are set as output port R20-R25. In the expanded 4M minimum and maximum modes, all of the 22-bit terminals are set as the address bus (A0-A21). The output terminals and output circuits for the read (RD)/write (WR) signals are shared with the output ports R26 and R27, and the function switches according to the bus mode setting. In the single chip mode, both the terminals are set as output port terminals and in other expanded modes, they are set as read (RD)/write (WR) signal output terminals. When they are set as read (RD)/write (WR) signal output terminals, the data register and high impedance control register for each output port (R26, R27) are disconnected from the output circuit and can be used as a generalpurpose data register with the ability to read/ write. When the address bus is set, the data register and high impedance control register of each output port are disconnected from the output circuit and can be used as general-purpose data registers with the ability to read/write. Bus mode Single chip 64K Output port Address bus R00 R01 A0 A1 R02 R03 R04 R05 R06 R07 A2 A3 A4 A5 A6 A7 R10 R11 R12 A8 A9 A10 R13 R14 A11 A12 R15 R16 R17 R20 R21 R22 R23 R24 R25 A13 A14 A15 A16 A17 A18 A19 A20 A21 Bus mode Output port RD/WR signal R26 RD Bus mode 64K 4M (min.) Single chip R27 WR 4M (max.) Bus mode 64K 4M (min.) 4M (max.) Fig. 3.6.2.1 Correspondence between address bus and output ports 18 These two signals are output only when the memory area for the external device is being accessed. They are not output when the internal memory is accessed. Refer to Section 3.6.5, "WAIT control", for the signal output timing. Fig. 3.6.3.1 Correspondence between read (RD)/write (WR) signal and output port 3.6.4 Chip enable (CE) signal The S1C88409 has a built-in address decoder which can output up to three chip enable (CE) signals. Consequently, three devices equipped with a chip enable (CE) or chip select (CS) terminal can be directly connected without an external address decoder. The three chip enable (CE0-CE2) signal output terminals and output circuits are shared with output ports R30-R32. In the expanded modes, the function, either CE or output port, can independently be selected by software according to the chips to be expanded. When the chip enable (CE) output is set, the data register and high impedance control register of the output port are disconnected from the output circuit and can be used as general-purpose data registers with the ability to read/write. In the single chip mode, they can be used as the output ports R30-R32. EPSON S1C88409 TECHNICAL MANUAL CHAPTER 3: CPU AND MEMORY Bus mode Single chip Output port CE signal R30 R31 CE0 CE1 R32 CE2 Bus mode 64K 4M (min.) 4M (max.) Fig. 3.6.4.1 Correspondence between CE signals and output ports The memory size assigned to three chip enable (CE) signals is determined by the bus mode setting. In the expanded 64K mode, four decoder outputs can be selected by software according to the memory expanded. Table 3.6.4.1 shows the addressable ranges which are assigned to the chip enable (CE) signal in each mode. When the internal memory area is accessed, the CE signal is not output. Be aware that the part has been irregular setting. External devices can be allocated to an area selected by an optional chip enable signal. It is not necessary to continue from a lower address of the memory space. The chip enable signal is output only when the external memory area is being accessed. It is not output when the internal memory is accessed. Furthermore, when the CPU is in standby status (HALT, SLEEP), all the CE signals go HIGH. It prohibits external memory access and gets the CPU into power save mode. Refer to Section 3.6.5, "WAIT control", for the signal output timing. Table 3.6.4.1 CE0-CE2 address settings (1) Expanded 64K mode + MCU mode CE signal CE0 CE1 CE2 Addressing range (selected with software) 8KB 16KB 32KB 008000H-009FFFH 007000H-00AFFFH 008000H-00EFFFH 00A000H-00BFFFH 00B000H-00EFFFH - 00C000H-00DFFFH - - (2) Expanded 64K mode + MPU mode CE signal CE0 CE1 CE2 Addressing range (selected with software) 8KB 16KB 32KB 64KB 000000H-001FFFH 000000H-003FFFH 000000H-007FFFH 000000H-00EFFFH 002000H-003FFFH 004000H-007FFFH 008000H-00EFFFH - 004000H-005FFFH 008000H-00BFFFH - - (3) Expanded 4M minimum/maximum mode CE signal CE0 CE1 CE2 S1C88409 TECHNICAL MANUAL Addressing range (selected with software) MCU mode MPU mode C00000H-FFFFFFH 000000H-00EFFFH, 010000H-3FFFFFH 400000H-7FFFFFH 400000H-7FFFFFH 800000H-BFFFFFH 800000H-BFFFFFH EPSON 19 CHAPTER 3: CPU AND MEMORY 3.6.5 WAIT control In order to guarantee accessing of external low speed devices during high speed operation, the S1C88409 is equipped with a WAIT function that prolongs access time. (Refer to the "S1C88 Core CPU Manual" for details of the WAIT function.) The WAIT state numbers to be inserted can be selected with software from four values as shown in Table 3.6.5.1. Table 3.6.5.1 Selectable WAIT state numbers Selection No. 1 2 3 4 Insert states 0 4 8 12 The WAIT states that are set with software are inserted between bus cycle states T3 and T4. Note, however, that WAIT states cannot be inserted when an internal register or internal memory is being accessed and when the CPU operates with the OSC1 oscillation clock (see Section 5.4, "Oscillation Circuit"). Consequently, WAIT state settings are invalid in the single chip mode. Figure 3.6.5.1 shows the memory read/write timing charts. The length of one state is 1/2 a cycle of the clock. T1 T2 T3 T4 T1 T2 T3 T4 CLK A0-A21 Address Address CE0 CE1 WR RD D0-D7 Read data Write data Read cycle Write cycle (1) No WAIT WAIT (4 states inserded) T1 T2 T3 Tw1 Tw2 Tw1 Tw2 WAIT (4 states inserded) T4 T1 T2 T3 Tw1 Tw2 Tw1 Tw2 T4 CLK A0-A21 Address Address CE0 CE1 WR RD D0-D7 Read data Write data Read cycle Write cycle (2) WAIT state insertion Fig. 3.6.5.1 Memory read/write cycle 20 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 4: INITIAL RESET CHAPTER 4 INITIAL RESET To initialize the S1C88409 circuits, initial reset must be executed. This section explains the initial reset factor and the initial settings for internal registers. 4.1 Initial Reset Factors 4.1.1 RESET terminal There are two initial reset factors for the S1C88409 as shown below. Initial reset can be done by executed externally inputting a LOW level to the RESET terminal. Be sure to maintain the RESET terminal at LOW level for the regulation time after the power on to assure the initial reset. In addition, be sure to use the RESET terminal for the first initial reset after the power is turned on. The RESET terminal is equipped with a pull-up resistor. You can select whether or not to use by mask option. (1) RESET terminal (2) Simultaneous LOW level input at input port terminals K00-K03. Figure 4.1.1 shows the configuration of the initial reset circuit. The CPU and peripheral circuits are initialized by means of initial reset factors. When the factor is canceled, the CPU commences reset exception processing. (See "S1C88 Core CPU Manual".) When this occurs, reset exception processing vectors, Bank 0, 000000H-000001H from program memory are read out and the program (initialization routine) which begins at the readout address is executed. K00 Input port K00 K01 Input port K01 K02 Input port K02 K03 Input port K03 SLEEP status Oscillation stability waiting signal Time authorize circuit Internal initial reset VDD Mask option RESET Fig. 4.1.1 Configuration of initial reset circuit S1C88409 TECHNICAL MANUAL EPSON 21 CHAPTER 4: INITIAL RESET 4.1.2 Simultaneous LOW level input at input port terminals K00-K03 4.2 Initial Reset Sequence Another way of executing initial reset externally is to input a LOW level simultaneously to the input ports (K00-K03) selected by mask option. Since there is a built-in time authorize circuit, be sure to maintain the designated input port terminal at LOW level for two seconds (when the oscillation frequency is fOSC1 = 32.768 kHz) or more to perform the initial reset by means of this function. However, the time authorize circuit is bypassed during the SLEEP (standby) status and oscillation stabilization waiting period, and initial reset is executed immediately after the simultaneous LOW level input to the designated input ports. The combination of input ports (K00-K03) that can be selected by mask option are as follows: (1) Not use (2) K00 & K01 (3) K00 & K01 & K02 (4) K00 & K01 & K02 & K03 For instance, let's say that mask option (4) "K00 & K01 & K02 & K03" is selected. When the input level at input ports K00-K03 is simultaneously LOW, initial reset will take place. After cancellation of the LOW level input to the RESET terminal, when the power is turned on, the start-up of the CPU is held back until the oscillation stabilization waiting time (8,192/fOSC1 sec.) has elapsed. Figure 4.2.1 shows the operating sequence following initial reset release. Also, when using the initial reset by simultaneous LOW level input into the input port, you should be careful of the following points. (1) During SLEEP status, since the time authorization circuit is bypassed, an initial reset is triggered immediately after a LOW level simultaneous input value. In this case, the CPU starts after waiting the oscillation stabilization time, following cancellation of the LOW level simultaneous input. (2) Other than during SLEEP status, an initial reset will be triggered 1-2 seconds after a LOW level simultaneous input. In this case, since a reset differential pulse (64/fOSC1 sec.) is generated inside the S1C88409, the CPU will start even if the LOW level simultaneous input status is not canceled. When using this function, make sure that the designated input ports do not simultaneously switch to LOW level while the system is in normal operation. fOSC1 RESET Internal initial reset Internal address bus PC Internal data bus PC Dummy PC Dummy 00-0000 VECL Internal read signal 8192/fOSC1 [sec] Oscillation stable waiting time Dummy cycle Reset exception processing Fig. 4.2.1 Initial reset sequence 22 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 4: INITIAL RESET 4.3 Initial Settings at Initial Reset Initial settings of internal registers The internal registers in the CPU are initialized as follows during initial reset. Table 4.3.1 Initial settings Register name Data register A Data register B Symbol Bit length Initial value A B 8 8 Undefined Undefined Index (data) register L L 8 Undefined Index (data) register H Index register IX H IX 8 16 Undefined Undefined Index register IY Program counter Stack pointer IY PC SP 16 16 16 Undefined Undefined* Undefined Base register Zero flag Carry flag Overflow flag Negative flag BR Z C V N 8 1 1 1 1 Undefined 0 0 0 0 Decimal flag Unpack flag Interrupt flag 0 D U I0 1 1 1 0 0 1 Interrupt flag 1 New code bank register Code bank register I1 NB CB 1 8 8 1 01H Undefined* Expand page register Expand page register for IX EP XP 8 8 00H 00H Expand page register for IY YP 8 00H The stack pointer SP is undefined at initial reset. Be sure to initialize SP before subroutines and interrupts generate. In the S1C88409, the stack page is fixed at Page 0. Therefore, reserve the stack area in the RAM expanded in Page 0 or the data memory area of the internal RAM (-00FEFFH). Note: The display memory area configured by mask option may be used as data memory. However, the stack area cannot be assigned there. Internal RAM (Data memory, Display memory) Since the internal RAM is not initialized at initial reset, initialize with software. System and terminal configuration When the S1C88409 is used in the MCU mode, the bus mode is set to the single chip mode at initial reset. In the MPU mode, it is set to the mode selected by the mask option. Refer to Section 1.4, "Pin Layout Diagram", for the terminal configuration depending on the bus mode setting. Internal peripheral circuit The reset exception processing loads the value stored in Bank 0, 00000H-000001H into the PC. At the same time, the NB initial value 01H is loaded into CB. Registers which are not initialized at initial reset should be initialized using software. Stack The internal peripheral circuits are initialized to prescribed status. Initialize with software if necessary. Especially the input/output terminals of the peripheral circuits are all set as the output port terminals and the I/O port terminals. Switch them according to the peripheral circuit to be used. Refer to Section 5.1, "I/O Memory Map", or respective sections of the peripheral circuits for details of the status and initial values. Interrupt After initial reset, all the interrupts including NMI are masked until the appropriate values are written to the I/O memory addresses "00FF00H" and "00FF01H" to prevent malfunctions that may occur before setting the system configuration. Refer to Section 5.2, "System Controller and Bus Control", for the contents of the addresses. S1C88409 TECHNICAL MANUAL EPSON 23 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) CHAPTER 5 PERIPHERAL CIRCUITS AND OPERATION The peripheral circuits of the S1C88409 are interfaced with the CPU in the memory mapped I/O method. Thus, the peripheral circuits can be controlled by using the memory operation instructions to access the I/O memory. This chapter explains the operation and control of the peripheral circuits, individually. 5.1 I/O Memory Map Table 5.1.1(a) I/O Memory map (00FF00H, 00FF01H) Address Bit 00FF00 D7 MCU mode D6 D5 D4 D3 D2 D1 D0 00FF00 D7 MPU mode D6 D5 D4 D3 D2 D1 D0 00FF01 D7 D6 D5 D4 D3 D2 D1 D0 Name Function BSMD1 Bus mode (CPU mode) selection BSMD1 BSMD0 Mode 1 1 4M(Maximum) BSMD0 1 0 4M(Minimum) 0 1 64K 0 0 Single chip CEMD1 Expanded 64K chip enable mode CEMD1 CEMD0 Mode 1 1 - CEMD0 1 0 32K(CE0) 0 1 16K(CE0, CE1) 0 0 8K(CE0-CE2) - - CE2 CE2(R32) CE signal output enable/disable CE1 CE1(R31) enable: CE signal output CE0 CE0(R30) disable: DC output (R3x) BSMD1 Bus mode (CPU mode) selection BSMD1 BSMD0 Mode 1 1 4M(Maximum) BSMD0 1 0 4M(Minimum) 0 1 64K 0 0 Option selection CEMD1 Expanded 64K chip enable mode CEMD1 CEMD0 Mode 1 1 64K(CE0) CEMD0 1 0 32K(CE0, CE1) 0 1 16K(CE0-CE2) 0 0 8K(CE0-CE2) - - CE2 CE2(R32) CE signal output enable/disable CE1 CE1(R31) enable: CE signal output CE0 CE0(R30) disable: DC output (R3x) - - - - WT1 Wait state control WT1 WT0 Number of states 1 1 12(3 cycles) WT0 1 0 8(2 cycles) 0 1 4(1 cycle) 0 0 No wait CLKCHG CPU operating clock switch OSCC OSC3 oscillation ON/OFF control VD1C1 VD1 output level setting VD1C1 VD1C0 VD1 (Typ.) 1 1 4.2 V 1 0 3.2 V VD1C0 0 1 1.6 V 0 0 2.4 V 1 0 Init R/W 0 R/W Comment 0 R/W 1 R/W Only for 64K bus mode 1 R/W - CE2 enable CE1 enable CE0 enable - CE2 disable CE1 disable CE0 disable - 1 1 1 - R/W R/W R/W R/W "0" when being read In the single chip mode, these setting are fixed at DC output Initial setting can be selected from 3 types (64K, 4M min, 4M R/W max) by mask option 1 R/W Only for 64K bus mode 1 R/W - CE2 enable CE1 enable CE0 enable - - - CE2 disable CE1 disable CE0 disable - - - 1 1 1 - - 0 - "0" when being read R/W R/W R/W - "0" when being read - R/W 0 R/W OSC3 On OSC1 Off 0 R/W 0 R/W 0 R/W 0 R/W Note: All the interrupts including NMI are masked until the appropriate values are written to both the "00FF00H" and "00FF01H" addresses. 24 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(b) I/O Memory map (00FF10H-00FF13H) Address Bit Name Function 00FF10 D7 PRPRT1 16-bit programmable timer 1 clock control D6 PST12 16-bit programmable timer 1 division ratio PST12 PST11 PST10 (OSC3) (OSC1) 1 1 1 fOSC3 / 4096 fOSC1 / 128 fOSC3 / 1024 fOSC1 / 64 1 1 0 D5 PST11 fOSC3 / 256 fOSC1 / 32 1 0 1 fOSC3 / 128 fOSC1 / 16 1 0 0 fOSC3 / 64 fOSC1 / 8 0 1 1 D4 PST10 fOSC3 / 32 fOSC1 / 4 0 1 0 fOSC3 / 8 fOSC1 / 2 0 0 1 fOSC3 / 2 fOSC1 / 1 0 0 0 D3 PRPRT0 16-bit programmable timer 0 clock control D2 PST02 16-bit programmable timer 0 division ratio PST02 PST01 PST00 (OSC3) (OSC1) 1 1 1 fOSC3 / 4096 fOSC1 / 128 fOSC3 / 1024 fOSC1 / 64 1 1 0 D1 PST01 fOSC3 / 256 fOSC1 / 32 1 0 1 fOSC3 / 128 fOSC1 / 16 1 0 0 fOSC3 / 64 fOSC1 / 8 0 1 1 D0 PST00 fOSC3 / 32 fOSC1 / 4 0 1 0 fOSC3 / 8 fOSC1 / 2 0 0 1 fOSC3 / 2 fOSC1 / 1 0 0 0 1 On 00FF11 D7 - - D6 - - D5 - - D4 - - D3 PRPRT2 8-bit programmable timer clock control D2 PST22 8-bit programmable timer division ratio PST22 PST21 PST20 Division ratio 1 1 1 fOSC3 / 256 fOSC3 / 128 1 1 0 D1 PST21 fOSC3 / 64 1 0 1 fOSC3 / 32 1 0 0 fOSC3 / 16 0 1 1 D0 PST20 fOSC3 / 8 0 1 0 fOSC3 / 4 0 0 1 fOSC3 / 2 0 0 0 - - - - On 00FF12 D7 D6 D5 D4 D3 D2 D1 D0 00FF13 D7 D6 D5 D4 D3 D2 - - - - - - PRTF1 PRTF0 - - - - PRAD PSAD2 D1 PSAD1 D0 PSAD0 Init R/W 0 R/W 0 R/W Comment 0 R/W 0 R/W On Off 0 R/W 0 R/W 0 R/W 0 R/W - - - - Off - - "0" when being read - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W - - - - - - 16-bit programmable timer 1 source clock selection 16-bit programmable timer 0 source clock selection - - - - A/D converter clock control A/D converter division ratio PSAD2 PSAD1 PSAD0 Division ratio 1 x x fOSC3 / 16 0 1 1 fOSC3 / 8 fOSC3 / 4 0 1 0 fOSC3 / 2 0 0 1 fOSC3 / 1 0 0 0 S1C88409 TECHNICAL MANUAL 0 Off EPSON - - - - - - - - - - - - fOSC1 fOSC1 - - - - On fOSC3 fOSC3 - - - - Off - - - - - - 0 0 - - - - 0 0 - "0" when being read - - - - - R/W R/W - "0" when being read - - - R/W R/W 0 R/W 0 R/W 25 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(c) I/O Memory map (00FF14H-00FF16H) Address Bit 00FF14 D7 D6 D5 D4 D3 D2 D1 D0 00FF15 D7 D6 D5 D4 D3 D2 D1 D0 00FF16 D7 D6 D5 D4 D3 D2 D1 D0 26 Name Function PRFO1 FOUT1 output control PSF12 FOUT1 division ratio PSF12 PSF11 PSF10 Division ratio 1 1 1 fOSC1 / 128 fOSC1 / 64 1 1 0 PSF11 fOSC1 / 32 1 0 1 fOSC1 / 16 1 0 0 fOSC1 / 8 0 1 1 PSF10 fOSC1 / 4 0 1 0 fOSC1 / 2 0 0 1 fOSC1 / 1 0 0 0 PRFO3 FOUT3 output control PSF32 FOUT3 division ratio PSF32 PSF31 PSF30 Division ratio 1 1 1 fOSC3 / 128 fOSC3 / 64 1 1 0 PSF31 fOSC3 / 32 1 0 1 fOSC3 / 16 1 0 0 fOSC3 / 8 0 1 1 PSF30 fOSC3 / 4 0 1 0 fOSC3 / 2 0 0 1 fOSC3 / 1 0 0 0 - - - - - - - - - - - - PK11ON EXCL01 input clock ON/OFF control PK10ON EXCL00 input clock ON/OFF control - - - - - - - - PRTP Touch panel controller clock control PSTP2 Touch panel controller clock ratio PSTP2 PSTP1 PSTP0 Division ratio 1 x x fOSC3 / 16 PSTP1 1 1 0 fOSC3 / 8 1 0 fOSC3 / 4 0 PSTP0 fOSC3 / 2 0 1 0 fOSC3 / 1 0 0 0 1 On 0 Off Init R/W 0 R/W 0 R/W Comment 0 R/W 0 R/W On Off 0 R/W 0 R/W 0 R/W 0 R/W - - - - - - On On - - - - On - - - - - - Off Off - - - - Off - - - - - - 0 0 - - - - 0 0 - "0" when being read - - - - - R/W R/W - "0" when being read - - - R/W R/W 0 R/W 0 R/W EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(d) I/O Memory map (00FF20H-00FF25H) Address Bit 00FF20 D7 D6 D5 D4 D3 D2 D1 D0 00FF21 D7 D6 D5 D4 D3 D2 D1 D0 00FF22 D7 D6 D5 D4 D3 D2 D1 D0 00FF23 D7 D6 D5 D4 D3 D2 D1 D0 00FF24 D7 Name PK11 PK10 PK01 PK00 PTM11 PTM10 PTM01 PTM00 PTM21 PTM20 PSI1 PSI0 PCTM1 PCTM0 PLCD1 PLCD0 PAD1 PAD0 PTP1 PTP0 - - - - EK13 EK12 EK11 EK10 EK0 - - - ETU2 D6 ETC1 D5 ETU1 D4 ETC0 D3 ETU0 D2 ESTX D1 ESRX D0 ESERR 00FF25 D7 ET60S D6 ECTM1 D5 ECTM2 D4 ECTM8 D3 ECTM32 D2 ELCD D1 - D0 - Function K10-K13 interrupt priority register K00-K07 interrupt priority register 16-bit programmable timer 1 interrupt priority register 16-bit programmable timer 0 interrupt priority register 8-bit programmable timer interrupt priority register Serial interface interrupt priority register Clock timer interrupt priority register LCD controller interrupt priority register A/D converter interrupt priority register Touch panel controller interrupt priority register - - - - K13 interrupt enable register K12 interrupt enable register K11 interrupt enable register K10 interrupt enable register K00-K07 interrupt enable register - - - 8-bit programmable timer underflow interrupt enable register 16-bit programmable timer 1 compare match interrupt enable register 16-bit programmable timer 1 underflow interrupt enable register 16-bit programmable timer 0 compare match interrupt enable register 16-bit programmable timer 0 underflow interrupt enable register Serial interface transmit completion interrupt enable register Serial interface receive completion interrupt enable register Serial interface receive error interrupt enable register Clock timer 60 S interrupt enable register Clock timer 1 Hz interrupt enable register Clock timer 2 Hz interrupt enable register Clock timer 8 Hz interrupt enable register Clock timer 32 Hz interrupt enable register LCD controller interrupt enable register - - S1C88409 TECHNICAL MANUAL EPSON 1 PK11 PK01 PTM11 PTM01 1 1 0 0 PTM21 PSI1 PCTM1 PLCD1 1 1 0 0 PAD1 PTP1 1 1 0 0 0 PK10 PK00 PTM10 PTM00 1 0 1 0 PTM20 PSI0 PCTM0 PLCD0 1 0 1 0 PAD0 PTP0 1 0 1 0 Interrupt is enabled Priority level Level 3 Level 2 Level 1 Level 0 Priority level Level 3 Level 2 Level 1 Level 0 Priority level Level 3 Level 2 Level 1 Level 0 Interrupt is disabled Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - 0 0 0 0 0 - - - 0 R/W Comment R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - R/W R/W R/W R/W R/W - "0" when being read - - R/W 0 R/W 0 R/W 0 R/W Interrupt is enabled Interrupt is disabled 0 R/W 0 R/W 0 R/W 0 R/W Interrupt is enabled Interrupt is disabled 0 0 0 0 0 0 - - R/W R/W R/W R/W R/W R/W - "0" when being read - 27 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(e) I/O Memory map (00FF26H-00FF2AH) Address Bit 00FF26 D7 Name EAD D6 ETPPD D5 ETPDR D4 D3 D2 D1 D0 00FF27 D7 D6 D5 D4 D3 D2 D1 D0 00FF28 D7 - - - - - FK13 FK12 FK11 FK10 FK0 - - - FTU2 D6 FTC1 D5 FTU1 D4 FTC0 D3 FTU0 D2 FSTX D1 FSRX D0 FSERR 00FF29 D7 FT60S D6 FCTM1 D5 FCTM2 D4 FCTM8 D3 FCTM32 D2 FLCD D1 - D0 - 00FF2A D7 FAD 28 D6 FTPPD D5 FTPDR D4 D3 D2 D1 D0 - - - - - Function A/D converter conversion completion interrupt enable register Touch panel controller pen-down interrupt enable register Touch panel controller converted data update interrupt enable register - - - - - K13 interrupt factor flag K12 interrupt factor flag K11 interrupt factor flag K10 interrupt factor flag K00-K07 interrupt factor flag - - - 8-bit programmable timer underflow interrupt factor flag 16-bit programmable timer 1 compare match interrupt factor flag 16-bit programmable timer 1 underflow interrupt factor flag 16-bit programmable timer 0 compare match interrupt factor flag 16-bit programmable timer 0 underflow interrupt factor flag Serial interface transmit completion interrupt factor flag Serial interface receive completion interrupt factor flag Serial interface receive error interrupt factor flag Clock timer 60 S interrupt factor flag Clock timer 1 Hz interrupt factor flag Clock timer 2 Hz interrupt factor flag Clock timer 8 Hz interrupt factor flag Clock timer 32 Hz interrupt factor flag LCD controller interrupt factor flag - - A/D converter conversion completion interrupt factor flag Touch panel controller pen-down interrupt factor flag Touch panel controller converted data update interrupt factor flag - - - - - EPSON 1 0 Init R/W 0 R/W Comment 0 R/W Interrupt is enabled Interrupt is disabled (R) Interrupt factor has generated (R) Interrupt factor has not generated (W) Reset (W) Invalid (R) Interrupt factor has generated (R) Interrupt factor has not generated 0 R/W - - - - - 0 0 0 0 0 - - - 0 - "0" when being read - - - - R/(W) R/(W) R/(W) R/(W) R/(W) - "0" when being read - - R/(W) 0 R/(W) 0 R/(W) 0 R/(W) 0 R/(W) 0 R/(W) (W) Reset (W) Invalid 0 R/(W) 0 R/(W) (R) Interrupt factor has generated (R) Interrupt factor has not generated (W) Reset (W) Invalid (R) Interrupt factor has generated (R) Interrupt factor has not generated (W) Reset (W) Invalid 0 0 0 0 0 0 - - 0 R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) - "0" when being read - R/W 0 R/W 0 R/W - - - - - - - - - - "0" when being read S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(f) I/O Memory map (00FF30H-00FF37H) Address Bit Name 00FF30 D7 MODE16 D6 - D5 - D4 - D3 PTOUT0 D2 PTRUN0 D1 PSET0 D0 CKSEL0 00FF31 D7 - D6 - D5 - D4 - D3 PTOUT1 D2 PTRUN1 D1 PSET1 D0 CKSEL1 00FF32 D7 RDR07 D6 RDR06 D5 RDR05 D4 RDR04 D3 RDR03 D2 RDR02 D1 RDR01 D0 RDR00 00FF33 D7 RDR17 D6 RDR16 D5 RDR15 D4 RDR14 D3 RDR13 D2 RDR12 D1 RDR11 D0 RDR10 00FF34 D7 CDR07 D6 CDR06 D5 CDR05 D4 CDR04 D3 CDR03 D2 CDR02 D1 CDR01 D0 CDR00 00FF35 D7 CDR17 D6 CDR16 D5 CDR15 D4 CDR14 D3 CDR13 D2 CDR12 D1 CDR11 D0 CDR10 00FF36 D7 PTM07 D6 PTM06 D5 PTM05 D4 PTM04 D3 PTM03 D2 PTM02 D1 PTM01 D0 PTM00 00FF37 D7 PTM17 D6 PTM16 D5 PTM15 D4 PTM14 D3 PTM13 D2 PTM12 D1 PTM11 D0 PTM10 Function 16-bit PTM 8-/16-bit mode selection - - - 16-bit PTM0 clock output control 16-bit PTM0 RUN/STOP control 16-bit PTM0 preset 16-bit PTM0 input clock selection - - - - 16-bit PTM1 clock output control 16-bit PTM1 RUN/STOP control 16-bit PTM1 preset 16-bit PTM1 input clock selection 16-bit programmable timer 0 reload data register 16-bit programmable timer 1 reload data register 16-bit programmable timer 0 compare data register 16-bit programmable timer 1 compare data register 16-bit programmable timer 0 data register 16-bit programmable timer 1 data register S1C88409 TECHNICAL MANUAL D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) EPSON 1 0 Init R/W Comment 16-bit 8-bit x 2 0 R/W - - - - "0" when being read - - - - - - - - On Off 0 R/W Run Stop 0 R/W Preset Invalid 0 W "0" when being read External clock Internal clock 0 R/W - - - - "0" when being read - - - - - - - - - - - - On Off 0 R/W Run Stop 0 R/W Preset Invalid 0 W "0" when being read External clock Internal clock 0 R/W 1 R/W Low-order 8 bits data 1 R/W in 16-bit mode 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W High-order 8 bits data 1 R/W in 16-bit mode 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R/W Low-order 8 bits data 0 R/W in 16-bit mode 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W High-order 8 bits data 0 R/W in 16-bit mode 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R Low-order 8 bits data 1 R in 16-bit mode 1 R 1 R 1 R 1 R 1 R 1 R 1 R High-order 8 bits data 1 R in 16-bit mode 1 R 1 R 1 R 1 R 1 R 1 R 29 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(g) I/O Memory map (00FF38H-00FF3AH) Address Bit 00FF38 D7 D6 D5 D4 D3 D2 D1 D0 00FF39 D7 D6 D5 D4 D3 D2 D1 D0 00FF3A D7 D6 D5 D4 D3 D2 D1 D0 30 Name - - - - - PTOUT PSET PRUN RLD7 RLD6 RLD5 RLD4 RLD3 RLD2 RLD1 RLD0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Function - - - - - 8-bit programmable timer clock output control 8-bit programmable timer preset 8-bit programmable timer RUN/STOP control 8-bit programmable timer D7(MSB) reload data register D6 D5 D4 D3 D2 D1 D0(LSB) 8-bit programmable timer D7(MSB) data register D6 D5 D4 D3 D2 D1 D0(LSB) EPSON 1 - - - - - On Preset Run 0 - - - - - Off Invalid Stop Init - - - - - 0 - 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W Comment - "0" when being read - - - - R/W W "0" when being read R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(h) I/O Memory map (00FF40H-00FF43H) Address Bit 00FF40 D7 D6 D5 D4 D3 D2 D1 D0 00FF41 D7 D6 D5 D4 D3 D2 D1 D0 00FF42 D7 D6 D5 D4 D3 D2 D1 D0 00FF43 D7 D6 D5 D4 D3 D2 D1 D0 Name SIOSEL EPR PMD STPB - SMD1 Function 1 Serial I/F terminal selection P14-P17 Serial I/F parity enable With parity Serial I/F parity mode selection Odd Serial I/F stop bit selection 2 bits - - Serial I/F mode selection SMD0 Mode SMD1 1 8-bit asynchronous 1 0 7-bit asynchronous SMD0 1 1 Clock synchronous slave 0 0 Clock synchronous master 0 ESIF Serial I/F enable Serial I/F - - - FER Serial I/F Error framing error flag Reset (0) PER Serial I/F Error parity error flag Reset (0) OER Serial I/F Error overrun error flag Reset (0) RXTRG Serial I/F Run receive trigger/status Trigger RXEN Serial I/F receive enable Enable TXTRG Serial I/F Run transmit trigger/status Trigger TXEN Serial I/F transmit enable Enable TRXD7 Serial I/F D7(MSB) TRXD6 transmit/receive data register D6 TRXD5 D5 TRXD4 D4 High TRXD3 D3 TRXD2 D2 TRXD1 D1 TRXD0 D0(LSB) - - - - - - - - - - - - IRTL IrDA interface output logic inversion Inverse IRIL IrDA interface input logic inversion Inverse IRST1 IrDA interface setting IRST1 IRST0 Setting 1 1 Reserved (do not set) 1 0 IrDA interface IRST0 0 1 Reserved (do not set) 0 0 Normal interface S1C88409 TECHNICAL MANUAL EPSON 0 P10-P13 No parity Even 1 bit - Init 0 0 0 0 - 0 R/W Comment R/W R/W R/W R/W - "0" when being read R/W 0 R/W I/O port - No error Invalid No error Invalid No error Invalid Stop Invalid Disable Stop Invalid Disable Low - - - - Normal Normal 0 R/W - - "0" when being read 0 R W 0 R W 0 R W 0 R W 0 R/W 0 R W 0 R/W x R/W TRXD7 is invalid in x R/W 7-bit asynchronous x R/W mode x R/W x R/W x R/W x R/W x R/W - - "0" when being read - - - - - - 0 R/W 0 R/W 0 R/W Valid only when SIOSEL = "1" in asynchronous mode 0 R/W 31 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(i) I/O Memory map (00FF50H-00FF53H) Address Bit Name Function 1 0 Init R/W Comment 00FF50 D7 - - - - - - "0" when being read D6 - - - - - - D5 - - - - - - D4 - - - - - - D3 - - - - - - D2 - - - - - - D1 TMRST Clock timer reset Reset Invalid - W D0 TMRUN Clock timer RUN/STOP Run Stop 0 R/W 00FF51 D7 TMD7 Clock timer data 1 Hz 0 R D6 TMD6 Clock timer data 2 Hz 0 R D5 TMD5 Clock timer data 4 Hz 0 R D4 TMD4 Clock timer data 8 Hz 0 R High Low D3 TMD3 Clock timer data 16 Hz 0 R D2 TMD2 Clock timer data 32 Hz 0 R D1 TMD1 Clock timer data 64 Hz 0 R D0 TMD0 Clock timer data 128 Hz 0 R 00FF52 D7 - - - - - - "0" when being read D6 TMMD6 Clock timer data 10 sec (BCD) 0 R/W D5 TMMD5 0 R/W D4 TMMD4 0 R/W D3 TMMD3 Clock timer data 1 sec (BCD) 0 R/W D2 TMMD2 0 R/W D1 TMMD1 0 R/W D0 TMMD0 0 R/W 00FF53 D7 WRWD EWD, WDCL write enable Write enable Write disable 0 R/W 1 D6 EWD Watchdog timer NMI enable NMI enable NMI disable 1 R/W 1 D5 WDCL Watchdog timer input clock selection fOSC3/16 fOSC1/16 0 R/W 1 - - D4 - - - - "0" when being read - - D3 - - - - - - D2 - - - - - - D1 - - - - Reset Invalid D0 WDRST Watchdog timer reset - W 1 Writing to EWD or WDCL is valid after "1" is written to WRWD. WRWD is automatically returns to "0" after writing to EWD or WDCL. 32 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(j) I/O Memory map (00FF54H-00FF55H) Address Bit 00FF54 D7 D6 D5 Name - BZSTP BZSHT D4 D3 D2 D1 D0 00FF55 D7 D6 SHTPW ENRTM ENRST ENON BZON - DUTY2 1 Function - One-shot buzzer forcibly stop One-shot buzzer trigger/status One-shot buzzer duration width selection Envelope attenuation time Envelope reset Envelope On/Off control Buzzer output control - Buzzer signal duty ratio selection DUTY2-1 Buzzer frequency (Hz) 4096.0 3276.8 2730.7 2340.6 2 1 0 2048.8 1638.4 1365.3 1170.3 D5 DUTY1 0 0 0 8/16 8/20 12/24 12/28 0 0 1 7/16 7/20 11/24 11/28 0 1 0 6/16 6/20 10/24 10/28 0 1 1 5/16 5/20 9/24 9/28 1 0 0 4/16 4/20 8/24 8/28 D4 DUTY0 1 0 1 3/16 3/20 7/24 7/28 1 1 0 2/16 2/20 6/24 6/28 1 1 1 1/16 1/20 5/24 5/28 D3 - - D2 BZFQ2 Buzzer frequency selection BZFQ2 BZFQ1 BZFQ0 Frequency (Hz) 0 0 0 4096.0 0 0 1 3276.8 D1 BZFQ1 0 1 0 2730.7 0 1 1 2340.6 1 0 0 2048.0 D0 BZFQ0 1 0 1 1638.4 1 1 0 1365.3 1 1 1 1170.3 ENON is reset to "0" during one-shot output. 1 0 Init R/W Comment - - - - "0" when being read Forcibly stop No operation - W Busy Ready 0 R Trigger No operation 0 W 125 msec 31.25 msec 0 R/W 1 sec 0.5 sec 0 R/W Reset No operation - W "0" when being read On Off 0 R/W 1 On Off 0 R/W - - - - "0" when being read 0 R/W 0 R/W 0 R/W - - - - "0" when being read 0 R/W 0 R/W 0 R/W Table 5.1.1(k) I/O Memory map (00FF56H) Address Bit 00FF56 D7 D6 D5 D4 D3 D2 D1 D0 Name - - - - SVD1 Function - - - - SVD criteria voltage setting SVD1 SVD0 Voltage (V) 1 x 3.4 V SVD0 0 1 2.8 V 0 0 1.9 V SVDDT SVD data SCDON SVD On/Off control S1C88409 TECHNICAL MANUAL 1 - - - - 0 - - - - Init R/W Comment - - "0" when being read - - - - - - 0 R/W 0 R/W Low On EPSON Normal Off 0 R 0 R/W 33 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(l) I/O Memory map (00FF60H-00FF65H) Address Bit 00FF60 D7 D6 D5 D4 D3 D2 Name Function DISP Display On/Off control REV Normal/Inverse display control CKCN2 Scanning line frequency selection CKCN2 CKCN1 CKCN0 POINT5 0 0 0 0 0 0 0 1 0 0 1 0 CKCN1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 CKCN0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 POINT5 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 On Inverse Frequency fOSC1 fOSC1 / 1.5 fOSC1 / 2 fOSC1 / 2.5 fOSC1 / 3 fOSC1 / 3.5 fOSC1 / 4 fOSC1 / 4.5 fOSC1 / 5 fOSC1 / 5.5 fOSC1 / 6 fOSC1 / 6.5 fOSC1 / 7 fOSC1 / 7.5 fOSC1 / 8 fOSC1 / 8.5 D1 GRAY Gray/B&W mode selection D0 BITNO 8-bit/4-bit transfer selection 00FF61 D7 - - D6 - - D5 - - D4 S1570AS Hardware auto-transfer status D3 LCDEN LCD power On/Off control D2 S1570A Hardware auto-transfer control D1 S1570O One-shot transfer trigger/status D0 00FF62 D7 D6 D5 D4 D3 D2 D1 D0 00FF63 D7 D6 D5 D4 D3 D2 D1 D0 00FF64 D7 D6 D5 D4 D3 D2 D1 D0 00FF65 D7 D6 D5 D4 D3 D2 D1 D0 34 S1606 - LBC6 LBC5 LBC4 LBC3 LBC2 LBC1 LBC0 SAD7 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 SAD15 SAD14 SAD13 SAD12 SAD11 SAD10 SAD9 SAD8 SLT7 SLT6 SLT5 SLT4 SLT3 SLT2 SLT1 SLT0 Continuous refresh transfer control - Number of bytes per display line Display start address (lower 8 bits) Display start address (upper 8 bits) Total display lines 0 Off Normal D6(MSB) D5 D4 D3 D2 D1 D0(LSB) D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EPSON Init 0 0 0 R/W R/W R/W R/W Comment 0 R/W 0 R/W 0 R/W Gray 8 bits - - - Busy On On Busy Trigger On - B&W 4 bits - - - Standby Off Off Standby Invalid Off - High Low High Low High Low High Low 0 0 - - - 0 0 0 0 0 1 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W - "0" when being read - - R R/W R/W R W R/W - "0" when being read R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(m) I/O Memory map (00FF66H-00FF6AH) Address Bit 00FF66 D7 D6 D5 D4 D3 D2 D1 D0 00FF67 D7 D6 D5 D4 D3 D2 D1 D0 00FF68 D7 D6 D5 D4 D3 D2 D1 D0 00FF69 D7 D6 D5 D4 D3 D2 D1 D0 00FF6A D7 D6 D5 D4 D3 D2 D1 D0 Name - - - - - - - SLT8 APADJ7 APADJ6 APADJ5 APADJ4 APADJ3 APADJ2 APADJ1 APADJ0 GS17 GS16 GS15 GS14 GS13 GS12 GS11 GS10 GS27 GS26 GS25 GS24 GS23 GS22 GS21 GS20 GS37 GS36 GS35 GS34 GS33 GS32 GS31 GS30 Function - - - - - - - Total display lines (MSB) Address pitch adjustment Gray scale (0,1) conversion code Gray scale (1,0) conversion code Gray scale (1,1) conversion code S1C88409 TECHNICAL MANUAL D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 EPSON 1 - - - - - - - High 0 - - - - - - - Low High Low High Low High Low High Low Init - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W Comment - "0" when being read - - - - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 35 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(n) I/O Memory map (00FF80H-00FF82H) Address Bit 00FF80 D7 D6 D5 D4 D3 D2 D1 D0 00FF81 D7 D6 D5 D4 D3 D2 D1 D0 00FF82 D7 D6 D5 D4 D3 D2 D1 D0 Name ADRUN - - VRC VRO CHS2 Function A/D conversion start control register - - AVREF control (Touch pamel controller) AVREF swich Analog input channel selection CHS2 CHS1 CHS0 Input channel 1 1 1 AD7 1 1 0 AD6 CHS1 1 0 1 AD5 1 0 0 AD4 0 1 1 AD3 CHS0 0 1 0 AD2 0 0 1 AD1 0 0 0 AD0 ADDR9 A/D conversion result ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 - - - - - - - - - - - - ADDR1 A/D conversion result ADDR0 1 Start - - Enable On 0 Invalid - - Invalid Off Init 0 - - 0 0 0 R/W Comment W "0" when being read - - R/W R/W R/W 0 R/W 0 R/W D9(MSB) D8 D7 D6 D5 D4 D3 D2 - - - - - - - - - - - - D1 D0(LSB) - - - - - - - - - - - - - - - - R R R R R R R R - - - - - - R R "0" when being read Table 5.1.1(o) I/O Memory map (00FF90H-00FF91H) Address Bit 00FF90 D7 D6 D5 D4 D3 D2 D1 D0 00FF91 D7 D6 D5 D4 D3 D2 D1 D0 36 Name Function - - - - - - - - - - - - - - DAE D/A conversion result analog output control DADR7 D/A converter D7(MSB) DADR6 D/A conversion output data register D6 DADR5 D5 DADR4 D4 DADR3 D3 DADR2 D2 DADR1 D1 DADR0 D0(LSB) EPSON 1 - - - - - - - Enable 0 - - - - - - - Disable Init - - - - - - - 0 0 0 0 0 0 0 0 0 R/W Comment - "0" when being read - - - - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(p) I/O Memory map (00FFA0H-00FFA2H) Address Bit 00FFA0 D7 D6 D5 D4 D3 D2 Name - PDC RST CONST - AVN2 D1 AVN1 D0 AVN0 00FFA1 D7 D6 D5 D4 D3 - - - - WAIT3 D2 WAIT2 D1 WAIT1 D0 WAIT0 00FFA2 D7 D6 D5 D4 D3 - - - - CND3 D2 CND2 D1 CND1 D0 CND0 Function - Pen-down check control TPC circuit reset control Mode setting - Mean count setting Mean count AVN2 AVN1 AVN0 0 0 16 x 16 0 16 x 8 0 1 0 16 x 4 1 0 0 16 x 2 1 1 0 16 x 1 x x 1 - - - - Voltage stabilization waiting time setting 1 - Check Cancel Constant-speed - 0 - Cancel Reset Normal - CND3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S1C88409 TECHNICAL MANUAL CND2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CND1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CND0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EPSON Comment "0" when being read Valid when "RST=0" "0" when being read Invalid when Normal mode 0 R/W - - - - - - - - - - "0" when being read - - - - - - 0 R/W 1 R/W 0 R/W 0 R/W - - - - Value 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 R/W - R/W R/W R/W - R/W 0 R/W WAIT3 WAIT2 WAIT1 WAIT0 Waiting time 0 0 0 0 16 x 1/f 0 0 0 1 16 x 2/f 0 0 1 0 16 x 3/f 0 0 1 1 16 x 4/f 0 1 0 0 16 x 5/f 0 1 0 1 16 x 6/f 0 1 1 0 16 x 7/f 0 1 1 1 16 x 8/f 1 0 0 0 16 x 9/f 1 0 0 1 16 x 10/f 1 0 1 0 16 x 11/f 1 0 1 1 16 x 12/f 1 1 0 0 16 x 13/f 1 1 0 1 16 x 14/f 1 1 1 0 16 x 15/f 1 1 1 1 16 x 16/f - - - - Noise judgment threshold value setting Init - 0 0 0 - 0 - - - - - - "0" when being read - - - - - - 1 R/W 0 R/W 0 R/W 0 R/W 37 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(q) I/O Memory map (00FFA3H-00FFA4H) Address Bit 00FFA3 D7 D6 D5 D4 D3 D2 PUD2 D1 PUD1 D0 PUD0 00FFA4 D7 38 Name - - - - PUD3 Function - - - - Pen-up decision threshold value setting PUD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PUD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PUD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PUD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 - - - - Value 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 MVML3 Middle-low-speed judgment threshold value setting D6 MVML2 D5 MVML1 D4 MVML0 D3 MVL3 D2 MVL2 D1 MVL1 D0 MVL0 MVML3 MVML2 MVML1 MVML0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Value 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Low-speed judgment threshold value setting MVL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MVL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MVL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MVL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Value 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 EPSON 0 - - - - Init R/W Comment - - "0" when being read - - - - - - 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 1 R/W MVMLMVL 0 R/W 0 R/W 0 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 0 R/W MVMLMVL 1 R/W 0 R/W S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(r) I/O Memory map (00FFA5H-00FFA6H) Address Bit 00FFA5 D7 Name MVH3 D6 MVH2 D5 MVH1 D4 MVH0 D3 D2 D1 D0 00FFA6 D7 D6 D5 D4 D3 Function High-speed judgment threshold value setting MVH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MVH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MVH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MVH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 Value 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 R/W 0 R/W MVMH3 Middle-high-speed judgment threshold value setting 0 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 1 R/W MVMLMVL MVMH3 MVMH2 MVMH1 MVMH0 Value 0 0 0 2 0 0 0 1 4 0 0 1 0 6 0 MVMH2 0 1 1 8 0 1 0 0 10 0 1 0 1 12 0 1 1 0 14 0 1 1 1 16 0 MVMH1 0 0 0 18 1 0 0 1 20 1 0 1 0 22 1 0 1 1 24 1 1 0 0 26 1 MVMH0 1 0 1 28 1 1 1 0 30 1 1 1 1 32 1 - - - - IVL3 D2 IVL2 D1 IVL1 D0 IVL0 - - - - IVL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S1C88409 TECHNICAL MANUAL IVL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IVL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 R/W 0 R/W - - - - Interval time setting IVL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interval time 128 x 1 x2 x3 x4 x5 x6 x7 x8 x9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 EPSON Init R/W Comment 1 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 0 R/W MVMLMVL - - - - - - "0" when being read - - - - - - 0 R/W 0 R/W 1 R/W 0 R/W 39 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(s) I/O Memory map (00FFA7H-00FFABH) Address Bit 00FFA7 D7 D6 D5 D4 D3 D2 D1 D0 00FFA8 D7 D6 D5 D4 D3 D2 D1 D0 00FFA9 D7 D6 D5 D4 D3 D2 D1 D0 00FFAA D7 D6 D5 D4 D3 D2 D1 D0 00FFAB D7 D6 D5 D4 D3 D2 D1 D0 40 Name - - - - - - - PEN DX11 DX10 DX9 DX8 DX7 DX6 DX5 DX4 - - - - DX3 DX2 DX1 DX0 DY11 DY10 DY9 DY8 DY7 DY6 DY5 DY4 - - - - DY3 DY2 DY1 DY0 Function - - - - - - - Pen-up/pen-down status X coordinate data 1 - - - - - - - Pen-down D11(MSB) D10 D9 D8 D7 D6 D5 D4 - - - - D3 D2 D1 D0(LSB) D11(MSB) D10 D9 D8 D7 D6 D5 D4 X coordinate data Y coordinate data - - - - Y coordinate data D3 D2 D1 D0(LSB) EPSON 0 - - - - - - - Pen-up Init R/W Comment - - "0" when being read - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R - - "0" when being read - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R - - "0" when being read - - - - - - 0 R 0 R 0 R 0 R S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(t) I/O Memory map (00FFC0H-00FFC4H) Address Bit 00FFC0 D7 D6 D5 D4 D3 D2 D1 D0 00FFC1 D7 D6 D5 D4 D3 D2 D1 D0 00FFC2 D7 D6 D5 D4 D3 D2 D1 D0 00FFC3 D7 D6 D5 D4 D3 D2 D1 D0 00FFC4 D7 D6 D5 D4 D3 D2 D1 D0 Name SIK07 SIK06 SIK05 SIK04 SIK03 SIK02 SIK01 SIK00 KCP07 KCP06 KCP05 KCP04 KCP03 KCP02 KCP01 KCP00 - - - - KCP13 KCP12 KCP11 KCP10 K07D K06D K05D K04D K03D K02D K01D K00D - - - - K13D K12D K11D K10D Function K07 interrupt selection register K06 interrupt selection register K05 interrupt selection register K04 interrupt selection register K03 interrupt selection register K02 interrupt selection register K01 interrupt selection register K00 interrupt selection register K07 input comparison register K06 input comparison register K05 input comparison register K04 input comparison register K03 input comparison register K02 input comparison register K01 input comparison register K00 input comparison register - - - - K13 input comparison register K12 input comparison register K11 input comparison register K10 input comparison register K07 input port data K06 input port data K05 input port data K04 input port data K03 input port data K02 input port data K01 input port data K00 input port data - - - - K13 input port data K12 input port data K11 input port data K10 input port data S1C88409 TECHNICAL MANUAL EPSON 1 0 Interrupt is enabled Interrupt is disabled Falling edge generates interrupt Rising edge generates interrupt - - - - - - - - Falling edge generates interrupt Rising edge generates interrupt High Low - - - - - - - - High Low Init 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 - - - - - - - - - - - - - - - - R/W Comment R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - R/W R/W R/W R/W R R R R R R R R - "0" when being read - - - R R R R 41 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(u) I/O Memory map (00FFD0H-00FFD4H) Address Bit 00FFD0 D7 D6 D5 D4 D3 D2 D1 D0 00FFD1 D7 D6 D5 D4 D3 D2 D1 D0 00FFD2 D7 D6 D5 D4 D3 D2 D1 D0 00FFD3 D7 D6 D5 D4 D3 D2 D1 D0 00FFD4 D7 D6 D5 D4 D3 D2 D1 D0 42 Name HZR07 HZR06 HZR05 HZR04 HZR03 HZR02 HZR01 HZR00 HZR17 HZR16 HZR15 HZR14 HZR13 HZR12 HZR11 HZR10 HZR27 HZR26 HZR25 HZR24 HZR23 HZR22 HZR21 HZR20 - - - - - HZR32 HZR31 HZR30 - - - - - HZR42 HZR41 HZR40 Function R07 high impedance control register R06 high impedance control register R05 high impedance control register R04 high impedance control register R03 high impedance control register R02 high impedance control register R01 high impedance control register R00 high impedance control register R17 high impedance control register R16 high impedance control register R15 high impedance control register R14 high impedance control register R13 high impedance control register R12 high impedance control register R11 high impedance control register R10 high impedance control register R27 high impedance control register R26 high impedance control register R25 high impedance control register R24 high impedance control register R23 high impedance control register R22 high impedance control register R21 high impedance control register R20 high impedance control register - - - - - R32 high impedance control register R31 high impedance control register R30 high impedance control register - - - - - R42 high impedance control register R41 high impedance control register R40 high impedance control register EPSON 1 0 High impedance Complementary High impedance Complementary High impedance Complementary - - - - - - - - - - High impedance Complementary - - - - - - - - - - High impedance Complementary Init 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 R/W Comment R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - - R/W R/W R/W - "0" when being read - - - - R/W R/W R/W S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(v) I/O Memory map (00FFD5H-00FFD9H) Address Bit 00FFD5 D7 D6 D5 D4 D3 D2 D1 D0 00FFD6 D7 D6 D5 D4 D3 D2 D1 D0 00FFD7 D7 D6 D5 D4 D3 D2 D1 D0 00FFD8 D7 D6 D5 D4 D3 D2 D1 D0 00FFD9 D7 D6 D5 D4 D3 D2 D1 D0 Name R07D R06D R05D R04D R03D R02D R01D R00D R17D R16D R15D R14D R13D R12D R11D R10D R27D R26D R25D R24D R23D R22D R21D R20D - - - - - R32D R31D R30D - - - - - R42D R41D R40D Function R07 output port data register R06 output port data register R05 output port data register R04 output port data register R03 output port data register R02 output port data register R01 output port data register R00 output port data register R17 output port data register R16 output port data register R15 output port data register R14 output port data register R13 output port data register R12 output port data register R11 output port data register R10 output port data register R27 output port data register R26 output port data register R25 output port data register R24 output port data register R23 output port data register R22 output port data register R21 output port data register R20 output port data register - - - - - R32 output port data register R31 output port data register R30 output port data register - - - - - R42 output port data register R41 output port data register R40 output port data register S1C88409 TECHNICAL MANUAL EPSON 1 0 High Low High Low High Low - - - - - - - - - - High Low - - - - - - - - - - High Low Init 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 R/W Comment R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - - R/W R/W R/W - "0" when being read - - - - R/W R/W R/W 43 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(w) I/O Memory map (00FFE0H-00FFE6H) Address Bit 00FFE0 D7 D6 D5 D4 D3 D2 D1 D0 00FFE1 D7 D6 D5 D4 D3 D2 D1 D0 00FFE2 D7 D6 D5 D4 D3 D2 D1 D0 00FFE3 D7 D6 D5 D4 D3 D2 D1 D0 00FFE4 D7 D6 D5 D4 D3 D2 D1 D0 00FFE5 D7 D6 D5 D4 D3 D2 D1 D0 00FFE6 D7 D6 D5 D4 D3 D2 D1 D0 Name IOC07 IOC06 IOC05 IOC04 IOC03 IOC02 IOC01 IOC00 IOC17 IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 - - - - IOC23 IOC22 IOC21 IOC20 IOC37 IOC36 IOC35 IOC34 IOC33 IOC32 IOC31 IOC30 P07D P06D P05D P04D P03D P02D P01D P00D P17D P16D P15D P14D P13D P12D P11D P10D - - - - P23D P22D P21D P20D Function P07 I/O control register P06 I/O control register P05 I/O control register P04 I/O control register P03 I/O control register P02 I/O control register P01 I/O control register P00 I/O control register P17 I/O control register P16 I/O control register P15 I/O control register P14 I/O control register P13 I/O control register P12 I/O control register P11 I/O control register P10 I/O control register - - - - P23 I/O control register P22 I/O control register P21 I/O control register P20 I/O control register P37 I/O control register P36 I/O control register P35 I/O control register P34 I/O control register P33 I/O control register P32 I/O control register P31 I/O control register P30 I/O control register P07 I/O port data register P06 I/O port data register P05 I/O port data register P04 I/O port data register P03 I/O port data register P02 I/O port data register P01 I/O port data register P00 I/O port data register P17 I/O port data register P16 I/O port data register P15 I/O port data register P14 I/O port data register P13 I/O port data register P12 I/O port data register P11 I/O port data register P10 I/O port data register - - - - P23 I/O port data register P22 I/O port data register P21 I/O port data register P20 I/O port data register 1 0 Output Input Output Input - - - - - - - - Output Input Output Input High Low High Low - - - - - - - - High Low Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 R/W Comment R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - R/W R/W R/W R/W Note: At initial reset, the data registers at addresses "00FFE4H", "00FFE5H" and "00FFE6H" are set to "1". 44 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map) Table 5.1.1(x) I/O Memory map (00FFE7H-00FFE9H) Address Bit 00FFE7 D7 D6 D5 D4 D3 D2 D1 D0 00FFE8 D7 D6 D5 D4 D3 D2 D1 D0 00FFE9 D7 D6 D5 D4 D3 D2 D1 D0 Name P37D P36D P35D P34D P33D P32D P31D P30D PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 PDA7 PDA6 - - - - - - Function P37 I/O port data register P36 I/O port data register P35 I/O port data register P34 I/O port data register P33 I/O port data register P32 I/O port data register P31 I/O port data register P30 I/O port data register P37 A/D converter input control P36 A/D converter input control P35 A/D converter input control P34 A/D converter input control P33 A/D converter input control P32 A/D converter input control P31 A/D converter input control P30 A/D converter input control P37 D/A converter output control P36 D/A converter output control - - - - - - 1 0 High Low A/D converter input I/O port D/A converter output - - - - - - I/O port - - - - - - Init 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 - - - - - - R/W Comment R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - - - Note: At initial reset, the data register at address "00FFE7H" is set to "1". S1C88409 TECHNICAL MANUAL EPSON 45 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (System Controller and Bus Control) 5.2 System Controller and Bus Control At initial reset, the bus mode is set as follows: The system controller is a control unit which sets the bus mode according to the system configuration such as the external memory. The software can set the following items to control the system. At initial reset, the S1C88409 is set in the single chip mode. Accordingly, the system is activated by the program written to the internal ROM in the MCU mode even if the external memory has been expanded. When the external memory has been expanded, set the corresponding bus mode with the initial routine written in the internal ROM. MCU mode: (1) Bus mode (CPU mode) (2) Chip enable (CE) signal output (3) WAIT state for external memory The following explains the settings. MPU mode: The S1C88409 has four bus modes as shown in Section 3.5.2, "Bus mode". The bus mode should be set according to the capacity of the memory expanded. When the MPU mode is used, the expanded mode (expanded 64K mode, expanded 4M minimum mode or expanded 4M maximum mode) at initial reset, has to have been previously selected by the mask option. Set it according to the system configuration. The bus mode can be set by writing to the BSMD register (two bits) as shown in Table 5.2.1.1. The function of I/O terminals is set as shown in Table 5.2.1.2 depending on the mode selection. 5.2.1 Bus mode settings Table 5.2.1.1 Bus mode settings Setting value BSMD0 BSMD1 1 1 0 0 1 0 1 0 Configuration of external memory Bus mode Expanded 4M maximum mode Expanded 4M minimum mode ROM+RAM>64K bytes (Program>64K bytes) ROM+RAM>64K bytes (Program64K bytes) Expanded 64K mode Single chip mode (MCU) Optional setting of one of the expanded modes (MPU) ROM+RAM64K bytes None See above The single chip mode can be set only when the S1C88409 is used in the MCU mode. In the MPU mode, the single chip mode cannot be set since the MPU mode does not use the internal ROM. When using the S1C88409 in the MPU mode, it is necessary to select the bus mode at initial reset (and when the BSMD register is set to "0") by mask option from the three types of expanded modes: expanded 64K mode, expanded 4M minimum mode and expanded 4M maximum mode. Select the expanded 4M maximum mode, when the MPU mode is not used. 46 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (System Controller and Bus Control) Table 5.2.1.2 I/O terminal settings Terminal R00 R01 R02 Bus mode Single chip Expanded 64K Expanded 4M Output port R00 Output port R01 Address bus A0 Address bus A1 Output port R02 Address bus A2 R03 Output port R03 Address bus A3 R04 R05 Output port R04 Output port R05 Address bus A4 Address bus A5 R06 Output port R06 Address bus A6 R07 Output port R07 Output port R10 Address bus A7 Address bus A8 R10 R11 R12 R13 R14 R15 R16 R17 R20 Output port R11 Address bus A9 Output port R12 Output port R13 Output port R14 Address bus A10 Address bus A11 Address bus A12 Output port R15 Output port R16 Output port R17 Address bus A13 Address bus A14 Address bus A15 R21 R22 R23 R24 Output port R20 Output port R21 Address bus A16 Address bus A17 Output port R22 Output port R23 Output port R24 Address bus A18 Address bus A19 Address bus A20 Output port R25 Address bus A21 R25 R26 R27 Output port R26 RD signal Output port R27 P00 P01 I/O port P00 I/O port P01 WR signal Data bus D0 Data bus D1 P02 P03 P04 I/O port P02 I/O port P03 Data bus D2 Data bus D3 P05 P06 I/O port P04 I/O port P05 I/O port P06 Data bus D4 Data bus D5 Data bus D6 P07 I/O port P07 Data bus D7 S1C88409 TECHNICAL MANUAL EPSON 47 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (System Controller and Bus Control) 5.2.2 Address decoder (CE output) settings As explained in Section 3.6.4, the S1C88409 has a built-in address decoder that can output up to three chip enable signals (CE0-CE2) to external devices. The output terminals and output circuits for CE0- CE2 are shared with the output ports R30-R32. At initial reset, they are set as the CE terminals. Unused CE terminals can be set to generalpurpose output port terminals by writing "0" to the CE0-CE2 registers. Table 5.2.2.1 shows the address range assigned to the chip enable (CE) signals. External devices can be allocated to an area selected with an optional chip enable signal. It is not necessary to continue from a lower address of the memory space. However in the MPU mode, the program memory must be assigned to CE0. In the expanded 4M mode, the address range of each CE signal is fixed. In the expanded 64K mode, four address ranges can be selected using the CEMD register (two bits) according to the memory to be used. These signals are output only when the corresponding external memory area is accessed and are not output when the internal memory is accessed. Furthermore, when the CPU is in standby status (HALT, SLEEP), all the CE signals go HIGH to disable external memory access. Table 5.2.2.1 Address settings of CE0-CE2 (1) Expanded 64K mode + MCU mode CEMD1 CEMD0 Chip size CE0 CE1 CE2 1 1 - - - - 1 0 32KB 008000H-00EFFFH - - 0 1 16KB 007000H-00AFFFH 00B000H-00EFFFH - 0 0 8KB 008000H-009FFFH 00A000H-00BFFFH 00C000H-00DFFFH (2) Expanded 64K mode + MPU mode CEMD1 CEMD0 Chip size 1 1 64KB 1 0 32KB 0 1 16KB 0 0 8KB CE0 CE1 CE2 000000H-00EFFFH - - 000000H-007FFFH 008000H-00EFFFH - 000000H-003FFFH 004000H-007FFFH 008000H-00BFFFH 000000H-001FFFH 002000H-003FFFH 004000H-005FFFH (3) Expanded 4M minimum/maximum mode CE signal CE0 CE1 CE2 Address range MCU mode C00000H-FFFFFFH 400000H-7FFFFFH 800000H-BFFFFFH MPU mode 000000H-00EFFFH, 010000H-3FFFFFH 400000H-7FFFFFH 800000H-BFFFFFH 5.2.3 WAIT state settings In order to guarantee accessing of external low speed devices during high speed operation, the S1C88409 is equipped with a WAIT function that prolongs access time. The number of wait states to be inserted can be selected from four values by the WT register (two bits) as shown in Table 5.2.3.1. The WAIT states that are set with software are inserted between the bus cycle states T3 and T4. Note, however, that WAIT states cannot be inserted when an internal register or internal memory are being accessed and when the CPU operates with the OSC1 oscillation clock (see Section 5.4, "Oscillation Circuit"). 48 Consequently, WAIT state settings are invalid in the single chip mode. Table 5.2.3.1 Setting the number of WAIT states WT1 1 1 0 0 WT0 1 0 1 0 Number of inserted states 12 8 4 No wait The length of one state is 1/2 a cycle of the clock. Refer to Section 3.6.5, "WAIT control", for the timing chart for WAIT insertion. EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (System Controller and Bus Control) 5.2.4 I/O memory of system controller Table 5.2.4.1 shows the control bits for the system controller. Table 5.2.4.1 System controller control bits Address Bit 00FF00 D7 MCU mode D6 D5 D4 D3 D2 D1 D0 00FF00 D7 MPU mode D6 D5 D4 D3 D2 D1 D0 00FF01 D7 D6 D5 D4 D3 D2 D1 D0 Name Function BSMD1 Bus mode (CPU mode) selection BSMD1 BSMD0 Mode 1 1 4M(Maximum) BSMD0 1 0 4M(Minimum) 0 1 64K 0 0 Single chip CEMD1 Expanded 64K chip enable mode CEMD1 CEMD0 Mode 1 1 - CEMD0 1 0 32K(CE0) 0 1 16K(CE0, CE1) 0 0 8K(CE0-CE2) - - CE2 CE2(R32) CE signal output enable/disable CE1 CE1(R31) enable: CE signal output CE0 CE0(R30) disable: DC output (R3x) BSMD1 Bus mode (CPU mode) selection BSMD1 BSMD0 Mode 1 1 4M(Maximum) BSMD0 1 0 4M(Minimum) 0 1 64K 0 0 Option selection CEMD1 Expanded 64K chip enable mode CEMD1 CEMD0 Mode 1 1 64K(CE0) CEMD0 1 0 32K(CE0, CE1) 0 1 16K(CE0-CE2) 0 0 8K(CE0-CE2) - - CE2 CE2(R32) CE signal output enable/disable CE1 CE1(R31) enable: CE signal output CE0 CE0(R30) disable: DC output (R3x) - - - - WT1 Wait state control WT1 WT0 Number of states 1 1 12(3 cycles) WT0 1 0 8(2 cycles) 0 1 4(1 cycle) 0 0 No wait CLKCHG CPU operating clock switch OSCC OSC3 oscillation ON/OFF control VD1C1 VD1 output level setting VD1C1 VD1C0 VD1 (Typ.) 1 1 4.2 V 1 0 3.2 V VD1C0 0 1 1.6 V 0 0 2.4 V 1 0 Init R/W 0 R/W Comment 0 R/W 1 R/W Only for 64K bus mode 1 R/W - CE2 enable CE1 enable CE0 enable - CE2 disable CE1 disable CE0 disable - 1 1 1 - R/W R/W R/W R/W "0" when being read In the single chip mode, these setting are fixed at DC output Initial setting can be selected from 3 types (64K, 4M min, 4M R/W max) by mask option 1 R/W Only for 64K bus mode 1 R/W - CE2 enable CE1 enable CE0 enable - - - CE2 disable CE1 disable CE0 disable - - - 1 1 1 - - 0 - "0" when being read R/W R/W R/W - "0" when being read - R/W 0 R/W OSC3 On OSC1 Off 0 R/W 0 R/W 0 R/W 0 R/W Note: All the interrupts including NMI are masked until the appropriate values are written to both the "00FF00H" and "00FF01H" addresses. S1C88409 TECHNICAL MANUAL EPSON 49 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (System Controller and Bus Control) BSMD0, BSMD1: Bus mode selection register (00FF00H*D6, D7) Sets the bus mode as shown in Table 5.2.4.2. Table 5.2.4.3 CE signal settings CEMD1 CEMD0 Table 5.2.4.2 Bus mode settings Setting value BSMD1 BSMD0 Bus mode 1 1 Expanded 4M maximum mode 1 0 0 1 Expanded 4M minimum mode 0 0 Address Usable terminals MCU mode MPU mode range 1 1 64K bytes Invalid CE0 1 0 0 1 32K bytes 16K bytes CE0 CE0, CE1 0 0 8K bytes CE0, CE1 CE0-CE2 CE0-CE2 CE0-CE2 This setting is invalid for modes other than the expanded 64K mode. At initial reset, the CEMD register is set to "11B". However, since "11B" is invalid in the MCU mode, set it to another value. Expanded 64K mode Single chip mode (MCU) Optional setting of one of the expanded mode (MPU) The single chip mode can be set only when the S1C88409 is used in the MCU mode. When using the external MPU interface, only the single chip mode can be set. CE0-CE2: CE signal output enable register (00FF00H*D0-D2) Sets the CE output terminals to be used. When "1" is written: CE output enabled When "0" is written: CE output disabled Reading: Valid In the MPU mode, the single chip mode cannot be set since the MPU mode does not use the internal ROM. When using the S1C88409 in the MPU mode, it is necessary to select the bus mode set at initial reset (and when the BSMD register is set to "0") by mask option from the three types of expanded modes: expanded 64K mode, expanded 4M minimum mode and expanded 4M maximum mode. Select the expanded 4M maximum mode, when the MPU mode is not used. At initial reset, the BSMD register is set to "0" (single chip mode in the MCU mode or an expanded mode selected by mask option in the MPU mode). Writing "1" to the CE0-CE2 register enables the corresponding CE signal to output. Writing "0" to the register disables the CE signal to output, and the terminal functions as the output port (R30-R32). At initial reset, the CE registers are all set to "1". WT0, WT1: WAIT state control register (00FF01H*D4, D5) Controls the WAIT state insertion. Table 5.2.4.4 shows the register setting and the number of WAIT states inserted. Table 5.2.4.4 WAIT state settings Note: After initial reset, all the interrupts including NMI are masked until the appropriate values are written to the I/O memory addresses "00FF00H" and "00FF01H" to prevent malfunctions that may occur before setting the system configuration. Therefore, write data to the addresses in the initial routine even though operating the S1C88409 in the initial settings (single chip mode). Furthermore, set the stack pointer SP prior to writing so that interrupt processing will operate normally. CEMD0, CEMD1: Expanded 64K chip enable mode selection register (00FF00H*D4, D5) Sets the CE signal address range (valid only in the expanded 64K mode). Set this register according to the external memory chip size as shown in Table 5.2.4.3. 50 WT1 1 1 0 0 WT0 1 0 1 0 Number of inserted states 12 8 4 No wait The length of one state is 1/2 a cycle of the clock. At initial reset, the WT register is set to "0" (no wait). 5.2.5 Programming note After initial reset, all the interrupts including NMI are masked until the appropriate values are written to the I/O memory addresses "00FF00H" and "00FF01H" to prevent malfunctions that may occur before setting the system configuration. Therefore, write data to the addresses in the initial routine even though the initial settings are used. Furthermore, set the stack pointer SP prior to writing so that interrupt processing will operate normally. EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer) 5.3 Watchdog Timer 5.3.1 Configuration of watchdog timer The S1C88409 has a built-in watchdog timer that detects CPU runaway. fOSC1 OSC1 oscillation circuit 1/16 divider fOSC3 OSC3 oscillation circuit 1/16 divider Overflow Clock selector Watchdog timer (12 bits) WDCL WDRST Non-maskable interrupt (NMI) EWD Fig. 5.3.1.1 Block diagram of watchdog timer The watchdog timer is composed of a 12-bit upcounter that uses the OSC1 or OSC3 oscillation circuit as a clock source. This counter must be reset cyclically by software. If the counter is not reset and an overflow occurs, the watchdog timer generates NMI (non-maskable interrupt) to the CPU. Figure 5.3.1.1 is a block diagram of the watchdog timer. 5.3.2 Control of watchdog timer (1) HALT status The OSC1 oscillation circuit and the OSC3 oscillation circuit operate in HALT status. Therefore, the watchdog timer also operates. The watchdog timer generates NMI when HALT status continues more than a reset cycle. HALT status is released at that point. The input clock of the watchdog timer can be selected using the input clock selection register WDCL from the two listed below. WDCL = "1": 1/16 OSC1 dividing clock WDCL = "0": 1/16 OSC3 dividing clock At initial reset, the input clock is set to fOSC1/16. The following shows an example of a watchdog timer reset cycle according to the input clock selected. within 2 sec within 64 msec within 10 msec within 8 msec The WDCL register is set to write disabling status usually to prevent modification of the reset cycle by a wrong writing. To change the input clock, it is necessary to set the WDCL register in write authorized status by writing "1" to the write enable register WRWD beforehand. The write authorization by the WRWD register enables only one write for the WDCL register. When data is written to the WDCL register after setting in write authorization, the WRWD register returns to "0", and the WDCL register is also returned to write disabling status. S1C88409 TECHNICAL MANUAL When the watchdog timer is used, it is necessary to reset the counter before an overflow is generated. The watchdog timer is reset by writing "1" to the watchdog timer reset bit WDRST. By resetting the watchdog timer on the main routine, program runaway that does not pass the reset routine can be detected. Ordinarily this routine is incorporated to a place where it is executed regularly. Operation in HALT/SLEEP status Input clock selection When fOSC1/16 is selected: fOSC1 = 32.768 kHz When fOSC3/16 is selected: fOSC3 = 1 MHz fOSC3 = 6 MHz fOSC3 = 8 MHz Resetting the watchdog timer (2) SLEEP status The OSC1 oscillation circuit and the OSC3 oscillation circuit stop in SLEEP status. Therefore, the watchdog timer also stops. Since the counter maintains the value at the point it stops, the counter resumes counting from the value after SLEEP status is canceled. However, the oscillation clock becomes unstable immediately after SLEEP is canceled. Therefore, reset the watchdog timer before shifting to SLEEP status and after SLEEP status is canceled so that an unnecessary NMI will not be generated. EPSON 51 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer) When watchdog timer is not used 5.3.3 Interrupt function The watchdog timer always operates unless the oscillation circuit specified for the input clock stops. If monitoring the system by the watchdog timer is unnecessary, it is possible to disable the watchdog timer interrupt (NMI) by writing "0" to the watchdog timer enable register EWD. At initial reset, the watchdog timer starts counting by inputting the fOSC1/16 clock and is set to generate NMI. When the watchdog timer is not used, write "0" to the EWD register before the first overflow is generated. When the watchdog timer is not reset cyclically by software, the watchdog timer outputs an interrupt signal to the NMI (level 4) input of the core CPU. This interrupt cannot be masked and the exception processing has priority over other interrupts. Refer to the "S1C88 Core CPU Manual" for details of the NMI exception processing. This exception processing vector address is set to 000004H. The EWD register is set to write disabling status same as the WDCL register. Set it in write authorized status using the WRWD register before writing to the EWD register. In this case, only one write is enabled for the EWD register. When the EWD register is set to "0", this interrupt is not generated. 5.3.4 I/O memory of watchdog timer Table 5.3.4.1 shows the control bits for the watchdog timer. Table 5.3.4.1 Watchdog timer control bits Address Bit Name Function 1 0 Init R/W Comment 00FF53 D7 WRWD EWD, WDCL write enable Write enable Write disable 0 R/W 1 D6 EWD Watchdog timer NMI enable NMI enable NMI disable 1 R/W 1 D5 WDCL Watchdog timer input clock selection fOSC3/16 fOSC1/16 0 R/W 1 - - D4 - - - - "0" when being read - - D3 - - - - - - D2 - - - - - - D1 - - - - Reset Invalid D0 WDRST Watchdog timer reset - W 1 Writing to EWD or WDCL is valid after "1" is written to WRWD. WRWD is automatically returns to "0" after writing to EWD or WDCL. EWD: NMI enable register (00FF53H*D6) Controls non-maskable interrupt (NMI) generation by watchdog timer. WRWD: EWD, WDCL write enable register (00FF53H*D7) Enables writing to the EWD and WDCL register. When "1" is written: Write is enabled When "0" is written: Write is disabled Reading: Valid The EWD and WDCL registers are set to write disabling status usually to prevent unnecessary modification. When "1" is written to the WRWD register, only one write is permitted. When data is written to either the EWD or WDCL registers or both, the WRWD register returns to "0", and the EWD and WDCL registers go to write disabling status. Writing "0" to the WRWD register during a write authorized state (WRWD="1") also returns to write disabling status. At initial reset, the WRWD register is set to "0" (write is disabled). 52 When "1" is written: NMI is valid When "0" is written: NMI is invalid Reading: Valid When "0" is written to the EWD register, the watchdog timer interrupt signal is masked and NMI is not generated to the CPU. When the EWD register is set to "1", NMI is generated due to an overflow of the counter. Writing to the EWD register is effective only when the WRWD register is set to "1". The count operation is continued even when the EWD register is set to "0" if the clock is input. Therefore, when NMI is invalidated temporarily, reset the watchdog timer before changing back the EWD register to "1". At initial reset, the EWD register is set to "1" (NMI is valid). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer) 5.3.5 Programming notes WDCL: Input clock selection register (00FF53H*D5) Selects the input clock for the watchdog timer. (1) When the watchdog timer NMI is authorized, it is necessary to reset the counter by software before an overflow is generated. When "1" is written: fOSC3/16 When "0" is written: fOSC1/16 Reading: Valid When "1" is written to the WDCL register, fOSC3/16 clock is input to the watchdog timer as the count clock. When "0" is written, fOSC1/16 clock is input. When fOSC3/16 clock is used, the watchdog timer stops if the OSC3 oscillation circuit stops (including SLEEP). In this case, the counter value at stop is maintained. Writing to the WDCL register is effective only when the WRWD register is set to "1". At initial reset, the WDCL register is set to "0" (fOSC1/16). WDRST: Watchdog timer reset (00FF53H*D0) Resets the watchdog timer. (2) At initial reset, the watchdog timer starts counting by inputting the fOSC1/16 clock and is set to generate NMI. When the watchdog timer is not used, write "0" to the EWD register before the first overflow is generated. (3) The count operation is continued even when the EWD register is set to "0" if the clock is input. Therefore, when NMI is invalidated temporarily, reset the watchdog timer before changing back the EWD register to "1". (4) The oscillation clock becomes unstable immediately after SLEEP is canceled. Therefore, reset the watchdog timer before shifting to SLEEP status and after SLEEP status is canceled so that an unnecessary NMI will not be generated. When "1" is written: Watchdog timer is reset When "0" is written: No operation Reading: Always "0" By writing "1" to WDRST, the watchdog timer is reset and restarts immediately after. When "0" is written, no operation results. WDRST is dedicated for writing, and is always "0" for reading. S1C88409 TECHNICAL MANUAL EPSON 53 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 5.4 Oscillation Circuit 5.4.1 Configuration of oscillation circuit The S1C88409 has been designed as a twin clock system with two internal oscillation circuits (OSC1 and OSC3). The OSC1 oscillation circuit generates the 32.768 kHz (Typ.) operating clock, and the OSC3 oscillation circuit generates the high-speed clock for the CPU and the peripheral circuits (serial interface, programmable timer, A/D converter, etc.). Figure 5.4.1.1 shows the configuration of the oscillation circuit. To peripheral circuit (fOSC1) OSC1 oscillation circuit Clock switch OSC3 oscillation circuit SLEEP status To peripheral circuit (fOSC3) Oscillation circuit control circuit OSCC To CPU (CLK) CPU clock selection circuit Either "Crystal oscillation", "Ceramic oscillation", "CR oscillation" or "External clock input" can be selected as a kind of OSC3 oscillation circuit same as the OSC1. 5.4.3 OSC1 oscillation circuit The OSC1 oscillation circuit generates the 32.768 kHz (Typ.) system clock. The OSC1 oscillation clock is used for the low-speed (low power) operation clock of the CPU. Furthermore, it is used as the source clock for the clock timer and watchdog timer even when OSC3 is used as the system clock. The OSC1 oscillation circuit stops when the SLP instruction is executed. Either "Crystal oscillation", "CR oscillation", "Crystal oscillation (gate capacitor built-in)" or "External clock input" can be selected by mask option as a kind of OSC1 oscillation circuit. Figure 5.4.3.1 shows the structure of the OSC1 oscillation circuit. SLEEP status CLKCHG OSC1 Fig. 5.4.1.1 Configuration of oscillation circuit fOSC1 CG1 X'tal1 At initial reset, the OSC1 oscillation clock is selected for the CPU operating clock. Turning the OSC3 oscillation circuit on/off and switching the system clock (OSC1OSC3) can be controlled by software. The OSC3 oscillation circuit is used when the CPU and the peripheral circuits require high-speed operation. When the CPU has to handle low-speed operation (e.g. clock control), stop the OSC3 oscillation and use OSC1 as the operating clock to reduce current consumption. OSC2 VSS VSS (1) Crystal oscillation circuit OSC1 fOSC1 OSC2 SLEEP status (2) CR oscillation circuit 5.4.2 Mask option SLEEP status VDD VSS OSC1 oscillation circuit Crystal oscillation circuit CR oscillation circuit External clock input Crystal oscillation circuit (gate capacitor built-in) OSC3 oscillation circuit Crystal oscillation circuit Ceramic oscillation circuit CR oscillation circuit External clock input Either "Crystal oscillation", "CR oscillation", "Crystal oscillation (gate capacitor built-in)" or "External clock input" can be selected by mask option as a kind of OSC1 oscillation circuit. 54 OSC1 fOSC1 External clock N.C. VSS OSC2 (3) External clock input SLEEP status OSC1 X'tal1 OSC2 fOSC1 VSS VSS (4) Crystal oscillation circuit (gate capacitor built-in) Fig. 5.4.3.1 OSC1 oscillation circuit EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) When crystal oscillation is selected, the crystal oscillation circuit can be configured simply by connecting a crystal oscillator X'tal1 (Typ. 32.768 kHz) between the OSC1 and OSC2 terminals and a trimmer capacitor CG1 (5-25pF) between the OSC1 terminal and VSS. For the CG1, the built-in capacitor can also be selected by mask option. When CR oscillation is selected, the CR oscillation circuit can be configured by connecting a resistor between the OSC1 and OSC2 terminals. When external clock input is selected, open the OSC2 terminal and input a square wave clock to the OSC1 terminal. 5.4.4 OSC3 oscillation circuit The OSC3 oscillation circuit generates the system clock for the CPU and peripheral circuits (serial interface, programmable timer, A/D converter, etc.). The OSC3 oscillation circuit stops when the SLP instruction is executed, or the OSCC register is set to "0". Either "Crystal oscillation", "Ceramic oscillation", "CR oscillation" or "External clock input" can be selected by mask option as a kind of OSC3 oscillation circuit. Figure 5.4.4.1 shows the structure of the OSC3 oscillation circuit. CG2 When crystal/ceramic oscillation circuit is selected, the crystal or ceramic oscillation circuit is configured by connecting either a crystal oscillator (X'tal2) or a ceramic oscillator (Ceramic) and a feedback resistor (Rf) between the OSC3 and OSC4 terminals and two capacitors (CG2, CD2) between the OSC3 terminal and VSS, and between the OSC4 terminal and VSS, respectively. When CR oscillation is selected, the CR oscillation circuit can be configured by connecting a resistor (RCR3) between the OSC3 and OSC4 terminals. When external clock input is selected, open the OSC4 terminal and input a square wave clock to the OSC3 terminal. When the OSC3 oscillation circuit is not used, select external clock input by mask option, and pull down the OSC3 terminal to VSS. The maximum frequency of the clock, which can be generated by the OSC3 oscillation circuit or can be input to the OSC3 oscillation circuit, is limited depending on the supply voltage as shown in Table 5.4.4.1. Table 5.4.4.1 Limit of OSC3 clock frequency depending on supply voltage Operable voltage range (VDD) 1.8 V-5.5 V Max. operable frequency 1.1 MHz 2.6 V-5.5 V 3.5 V-5.5 V 4.5 V-5.5 V 4.4 MHz 6.6 MHz 8.8 MHz OSC3 CD2 VSS fOSC3 X'tal2 or Ceramic Rf OSC4 Oscillation circuit control signal SLEEP status (1) Crystal/Ceramic oscillation circuit OSC3 fOSC3 RCR3 Oscillation circuit control signal SLEEP status OSC4 (2) CR oscillation circuit VDD VSS OSC3 fOSC3 External clock N.C. OSC4 Oscillation circuit control signal SLEEP status (3) External clock input Fig. 5.4.4.1 OSC3 oscillation circuit S1C88409 TECHNICAL MANUAL EPSON 55 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 5.4.5 Switching of CPU clock and operating voltage VD1 * The VD1 voltage required at least 5 msec of voltage stabilizing time after switching. Do not turn the OSC3 oscillation circuit on during this period. The OSC3 oscillation circuit can be turned on and off. It should be turned on when operating peripheral circuit (serial interface, programmable timer, A/D converter, etc.) that needs a high-speed clock. Further, the CPU operating clock can be switched from OSC1 to OSC3 to execute the program in high-speed. In the S1C88409, the internal operating voltage VD1 can also be switched by software for stable operation in large supply voltage and operating frequency ranges and for saving power. * VD1 cannot be switched directly to a level that is two or three levels different from the current level. The middle level must be set between switching. To switch from 1,6 (3.2) V to 3.2 (1.6) V: 1.6 V 2.4 V 3.2 V 1.6 V 2.4 V 3.2 V To switch from 1.6 (4.2) V to 4.2 (1.6) V: 1.6 V 2.4 V 3.2 V 4.2 V 1.6 V 2.4 V 3.2 V 4.2 V To switch from 2.4 (4.2) V to 4.2 (2.4) V: 2.4 V 3.2 V 4.2 V 2.4 V 3.2 V 4.2 V A 5 msec interval is required for each switching step. Switching operating voltage VD1 When operating the OSC3 oscillation circuit, it is necessary to switch the internal operating voltage VD1 according to the oscillation frequency. Table 5.4.5.1 shows the relation between the supply voltage to be used, oscillation frequency and the internal operating voltage VD1 that should be set. Table 5.4.5.1 Oscillation frequency and internal operating voltage VD1 OSC3 OSC3 oscillator frequency OFF ON Supply VD1 voltage 1.6 V 2.4 V 3.2 V 4.2 V 1.8-5.5 V 0.03-1.1 MHz 1.8-5.5 V 0.03-4.4 MHz 2.6-5.5 V 0.03-6.6 MHz 3.5-5.5 V 0.03-8.8 MHz 4.5-5.5 V x x x x x x x VD1 is switched with the VD1 level setting register VD1C. Table 5.4.5.2 VD1 settings VD1C0 Operating voltage VD1 4.2 V 1 0 3.2 V 1 1.6 V 0 2.4 V At initial reset, VD1 is set to 2.4 V (Typ.). VD1 should be switched to 1.6 V (Typ.) when using an OSC3 clock lower than 1.1 MHz or the OSC3 oscillation is stopped. Note: * The VD1 level must be switched while the OSC3 oscillation circuit is off (before turning on and after turning off). Switching during operation may cause malfunction. 56 The OSC3 oscillation circuit can be turned on and off using the OSCC register. It is necessary to switch the VD1 voltage. The switching procedure is as follows. The following procedures are described assuming the VD1 has been set to 1.6 V before turning the OSC3 oscillation on. [OSC3 on sequence] * OSC3 = 0.03 MHz-1.1 MHz 1. Write "1" to the OSCC register. (turning the OSC3 oscillation circuit on) 2. Wait at least 20 msec. Operation with OSC1 clock Can be set Can be set (However, it increases current consumption) Cannot be set VD1C1 1 1 0 0 Turning the OSC3 oscillation circuit on and off * OSC3 = 0.03 MHz-4.4 MHz 1. Write "00B" to the VD1C register. (VD1 = 2.4 V) 2. Wait at least 5 msec. 3. Write "1" to the OSCC register. (turning the OSC3 oscillation circuit on) 4. Wait at least 20 msec. * OSC3 = 0.03 MHz-6.6 MHz 1. Write "00B" to the VD1C register. (VD1 = 2.4 V) 2. Wait at least 5 msec. 3. Write "10B" to the VD1C register. (VD1 = 3.2 V) 4. Wait at least 5 msec. 5. Write "1" to the OSCC register. (turning the OSC3 oscillation circuit on) 6. Wait at least 20 msec. EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) * OSC3 = 0.03 MHz-8.8 MHz 1. Write "00B" to the VD1C register. (VD1 = 2.4 V) 2. Wait at least 5 msec. 3. Write "10B" to the VD1C register. (VD1 = 3.2 V) 4. Wait at least 5 msec. 5. Write "11B" to the VD1C register. (VD1 = 4.2 V) 6. Wait at least 5 msec. 7. Write "1" to the OSCC register. (turning the OSC3 oscillation circuit on) 8. Wait at least 20 msec. Note: * The OSC3 oscillation circuit takes a maximum 20 msec for stabilizing oscillation after turning the OSC3 oscillation circuit on. Therefore, take an enough interval after the OSC3 oscillation goes on before starting control of the peripheral circuit, such as the programmable timer, serial interface and A/D converter, that uses the OSC3 oscillation circuit as the clock source. (The oscillation start time varies depending on the oscillator and external component to be used. Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS", in which an example of oscillation start time is indicated.) * Do not turn the OSC3 oscillation circuit on to reduce current consumption when the OSC3 clock is not necessary. [OSC3 off sequence] * OSC3 = 0.03 MHz-1.1 MHz 1. Write "0" to the OSCC register. (turning the OSC3 oscillation circuit off) * OSC3 = 0.03 MHz-4.4 MHz 1. Write "0" to the OSCC register. (turning the OSC3 oscillation circuit off) 2. Write "01B" to the VD1C register. (VD1 = 1.6 V) * OSC3 = 0.03 MHz-6.6 MHz 1. Write "0" to the OSCC register. (turning the OSC3 oscillation circuit off) 2. Write "00B" to the VD1C register. (VD1 = 2.4 V) 3. Wait at least 5 msec. 4. Write "01B" to the VD1C register. (VD1 = 1.6 V) Note: To prevent malfunction, before stopping the OSC3 oscillation, stop the operation of the peripheral circuits that use the OSC3 oscillation circuit as the clock source, such as programmable timer, serial interface and A/D converter. Furthermore, when turning the OSC3 oscillation circuit off, make sure that the CPU operating clock is OSC1. Switching the CPU operating clock from OSC1 to OSC3 When operating the CPU in high speed, the CPU operating clock should be switched from the OSC1 clock to the OSC3 clock using the CLKCHG register. The switching procedure is as follows: 1. Execute the OSC3 on sequence as described above. 2. Write "1" to the CLKCHG register. (OSC1 OSC3) Note: Be sure to wait 20 msec or more for oscillation stabilizing time between turning the OSC3 oscillation circuit on and switching the CPU operating clock. Switching the CPU operating clock from OSC3 to OSC1 When the CPU has to handle low-speed operation (e.g. clock control), the OSC3 oscillation can be stopped and OSC1 can be used as the operating clock to reduce current consumption. The switching procedure is as follows: 1. Write "0" to the CLKCHG register. (OSC3 OSC1) 2. Execute the OSC3 off sequence described above. Note: Use a separate instruction for switching the clock from OSC3 to OSC1 and turning the OSC3 oscillation off. Handling with one instruction may cause malfunction of the CPU. * OSC3 = 0.03 MHz-8.8 MHz 1. Write "0" to the OSCC register. (turning the OSC3 oscillation circuit off) 2. Write "10B" to the VD1C register. (VD1 = 3.2 V) 3. Wait at least 5 msec. 4. Write "00B" to the VD1C register. (VD1 = 2.4 V) 5. Wait at least 5 msec. 6. Write "01B" to the VD1C register. (VD1 = 1.6 V) S1C88409 TECHNICAL MANUAL EPSON 57 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 5.4.6 I/O memory of oscillation circuit Table 5.4.6.1 shows the control bits for the oscillation circuit. Table 5.4.6.1 Oscillation circuit control bits Address Bit 00FF01 D7 D6 D5 Name - - WT1 Function - - 1 - - Wait state control WT1 WT0 Number of states 1 1 12(3 cycles) 1 0 8(2 cycles) D4 WT0 0 1 4(1 cycle) 0 0 No wait D3 CLKCHG CPU operating clock switch D2 OSCC OSC3 oscillation ON/OFF control D1 VD1C1 VD1 output level setting VD1C1 VD1C0 VD1 (Typ.) 1 1 4.2 V 1 0 3.2 V D0 VD1C0 0 1 1.6 V 0 0 2.4 V OSC3 On 1 1 0 0 1 0 1 0 0 R/W 0 R/W 0 R/W OSCC: OSC3 oscillation control register (00FF01H*D2) Turns the OSC3 oscillation circuit on and off. When "1" is written: OSC3 oscillation ON When "0" is written: OSC3 oscillation OFF Reading: Valid OSC3 oscillation ON (0.03-8.8 MHz) ON (0.03-6.6 MHz) ON (0.03-1.1 MHz) or OFF ON (0.03-4.4 MHz) The VD1 level should be switched according to the operation of the OSC3 oscillation circuit. The OSC3 oscillation circuit must be off when switching the VD1 voltage. VD1 cannot be switched directly to a level that is two or three levels different from the current level. The middle level must be set between switching. To switch from 1,6 (3.2) V to 3.2 (1.6) V: 1.6 V 2.4 V 3.2 V 1.6 V 2.4 V 3.2 V To switch from 1.6 (4.2) V to 4.2 (1.6) V: 1.6 V 2.4 V 3.2 V 4.2 V 1.6 V 2.4 V 3.2 V 4.2 V To switch from 2.4 (4.2) V to 4.2 (2.4) V: 2.4 V 3.2 V 4.2 V 2.4 V 3.2 V 4.2 V A 5 msec interval is required for each switching step. At initial reset, the VD1C register is set to "0" (2.4 V, Typ.). 58 OSC1 Off 0 R/W Table 5.4.6.2 VD1 settings Operating voltage VD1 4.2 V 3.2 V 1.6 V 2.4 V Init R/W Comment - - "0" when being read - - 0 R/W 0 R/W VD1C0, VD1C1: VD1 output level setting register (00FF01H* D0, D1) Selects the VD1 level. VD1C1 VD1C0 0 - - When it is necessary to operate the CPU and peripheral circuits (serial interface, programmable timer, A/D converter, etc.) at high-speed, write "1" to the OSCC register. At other times, set it to "0" to reduce current consumption. At initial reset, the OSCC register is set to "0" (OSC3 oscillation OFF). CLKCHG: CPU operating clock switching register (00FF01H*D3) Selects the operating clock for the CPU. When "1" is written: OSC3 clock When "0" is written: OSC1 clock Reading: Valid When the CPU operating clock is to be OSC3, write "1" to the CLKCHG register; for OSC1, write "0". The OSC3 oscillation circuit takes a maximum 20 msec to stabilize oscillation after turning the OSC3 oscillation circuit on. Therefore, switching the system clock should be done after the stabilization time has passed. At initial reset, the CLKCHG register is set to "0" (OSC1 clock). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 5.4.7 Programming notes (1) The VD1 level must be switched while the OSC3 oscillation circuit is off (before turning on and after turning off). Switching during operation may cause malfunction. Furthermore, the VD1 voltage required at least 5 msec of voltage stabilizing time after switching. Do not turn the OSC3 oscillation circuit on during this period. (2) VD1 cannot be switched directly to a level that is two or three levels different from the current level. The middle level must be set between switching. To switch from 1,6 (3.2) V to 3.2 (1.6) V: 1.6 V 2.4 V 3.2 V 1.6 V 2.4 V 3.2 V To switch from 1.6 (4.2) V to 4.2 (1.6) V: 1.6 V 2.4 V 3.2 V 4.2 V 1.6 V 2.4 V 3.2 V 4.2 V To switch from 2.4 (4.2) V to 4.2 (2.4) V: 2.4 V 3.2 V 4.2 V 2.4 V 3.2 V 4.2 V A 5 msec interval is required for each switching step. (5) Use a separate instruction for switching the clock from OSC3 to OSC1 and turning the OSC3 oscillation off. Handling with one instruction may cause malfunction of the CPU. (6) To prevent malfunction, before stopping the OSC3 oscillation, stop the operation of the peripheral circuits that use the OSC3 oscillation circuit as the clock source, such as programmable timer, serial interface and A/D converter. (7) Do not turn the OSC3 oscillation circuit on to reduce current consumption when the OSC3 clock is not necessary. (3) To generate VD1 with specified voltage, the supply voltage must be higher than the specified voltage. To prevent malfunction, make sure that the supply voltage is not lowered under the VD1 value to be set using the SVD circuit before switching VD1. Do not switch VD1 to a voltage higher than the supply voltage if the supply voltage drops. (4) The OSC3 oscillation circuit takes a maximum 20 msec for stabilizing oscillation after turning the OSC3 oscillation circuit on. Therefore, take an enough interval after the OSC3 oscillation goes on before starting control of the peripheral circuit, such as the programmable timer, serial interface and A/D converter, that uses the OSC3 oscillation circuit as the clock source. (The oscillation start time varies depending on the oscillator and external component to be used. Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS", in which an example of oscillation start time is indicated.) S1C88409 TECHNICAL MANUAL EPSON 59 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Prescaler and Clock Control Circuit) 5.5 Prescaler and Clock Control Circuit for Peripheral Circuits 5.5.1 Configuration of prescaler The S1C88409 has a prescaler that generates the clocks for the internal peripheral circuit by dividing the output clock of the OSC1 oscillation circuit and OSC3 oscillation circuit. The division ratio of the prescaler can be selected individually for each peripheral circuit by software. Furthermore, the clock control circuit is provided to control clock supply to each peripheral circuit. The peripheral circuits which use the output clock are as follows: * 16-bit programmable timer 0 * 16-bit programmable timer 1 * 8-bit programmable timer * Clock output (FOUT1, FOUT3) * A/D converter * Touch panel controller Figure 5.5.1.1 shows the configuration of the prescaler. For control of each peripheral circuit, refer to respective section. fOSC1 1/1 1/2 1/4 1/8 Selector & ON/OFF control 5.5.2 Setting of source clock The prescaler uses the OSC1 clock and OSC3 clock as the source clocks. The OSC1 prescaler always operates except for SLEEP status. When using an output clock from the OSC3 prescaler, it is necessary to turn the OSC3 oscillation circuit on. Refer to Section 5.4.5, "Switching of CPU clock and operating voltage VD1" for control of the OSC3 oscillation circuit and switching of the CPU operating clock. At initial reset, the OSC3 oscillation circuit stops. The OSC3 oscillation circuit takes a maximum 20 msec for stabilizing oscillation after turning the OSC3 oscillation circuit on. Therefore, wait a long enough interval after the OSC3 oscillation goes on before turning the clock output of the OSC3 prescaler on. (The oscillation start time varies depending on the oscillator and external components to be used. Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS", in which an example of oscillation start time is indicated.) Among the peripheral circuits that use the clock output from the prescaler, the 16-bit programmable timer can select the clock source from either OSC1 or OSC3. Select the clock source before supplying the clock to the 16-bit programmable timer. * * * 1/128 FOUT1 Selector & ON/OFF control Selector & ON/OFF control EXCL00 (K10) Selector & ON/OFF control EXCL01 (K11) Selector & ON/OFF control 16-bit programmable timer 0 16-bit programmable timer 1 Selector & ON/OFF control fOSC3 1/1 8-bit programmable timer Selector & ON/OFF control A/D converter Selector & ON/OFF control Touch panel controller Selector & ON/OFF control FOUT3 1/2 1/4 1/8 * * * 1/4096 Fig. 5.5.1.1 Configuration of prescaler and clock control circuit 60 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Prescaler and Clock Control Circuit) 5.5.3 Prescaler division ratio selection and output control Table 5.5.3.4 Division ratio and control registers The prescaler has division ratio selection registers and clock output control registers for the peripheral circuits, so the division ratio and the clock output for each circuit can be controlled individually. The prescaler division ratio is selected by the division ratio selection register from 8 types set for each peripheral circuit. The dividing clock is output to the peripheral circuit by writing "1" to the clock output control register. The following shows the division ratio selection register and the clock output control register for each peripheral circuit. 16-bit programmable timer 1 (Clock source: OSC1) Selection register Division Output PST12 PST11 PST10 ratio control fOSC1/128 PRPRT1 1 1 1 1 1 0 register fOSC1/64 1 0 1 fOSC1/32 1 0 0 "1": ON fOSC1/16 "0": OFF 0 1 1 fOSC1/8 0 1 0 fOSC1/4 0 0 1 fOSC1/2 0 0 0 fOSC1/1 The source clock (OSC1, OSC3) is selected by the PRTF1 register. 8-bit programmable timer Table 5.5.3.5 Division ratio and control registers 8-bit programmable timer Selection register Division PST22 PST21 PST20 ratio 1 1 1 fOSC3/256 1 1 0 fOSC3/128 1 0 1 fOSC3/64 1 0 0 fOSC3/32 0 1 1 fOSC3/16 0 1 0 fOSC3/8 0 0 1 fOSC3/4 0 0 0 fOSC3/2 16-bit programmable timer 0 Table 5.5.3.1 Division ratio and control registers 16-bit programmable timer 0 (Clock source: OSC3) Selection register Division Output PST02 PST01 PST00 ratio control 1 1 1 fOSC3/4096 PRPRT0 1 1 0 fOSC3/1024 register 1 0 1 fOSC3/256 1 0 0 fOSC3/128 "1": ON 0 1 1 "0": OFF fOSC3/64 0 1 0 fOSC3/32 0 0 1 fOSC3/8 0 0 0 fOSC3/2 Output control PRPRT2 register "1": ON "0": OFF FOUT1/FOUT3 clock output Table 5.5.3.6 Division ratio and control registers Table 5.5.3.2 Division ratio and control registers FOUT1 clock Selection register PSF12 PSF11 PSF10 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 16-bit programmable timer 0 (Clock source: OSC1) Selection register Division Output PST02 PST01 PST00 ratio control 1 1 1 fOSC1/128 PRPRT0 1 1 0 fOSC1/64 register 1 0 1 fOSC1/32 1 0 0 "1": ON fOSC1/16 0 1 1 "0": OFF fOSC1/8 0 1 0 fOSC1/4 0 0 1 fOSC1/2 0 0 0 fOSC1/1 Output control PRFO1 register "1": ON "0": OFF Table 5.5.3.7 Division ratio and control registers The source clock (OSC1, OSC3) is selected by the PRTF0 register. FOUT3 clock Selection register PSF32 PSF31 PSF30 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 16-bit programmable timer 1 Table 5.5.3.3 Division ratio and control registers 16-bit programmable timer 1 (Clock source: OSC3) Selection register Division Output PST12 PST11 PST10 ratio control 1 1 1 fOSC3/4096 PRPRT1 1 1 0 fOSC3/1024 register 1 0 1 fOSC3/256 1 0 0 fOSC3/128 "1": ON 0 1 1 "0": OFF fOSC3/64 0 1 0 fOSC3/32 0 0 1 fOSC3/8 0 0 0 fOSC3/2 S1C88409 TECHNICAL MANUAL Division ratio fOSC1/128 fOSC1/64 fOSC1/32 fOSC1/16 fOSC1/8 fOSC1/4 fOSC1/2 fOSC1/1 EPSON Division ratio fOSC3/128 fOSC3/64 fOSC3/32 fOSC3/16 fOSC3/8 fOSC3/4 fOSC3/2 fOSC3/1 Output control PRFO3 register "1": ON "0": OFF 61 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Prescaler and Clock Control Circuit) A/D converter Table 5.5.3.8 Division ratio and control registers A/D converter Selection register PSAD2 PSAD1 PSAD0 1 x x 0 1 1 0 1 0 0 0 1 0 0 0 Division ratio fOSC3/16 fOSC3/8 fOSC3/4 fOSC3/2 fOSC3/1 Output control PRAD register "1": ON "0": OFF Touch panel controller 5.5.4 Control of external clock for event counter The 16-bit programmable timer can operate as an event counter with the clock input from the EXCL00, EXCL01 (K10, K11) input terminals. These external clocks are controlled to supply the 16-bit programmable timer by the individual input control registers. Table 5.5.4.1 shows the input terminals, the input control registers and the timers. Table 5.5.4.1 Input control registers for an event counter clock Table 5.5.3.9 Division ratio and control registers Touch panel controller Selection register PSTP2 PSTP1 PSTP0 1 x x 0 1 1 0 1 0 0 0 1 0 0 0 62 Division ratio fOSC3/16 fOSC3/8 fOSC3/4 fOSC3/2 fOSC3/1 Output control PRTP register Input terminal EXCL00 (K10) EXCL01 (K11) Input control register PK10ON PK11ON Event counter Timer 0 Timer 1 "1": ON "0": OFF EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Prescaler and Clock Control Circuit) 5.5.5 I/O memory of prescaler Table 5.5.5.1 shows the control bits for the prescaler. Table 5.5.5.1(a) Prescaler control bits Address Bit 00FF01 D7 D6 D5 Name - - WT1 Function - - 1 - - Wait state control WT1 WT0 Number of states 1 1 12(3 cycles) D4 WT0 1 0 8(2 cycles) 0 1 4(1 cycles) 0 0 No wait D3 CLKCHG CPU operating clock switch D2 OSCC OSC3 oscillation ON/OFF control D1 VD1C1 VD1 output level setting VD1C1 VD1C0 VD1(Typ.) 1 1 4.2 V D0 VD1C0 1 0 3.2 V 0 1 1.6 V 0 0 2.4 V 00FF10 D7 PRPRT1 16-bit programmable timer 1 clock control D6 PST12 16-bit programmable timer 1 division ratio PST12 PST11 PST10 (OSC3) (OSC1) 1 1 1 fOSC3 / 4096 fOSC1 / 128 fOSC3 / 1024 fOSC1 / 64 1 1 0 D5 PST11 fOSC3 / 256 fOSC1 / 32 1 0 1 fOSC3 / 128 fOSC1 / 16 1 0 0 fOSC3 / 64 fOSC1 / 8 0 1 1 D4 PST10 fOSC3 / 32 fOSC1 / 4 0 1 0 fOSC3 / 8 fOSC1 / 2 0 0 1 fOSC3 / 2 fOSC1 / 1 0 0 0 D3 PRPRT0 16-bit programmable timer 0 clock control D2 PST02 16-bit programmable timer 0 division ratio PST02 PST01 PST00 (OSC3) (OSC1) 1 1 1 fOSC3 / 4096 fOSC1 / 128 fOSC3 / 1024 fOSC1 / 64 1 1 0 D1 PST01 fOSC3 / 256 fOSC1 / 32 1 0 1 fOSC3 / 128 fOSC1 / 16 1 0 0 fOSC3 / 64 fOSC1 / 8 0 1 1 D0 PST00 fOSC3 / 32 fOSC1 / 4 0 1 0 fOSC3 / 8 fOSC1 / 2 0 0 1 fOSC3 / 2 fOSC1 / 1 0 0 0 00FF11 D7 - - D6 - - D5 - - D4 - - D3 PRPRT2 8-bit programmable timer clock control D2 PST22 8-bit programmable timer division ratio PST22 PST21 PST20 Division ratio 1 1 1 fOSC3 / 256 fOSC3 / 128 1 1 0 D1 PST21 fOSC3 / 64 1 0 1 fOSC3 / 32 1 0 0 fOSC3 / 16 0 1 1 D0 PST20 fOSC3 / 8 0 1 0 fOSC3 / 4 0 0 1 fOSC3 / 2 0 0 0 00FF12 D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - PRTF1 PRTF0 Init R/W Comment - - "0" when being read - - 0 R/W 0 R/W OSC3 On OSC1 Off 0 R/W 0 R/W 0 R/W 0 R/W On Off 0 R/W 0 R/W 0 R/W 0 R/W On Off 0 R/W 0 R/W 0 R/W 0 R/W - - - - On - - - - Off - - "0" when being read - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W - - - - - - 16-bit programmable timer 1 source clock selection 16-bit programmable timer 0 source clock selection S1C88409 TECHNICAL MANUAL 0 - - EPSON - - - - - - - - - - - - fOSC1 fOSC1 fOSC3 fOSC3 - - "0" when being read - - - - - - - - - - 0 R/W 0 R/W 63 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Prescaler and Clock Control Circuit) Table 5.5.5.1(b) Prescaler control bits Address Bit 00FF13 D7 D6 D5 D4 D3 D2 Function - - - - A/D converter clock control A/D converter division ratio PSAD2 PSAD1 PSAD0 Division ratio 1 x x fOSC3 / 16 PSAD1 0 1 1 fOSC3 / 8 fOSC3 / 4 0 1 0 PSAD0 fOSC3 / 2 0 0 1 fOSC3 / 1 0 0 0 PRFO1 FOUT1 output control PSF12 FOUT1 division ratio PSF12 PSF11 PSF10 Division ratio 1 1 1 fOSC1 / 128 fOSC1 / 64 1 1 0 PSF11 fOSC1 / 32 1 0 1 fOSC1 / 16 1 0 0 fOSC1 / 8 0 1 1 PSF10 fOSC1 / 4 0 1 0 fOSC1 / 2 0 0 1 fOSC1 / 1 0 0 0 PRFO3 FOUT3 output control PSF32 FOUT3 division ratio PSF32 PSF31 PSF30 Division ratio 1 1 1 fOSC3 / 128 fOSC3 / 64 1 1 0 PSF31 fOSC3 / 32 1 0 1 fOSC3 / 16 1 0 0 fOSC3 / 8 0 1 1 PSF30 fOSC3 / 4 0 1 0 fOSC3 / 2 0 0 1 fOSC3 / 1 0 0 0 1 - - - - On 00FF15 D7 - - D6 - - D5 - - D4 - - D3 - - D2 - - D1 PK11ON EXCL01 input clock ON/OFF control D0 PK10ON EXCL00 input clock ON/OFF control 00FF16 D7 - - D6 - - D5 - - D4 - - D3 PRTP Touch panel controller clock control D2 PSTP2 Touch panel controller clock ratio PSTP2 PSTP1 PSTP0 Division ratio 1 x x fOSC3 / 16 D1 PSTP1 1 1 0 fOSC3 / 8 1 0 fOSC3 / 4 0 D0 PSTP0 fOSC3 / 2 0 1 0 fOSC3 / 1 0 0 0 - - - - - - On On - - - - On D1 D0 00FF14 D7 D6 D5 D4 D3 D2 D1 D0 64 Name - - - - PRAD PSAD2 0 - - - - Off Init R/W Comment - - "0" when being read - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W On Off 0 R/W 0 R/W 0 R/W 0 R/W On Off 0 R/W 0 R/W 0 R/W 0 R/W - - - - - - Off Off - - - - Off - - - - - - 0 0 - - - - 0 0 - "0" when being read - - - - - R/W R/W - "0" when being read - - - R/W R/W 0 R/W 0 R/W EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Prescaler and Clock Control Circuit) PK10ON: EXCL00 clock control register (00FF15H*D0) Controls the event counter clock of the 16-bit programmable timer 0. OSCC: OSC3 oscillation control register (00FF01H*D2) Turns the OSC3 oscillation circuit on and off. When "1" is written: OSC3 oscillation ON When "0" is written: OSC3 oscillation OFF Reading: Valid When using the clock of which the clock source is OSC3, set the OSCC register to "1". Refer to Section 5.4, "Oscillation Circuit", for details of the oscillation control. At initial reset, the OSCC register is set to "0" (OSC3 oscillation OFF). PRTF0: 16-bit programmable timer 0 source clock selection register (00FF12H*D0) Selects the source clock for the 16-bit programmable timer 0. When "1" is written: fOSC1 When "0" is written: fOSC3 Reading: Valid When "1" is written to the PRTF0 register, the OSC1 clock is selected as the source clock for the 16-bit programmable timer 0. When "0" is written, the OSC3 clock is selected. At initial reset, the PRTF0 register is set to "0" (fOSC3). When "1" is written to the PRTF1 register, the OSC1 clock is selected as the source clock for the 16-bit programmable timer 1. When "0" is written, the OSC3 clock is selected. At initial reset, the PRTF1 register is set to "0" (fOSC3). PST00-PST02: 16-bit programmable timer 0 division ratio selection register (00FF10H*D0-D2) Selects the clock for the 16-bit programmable timer 0. It can be selected from 8 types of division ratio shown in Table 5.5.5.1(a). This register can also be read. At initial reset, the PST0 register is set to "0". When "1" is written: ON When "0" is written: OFF Reading: Valid By writing "1" to the PRPRT0 register, the clock that is selected with the PST0 register is output to the 16-bit programmable timer 0. When "0" is written, the clock is not output. At initial reset, the PRPRT0 register is set to "0" (OFF). S1C88409 TECHNICAL MANUAL By writing "1" to the PK10ON register, the EXCL00 (K10 input) clock is output to the 16-bit programmable timer 0. When "0" is written, the clock is not output. At initial reset, the PK10ON register is set to "0" (OFF). PRTF1: 16-bit programmable timer 1 source clock selection register (00FF12H*D1) Selects the source clock for the 16-bit programmable timer 1. When "1" is written: fOSC1 When "0" is written: fOSC3 Reading: Valid PRPRT0: 16-bit programmable timer 0 clock control register (00FF10H*D3) Controls the clock supply of the 16-bit programmable timer 0. When "1" is written: ON When "0" is written: OFF Reading: Valid PST10-PST12: 16-bit programmable timer 1 division ratio selection register (00FF10H*D4-D6) Selects the clock for the 16-bit programmable timer 1. It can be selected from 8 types of division ratio shown in Table 5.5.5.1(a). This register can also be read. At initial reset, the PST1 register is set to "0". PRPRT1: 16-bit programmable timer 1 clock control register (00FF10H*D7) Controls the clock supply of the 16-bit programmable timer 1. When "1" is written: ON When "0" is written: OFF Reading: Valid By writing "1" to the PRPRT1 register, the clock that is selected with the PST1 register is output to the 16-bit programmable timer 1. When "0" is written, the clock is not output. At initial reset, the PRPRT1 register is set to "0" (OFF). EPSON 65 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Prescaler and Clock Control Circuit) PK11ON: EXCL01 clock control register (00FF15H*D1) Controls the event counter clock of the 16-bit programmable timer 1. PRAD: A/D converter clock control register (00FF13H*D3) Controls the clock supply of the A/D converter. When "1" is written: ON When "0" is written: OFF Reading: Valid When "1" is written: ON When "0" is written: OFF Reading: Valid By writing "1" to the PK11ON register, the EXCL01 (K11 input) clock is output to the 16-bit programmable timer 1. When "0" is written, the clock is not output. At initial reset, the PK11ON register is set to "0" (OFF). PST20-PST22: 8-bit programmable timer division ratio selection register (00FF11H*D0-D2) Selects the clock for the 8-bit programmable timer. It can be selected from 8 types of division ratio shown in Table 5.5.5.1(a). This register can also be read. At initial reset, the PST2 register is set to "0" (fOSC3/2). PRPRT2: 8-bit programmable timer clock control register (00FF11H*D3) Controls the clock supply of the 8-bit programmable timer. When "1" is written: ON When "0" is written: OFF Reading: Valid By writing "1" to the PRPRT2 register, the clock that is selected with the PST2 register is output to the 8-bit programmable timer. When "0" is written, the clock is not output. At initial reset, the PRPRT2 register is set to "0" (OFF). PSAD0-PSAD2: A/D converter clock division ratio selection register (00FF13H*D0-D2) Selects the clock for the A/D converter. It can be selected from 5 types of division ratio as shown in Table 5.5.5.1(b). This register can also be read. At initial reset, the PSAD register is set to "0" (fOSC3/1). 66 By writing "1" to the PRAD register, the clock that is selected with the PSAD register is output to the A/D converter. When "0" is written, the clock is not output. At initial reset, the PRAD register is set to "0" (OFF). PSF10-PSF12: FOUT1 division ratio selection register (00FF14H*D4-D6) Selects the frequency for the FOUT1 clock. It can be selected from 8 types of division ratio shown in Table 5.5.5.1(b). This register can also be read. At initial reset, the PSF1 register is set to "0" (fOSC1/1). PRFO1: FOUT1 output control register (00FF14H*D7) Controls the FOUT1 output. When "1" is written: ON When "0" is written: OFF Reading: Valid When "1" is written to the PRFO1 register, the FOUT1 (R41) terminal outputs the clock selected with the PSF1 register. However, the high-impedance control register HZR41 of the output port R41 must be set to "0" and the data register R41D must be set to "1". When "0" is written, the clock is not output. At initial reset, the PRFO1 register is set to "0" (OFF). PSF30-PSF32: FOUT3 division ratio selection register (00FF14H*D0-D2) Selects the frequency for the FOUT3 clock. It can be selected from 8 types of division ratio shown in Table 5.5.5.1(b). This register can also be read. At initial reset, the PSF3 register is set to "0" (fOSC3/1). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Prescaler and Clock Control Circuit) 5.5.6 Programming note PRFO3: FOUT3 output control register (00FF14H*D3) Controls the FOUT3 output. When "1" is written: ON When "0" is written: OFF Reading: Valid When "1" is written to the PRFO3 register, the FOUT3 (R40) terminal outputs the clock selected with the PSF3 register. However, the high-impedance control register HZR40 of the output port R40 must be set to "0" and the data register R40D must be set to "1". When "0" is written, the clock is not output. At initial reset, the PRFO3 register is set to "0" (OFF). When using an output clock from the OSC3 prescaler, it is necessary to turn the OSC3 oscillation circuit on. Furthermore, the OSC3 oscillation circuit takes a maximum 20 msec for stabilizing oscillation after turning the OSC3 oscillation circuit on. Therefore, wait a long enough interval after the OSC3 oscillation goes on before turning the clock output of the OSC3 prescaler on. (The oscillation start time varies depending on the oscillator and external components to be used. Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS", in which an example of oscillation start time is indicated.) PSTP0-PSTP2: Touch panel controller clock division ratio selection register (00FF16H*D0-D2) Selects the clock for the touch panel controller. It can be selected from 5 types of division ratio as shown in Table 5.5.5.1(b). This register can also be read. At initial reset, the PSTP register is set to "0" (fOSC3/1). PRTP: Touch panel controller clock control register (00FF16H*D3) Controls the clock supply of the touch panel controller. When "1" is written: ON When "0" is written: OFF Reading: Valid By writing "1" to the PRTP register, the clock that is selected with the PSTP register is output to the touch panel controller. When "0" is written, the clock is not output. At initial reset, the PRTP register is set to "0" (OFF). S1C88409 TECHNICAL MANUAL EPSON 67 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 5.6.2 Mask option 5.6 Input Ports (K ports) Input port pull-up resistors K00 With resistor K01 With resistor K02 With resistor K03 With resistor K04 With resistor K05 With resistor K06 With resistor K07 With resistor K10 With resistor K11 With resistor K12 With resistor K13 With resistor 5.6.1 Configuration of input ports The S1C88409 has 12 bits of input ports built-in, and all the ports can be used as a general-purpose input port that has an interrupt function. K0 port: K1 port: K00-K07 K10-K13 8 bits 4 bits The K10 and K11 terminals serve both as the general-purpose input port terminal and the external clock (EXCL00, EXCL01) input terminal for the 16-bit programmable timer (event counter), and the input signal is common used. (Refer to Section 5.12, "16-bit Programmable Timer") Figure 5.6.1.1 shows the structure of the input port. Input interrupt circuit Mask option KxxD Kxx Address VSS Fig. 5.6.1.1 Structure of input port Each input port terminal is directly connected to the data bus via a three-state buffer. The input signal status can be read via the I/O memory as data. Data bus VDD Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct The input port has a built-in pull-up resistor, and it can be individually selected for use or not by the mask option. The "With resistor" option is suitable for push switch and key matrix input. When the input terminal is changed from a low level to a high level by the built-in pull-up resistor, the rise of the waveform is delayed on account of the time constant of the pull-up resistor and load capacitance of the terminal. Hence, when reading the input port, it is necessary to wait an appropriate amount of time. Particular care must be taken of the key scan for the key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression. Waiting time = RIN x (CIN + CL) x 1.6 [sec] RIN: Pull-up resistance Max. value CIN: Terminal capacitance Max. value CL: Load capacitance on the board When "Gate direct" is selected, the pull-up resistor is disconnected and the port is suitable for slide switch input and interfacing with other LSIs. In this case, take care that a floating status does not occur in the input. For unused input ports, select "With resistor" as the default setting. 68 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 5.6.3 Interrupt function All the input ports provide the interrupt function. The input ports are divided into five systems: K0 (K00-K07), K10, K11, K12 and K13. The interrupt generation condition for each system can be set with software. When the interrupt generation condition set for each terminal system is met, the interrupt factor flag (FK0, FK10, FK11, FK12 and FK13) corresponding to the terminal system is set to "1", and an interrupt is generated. The interrupt can be prohibited by setting the interrupt enable register (EK0, EK10, EK11, EK12 and EK13) corresponding to each interrupt factor flag. Furthermore, the priority level of the input interrupt for the CPU can be set at an optional level (0-3) using the interrupt priority registers PK0 and PK1 (two bits each) corresponding to two systems K0 and K1. Refer to Section 5.20, "Interrupt and Standby Mode", for details of the interrupt control registers and operations subsequent to interrupt generation. The exception processing vectors for each interrupt factor are set as follows: K10 input interrupt: K11 input interrupt: K12 input interrupt: K13 input interrupt: K0 input interrupt: 000006H 000008H 00000AH 00000CH 00000EH K0 input interrupt Figure 5.6.3.1 shows the configuration of the K0 (K00-K07) input interrupt circuit. K00 Input port K00D Input comparison register KCP00 Data bus Address Interrupt factor flag FK0 Interrupt selection register SIK00 Address Address K01 K02 K03 K04 K05 K06 K07 Interrupt enable register EK0 Interrupt priority level judgment circuit Interrupt request IRK0 Address Interrupt priority register PK00, PK01 Address Fig. 5.6.3.1 Configuration of K0 input interrupt circuit S1C88409 TECHNICAL MANUAL EPSON 69 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) K00 interrupt is disabled by the interrupt selection register (SIK00), so that an interrupt does not occur at (2). At (3), K03 changes to "0"; the data of the terminals K01-K07 in which an interrupt is enabled no longer match the data of the input comparison registers KCP01-KCP07, so that interrupt occurs. As already explained, the condition for the interrupt to occur is the change in the port data and contents of the input comparison registers from matching to no matching. Hence, in (4), when the no matching status changes to another no matching status, an interrupt does not occur. Therefore, to generate the interrupt again after an interrupt is generated, it is necessary to return the input terminal status to the same content as the input comparison register KCP0 or re-set the input comparison register KCP0. Further, terminals that have been disabled for interrupt do not affect the conditions for interrupt generation. The interrupt selection register SIK0 and input comparison register KCP0 for the K0 port is used to set the interrupt generation condition. Input port interrupt can be enabled or disabled by the setting of the interrupt selection registers SIK0. While the interrupt enable register EK0 masks the interrupt factor for the terminal system (8 bits), the interrupt selection register SIK0 masks in bit units. The input comparison register KCP0 selects the interrupt generation timing that an interrupt is to be generated at the rising edge or the falling edge for each input. When the status of the input terminals in which an interrupt has been enabled by the interrupt selection register SIK0 and the content of the input comparison register KCP0 change from a, matching to no matching, the interrupt factor flag FK0 is set to "1" and an interrupt is generated. Figure 5.6.3.2 shows an example of interrupt generation in the K0 terminal system. Interrupt selection register SIK0 SIK07 1 SIK06 1 SIK05 1 SIK04 1 SIK03 1 SIK02 1 SIK01 1 SIK00 0 Input comparison register KCP0 KCP07 KCP06 KCP05 KCP04 KCP03 KCP02 KCP01 KCP00 1 1 0 1 1 0 1 0 With the above setting, the K0 interrupt is generated under the following condition: Input port K0 (1) (2) (3) (4) K07 K06 K05 K04 K03 K02 K01 K00 1 1 0 1 1 0 1 0 K07 K06 K05 K04 K03 K02 K01 K00 1 1 0 1 1 0 1 1 K07 1 K06 1 K05 0 K04 1 K03 0 K02 0 K01 1 K00 0 K07 1 K06 1 K05 1 K04 1 K03 0 K02 0 K01 1 K00 0 (Initial value) Interrupt generation Because K00 interrupt is disabled, interrupt will be generated when no matching occurs between the contents of the 7 bits K01-K07 and the 7 bits input comparison register KCP01-KCP07. Fig. 5.6.3.2 Example of K0 (K00-K07) interrupt generation 70 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) K10-K13 input interrupt Figure 5.6.3.3 shows the configuration of the K10- K13 input interrupt circuit. K10 Input port K10D Input comparison register KCP10 Address Interrupt factor flag FK10 Interrupt priority level judgment circuit Data bus Address Interrupt enable register EK10 Interrupt request IRK10 IRK11 IRK12 IRK13 Address K11 K12 K13 Interrupt priority register PK10, PK11 Address Fig. 5.6.3.3 Configuration of K10-K13 input interrupt circuit Since the K10-K13 input ports can generate an interrupt by each bit, an interrupt selection register is not provided. The interrupts are enabled or disabled by the interrupt enable register EK1. The input comparison register KCP1 selects the interrupt generation timing that an interrupt is to be generated at the rising edge or the falling edge for each input. S1C88409 TECHNICAL MANUAL Each interrupt of the K10-K13 input ports is generated at the rising edge or the falling edge (depending on the setting of the input comparison register KCP1) when the interrupt has been enabled with the interrupt enable register EK1. EPSON 71 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 5.6.4 I/O memory of input ports Table 5.6.4.1 shows the input port control bits. Table 5.6.4.1 Input port control bits Address Bit 00FF20 D7 D6 D5 D4 D3 D2 D1 D0 00FF23 D7 D6 D5 D4 D3 D2 D1 D0 00FF27 D7 D6 D5 D4 D3 D2 D1 D0 00FFC0 D7 D6 D5 D4 D3 D2 D1 D0 00FFC1 D7 D6 D5 D4 D3 D2 D1 D0 00FFC2 D7 D6 D5 D4 D3 D2 D1 D0 00FFC3 D7 D6 D5 D4 D3 D2 D1 D0 00FFC4 D7 D6 D5 D4 D3 D2 D1 D0 72 Name PK11 PK10 PK01 PK00 PTM11 PTM10 PTM01 PTM00 EK13 EK12 EK11 EK10 EK0 - - - FK13 FK12 FK11 FK10 FK0 - - - SIK07 SIK06 SIK05 SIK04 SIK03 SIK02 SIK01 SIK00 KCP07 KCP06 KCP05 KCP04 KCP03 KCP02 KCP01 KCP00 - - - - KCP13 KCP12 KCP11 KCP10 K07D K06D K05D K04D K03D K02D K01D K00D - - - - K13D K12D K11D K10D Function K10-K13 interrupt priority register K00-K07 interrupt priority register 16-bit programmable timer 1 interrupt priority register 16-bit programmable timer 0 interrupt priority register K13 interrupt enable register K12 interrupt enable register K11 interrupt enable register K10 interrupt enable register K00-K07 interrupt enable register - - - K13 interrupt factor flag K12 interrupt factor flag K11 interrupt factor flag K10 interrupt factor flag K00-K07 interrupt factor flag - - - K07 interrupt selection register K06 interrupt selection register K05 interrupt selection register K04 interrupt selection register K03 interrupt selection register K02 interrupt selection register K01 interrupt selection register K00 interrupt selection register K07 input comparison register K06 input comparison register K05 input comparison register K04 input comparison register K03 input comparison register K02 input comparison register K01 input comparison register K00 input comparison register - - - - K13 input comparison register K12 input comparison register K11 input comparison register K10 input comparison register K07 input port data K06 input port data K05 input port data K04 input port data K03 input port data K02 input port data K01 input port data K00 input port data - - - - K13 input port data K12 input port data K11 input port data K10 input port data 1 0 Init R/W Comment PK11 PK10 0 R/W PK01 PK00 0 R/W PTM11 PTM10 Priority 0 R/W level PTM01 PTM00 0 R/W Level 3 0 R/W 1 1 Level 2 0 R/W 1 0 Level 1 0 R/W 0 1 Level 0 0 R/W 0 0 0 R/W 0 R/W 0 R/W Interrupt is Interrupt is 0 R/W enabled disabled 0 R/W - - "0" when being read - - - - (R) (R) 0 R/(W) Interrupt Interrupt 0 R/(W) factor has factor has not 0 R/(W) generated generated 0 R/(W) 0 R/(W) (W) (W) - - "0" when being read Reset Invalid - - - - 0 R/W 0 R/W 0 R/W Interrupt Interrupt 0 R/W is enabled is disabled 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W Falling edge Rising edge 1 R/W generates generates 1 R/W interrupt interrupt 1 R/W 1 R/W 1 R/W - - - - "0" when being read - - - - - - - - - - - - 1 R/W Falling edge Rising edge 1 R/W generates generates 1 R/W interrupt interrupt 1 R/W - R - R - R - R High Low - R - R - R - R - - - - "0" when being read - - - - - - - - - - - - - R - R High Low - R - R EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) K00D-K07D: K0 input port data (00FFC3H) K10D-K13D: K1 input port data (00FFC4H*D0-D3) Input data of the input port terminals can be read out. When "1" is read: HIGH level When "0" is read: LOW level Writing: Invalid The terminal voltage of each of the input ports K00-K07 and K10-K13 can be directly read as either a "1" when the terminal is high (VDD) level or a "0" when the terminal is low (VSS) level. These bits are dedicated for reading, so writing cannot be done. Table 5.6.4.2 Interrupt priority level settings PK11 PK10 PK01 PK00 1 1 0 1 0 1 0 SIK00-SIK07: K0 port interrupt selection register (00FFC0H) Sets the interrupt generation condition (enables/ disables interrupt) for the K0 input port. 0 Interrupt priority level Level 3 Level 2 Level 1 Level 0 (IRQ3) (IRQ2) (IRQ1) (None) At initial reset, the PK register is set to "0" (level 0). When "1" is written: Interrupt is enabled When "0" is written: Interrupt is disabled Reading: Valid SIK0 is the interrupt selection register corresponding to the input port K0. An interrupt of the port in which the SIK0 bit is set to "1" is enabled, and the others in which the SIK0 bit is set to "0" are disabled. Change of the input terminal in which the interrupt is disabled does not affect the interrupt generation. At initial reset, the SIK0 register is set to "0" (interrupt is disabled). The K10-K13 input port has no interrupt selection register because the port can generate interrupts in bit units. KCP00-KCP07: K0 port input comparison register (00FFC1H) KCP10-KCP13: K1 port input comparison register (00FFC2H*D0-D3) Sets the interrupt generation condition (interrupt generation timing) for the K0 or K1 input port. EK0: K0 input interrupt enable register (00FF23H*D3) EK10-EK13: K1 input interrupt enable register (00FF23H*D4-D7) Enables or disables the interrupt generation to the CPU. When "1" is written: Interrupt is enabled When "0" is written: Interrupt is disabled Reading: Valid EK0 is the interrupt enable register corresponding to eight bits of the K0 port and EK10-EK13 correspond to each bit of the K10-K13 ports. An interrupt of the port in which the EK register is set to "1" is enabled, and the others in which the EK register is set to "0" are disabled. At initial reset, the EK register is set to "0" (interrupt is disabled). FK0: K0 input interrupt factor flag (00FF27H*D3) FK10-FK13: K1 input interrupt factor flag (00FF27H*D4-D7) Indicates the generation of input interrupt factor. When "1" is written: Falling edge When "0" is written: Rising edge Reading: Valid When "1" is read: Int. factor has generated When "0" is read: Int. factor has not generated KCP is the input comparison register corresponding to each input port. An interrupt of the port in which the KCP bit is set to "1" is generated at the falling edge of the input and an interrupt in which the KCP bit is set to "0" is generated at the rising edge. At initial reset, the KCP register is set to "1" (falling edge). S1C88409 TECHNICAL MANUAL PK00, PK01: K0 input interrupt priority register (00FF20H*D4, D5) PK10, PK11: K1 input interrupt priority register (00FF20H*D6, D7) Sets the input interrupt priority level. PK0 and PK1 are the interrupt priority registers corresponding to the K0, K1 input interrupts. Table 5.6.4.2 shows the interrupt priority level which can be set by this register. When "1" is written: Factor flag is reset When "0" is written: Invalid FK0 is the interrupt factor flag corresponding to eight bits of the K0 port and FK10-FK13 correspond to each bit of the K10-K13 ports. The interrupt factor flag is set to "1" when the interrupt generation condition is met. EPSON 73 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) At this point, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I0 and I1), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "1" when the interrupt generation condition is met. To accept the subsequent interrupt after an interrupt generation, it is necessary to re-set the interrupt flags (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "0" by writing "1". At initial reset, the FK flags are all reset to "0". 5.6.5 Programming note When the input terminal is changed from a low level to a high level by the built-in pull-up resistor, the rise of the waveform is delayed on account of the time constant of the pull-up resistor and load capacitance of the terminal. Hence, when reading the input port, it is necessary to wait an appropriate amount of time. Particular care must be taken of the key scan for the key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression. Waiting time = RIN x (CIN + CL) x 1.6 [sec] RIN: Pull-up resistance Max. value CIN: Terminal capacitance Max. value CL: Load capacitance on the board 74 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 5.7 Output Ports (R ports) Address High impedance control register Data bus 5.7.1 Configuration of output ports The S1C88409 has 30 bits of output ports. R0 port: R1 port: R2 port: R3 port: R4 port: R00-R07 R10-R17 R20-R27 R30-R32 R40-R42 8 bits 8 bits 8 bits 3 bits 3 bits R02 R03 R04 R05 R06 R07 R10 R11 R12 R13 R14 R15 R16 R17 R20 R21 R22 R23 R24 R25 R26 R27 R30 R31 R32 R40 VSS R41 R42 Bus mode Single chip Expanded 64K Expanded 4M Output port R00 Address A0 Output port R01 Address A1 Output port R02 Address A2 Output port R03 Address A3 Output port R04 Address A4 Output port R05 Output port R06 Address A5 Address A6 Output port R07 Output port R10 Output port R11 Output port R12 Address A7 Address A8 Address A9 Address A10 Output port R13 Output port R14 Address A11 Address A12 Output port R15 Output port R16 Output port R17 Output port R20 Output port R21 Address A13 Address A14 Address A15 Address A16 Address A17 Output port R22 Output port R23 Output port R24 Address A18 Address A19 Address A20 The data register and high impedance control register of the output port which is used for the bus function can be used as general purpose registers with the ability to read and write. They do not affect the bus signal output. 5.7.2 High impedance control Each output port can be set in high impedance by software. Thus the output signal lines can be shared with other external devices. By setting the bits of the high impedance control register to "1", the corresponding output ports go to a high impedance status. The output port in which the register is set to "0" becomes a complementary output. 5.7.3 DC output As shown in Figure 5.7.1.1, when "1" is written to the output port data register, the output terminal goes high (VDD) level and when "0" is written it goes low (VSS) level. The data written to the data register during high impedance status is output from the terminal when the output is switched to complementary. 5.7.4 Special output Output port R25 Output port R26 Output port R27 Output port R30 Address A21 RD signal WR signal Output port R30/CE0 signal Output port R31/CE1 signal Output port R32/CE2 signal The R40 to R42 terminals are shared with the special output terminals shown in Table 5.7.4.1. Table 5.7.4.1 Special outputs Output port R31 Output port R32 Output port R40 Output port R41 Output port R42 Output port Special output R40 Clock output : TOUT0/FOUT3 R41 Clock output : TOUT1/FOUT1 R42 Buzzer output : BZ This section explains only the control of generalpurpose output ports. Refer to Section 5.2, "System Controller and Bus Control", for the bus control. Figure 5.7.1.1 shows the structure of the output port. S1C88409 TECHNICAL MANUAL Rxx Fig. 5.7.1.1 Structure of output port Table 5.7.1.1 Configuration of output ports R00 R01 Data register Address Depending on the bus mode setting, the configuration of the output ports may vary as shown in the table below. Terminal VDD When using a special output, fix the high-impedance control register HZR4x of the port to "0" and the output data register R4xD to "1". Refer to Section 5.9, "Clock Output", for the TOUT and FOUT outputs, and to Section 5.15, "Sound Generator", for the BZ output. EPSON 75 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 5.7.5 I/O memory of output ports Table 5.7.5.1 shows the output port control bits. Table 5.7.5.1(a) Output port control bits Address Bit 00FFD0 D7 D6 D5 D4 D3 D2 D1 D0 00FFD1 D7 D6 D5 D4 D3 D2 D1 D0 00FFD2 D7 D6 D5 D4 D3 D2 D1 D0 00FFD3 D7 D6 D5 D4 D3 D2 D1 D0 00FFD4 D7 D6 D5 D4 D3 D2 D1 D0 00FFD5 D7 D6 D5 D4 D3 D2 D1 D0 00FFD6 D7 D6 D5 D4 D3 D2 D1 D0 76 Name HZR07 HZR06 HZR05 HZR04 HZR03 HZR02 HZR01 HZR00 HZR17 HZR16 HZR15 HZR14 HZR13 HZR12 HZR11 HZR10 HZR27 HZR26 HZR25 HZR24 HZR23 HZR22 HZR21 HZR20 - - - - - HZR32 HZR31 HZR30 - - - - - HZR42 HZR41 HZR40 R07D R06D R05D R04D R03D R02D R01D R00D R17D R16D R15D R14D R13D R12D R11D R10D Function R07 high impedance control register R06 high impedance control register R05 high impedance control register R04 high impedance control register R03 high impedance control register R02 high impedance control register R01 high impedance control register R00 high impedance control register R17 high impedance control register R16 high impedance control register R15 high impedance control register R14 high impedance control register R13 high impedance control register R12 high impedance control register R11 high impedance control register R10 high impedance control register R27 high impedance control register R26 high impedance control register R25 high impedance control register R24 high impedance control register R23 high impedance control register R22 high impedance control register R21 high impedance control register R20 high impedance control register - - - - - R32 high impedance control register R31 high impedance control register R30 high impedance control register - - - - - R42 high impedance control register R41 high impedance control register R40 high impedance control register R07 output port data register R06 output port data register R05 output port data register R04 output port data register R03 output port data register R02 output port data register R01 output port data register R00 output port data register R17 output port data register R16 output port data register R15 output port data register R14 output port data register R13 output port data register R12 output port data register R11 output port data register R10 output port data register EPSON 1 0 High impedance Complementary High impedance Complementary High impedance Complementary - - - - - - - - - - High impedance Complementary - - - - - - - - - - High impedance Complementary High Low High Low Init 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W Comment R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - - R/W R/W R/W - "0" when being read - - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) Table 5.7.5.1(b) Output port control bits Address Bit 00FFD7 D7 D6 D5 D4 D3 D2 D1 D0 00FFD8 D7 D6 D5 D4 D3 D2 D1 D0 00FFD9 D7 D6 D5 D4 D3 D2 D1 D0 Name R27D R26D R25D R24D R23D R22D R21D R20D - - - - - R32D R31D R30D - - - - - R42D R41D R40D Function R27 output port data register R26 output port data register R25 output port data register R24 output port data register R23 output port data register R22 output port data register R21 output port data register R20 output port data register - - - - - R32 output port data register R31 output port data register R30 output port data register - - - - - R42 output port data register R41 output port data register R40 output port data register HZR00-HZR07: R0 port high impedance control register (00FFD0H) HZR10-HZR17: R1 port high impedance control register (00FFD1H) HZR20-HZR27: R2 port high impedance control register (00FFD2H) HZR30-HZR32: R3 port high impedance control register (00FFD3H*D0-D2) HZR40-HZR42: R4 port high impedance control register (00FFD4H*D0-D2) Sets the output terminals into a high impedance state. When "1" is written: High impedance When "0" is written: Complementary Reading: Valid The HZR register is the high impedance control register corresponding to each output port. When a HZR bit is set to "1", the corresponding output port terminal goes to a high impedance status and when "0" is set, it becomes a complementary output. The high impedance control register of the output port which is used for bus function can be used as a general purpose register with the ability to read and write. It does not affect the bus signal output. Among R40 to R42, the high-impedance control register of the port which is used for special output (TOUT/FOUT, BZ) should be fixed at "0". At initial reset, the HZR register is set to "1" (high impedance). S1C88409 TECHNICAL MANUAL 1 0 High Low - - - - - - - - - - High Low - - - - - - - - - - High Low Init 1 1 1 1 1 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 R/W Comment R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - - R/W R/W R/W - "0" when being read - - - - R/W R/W R/W R00D-R07D: R0 port output data register (00FFD5H) R10D-R17D: R1 port output data register (00FFD6H) R20D-R27D: R2 port output data register (00FFD7H) R30D-R32D: R3 port output data register (00FFD8H*D0-D2) R40D-R42D: R4 port output data register (00FFD9H*D0-D2) Sets the data output from the output port terminal. When "1" is written: HIGH level output When "0" is written: LOW level output Reading: Valid RxxD is the data register for each output port. When "1" is set, the corresponding output port terminal goes high (VDD) level, and when "0" is set, it goes low (VSS) level. The data register of the output port which is used for the bus function can be used as general purpose register with the ability to read and write. It does not affect the bus signal output. Among R40 to R42, the data register of the port which is used for special output (TOUT/FOUT, BZ) should be fixed at "1". At initial reset, all the data bits are set to "1" (HIGH level output). EPSON 77 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 5.8 I/O Ports (P ports) VDD 5.8.1 Configuration of I/O ports I/O control register The S1C88409 has 28 bits of I/O ports. P00-P07 P10-P17 P20-P23 P30-P37 8 bits 8 bits 4 bits 8 bits Data register Data bus P0 port: P1 port: P2 port: P3 port: These ports can be switched between generalpurpose I/O ports and input/output ports for the following functions by software. D/A converter I/O control register Mask option Data bus Data register Pxx VSS (a) P00-P07, P10-P17, P20-P23 VDD Data bus I/O control register P30 ~P35 Input control VSS A/D converter input control A/D converter 1: During output mode 2: During input mode (c) P36, P37 Fig. 5.8.1.1 Structure of I/O port The port can be set individually in input mode or output mode when it is used as a general-purpose I/O port. This setting is done by writing data to the I/O control register (IOC). 5.8.2 Terminal configuration of I/O port and change of function When the expanded bus mode is set (P00-P07) Mask option Data register *2 VSS The I/O port terminals are shared with two or three functions. Therefore, the configuration of the terminals changes depending on the setting of each function. Since all the terminals are set for the I/O port at initial reset except for the MPU mode, switch them using software according to the functions to be used. Table 5.8.2.1 lists the terminal functions. 1: During output mode 2: During input mode *1 Input control A/D converter VDD Input control *2 D/A converter output control This section explains control only when using these ports as general-purpose I/O ports. Refer to respective sections for other functions. Figure 5.8.1.1 shows the structure of the I/O port. 2 *1 P36 P37 A/D converter input control * Data bus for external memory access * Serial interface * Touch panel controller * A/D converter * D/A converter 1 Mask option When a bus mode except for the single chip mode is set, P00-P07 functions as the data bus D0-D7. In this case, the data register P00D-P07D and the I/O control register IOC00-IOC07 can be used as a general-purpose register that does not affect the input/output for the data bus. Refer to Section 5.2, "System Controller and Bus Control", for setting of bus mode. 1: During output mode 2: During input mode (b) P30-P35 78 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) Table 5.8.2.1 Terminal function list Terminal P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P30 P31 P32 P33 P34 P35 P36 Standard function I/O port I/O port I/O port I/O port P37 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P30 P31 P32 P33 P34 P35 P36 P37 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Sub-function Data bus for external memory (Expanded mode) Serial I/F data input Serial I/F data output Serial I/F clock input/output Serial I/F ready output Serial I/F data input/IR input Serial I/F data output/IR output Serial I/F clock input/output Serial I/F ready output Touch panel controller control signal output Touch panel controller control signal output Touch panel controller control signal output Touch panel controller control signal output A/D converter analog signal input A/D converter analog signal input A/D converter analog signal input A/D converter analog signal input A/D converter analog signal input A/D converter analog signal input A/D converter analog signal input or D/A converter analog signal output I/O A/D converter analog signal input or D/A converter analog signal output D0 D1 D2 D3 D4 D5 D6 D7 SIN SOUT SCLK SRDY SIN/IRI SOUT/IRO SCLK SRDY BYH BYL BXH BXL AD0 AD1 AD2 AD3 AD4 AD5 AD6 DA0 AD7 DA1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I/O O I O I/O O O O O O I I I I I I I O I O When the serial interface is used (P10-P17) When the touch panel controller is used (P20-P23) The S1C88409 has a serial interface built-in. The serial interface uses the following terminals and unused terminals can be used as a general-purpose I/O ports. The S1C88409 has a built-in touch panel controller. When the touch panel controller is used, the P20- P23 terminals work as the touch panel control signal output terminals (BYH, BYL, BXH, BXL). Transfer mode Note: When the touch panel function is selected by mask option, the P20-P23 terminals are configured as follows at initial reset: P20 (BYH) High level P21 (BYL) Low level P22 (BXH) High level P23 (BXL) Low level Terminals used for serial I/F (P10-P17) Asynchronous P10, P11 (or P14, P15) Clock sync. slave P10-P13 (or P14-P17) Clock sync. master P10-P12 (or P14-P16) IrDA interface P14, P15 The data register and the I/O control register of the port which is assigned to the serial interface can be used as a general-purpose register that does not affect the input/output. Refer to Section 5.14, "Serial Interface", for setting of the serial interface. The P20-P23 terminals are disconnected from the I/O control and data registers, and are controlled from the touch panel controller. Thus it is unnecessary to configure these terminals by software. The I/O control and data registers for these ports can be used as general-purpose registers. Refer to Section 5.17, "Touch Panel Controller" for setting the touch panel controller. Since the touch panel controller uses the A/D converter, the P3x terminals used for inputting analog signals cannot be used as I/O ports. S1C88409 TECHNICAL MANUAL EPSON 79 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) When A/D converter and/or D/A converter is used (P30-P37) It is possible to set any terminals in the P30-P37 terminals as the analog input terminal for the A/D converter. Further, either the P36 or P37 terminal or both can also be set as the analog output terminal of the D/A converter. The data register and the I/O control register of the port which is set to the A/D converter input or D/A converter output do not affect the terminal status, but the port reading can be done the same as the I/O port. In the input mode, the terminal status is read out (as binary data), and in the output mode, the content of the data register is read out. The content of the data register is not output to the terminal even in the output mode. The port which is not used for the A/D converter and D/A converter within P30-P37 can be used as a general-purpose I/O port. Refer to Section 5.18, "A/D Converter", for setting of the A/D converter and to Section 5.19, "D/A Converter" for setting of the D/A converter. For unused I/O port, select "With resistor" default setting. When using the A/D converter and/or D/A converter, select "Gate direct" for the port to obtain the conversion precision. The I/O port is set in the input mode or output mode by writing data to the corresponding I/O control register (IOC). To set an I/O port to the input mode, write "0" to the I/O control register. The I/O port which is set in the input mode shifts to high impedance status and functions as an input port. Reading during the input mode gets the input terminal status directly: the data being "1" when the terminal is at high (VDD) level and "0" when it is at low (VSS) level. When "With resistor" is selected by mask option, the port terminal is pulled up during the input mode. Data can be written to the data registers without affecting the terminal status even in the input mode. Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct The I/O port has a built-in pull-up resistor that is activated during the input mode, and it can be individually selected for use or not by the mask option. 80 Waiting time = RIN x (CIN + CL) x 1.6 [sec] RIN: Pull-up resistance Max. value CIN: Terminal capacitance Max. value CL: Load capacitance on the board 5.8.4 I/O control registers and I/O mode 5.8.3 Mask option I/O port pull-up resistors P00 With resistor P01 With resistor P02 With resistor P03 With resistor P04 With resistor P05 With resistor P06 With resistor P07 With resistor P10 With resistor P11 With resistor P12 With resistor P13 With resistor P14 With resistor P15 With resistor P16 With resistor P17 With resistor P20 With resistor P21 With resistor P22 With resistor P23 With resistor P30 With resistor P31 With resistor P32 With resistor P33 With resistor P34 With resistor P35 With resistor P36 With resistor P37 With resistor When "With resistor" is selected, the pull-up resistor of the port turns on during the input mode. When the port terminal is changed from a low level to a high level by the built-in pull-up resistor, the rise of the waveform is delayed on account of the time constant of the pull-up resistor and load capacitance of the terminal. So, when reading the I/O port, it is necessary to wait an appropriate amount of time. Make this waiting time the amount of time or more calculated by the following expression. To set an I/O port to the output mode, write "1" to the I/O control register. The I/O port which is set to output mode functions as an output port. When the data register is set to "1", the port goes high (VDD) level and when it is set to "0", the port goes low (VSS) level. Reading during the output mode gets the content of the data register. At initial reset, the I/O control registers are set to "0" (I/O ports are set in the input mode). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 5.8.5 I/O memory of I/O ports Table 5.8.5.1 shows the I/O port control bits. Table 5.8.5.1(a) I/O port control bits Address Bit 00FFE0 D7 D6 D5 D4 D3 D2 D1 D0 00FFE1 D7 D6 D5 D4 D3 D2 D1 D0 00FFE2 D7 D6 D5 D4 D3 D2 D1 D0 00FFE3 D7 D6 D5 D4 D3 D2 D1 D0 00FFE4 D7 D6 D5 D4 D3 D2 D1 D0 00FFE5 D7 D6 D5 D4 D3 D2 D1 D0 Name IOC07 IOC06 IOC05 IOC04 IOC03 IOC02 IOC01 IOC00 IOC17 IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 - - - - IOC23 IOC22 IOC21 IOC20 IOC37 IOC36 IOC35 IOC34 IOC33 IOC32 IOC31 IOC30 P07D P06D P05D P04D P03D P02D P01D P00D P17D P16D P15D P14D P13D P12D P11D P10D Function P07 I/O control register P06 I/O control register P05 I/O control register P04 I/O control register P03 I/O control register P02 I/O control register P01 I/O control register P00 I/O control register P17 I/O control register P16 I/O control register P15 I/O control register P14 I/O control register P13 I/O control register P12 I/O control register P11 I/O control register P10 I/O control register - - - - P23 I/O control register P22 I/O control register P21 I/O control register P20 I/O control register P37 I/O control register P36 I/O control register P35 I/O control register P34 I/O control register P33 I/O control register P32 I/O control register P31 I/O control register P30 I/O control register P07 I/O port data register P06 I/O port data register P05 I/O port data register P04 I/O port data register P03 I/O port data register P02 I/O port data register P01 I/O port data register P00 I/O port data register P17 I/O port data register P16 I/O port data register P15 I/O port data register P14 I/O port data register P13 I/O port data register P12 I/O port data register P11 I/O port data register P10 I/O port data register S1C88409 TECHNICAL MANUAL EPSON 1 0 Output Input Output Input - - - - - - - - Output Input Output Input High Low High Low Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W Comment R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 81 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) Table 5.8.5.1(b) I/O port control bits Address Bit 00FFE6 D7 D6 D5 D4 D3 D2 D1 D0 00FFE7 D7 D6 D5 D4 D3 D2 D1 D0 Name - - - - P23D P22D P21D P20D P37D P36D P35D P34D P33D P32D P31D P30D Function - - - - P23 I/O port data register P22 I/O port data register P21 I/O port data register P20 I/O port data register P37 I/O port data register P36 I/O port data register P35 I/O port data register P34 I/O port data register P33 I/O port data register P32 I/O port data register P31 I/O port data register P30 I/O port data register P00D-P07D: P0 port data register (00FFE4H) P10D-P17D: P1 port data register (00FFE5H) P20D-P23D: P2 port data register (00FFE6H*D0-D3) P30D-P37D: P3 port data register (00FFE7H) I/O port data can be read and output data can be set through these registers. High Low High Low Init - - - - 1 1 1 1 1 1 1 1 1 1 1 1 R/W Comment - "0" when being read - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When "1" is written: Output mode When "0" is written: Input mode Reading: Valid When "1" is written: HIGH level When "0" is written: LOW level When the I/O port is set in the output mode, the written data is output from the I/O port terminal. When "1" is written as the port data, the port terminal goes high (VDD) level, and when "0" is written, the terminal goes low (VSS) level. Port data can be written even in the input mode. When reading: The IOC register is the I/O control register corresponding to each I/O port individually. When an IOC bit is set to "1", the corresponding I/O port enters the output mode. When it is set to "0", the port enters the input mode. At initial reset, the IOC register is set to "0" (input mode). Refer to Section 5.8.2 for the I/O control register of the ports set in a function other than I/O port. When "1" is read: HIGH level ("1") When "0" is read: LOW level ("0") When the I/O port is in the input mode, the voltage level being input to the port terminal can be read. When the terminal voltage is high (VDD) level, "1" is read, and "0" is read when it is low (VSS) level. In the output mode, the content of the data register is read. At initial reset, the data bits are all set to "1" (HIGH level). 82 0 - - - - IOC00-IOC07: P0 port I/O control register (00FFE0H) IOC10-IOC17: P1 port I/O control register (00FFE1H) IOC20-IOC23: P2 port I/O control register (00FFE2H*D0-D3) IOC30-IOC37: P3 port I/O control register (00FFE3H) Sets the I/O port to the input or output mode. When writing: Refer to Section 5.8.2 for the data register of the ports set in a function other than I/O port. 1 - - - - 5.8.6 Programming note When the port terminal is changed from a low level to a high level by the built-in pull-up resistor, the rise of the waveform is delayed on account of the time constant of the pull-up resistor and load capacitance of the terminal. So, when reading the I/O port, it is necessary to wait an appropriate amount of time. Make this waiting time the amount of time or more calculated by the following expression. Waiting time = RIN x (CIN + CL) x 1.6 [sec] RIN: Pull-up resistance Max. value CIN: Terminal capacitance Max. value CL: Load capacitance on the board EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Output) 5.9 Clock Output 5.9.1 Configuration of clock output control circuit The S1C88409 can output 4 kinds of clocks to external devices. The kinds of clocks are as follows: * OSC3 dividing clock (FOUT3) * OSC1 dividing clock (FOUT1) * The output clock of the 16-bit programmable timer 0 (TOUT0) * The output clock of the 16-bit programmable timer 1 (TOUT1) Prescaler The output ports R40 and R41 are used for these outputs. Figure 5.9.1.1 shows the configuration of the clock output control circuit. The FOUT3 clock and TOUT0 clock cannot be output simultaneously, because they use the same port, similar to the FOUT1 clock and TOUT1 clock. The TOUT0 clock can be output when the 16-bit programmable timer operates in the 8-bit mode. Refer to Section 5.12, "16-bit Programmable Timer", for the output clock of the 16-bit programmable timer. FOUT3 PRFO3 16-bit programmable timer 0 TOUT0 FOUT3/TOUT0 (R40) PTOUT0 R40D HZR40 Prescaler FOUT1 PRFO1 16-bit programmable timer 1 TOUT1 FOUT1/TOUT1 (R41) PTOUT1 R41D HZR41 Fig. 5.9.1.1 Configuration of clock output control circuit S1C88409 TECHNICAL MANUAL EPSON 83 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Output) 5.9.2 Clock output control Note: * Be aware that the output is fixed at low (VSS) level when the data register of the output port used for the clock output is set to "0". Table 5.9.2.1 shows the output control register of each clock. To output the clock, fix the high-impedance control register of the output port to "0" and the output data register to "1". The output port terminal outputs the clock by writing "1" to the clock output control register in this status. The terminal goes high (VDD) level when "0" is written. Figure 5.9.2.1 shows the output waveform by this control. * A hazard may occur on the output signal when the clock output control register is changed. * Since the output clock becomes unstable when SLEEP mode is canceled, stop the output before shifting to SLEEP mode. The frequencies of the FOUT3 and FOUT1 clocks can be selected from eight types by setting the prescaler. Table 5.9.2.1 Clock output control registers Clock FOUT3 FOUT1 TOUT0 TOUT1 Output control register PRFO3 (00FF14H*D3) PRFO1 (00FF14H*D7) PTOUT0 (00FF30H*D3) PTOUT1 (00FF31H*D3) Hi-Z control register HZR40 (00FFD4H*D0) HZR41 (00FFD4H*D1) HZR40 (00FFD4H*D0) HZR41 (00FFD4H*D1) High impedance control register Fix at 0 Data register Fix at 1 Output control register 0 Data register R40D (00FFD9H*D0) R41D (00FFD9H*D1) R40D (00FFD9H*D0) R41D (00FFD9H*D1) 1 0 VDD VSS Clock output Fig. 5.9.2.1 Clock output waveform 84 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Output) 5.9.3 I/O memory of clock output Table 5.9.3.1 shows the clock output control bits. Table 5.9.3.1 Clock output control bits Address Bit 00FF14 D7 D6 D5 D4 D3 D2 D1 D0 00FF30 D7 D6 D5 D4 D3 D2 D1 D0 00FF31 D7 D6 D5 D4 D3 D2 D1 D0 00FFD4 D7 D6 D5 D4 D3 D2 D1 D0 00FFD9 D7 D6 D5 D4 D3 D2 D1 D0 Name Function PRFO1 FOUT1 output control PSF12 FOUT1 division ratio PSF12 PSF11 PSF10 Division ratio 1 1 1 fOSC1 / 128 fOSC1 / 64 1 1 0 PSF11 fOSC1 / 32 1 0 1 fOSC1 / 16 1 0 0 fOSC1 / 8 0 1 1 PSF10 fOSC1 / 4 0 1 0 fOSC1 / 2 0 0 1 fOSC1 / 1 0 0 0 1 On PRFO3 FOUT3 output control PSF32 FOUT3 division ratio PSF32 PSF31 PSF30 Division ratio 1 1 1 fOSC3 / 128 fOSC3 / 64 1 1 0 PSF31 fOSC3 / 32 1 0 1 fOSC3 / 16 1 0 0 fOSC3 / 8 0 1 1 PSF30 fOSC3 / 4 0 1 0 fOSC3 / 2 0 0 1 fOSC3 / 1 0 0 0 MODE16 16-bit PTM 8-/16-bit mode selection - - - - - - PTOUT0 16-bit PTM0 clock output control PTRUN0 16-bit PTM0 RUN/STOP control PSET0 16-bit PTM0 preset CKSEL0 16-bit PTM0 input clock selection - - - - - - - - PTOUT1 16-bit PTM1 clock output control PTRUN1 16-bit PTM1 RUN/STOP control PSET1 16-bit PTM1 preset CKSEL1 16-bit PTM1 input clock selection - - - - - - - - - - HZR42 R42 high impedance control register HZR41 R41 high impedance control register HZR40 R40 high impedance control register - - - - - - - - - - R42D R42 output port data register R41D R41 output port data register R40D R40 output port data register On S1C88409 TECHNICAL MANUAL 0 Off Init R/W 0 R/W 0 R/W Comment 0 R/W 0 R/W Off 0 R/W 0 R/W 0 R/W 0 R/W 16-bit 8-bit x 2 - - - - - - On Off Run Stop Preset Invalid External clock Internal clock - - - - - - - - On Off Run Stop Preset Invalid External clock Internal clock - - - - - - - - - - EPSON High impedance Complementary - - - - - - - - - - High Low 0 - - - 0 0 0 0 - - - - 0 0 0 0 - - - - - 1 1 1 - - - - - 1 1 1 R/W - - - R/W R/W W R/W - - - - R/W R/W W R/W - - - - - R/W R/W R/W - - - - - R/W R/W R/W "0" when being read "0" when being read "0" when being read "0" when being read "0" when being read "0" when being read 85 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Output) HZR40, HZR41: R4 port high impedance control register (00FFD4H*D0, D1) Sets the output terminals into a high impedance state. When "1" is written: High impedance When "0" is written: Complementary Reading: Valid The HZR40 and HZR41 registers are the high impedance control registers for the output ports R40 and R41 used for the clock output. Fix data of the port used for the clock output at "0". At initial reset, the HZR register is set to "1" (high impedance). R40D, R41D: R4 port output data register (00FFD9H*D0, D1) They are the data registers for the output ports R40, R41 used for the clock output. When "1" is written: Clock output is possible When "0" is written: LOW (VSS) level is output Reading: Valid Fix data of the port used for the clock output at "1". At initial reset, the data bits are all set to "1". PSF10-PSF12: FOUT1 division ratio selection register (00FF14H*D4-D6) Selects the frequency for the FOUT1 clock. It can be selected from 8 types of division ratio shown in Table 5.9.3.1. This register can also be read. At initial reset, the PSF1 register is set to "0" (fOSC1/1). PRFO3: FOUT3 output control register (00FF14H*D3) Controls the FOUT3 output. When "1" is written: ON When "0" is written: OFF Reading: Valid When "1" is written to the PRFO3 register, the FOUT3 (R40) terminal outputs the clock selected with the PSF3 register. However, the high-impedance control register HZR40 of the output port R40 must be set to "0" and the data register R40D must be set to "1". Furthermore, the OSC3 oscillation circuit must be used. When "0" is written, the clock is not output. At initial reset, the PRFO3 register is set to "0" (OFF). PTOUT0: 16-bit programmable timer 0 clock output control register (00FF30H*D3) Controls the output of the TOUT0 signal (16-bit programmable timer 0 clock). When "1" is written: ON When "0" is written: OFF Reading: Valid PRFO1: FOUT1 output control register (00FF14H*D7) Controls the FOUT1 output. When "1" is written: ON When "0" is written: OFF Reading: Valid When "1" is written to the PRFO1 register, the FOUT1 (R41) terminal outputs the clock selected with the PSF1 register. However, the high-impedance control register HZR41 of the output port R41 must be set to "0" and the data register R41D must be set to "1". When "0" is written, the clock is not output. At initial reset, the PRFO1 register is set to "0" (OFF). 86 PSF30-PSF32: FOUT3 division ratio selection register (00FF14H*D0-D2) Selects the frequency for the FOUT3 clock. It can be selected from 8 types of division ratio shown in Table 5.9.3.1. This register can also be read. At initial reset, the PSF3 register is set to "0" (fOSC3/1). The PTOUT0 register is the output control register for the TOUT0 signal. When "1" is written to this register, the TOUT0 signal is output from the TOUT0 (R40) terminal. When "0" is written, the terminal goes high (VDD) level. However, the highimpedance control register HZR40 of the output port R40 must be set to "0" and the data register R40D must be set to "1". The TOUT0 clock cannot be output simultaneously with the FOUT3 clock. Refer to Section 5.12, "16-bit Programmable Timer", for setting of clock frequency. At initial reset, the PTOUT0 register is set to "0" (OFF). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Output) 5.9.4 Programming notes PTOUT1: 16-bit programmable timer 1 clock output control register (00FF31H*D3) Controls the output of the TOUT1 signal (16-bit programmable timer 1 clock). (1) The FOUT3 clock and TOUT0 clock cannot be output simultaneously, because they use the same port, similar to the FOUT1 clock and TOUT1 clock. When "1" is written: ON When "0" is written: OFF Reading: Valid The PTOUT1 register is the output control register for the TOUT1 signal. When "1" is written to this register, the TOUT0 signal is output from the TOUT1 (R41) terminal. When "0" is written, the terminal goes high (VDD) level. However, the highimpedance control register HZR41 of the output port R41 must be set to "0" and the data register R41D must be set to "1". The TOUT1 clock cannot be output simultaneously with the FOUT1 clock. Refer to Section 5.12, "16-bit Programmable Timer", for setting of clock frequency. At initial reset, the PTOUT1 register is set to "0" (OFF). S1C88409 TECHNICAL MANUAL (2) Be aware that the output is fixed at low (VSS) level when the data register of the output port used for the clock output is set to "0". (3) A hazard may occur on the output signal when the clock output control register is changed. (4) Since the output clock becomes unstable when SLEEP mode is canceled, stop the output before shifting to SLEEP mode. EPSON 87 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) 5.10 LCD Controller 5.10.1 Configuration of LCD controller The S1C88409 has a built-in dot-matrix LCD controller and can drive a middle-scale LCD panel (eg., 240 x 100 dots, B&W) by connecting external common drivers (S1D16305 or S1D16700) and segment drivers (S1D16006 or S1D15700). This LCD controller can drive 4-level gray scale LCD panels in addition to B&W (black and white) LCD panels. It also allows software to control scrolling display. Figure 5.10.1.1 shows the configuration of the LCD controller and Figure 5.10.1.2 shows an example how to connect external LCD drivers. The S1D16006 or S1D15700 are available for external segment drivers. Select the S1D16006 for cost down. The S1D15700 is better to reduce power. SR XRD XWR XCEIO Control registers LCDEN DOFF (CPU interface) EB0~EB7 A00~A15 LCDON FOSC1 FOSC3 PK PL Next display line starting address calculator LCD and CPU synchronization control LCD display timing control XSCL LP YD FR Display data control SD0~SD7 XCESEG CLKCHG DBS1 DBS0 LCD refresh address counter Display memory write control Buffer for writing display data Buffer for reading display data XVRD VPK VPL XVWR VA00~VA15 LCD and CPU address mux Display memory read control (Display memory interface) VEB0~VEB7 CPU address buffer Fig. 5.10.1.1 Configuration of LCD controller 88 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) S1D16305 or S1D16700 DI INH FR YSCL V1 V4 COM00 ~ LCD PANEL (100 x 240) COM99 ~ EO FR EI S1D16006 or S1D15700 ~ EO SD3 V2 V3 S1D16006 or S1D15700 SEG160~SEG239 YD DOFF LP XSCL SD0 ~ FR EI YD DOFF LP XSCL SD0 VSS EO SD3 V2 V3 S1D16006 or S1D15700 FR EI YD DOFF LP XSCL SD0 VDD SEG80~SEG159 SD3 V2 V3 SEG00~SEG79 VDD V0 R V1 R V2 R V3 R V4 R + + + + + ~ SD3 SD0 XSCL LP FR VSSH YD DOFF V5 S1C88409 Fig. 5.10.1.2 Connection example of external LCD drivers 5.10.2 Output signals This LCD controller outputs the following signals for controlling the S1D16305 (or S1D16700) common driver and the S1D16006 (or S1D15700) segment driver: LCDEN A LCD power control signal. It goes high level (VDD) or low level (VSS) according to the value set in the LCDEN register. Note: When the LCD drive voltage is supplied to the LCD panel before supplying the power voltage (VDD) to the S1C88409, the LCD panel may be damaged. To prevent this problem, design the circuit so that the LCD power is supplied to the LCD panel by switching the LCDEN signal to high level with the software. At initial reset, the LCDEN signal goes low level. This power control is also necessary when turning the S1C88409 off. Be sure to turn the LCD panel off before turning the S1C88409 off. DOFF A forced blank signal to turn the display off. Connect this signal to the INH terminal of the S1D16305 (or S1D16700) and the DOFF terminal of the S1D16006 (or S1D15700) and control the signal using the DISP register. XSCL A display data shift clock. Connect this signal to the XSCL terminal of the S1D16006 (or S1D15700). LP A display data latch pulse. Connect this signal to the YSCL terminal of the S1D16305 (or S1D16700) and the LP terminal of the S1D16006 (or S1D15700). YD A scan start pulse. Connect this signal to the DI terminal of the S1D16305 (or S1D16700) and the YD terminal of the S1D16006 (or S1D15700). FR A frame signal. Connect this signal to the FR terminals of the S1D16305 (or S1D16700) and S1D16006 (or S1D15700). SD0-SD7 Display data signals. SD0 to SD3 are used in the 4bit transfer mode. In the 8-bit transfer mode, SD0 to SD7 are all used. S1C88409 TECHNICAL MANUAL EPSON 89 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) 5.10.3 Display control To use the LCD controller, the following control procedures are necessary: Setup of the LCD controller (1) Selecting B&W or gray-scale mode This LCD controller has two display mode: B&W (black and white) mode and 4-level gray scale mode. Select either one according to the LCD panel to be used. See Section 5.10.4, "B&W mode and gray-scale mode setting", for more information. (2) Selecting the transfer data size Select the size of data to be transferred to the segment drivers. 8-bit transfer and 4-bit transfer are available in this LCD controller. Select 4-bit transfer when using the S1D16006 or S1D15700. See Section 5.10.9, "Data transfer", for more information. (3) Setting the LCD panel size and display start address To correspond the display memory bits to the LCD panel dots one to one, it is necessary to set the LCD panel size in the LCD controller. Also a display start address should be set. See Section 5.10.6, "LCD panel", for more information. (4) Setting the frame frequency The frame frequency can be selected from 16 frequencies according to the LCD panel to be used. See Section 5.10.6, "LCD panel", for more information. (5) Back light LCD panel Since this LCD controller can reverse display by the REV register (REV = "1"), set in reverse display when using an LCD panel with a back light. The REV register can also be used to reverse display during normal display. Turning display on and off Besides the LCDEN register, the DISP register is provided for forced blanking function. When "1" is written to the DISP register, the LCD panel displays data in the display memory. When "0" is written, the display goes out. The control signals are output to the external drivers during forced blanking. Data transfer control The data transfer method can be selected according to the segment driver to be used. See Section 5.10.9, "Data transfer", for more information. The data transfer uses the OSC3 clock. Therefore, turn the OSC3 oscillation on before writing "1" to the LCDEN register. Furthermore, wait 20 msec or more after turning the OSC3 oscillation on for stabilizing oscillation. Do not turn the OSC3 oscillation off during data transfer. 5.10.4 B&W and gray-scale mode setting This LCD controller has two display mode: B&W (black and white) mode and 4-level gray scale mode. Select either one with the GRAY register according to the LCD panel to be used. GRAY register = "0": B&W mode GRAY register = "1": Gray-scale mode In the B&W mode, the display memory bits correspond to the LCD panel dots one to one. When a memory bit is "0", the corresponding dot goes off and when the bit is"1", the dot goes on. In the gray-scale mode, each two bits of the display memory corresponds to an LCD panel dot. When a display data is 00B, the corresponding dot goes off. As for the display data 01B, 10B and 11B, the intensity (gray-scale conversion code) can be specified using the GS1, GS2 and GS3 registers (8 bits each), respectively. The specified gray-scale conversion code controls the 8 frame cycles for turning the dots on and off as shown in Figure 5.10.4.1. By writing "1" to the LCDEN register, the LCD controller turns on and starts outputting the signals to the external drivers. The content of the LCDEN register is output from the LCDEN terminal. Use the signal to control the LCD power supply. When "0" is written to the LCDEN register, the LCD controller stops operating. Note: The power of the LCD panel must be turned on/off while the LCDEN register is "1". Switching while the LCD controller is off (LCDEN = "0") may damage the LCD panel. 90 8 frames D0 0 D1 1 D2 0 D3 1 D4 1 D5 0 D6 1 D7 1 ON OFF (GSn = DAH) Fig. 5.10.4.1 Gray-scale conversion code See LCD panel examples in Section 5.10.6 for correspondence between the display memory data and dots. EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) 5.10.5 Display memory 5.10.6 LCD panel The S1C88409 has a 3.75KB of RAM built-in and the display memory is allocated in the RAM. The display memory size can be selected from seven types listed in Table 5.10.5.1 by mask option. FR frequency The FR (frame) signal is generated by dividing the OSC1 clock. The dividing ratio can be selected using the CKCN and POINT5 registers. Select one according to the LCD panel to be used so that it is not out of the permissible range. Table 5.10.5.1 Display memory size 1 2 3 4 5 6 7 Data memory 1792 bytes 00F800H-00FEFFH 1536 bytes 00F900H-00FEFFH 1280 bytes 00FA00H-00FEFFH 1024 bytes 00FB00H-00FEFFH 768 bytes 00FC00H-00FEFFH 512 bytes 00FD00H-00FEFFH 256 bytes 00FE00H-00FEFFH Display memory 2048 bytes 00F000H-00F7FFH 2304 bytes 00F000H-00F8FFH 2560 bytes 00F000H-00F9FFH 2816 bytes 00F000H-00FAFFH 3072 bytes 00F000H-00FBFFH 3328 bytes 00F000H-00FCFFH 3584 bytes 00F000H-00FDFFH Table 5.10.6.1 FR frequency setting CKCN2 CKCN1 CKCN0 POINT5 FR frequency 0 0 0 0 fOSC1/(SLT+1) fOSC1/1.5/(SLT+1) 0 0 0 1 fOSC1/2/(SLT+1) 0 0 1 0 fOSC1/2.5/(SLT+1) 0 0 1 1 fOSC1/3/(SLT+1) 0 1 0 0 fOSC1/3.5/(SLT+1) 0 1 0 1 0 0 1 1 1 1 1 1 1 1 Note: The display memory area configured by mask option may be used as data memory. However, the stack area cannot be assigned there. The required display memory size is calculated by the following expressions according to the LCD panel size: B&W LCD panel: Memory size = (number of horizontal dots / 8) x Number of vertical dots Gray-scale panel: Memory size = (number of horizontal dots / 4) x Number of vertical dots When using the vertical scroll function or virtual screen function, the display memory size should be increased for the scroll area or virtual area. Use the LCD panel examples in Sections 5.10.6 to 5.10.8 as reference for deciding the memory size. 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 fOSC1/4/(SLT+1) fOSC1/4.5/(SLT+1) fOSC1/5/(SLT+1) fOSC1/5.5/(SLT+1) fOSC1/6/(SLT+1) fOSC1/6.5/(SLT+1) fOSC1/7/(SLT+1) fOSC1/7.5/(SLT+1) fOSC1/8/(SLT+1) fOSC1/8.5/(SLT+1) Setting the panel size To correspond the display memory bits to the LCD panel dots one to one, it is necessary to set the LCD panel size in the LCD controller. The following registers should be used for this setting. LBC6-LBC0: Sets the number of bytes for one line of display data. Specify [Number of horizontal dots / 8] in the B&W mode or [Number of horizontal dots / 4] in the gray-scale mode. SLT7-SLT0: Sets the number of lines (number of vertical dots) of the LCD panel. SAD15-SAD0: Sets the display start address in the display memory. S1C88409 TECHNICAL MANUAL EPSON 91 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) LCD panel examples (1) 240 x 100 dot B&W panel Display memory setting 3072 byte memory size is selected by mask option (00F000H-00FBFFH) In the B&W mode, the display memory bits correspond to the LCD panel dots one to one. D6 0 D5 0 F000H D4 D3 1 0 LBC = 1EH D2 1 D1 1 D0 0 F000H F01EH F01DH F03BH SLT = 64H D7 1 Register settings LBC register: 1EH (240/8 = 30 bytes) SLT register: 64H (100 dots) SAD register: F000H 100 dots Display memory LCD panel 240 dots FBA4H FBB7H Fig. 5.10.6.1 Correspondence between LCD panel and display memory (2) 160 x 80 dot gray-scale panel Register settings LBC register: 28H (160/4 = 40 bytes) SLT register: 50H (80 dots) SAD register: F000H Display memory setting 3328 byte memory size is selected by mask option (00F000H-00FCFFH) In the gray-scale mode, each two bits of the display memory corresponds to an LCD panel dot. D6 1 D5 1 F000H D4 D3 0 0 LBC = 28H D2 1 D1 0 D0 0 F000H F028H F027H F04FH SLT = 50H 80 dots D7 1 Display memory LCD panel 160 dots FC58H FC7FH Fig. 5.10.6.2 Correspondence between LCD panel and display memory The above examples are basic settings. See Sections 5.10.7 and 5.10.8 for examples when using the vertical scroll and virtual memory functions. 92 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) 5.10.7 Vertical scroll function Note: When using the vertical scroll function, it is necessary to reserve the display memory for the scroll area in addition to the memory for the LCD panel size. Do not specify a display start address that cannot entirely display one screen (as exceeding the last display memory address in the middle of the LCD panel). Since the display start address is specified by the SAD register, vertical scroll can be done by increasing/decreasing the address by one line at a step. F200H F21EH A Line 1 2 3 F21DH F23BH Display memory 240 dots FB42H FB60H A: SAD = 00F200H B: SAD = 00F21EH 80 lines LCD panel (B&W) 80 lines 80 dots B 80 81 82 FB5FH FB7DH Fig. 5.10.7.1 Vertical scroll In normal display, the beginning address of a line follows the end address of the previous line. In this LCD controller, the interval between the addresses can be specified using the APADJ register in byte units. This function can configure a virtual screen larger than the actual display size as shown in Figure 5.10.8.1. By controlling the display start address with the SAD register, the screen can be scrolled horizontally in byte units (B&W: 8-dot units, gray-scale: 4-dot units) or any part of the virtual screen can be displayed. Furthermore, when a virtual screen with a two page size is assigned, the page can simply be switched. Note: When using the virtual screen function, enough display memory must be reserved for the screen size. Do not specify a display start address that cannot entirely display one screen (as exceeding the last display memory address in the middle of the LCD panel). APADJ = 10H, SAD = 00F110H Display memory F000H LBC = 14H F110H F134H F123H F147H 100 dots Display area FCA4H LCD panel (B&W) F133H F157H SLT = 64H 5.10.8 Virtual screen function FCB7H FCC7H APADJ = 10H, SAD = 00F111H Display memory F000H F111H F135H F124H F148H Display area FCA5H FCB8H SLT = 64H LBC = 14H 160 dots F134H F158H FCC8H Fig. 5.10.8.1 Virtual screen function S1C88409 TECHNICAL MANUAL EPSON 93 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) 5.10.9 Data transfer Data transfer method Transfer data size The LCD controller has three data transfer modes for sending data to the segment drivers. The transfer data size can be set to either 8 bits or 4 bits using the BITNO register. 4-bit data transfer only is available for the S1D16006 and S1D15700 drivers. (1) 4-bit data transfer (BITNO = "0") In 4-bit data transfer, data is sent as shown in Figure 5.10.9.1. Display memory D7 D6 D5 D4 D3 D2 D1 D0 xxxxH a b c d e f g h j k l m n o p xxxx+1H i : : : : : : : : : 1 2 3 4 : Data output terminal SD3 SD2 SD1 SD0 a b c d e f g h i j k l m n o p : : : : LCD panel (B&W) abcdefghijklmnop... Fig. 5.10.9.1 4-bit data transfer (2) 8-bit data transfer (BITNO = "1") In 8-bit data transfer, data is sent as shown in Figure 5.10.9.2. Display memory D7 D6 D5 D4 D3 D2 D1 D0 xxxxH a b c d e f g h xxxx+1H i j k l m n o p : : : : : : : : : (1) Continuous data refresh mode This mode is available for both the S1D16006 and S1D15700 segment drivers. The S1D16006 and the gray-scale display can be controlled only in this mode. The continuous data refresh mode is set by writing "1" to the S1606 register. It is also set at initial reset. In this mode, the display memory data is continuously sent to the segment driver in every frames while the LCDEN register is "1". Figures 5.10.9.3 to 5.10.9.5 show the timing charts in the continuous data refresh mode. (2) One-shot transfer mode (software control) This mode is available only for the S1D15700 segment driver and only in the B&W mode. The S1D16006 and the gray-scale display cannot use this mode. To set the one-shot transfer mode, write "0" to the S1606 and S1570A registers. When "1" is written to the LCDEN register, the LCD controller outputs only the FR, LP and YD signals for a self-refresh of the S1D15700. When updating the display, rewrite the display memory then write "1" to the S1570O register. The LCD controller outputs one-frame data in the frame cycle immediately after the writing. After that, the LCD controller outputs the FR, LP and YD signals only. This mode is best to reduce current consumption in the three transfer mode because data is transferred only when it is necessary. Figure 5.10.9.6 shows the timing chart in the one-shot transfer mode. The S1570O register, which is used for a trigger of the one-shot transfer, can be read as a status. After "1" is written to the S1570O register, the register maintains "1" until the data transfer has completed to indicate that the data transfer circuit is in busy status. A new data transfer cannot be started during this period (writing "1" to the S1570O register is ignored). Further this mode can generate an interrupt at the end of a data transfer (see the next section). When updating the display, check to see if the data transfer is possible using these functions. Data output terminal SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 b c d e f g h 1 a j k l m n o p 2 i : : : : : : : : : LCD panel (B&W) abcdefghijklmnop... Fig. 5.10.9.2 8-bit data transfer 94 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) (3) Hardware auto-transfer mode This mode is available only for the S1D15700 segment driver and only in the B&W mode. The S1D16006 and the gray-scale display cannot use this mode. To set the hardware auto-transfer mode, write "0" to the S1606 register and write "1" to the S1570A register. When "1" is written to the LCDEN register, the LCD controller outputs only the FR, LP and YD signals for a self-refresh of the S1D15700. When data is written to the display memory, the LCD controller outputs one-frame data in the frame cycle immediately after the writing. After that, the LCD controller outputs the FR, LP and YD signals only. This mode does not need other software controls because data is automatically transferred by only writing display data. This mode can reduce current consumption better than the continuous data refresh mode. However, display data is transferred even if data is written in the scroll area or virtual screen that are out of the display range. To avoid such a transfer or to write display data separately from display update, use the oneshot transfer with software control. Figure 5.10.9.7 shows the timing chart in the hardware auto-transfer mode. The data transfer status in this mode can be read from the S1570AS register. The S1570AS register maintains "1" during data transfer to indicate that the data transfer circuit is in busy status. It goes to "0" while the segment drivers are in self-refresh operation (the data transfer circuit is in standby status). LCDEN FR YD 1 2 3 (100) 1 2 3 LP 1 LP XSCL FOSC3 SD0~SD3 Line data Next line data Fig. 5.10.9.3 Data transfer in continuous data refresh mode (B&W, 4-bit transfer) LCDEN FR YD 1 2 3 (100) 1 2 3 LP 1 LP XSCL FOSC3 SD0~SD3 Line data Next line data Fig. 5.10.9.4 Data transfer in continuous data refresh mode (gray-scale, 4-bit transfer) S1C88409 TECHNICAL MANUAL EPSON 95 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) LCDEN FR YD 1 2 3 (100) 1 2 3 LP 1 LP XSCL FOSC3 SD0~SD7 Line data Next line data Fig. 5.10.9.5 Data transfer in continuous data refresh mode (B&W, 8-bit transfer) LCDEN FR LP S1570O (WR) S1570O (RD) XSCL Wait time Data transfer for 1 frame Wait time Data transfer for 1 frame SD0~SD3 Interrupt Fig. 5.10.9.6 Data transfer in one-shot transfer mode LCDEN S1570A FR LP Writing to display memory XSCL S1570AS Fig. 5.10.9.7 Data transfer in hardware auto-transfer mode 96 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) 5.10.10 Interrupt function The LCD controller can generate an interrupt when a software one-shot data transfer or a hardware auto transfer has completed. Figure 5.10.10.1 shows the configuration of the LCD controller interrupt circuit. When a one-shot data transfer has completed, the interrupt factor flag FLCD is set to "1" and an interrupt is generated. The interrupt can be disabled using the interrupt enable register ELCD corresponding to the interrupt factor flag. See Figure 5.10.9.6 for the interrupt timing. Data bus Address One-shot transfer completion Hardware auto transfer completion In addition, a priority level of the LCD controller interrupt for the CPU can be optionally set at levels 0 to 3 by the interrupt priority register PLCD. For details on the above mentioned interrupt control registers and the operation following an interrupt generation, see Section 5.20, "Interrupt and Standby Mode". The exception processing vector address of the interrupt factor is set as below. LCD controller interrupt: 000024H Interrupt priority register PLCD0, PLCD1 Interrupt factor flag FLCD Interrupt priority level judgment circuit Address Address Interrupt request Interrupt enable register ELCD Fig. 5.10.10.1 Configuration of LCD interrupt circuit S1C88409 TECHNICAL MANUAL EPSON 97 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) 5.10.11 I/O memory of LCD controller Table 5.10.11.1 shows the control bits of the LCD controller. Table 5.10.11.1(a) LCD controller control bits Address Bit 00FF60 D7 D6 D5 D4 D3 D2 Name Function DISP Display On/Off control REV Normal/Inverse display control CKCN2 Scanning line frequency selection CKCN2 CKCN1 CKCN0 POINT5 0 0 0 0 0 0 0 1 0 0 1 0 CKCN1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 CKCN0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 POINT5 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 On Inverse Frequency fOSC1 fOSC1 / 1.5 fOSC1 / 2 fOSC1 / 2.5 fOSC1 / 3 fOSC1 / 3.5 fOSC1 / 4 fOSC1 / 4.5 fOSC1 / 5 fOSC1 / 5.5 fOSC1 / 6 fOSC1 / 6.5 fOSC1 / 7 fOSC1 / 7.5 fOSC1 / 8 fOSC1 / 8.5 D1 GRAY Gray/B&W mode selection D0 BITNO 8-bit/4-bit transfer selection 00FF61 D7 - - D6 - - D5 - - D4 S1570AS Hardware auto-transfer status D3 LCDEN LCD power On/Off control D2 S1570A Hardware auto-transfer control D1 S1570O One-shot transfer trigger/status D0 00FF62 D7 D6 D5 D4 D3 D2 D1 D0 00FF63 D7 D6 D5 D4 D3 D2 D1 D0 00FF64 D7 D6 D5 D4 D3 D2 D1 D0 00FF65 D7 D6 D5 D4 D3 D2 D1 D0 98 S1606 - LBC6 LBC5 LBC4 LBC3 LBC2 LBC1 LBC0 SAD7 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 SAD15 SAD14 SAD13 SAD12 SAD11 SAD10 SAD9 SAD8 SLT7 SLT6 SLT5 SLT4 SLT3 SLT2 SLT1 SLT0 Continuous refresh transfer control - Number of bytes per display line Display start address (lower 8 bits) Display start address (upper 8 bits) Total display lines 0 Off Normal D6(MSB) D5 D4 D3 D2 D1 D0(LSB) D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EPSON Init 0 0 0 R/W R/W R/W R/W Comment 0 R/W 0 R/W 0 R/W Gray 8 bits - - - Busy On On Busy Trigger On - B&W 4 bits - - - Standby Off Off Standby Invalid Off - High Low High Low High Low High Low 0 0 - - - 0 0 0 0 0 1 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W - "0" when being read - - R R/W R/W R W R/W - "0" when being read R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) Table 5.10.11.1(b) LCD controller control bits Address Bit Name Function 00FF66 D7 - - D6 - - D5 - - D4 - - D3 - - D2 - - D1 - - D0 SLT8 Total display lines (MSB) 00FF67 D7 APADJ7 Address pitch adjustment D6 APADJ6 D5 APADJ5 D4 APADJ4 D3 APADJ3 D2 APADJ2 D1 APADJ1 D0 APADJ0 00FF68 D7 GS17 Gray scale (0,1) conversion code D6 GS16 D5 GS15 D4 GS14 D3 GS13 D2 GS12 D1 GS11 D0 GS10 00FF69 D7 GS27 Gray scale (1,0) conversion code D6 GS26 D5 GS25 D4 GS24 D3 GS23 D2 GS22 D1 GS21 D0 GS20 00FF6A D7 GS37 Gray scale (1,1) conversion code D6 GS36 D5 GS35 D4 GS34 D3 GS33 D2 GS32 D1 GS31 D0 GS30 00FF21 D7 PTM21 8-bit programmable timer D6 PTM20 interrupt priority register D5 PSI1 Serial interface D4 PSI0 interrupt priority register D3 PCTM1 Clock timer D2 PCTM0 interrupt priority register D1 PLCD1 LCD controller D0 PLCD0 interrupt priority register 00FF25 D7 ET60S Clock timer 60 S interrupt enable register D6 ECTM1 Clock timer 1 Hz interrupt enable register D5 ECTM2 Clock timer 2 Hz interrupt enable register D4 ECTM8 Clock timer 8 Hz interrupt enable register D3 ECTM32 Clock timer 32 Hz interrupt enable register D2 ELCD LCD controller interrupt enable register D1 - - D0 - - 00FF29 D7 FT60S Clock timer 60 S interrupt factor flag D6 FCTM1 Clock timer 1 Hz interrupt factor flag D5 FCTM2 Clock timer 2 Hz interrupt factor flag D4 FCTM8 Clock timer 8 Hz interrupt factor flag D3 FCTM32 Clock timer 32 Hz interrupt factor flag D2 FLCD LCD controller interrupt factor flag D1 - - D0 - - S1C88409 TECHNICAL MANUAL D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 EPSON 1 - - - - - - - High 0 - - - - - - - Low High Low High Low High Low High Low PTM21 PTM20 PSI1 PSI0 PCTM1 PCTM0 Priority level PLCD1 PLCD0 Level 3 1 1 Level 2 1 0 Level 1 0 1 Level 0 0 0 Interrupt is enabled Interrupt is disabled (R) Interrupt factor has generated (R) Interrupt factor has not generated (W) Reset (W) Invalid Init - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - R/W Comment - "0" when being read - - - - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) - "0" when being read - 99 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) GRAY: Gray-scale/B&W mode selection register (00FF60H*D1) Selects the gray-scale mode or B&W mode. DISP: Display ON/OFF control register (00FF60H*D7) Turns the display on and off. When "1" is written: ON When "0" is written: OFF Reading: Valid When "1" is written: Gray-scale mode When "0" is written: B&W mode Reading: Valid When "1" is written to the DISP register, the DOFF terminal goes low and when "0" is written, the DOFF terminal goes high. This signal controls the external driver to turn the display on and off. At initial reset, the DISP register is set to "0" (OFF). REV: Normal/reverse display control register (00FF60H*D6) Controls reverse display. BITNO: 8-bit/4-bit transfer selection register (00FF60H*D0) Set the transfer data size. When "1" is written: Reverse display When "0" is written: Normal display Reading: Valid When "1" is written to the REV register, the display reverses and when "0" is written, it returns to the normal. When using an LCD panel with a back light, the setting reverses. At initial reset, the REV register is set to "0" (normal). POINT5, CKCN0-CKCN2: Scanning line frequency selection register (00FF60H*D2-D5) Selects a scanning line frequency from 16 types as shown in Table 5.10.11.2. Table 5.10.11.2 Selection of scanning line frequency CKCN2 CKCN1 CKCN0 POINT5 Frequency 0 0 0 0 fOSC1 0 0 0 1 fOSC1/1.5 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 fOSC1/2 fOSC1/2.5 fOSC1/3 fOSC1/3.5 fOSC1/4 fOSC1/4.5 fOSC1/5 fOSC1/5.5 fOSC1/6 fOSC1/6.5 fOSC1/7 fOSC1/7.5 fOSC1/8 fOSC1/8.5 When "1" is written: 8 bits When "0" is written: 4 bits Reading: Valid BITNO sets the size of data to be transferred to the segment drivers. When "1" is written to the BITNO register, 8-bit transfer is set and when "0" is written, 4-bit transfer is set. The 4-bit transfer uses the data output terminals SD0 to SD3 only. When using S1606 or S1570 as the segment driver, fix this register at "0". When the gray-scale mode is selected, 4-bit transfer only is available regardless of the BITNO register setting. At initial reset, the BITNO register is set to "0" (4 bits). LCDEN: LCD power control register (00FF61H*D3) Controls the power of the LCD controller. When "1" is written: ON When "0" is written: OFF Reading: Valid The frame frequency is set as "scanning frequency / (SLT+1)". At initial reset, these registers are set to "0" (fOSC1). 100 When "1" is written to the GRAY register, the grayscale mode is set and it displays a dot with 2 bits of the display memory. When "0" is written, the B&W mode is set and each bit of the display memory corresponds to a dot on the LCD panel one to one. At initial reset, the GRAY register is set to "0" (B&W mode). When "1" is written to the LCDEN register, the power of the LCD controller turns on and when "0" is written, it turns off. The LCDEN terminal goes high while the LCDEN register is "1" and goes low while the register is "0". Use this signal for controlling the power of the LCD panel so that the LCD panel does not turn on while the LCDEN is "0". At initial reset, the LCDEN register is set to "0" (OFF). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) When using other transfer modes, fix this register at "0". This transfer mode cannot be selected when using the S1606 segment driver and/or in grayscale mode. At initial reset, the S1570A register is set to "0" (OFF). S1606: Continuous refresh transfer selection register (00FF61H*D0) Sets the continuous refresh transfer mode. When "1" is written: ON When "0" is written: OFF Reading: Valid When "1" is written to the S1606 register, the continuous refresh transfer mode is set. In this mode, the display data is transferred to the segment drivers while the LCDEN register is "1". When using the S1606 segment driver and/or in gray-scale mode, fix this register at "1". When using other transfer mode, fix this register at "0". At initial reset, the S1606 register is set to "1" (ON). S1570O: One-shot transfer trigger/status (00FF61H*D1) Starts one-shot transfer and indicates the transfer status. When "1" is written: Trigger When "0" is written: Invalid When "1" is read: Busy When "0" is read: Standby By writing "1" to S1570O after rewriting the display memory, the LCD controller sends the display data to the segment drivers to update the display. Writing "0" and writing "1" during data transfer are invalid. S1570O also indicates the status of the data transfer circuit when reading. It goes "1" during data transfer and goes "0" in standby status. S1570O cannot be used for transferring data when using the S1606 segment driver and/or in grayscale mode. At initial reset, S1570O is set to "0" (standby). S1570A: Hardware auto-transfer control register (00FF61H*D2) Sets the hardware auto-transfer mode. When "1" is written: ON When "0" is written: OFF Reading: Valid When "1" is written to the S1570A register, the hardware auto-transfer mode is set. In this mode, the hardware automatically sends the display data to the segment drivers by writing data to the display memory while the LCDEN register is "1". S1C88409 TECHNICAL MANUAL S1570AS: Hardware auto-transfer status (00FF61H*D4) Indicates the hardware auto-transfer status. When "1" is read: Busy When "0" is read: Standby Writing: Invalid S1570AS indicates the status of the data transfer circuit; it goes "1" during hardware auto-transfer and "0" in standby status. S1570AS is a read only bit, so writing is invalid. At initial reset, S1570AS is set to "0" (standby). LBC0-LBC6: Horizontal LCD panel size setting register (00FF62H*D0-D6) The display line size should be specified as the number of bytes with this register. Specify [Number of dots / 8] in the B&W mode or [Number of dots / 4] in the gray-scale mode. At initial reset, the LBC register is set to "00H". SLT0-SLT8: Vertical LCD panel size setting register (00FF65H, 00FF66H*D0) Number of display lines (vertical dot number) should be specified with this register. At initial reset, the SLT register is set to "000H". SAD0-SAD15: Display start address setting register (00FF63H, 00FF64H) Specifies the display memory address that contains the data to be displayed at the first dot of the LCD panel. By changing this address successively, the screen scrolls. At initial reset, the SAD register is set to "0000H". APADJ0-APADJ7: Address pitch adjustment register (00FF67H) Specifies the address pitch between lines as number of bytes. After a line has been displayed, the specified number of addresses in the display memory are skipped and the next line begins from the following address. At initial reset, the APADJ register is set to "00H". EPSON 101 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) GS10-GS17: Gray-scale (0, 1) conversion code setting register (00FF68H) GS20-GS27: Gray-scale (1, 0) conversion code setting register (00FF69H) GS30-GS37: Gray-scale (1, 1) conversion code setting register (00FF6AH) Sets the gray-scale conversion code. The GS1, GS2 and GS3 registers correspond to gray levels 01B, 10B and 11B, respectively. Each register specifies a display pattern for eight frame cycles, thus the intensity of each gray level can be set. D0 to D7 in the register control dots on (1) and off (0) in each frame cycle. At initial reset, the GS register is set to "00H" (OFF). PLCD0, PLCD1: LCD controller interrupt priority register (00FF21H*D0, D1) Sets the priority level of the LCD controller interrupt. Table 5.10.11.3 shows the interrupt priority level which can be set by the PLCD register. Table 5.10.11.3 Interrupt priority level settings PLCD0 1 1 0 0 1 0 1 0 Interrupt priority level Level 3 Level 2 Level 1 Level 0 When "1" is read: Int. factor has generated When "0" is read: Int. factor has not generated When "1" is written: Factor flag is reset When "0" is written: Invalid When "1" is written: Dot goes ON When "0" is written: Dot goes OFF Reading: Valid PLCD1 FLCD: LCD controller interrupt factor flag (00FF29H*D2) Indicates the generation of LCD controller interrupt factor. (IRQ3) (IRQ2) (IRQ1) (None) FLCD is the interrupt factor flag corresponding to the LCD controller interrupt. It is set to "1" when a software one-shot data transfer or a hardware auto transfer has completed. At this point, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I0 and I1), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "1" when the interrupt generation condition is met. To accept the subsequent interrupt after an interrupt generation, it is necessary to reset the interrupt flag (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "0" by writing "1". At initial reset, the FLCD flag is reset to "0". At initial reset, the PLCD register is set to "0" (level 0). ELCD: LCD controller interrupt enable register (00FF25H*D2) Enables or disables the LCD controller interrupt generation to the CPU. When "1" is written: Interrupt is enabled When "0" is written: Interrupt is disabled Reading: Valid The ELCD register is the interrupt enable register corresponding to the LCD controller interrupt factor. When this register is set to "1", the interrupt is enabled, and when it is set to "0", the interrupt is disabled. At initial reset, the ELCD register is set to "0" (interrupt is disabled). 102 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (LCD Controller) 5.10.12 Programming notes (1) Do not write "0" to the LCDEN register while the LCD panel is ON. The LCD panel may be damaged. (2) Only the 4-bit continuous data refresh mode is available in the gray-scale mode. Do not use 8bit data transfer or another transfer mode. (3) The data transfer uses the OSC3 clock. Therefore, turn the OSC3 oscillation on before writing "1" to the LCDEN register. Furthermore, wait 20 msec or more after turning the OSC3 oscillation on for stabilizing oscillation. In the one-shot transfer mode or hardware auto-transfer mode, do not turn the OSC3 oscillation off before finishing data transfer. When the segment driver is in self-refresh status, the OSC3 oscillation can be stopped to reduce current consumption. (4) When setting the CPU in SLEEP status, be sure to turn the LCD panel power off and stop operation of the LCD controller. S1C88409 TECHNICAL MANUAL EPSON 103 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 5.11.2 Interrupt function 5.11 Clock Timer The clock timer can generate an interrupt by each of the 32 Hz, 8 Hz, 2 Hz and 1 Hz signals or when the 60-second counter overflows. Figure 5.11.2.1 shows the configuration of the clock timer interrupt circuit. 5.11.1 Configuration of clock timer The S1C88409 has a built-in clock timer that uses the OSC1 oscillation circuit as the clock source. The clock timer is composed of an 8-bit binary counter that inputs a 256 Hz clock divided from fOSC1 and a 7-bit BCD counter for counting up to 60 seconds. The 128-1 Hz and 0-60 second counter data can be read by software. The 60-second counter can preset data. Ordinarily, this clock timer is used for various timing functions such as clocks. Figure 5.11.1.1 shows the configuration of the clock timer. The interrupt factor flags FCTM32, FCTM8, FCTM2 and FCTM1 are set to "1" at the falling edge of the 32 Hz, 8 Hz, 2 Hz and 1 Hz signals, respectively. At that point, the interrupt is generated. When the 60-second counter overflows, FT60S is set to "1" to generate the 60S interrupt. The interrupt can also be prohibited by setting the interrupt enable registers ECTM32, ECTM8, ECTM2, ECTM1 and ET60S corresponding to the interrupt factor flags. Furthermore, the priority level of the input interrupt for the CPU can be set in an optional level (0-3) using the interrupt priority register PCTM (two bits). Data bus Clock timer OSC1 256 Hz 128 64 fOSC1 Prescaler oscillation Hz Hz circuit TMD0~TMD7 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 60-second counter 1 Hz 1 sec BCD TMMD0 ~TMMD6 10 sec BCD 60S TMRUN Clock timer Run/Stop Interrupt control circuit TMRST Preset Fig. 5.11.1.1 Configuration of clock timer Address 32 Hz falling edge Address Address 8 Hz falling edge Address Address Data bus Reset Reset TMMDW Writing data to TMMD Interrupt request 2 Hz falling edge Address Address 1 Hz falling edge Address Address 60S counter overflow Address Address Interrupt priority register PCTM0, PCTM1 Interrupt factor flag FCTM32 Interrupt enable register ECTM32 Interrupt factor flag FCTM8 Interrupt enable register ECTM8 Interrupt factor flag FCTM2 Interrupt enable register ECTM2 Interrupt priority level judgment circuit Interrupt request Interrupt factor flag FCTM1 Interrupt enable register ECTM1 Interrupt factor flag FT60S Interrupt enable register ET60S Fig. 5.11.2.1 Configuration of clock timer interrupt circuit 104 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Refer to Section 5.20, "Interrupt and Standby Mode", for details of the interrupt control registers and operations subsequent to interrupt generation. The exception processing vector address for the clock timer interrupt is set to 000028H. Figures 5.11.2.2 and 5.11.2.3 show the timing chart for the clock timer. fOSC1/128 256 Hz TMD0 128 Hz TMD1 64 Hz TMD2 32 Hz TMD3 16 Hz TMD4 8 Hz TMD5 4 Hz TMD6 2 Hz TMD7 1 Hz 32 Hz interrupt 8 Hz interrupt 2 Hz interrupt 1 Hz interrupt Fig. 5.11.2.2 Timing chart of clock timer (128 Hz-1 Hz) TMD7 1 Hz TMMD writing 50 sec (TMMD=50H) is preset TMMD6-4 (10 sec BCD) TMMD3-0 (1 sec BCD) 5 0 1 2 3 4 0 5 6 7 8 9 0 1 60S interrupt Fig. 5.11.2.3 Timing chart of clock timer (60-second counter) S1C88409 TECHNICAL MANUAL EPSON 105 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 5.11.3 I/O memory of clock timer Table 5.11.3.1 shows the clock timer control bits. Table 5.11.3.1 Clock timer control bits Address Bit Name Function 00FF21 D7 PTM21 8-bit programmable timer D6 PTM20 interrupt priority register D5 PSI1 Serial interface D4 PSI0 interrupt priority register D3 PCTM1 Clock timer D2 PCTM0 interrupt priority register D1 PLCD1 LCD controller D0 PLCD0 interrupt priority register 00FF25 D7 ET60S Clock timer 60 S interrupt enable register D6 ECTM1 Clock timer 1 Hz interrupt enable register D5 ECTM2 Clock timer 2 Hz interrupt enable register D4 ECTM8 Clock timer 8 Hz interrupt enable register D3 ECTM32 Clock timer 32 Hz interrupt enable register D2 ELCD LCD controller interrupt enable register D1 - - D0 - - 00FF29 D7 FT60S Clock timer 60 S interrupt factor flag D6 FCTM1 Clock timer 1 Hz interrupt factor flag D5 FCTM2 Clock timer 2 Hz interrupt factor flag D4 FCTM8 Clock timer 8 Hz interrupt factor flag D3 FCTM32 Clock timer 32 Hz interrupt factor flag D2 FLCD LCD controller interrupt factor flag D1 - - D0 - - 00FF50 D7 - - D6 - - D5 - - D4 - - D3 - - D2 - - D1 TMRST Clock timer reset D0 TMRUN Clock timer RUN/STOP 00FF51 D7 TMD7 Clock timer data 1 Hz D6 TMD6 Clock timer data 2 Hz D5 TMD5 Clock timer data 4 Hz D4 TMD4 Clock timer data 8 Hz D3 TMD3 Clock timer data 16 Hz D2 TMD2 Clock timer data 32 Hz D1 TMD1 Clock timer data 64 Hz D0 TMD0 Clock timer data 128 Hz 00FF52 D7 - - D6 TMMD6 Clock timer data 10 sec (BCD) D5 TMMD5 D4 TMMD4 D3 TMMD3 Clock timer data 1 sec (BCD) D2 TMMD2 D1 TMMD1 D0 TMMD0 106 EPSON 1 0 Init R/W Comment PTM21 PTM20 0 R/W PSI1 PSI0 0 R/W PCTM1 PCTM0 Priority 0 R/W level PLCD1 PLCD0 0 R/W Level 3 0 R/W 1 1 Level 2 0 R/W 1 0 Level 1 0 R/W 0 1 Level 0 0 R/W 0 0 0 R/W 0 R/W 0 R/W Interrupt is Interrupt is 0 R/W enabled disabled 0 R/W 0 R/W - - "0" when being read - - (R) (R) 0 R/(W) Interrupt Interrupt 0 R/(W) factor has factor has not 0 R/(W) generated generated 0 R/(W) 0 R/(W) (W) (W) 0 R/(W) Reset Invalid - - "0" when being read - - - - - - "0" when being read - - - - - - - - - - - - - - - - - - - - Reset Invalid - W Run Stop 0 R/W 0 R 0 R 0 R 0 R High Low 0 R 0 R 0 R 0 R - - - - "0" when being read 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) The clock timer starts counting by writing "1" to the TMRUN register and stops by writing "0". In STOP status, the count data is maintained until the timer is reset or is set in the next RUN status. Also, when STOP status changes to RUN status, the data that was maintained can be used for resuming the count. At initial reset, the TMRUN register is set to "0" (STOP). TMD0-TMD7: Clock timer data (00FF51H) The clock timer data (128 Hz-1 Hz) can be read. Correspondence between TMD bit and frequency is as follows: TMD0: 128 Hz TMD1: 64 Hz TMD2: 32 Hz TMD3: 16 Hz TMD4: 8 Hz TMD5: 4 Hz TMD6: 2 Hz TMD7: 1 Hz Since TMD is read only, the writing operation is invalid. At initial reset, the timer data is set to "00H". TMMD0-TMMD6: 60-second counter data (00FF52H*D0-D6) The 60-second counter data can be read. Correspondence between TMMD bit and data is as follows: TMMD6-TMMD4: TMMD3-TMMD0: PCTM0, PCTM1: Clock timer interrupt priority register (00FF21H*D2, D3) Sets the priority level of the clock timer interrupt. The PCTM register is the interrupt priority register corresponding to the clock timer interrupt. Table 5.11.3.2 shows the interrupt priority level which can be set by this register. Table 5.11.3.2 Interrupt priority level settings 10 sec BCD data 1 sec BCD data When data is written to the TMMD register, it is preset to the 60-second counter. At the same time, the timer for 128 Hz to 1 Hz is also reset. The counter is preset only when data is written to the TMMD register. The register does not maintain the preset data and returns to 0-second when the counter overflows. To prevent the counter from abnormal operation, do not preset data without a range of 0 to 59 (BCD). At initial reset, the counter data is set to "0". TMRST: Clock timer reset (00FF50H*D1) Resets the clock timer. When "1" is written: Clock timer reset When "0" is written: No operation Reading: Always "0" The clock timer TMD and the 60S counter TMMD are reset by writing "1" to TMRST. When the clock timer is reset in RUN status, it restarts immediately after resetting. In the case of STOP status, the reset data "00H" is maintained. No operation results when "0" is written to TMRST. TMRST is write only, and so it is always "0" at reading. TMRUN: Clock timer RUN/STOP control register (00FF50H*D0) Controls RUN/STOP of the clock timer. PCTM1 PCTM0 1 1 0 0 1 0 1 0 Interrupt priority level Level 3 Level 2 Level 1 Level 0 (IRQ3) (IRQ2) (IRQ1) (None) At initial reset, the PCTM register is set to "0" (level 0). ECTM32: Clock timer 32 Hz interrupt enable register (00FF25H*D3) ECTM8: Clock timer 8 Hz interrupt enable register (00FF25H*D4) ECTM2: Clock timer 2 Hz interrupt enable register (00FF25H*D5) ECTM1: Clock timer 1 Hz interrupt enable register (00FF25H*D6) ET60S: Clock timer 60S interrupt enable register (00FF25H*D7) Enables or disables the interrupt generation to the CPU. When "1" is written: Interrupt is enabled When "0" is written: Interrupt is disabled Reading: Valid ECTM32, ECTM8, ECTM2, ECTM1 and ET60S are the interrupt enable registers corresponding to 32 Hz, 8 Hz, 2 Hz, 1 Hz and 60S interrupt factors. Interrupt of the frequency in which the ECTM register is set to "1" is enabled, and the others in which the ECTM register is set to "0" are disabled. At initial reset, the interrupt enable registers are all set to "0" (interrupt is disabled). When "1" is written: RUN When "0" is written: STOP Reading: Valid S1C88409 TECHNICAL MANUAL EPSON 107 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) FCTM32: Clock timer 32 Hz interrupt factor flag (00FF29H*D3) FCTM8: Clock timer 8 Hz interrupt factor flag (00FF29H*D4) FCTM2: Clock timer 2 Hz interrupt factor flag (00FF29H*D5) FCTM1: Clock timer 1 Hz interrupt factor flag (00FF29H*D6) FT60S: Clock timer 60S interrupt factor flag (00FF29H*D7) Indicates the generation of clock timer interrupt factor. When "1" is read: Int. factor has generated When "0" is read: Int. factor has not generated (1) The clock timer actually entqzs into RUN or STOP status at the falling edge of the 256 Hz signal after writing to the TMRUN register. Consequently, when "0" is written to TMRUN, the timer stops after counting once more (+1). TMRUN is read as "1" until the timer actually stops. Figure 5.11.4.1 shows the timing chart at the RUN/STOP control. 256 Hz TMRUN (RD) TMRUN (WR) When "1" is written: Factor flag is reset When "0" is written: Invalid TMDX FCTM32, FCTM8, FCTM2 and FCTM1 are the interrupt factor flags corresponding to the 32 Hz, 8 Hz, 2 Hz and 1 Hz interrupt, and are set to "1" at the falling edge of the respective signals. FT60S is the interrupt factor flag corresponding to the 60S interrupt and is set to "1" due to an overflow of the 60-second counter. At this point, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I0 and I1), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "1" when the interrupt generation condition is met. To accept the subsequent interrupt after an interrupt generation, it is necessary to re-set the interrupt flags (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "0" by writing "1". At initial reset, the interrupt factor flags are all reset to "0". 108 5.11.4 Programming notes 57H 58H 59H 5AH 5BH 5CH Fig. 5.11.4.1 Timing chart at RUN/STOP control (2) The 60-second counter is preset only when data is written to the TMMD register. The register does not maintain the preset data and returns to 0-second when the counter overflows. To prevent the counter from abnormal operation, do not preset data without a range of 0 to 59 (BCD). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) Two 8-bit down counters, two reload data registers (RDR0, RDR1) and the compare data registers (CDR0, CDR1) corresponding to each down counter are arranged in the 16-bit programmable timer. The reload data register is used to set an initial value to the down counter. The compare data register stores data for comparison with the content of the down counter. By setting these registers, a TOUT signal is generated, and it can be output to external devices. 5.12 16-bit Programmable Timer 5.12.1 Configuration of 16-bit programmable timer The S1C88409 has a 16-bit programmable timer built-in. The timer consists of a 16-bit presettable down counter, and can be used as 16-bit x 1 channel or 8-bit x 2 channels of programmable timer. Furthermore, they function as event counters using the input port terminal. Figure 5.12.1.1 shows the configuration of the 16bit programmable timer. Timer 0 fOSC3/fOSC1 Input port Prescaler/clock control circuit INCL00 EXCL00 Clock selection circuit 8-bit reload data register (RDR0) 8-bit down counter (PTM0) Clock output Underflow Clock output circuit TOUT0 Comparator Compare match Control circuit Underflow interrupt Compare match interrupt 8-bit compare data register (CDR0) Interrupt circuit Data bus Timer 0 control registers Underflow signal Timer 1 fOSC3/fOSC1 Input port Prescaler/clock control circuit INCL01 EXCL01 Clock selection circuit 8-bit reload data register (RDR1) 8-bit down counter (PTM1) Clock output Underflow Clock output circuit TOUT1 Comparator Compare match Control circuit Underflow interrupt Compare match interrupt 8-bit compare data register (CDR1) Interrupt circuit Timer 1 control registers Fig. 5.12.1.1 Configuration of 16-bit programmable timer S1C88409 TECHNICAL MANUAL EPSON 109 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) 5.12.2 Operation mode The 16-bit programmable timer can be used as two channels of 8-bit timers or one channel of 16-bit timer. Two kinds of operation modes are provided corresponding to this configuration, and it can be selected by the 8-/16-bit mode selection register MODE16. MODE16 register = "0": 8-bit mode (8 bits x 2 channels) MODE16 register = "1": 16-bit mode (16 bits x 1 channel) In the 8-bit mode, Timer 0 and Timer 1 can be controlled individually. In the 16-bit mode, the underflow signal of Timer 0 is used as the input clock of Timer 1 so that the down counters operate as a 16-bit counter. The timer in the 16-bit mode is controlled with the control registers for Timer 0 except for the clock output. Figure 5.12.2.1 shows the timer configuration depending on the operation mode and Table 5.12.2.1 shows the configuration of the control registers. [8-bit mode] [16-bit mode] 8-bit data Low-order 8-bit data Timer 0 input clock Timer 0 Interrupt request Timer 0 input clock Timer 0 Timer 1 input clock Timer 1 Interrupt request Timer 0 underflow signal Timer 1 8-bit data Interrupt request High-order 8-bit data Fig. 5.12.2.1 Counter configuration in 8- and 16-bit mode Table 5.12.2.1(a) Control registers in 8-bit mode Address Bit Name 00FF30 D7 MODE16 D6 - D5 - D4 - D3 PTOUT0 D2 PTRUN0 D1 PSET0 D0 CKSEL0 00FF31 D7 - D6 - D5 - D4 - D3 PTOUT1 D2 PTRUN1 D1 PSET1 D0 CKSEL1 Function 16-bit PTM 8-/16-bit mode selection - - - 16-bit PTM0 clock output control 16-bit PTM0 RUN/STOP control 16-bit PTM0 preset 16-bit PTM0 input clock selection - - - - 16-bit PTM1 clock output control 16-bit PTM1 RUN/STOP control 16-bit PTM1 preset 16-bit PTM1 input clock selection 1 0 Init R/W Comment 16-bit 8-bit x 2 0 R/W - - - - "0" when being read - - - - "0" when being read - - - - "0" when being read On Off 0 R/W Run Stop 0 R/W Preset Invalid 0 W "0" when being read External clock Internal clock 0 R/W - - - - "0" when being read - - - - "0" when being read - - - - "0" when being read - - - - "0" when being read On Off 0 R/W Run Stop 0 R/W Preset Invalid 0 W "0" when being read External clock Internal clock 0 R/W Table 5.12.2.1(b) Control registers in 16-bit mode Address Bit Name 00FF30 D7 MODE16 D6 - D5 - D4 - D3 PTOUT0 D2 PTRUN0 D1 PSET0 D0 CKSEL0 00FF31 D7 - D6 - D5 - D4 - D3 PTOUT1 D2 PTRUN1 D1 PSET1 D0 CKSEL1 110 Function 16-bit PTM 8-/16-bit mode selection - - - Invalid (fixed at "0") 16-bit PTM RUN/STOP control 16-bit PTM preset 16-bit PTM input clock selection - - - - 16-bit PTM clock output control Invalid (fixed at "0") Invalid (fixed at "0") Invalid (fixed at "0") 1 16-bit - - - Invalid Run Preset External clock - - - - On Invalid Invalid Invalid EPSON 0 Init R/W Comment 8-bit x 2 0 R/W - - - "0" when being read - - - "0" when being read - - - "0" when being read Fixed at "0" 0 R/W Stop 0 R/W Invalid 0 W "0" when being read Internal clock 0 R/W - - - "0" when being read - - - "0" when being read - - - "0" when being read - - - "0" when being read Off 0 R/W Fixed at "0" 0 R/W Fixed at "0" 0 W "0" when being read Fixed at "0" 0 R/W S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) 5.12.3 Setting of input clock 5.12.4 Operation and control of timer The clock to be input to the counter can be selected from either the internal clock or external clock by the input clock selection register (CKSEL) provided for each timer. The internal clock is an output of the prescaler. The external clock is used for the event counter function. A signal from the input port is used as the count clock. Table 5.12.3.1 shows the input clock selection register and input clock of each timer. Reload data register and setting of initial value Table 5.12.3.1 Input clock selection Timer Register setting Input clock Timer 0 CKSEL0 = "0" CKSEL0 = "1" INCL00 (Prescaler) EXCL00 (K10 input) Timer 1 CKSEL1 = "0" CKSEL1 = "1" INCL01 (Prescaler) EXCL01 (K11 input) The reload data register can be read and written, and both the RDR0 and RDR1 registers are set to FFH at initial reset. When the internal clock is used, the clock frequency is set by selecting a source clock and a division ratio of the prescaler. When the external clock is selected, a signal from the input port is directly input to the programmable timer. However, it is necessary to control the output from the clock control circuit and to input the internal clock and external clock to the timers. Refer to Section 5.5, "Prescaler and Clock Control Circuit for Peripheral Circuits", for selection of the division ratio and clock output control. When the 16-bit mode is selected, the programmable timer operates with the clock input to Timer 0, and Timer 1 inputs the Timer 0 underflow signal as the clock. Therefore, the setting of Timer 1 input clock is invalid. S1C88409 TECHNICAL MANUAL The reload data register (RDR) is used to set an initial value of the down counter. In the 8-bit mode, it is used as two 8-bit registers RDR0 (Timer 0) and RDR1 (Timer 1) separate for each timer. In the 16-bit mode, the RDR0 register is handled as low-order 8 bits of reload data, and the RDR1 register is as high-order 8 bits. Data written in this register is loaded into the down counter, and a down counting starts from the value. The preset to down counter is done in the following two cases: 1) When software presets The software preset can be done using the preset control bits PSET0 (Timer 0) and PSET1 (Timer 1). When the preset control bit is set to "1", the content of the reload data register is loaded into the down counter at that point. In the 16-bit mode, a 16-bit reload data is loaded all at one time by setting PSET0. In this case, writing to PSET1 is invalid. 2) When down counter has underflowed during a count Since the down counter presets the reload data by the underflow, the underflow period is decided according to the value set in the reload data register. This underflow generates an interrupt, and controls the clock (TOUT signal) output. EPSON 111 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) Compare data register The programmable timer has a built-in data comparator so that count data can be compared with an optional value. The compare data register (CDR) is used to set the value to be compared. In the 8-bit mode, it is used as two 8-bit registers CDR0 (Timer 0) and CDR1 (Timer 1) separate for each timer. In the 16-bit mode, the CDR0 register is handled as low-order 8 bits of compare data, and the CDR1 register is as high-order 8 bits. The compare data register can be read and written, and both the CDR0 and CDR1 registers are set to 00H at initial reset. The programmable timer compares count data with the compare data register (CDR), and generates a compare match signal when they become the same value. This compare match signal generates an interrupt, and controls the clock (TOUT signal) output. Timer operation Timer 0 and Timer 1 are equipped with PTRUN0 (Timer 0) and PTRUN1 (Timer 1) registers which control the RUN/STOP of the timer. The programmable timer starts down counting by writing "1" to the PTRUN register. However, it is necessary to control the input clock and to preset the reload data before starting a count. When "0" is written to PTRUN register, clock input is prohibited, and the count stops. This RUN/STOP control does not affect data in the counter. The data in the counter is maintained during count deactivation, so it is possible to resume counting from the data. In the 8-bit mode, the channels can be controlled individually by the PTRUN0 register and the PTRUN1 register. In the 16-bit mode, the PTRUN0 register controls both channels as a 16-bit timer. In this case, control of the PTRUN1 register is invalid. The buffers PTM0 (Timer 0) and PTM1 (Timer 1) are attached to the counter, and reading is possible in optional timing. When the counter agrees with the data set in the compare data register during down counting, the timer generates a compare match interrupt. And, when the counter underflows, an underflow interrupt is generated, and the initial value set in the reload data register is loaded to the counter. The interrupt generated does not stop the down counting. After an underflow interrupt is generated, the counter continues counting from the initial value reloaded. PTRUN0(1) PSET0(1) RDR0(1) A6H A6H F3H CDR0(1) 58H 58H 58H Input clock PTM07(17) PTM06(16) PTM05(15) PTM04(14) PTM03(13) PTM02(12) PTM01(11) PTM00(10) Preset Compare match interrupt generation Reload & Underflow interrupt generation Fig. 5.12.4.1 Basic operation timing of counter (an example of 8-bit mode) 112 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) 5.12.5 Interrupt function Table 5.12.5.1 shows the interrupt factor flags, interrupt enable registers and interrupt priority registers corresponding to the interrupt factors. The 16-bit programmable timer can generate an interrupt with the compare match signal and underflow signal of each timer. Figure 5.12.5.1 shows the configuration of the 16bit programmable timer interrupt circuit. The compare match signal and underflow signal of each timer set the corresponding interrupt factor flag to "1". At that point, the interrupt is generated. The interrupt can also be prohibited by setting the interrupt enable register to correspond with the interrupt factor flag. Furthermore, the priority level of the interrupt for the CPU can be set to an optional level (0-3) using the interrupt priority register. In the 8-bit mode, the compare match interrupt factor flag and underflow interrupt factor flag are individually set to "1" by the timers. In the 16-bit mode, the interrupt factor flags of Timer 1 are set to "1" by the compare match and underflow of 16 bits. Refer to Section 5.20, "Interrupt and Standby Mode", for details of the interrupt control registers and operations subsequent to interrupt generation. The exception processing vector addresses for the 16-bit programmable timer interrupt are set as follows: Timer 0 underflow interrupt: Timer 0 compare match interrupt: Timer 1 underflow interrupt: Timer 1 compare match interrupt: Address Underflow Data bus Address Address Compare match Address Address 000010H 000012H 000014H 000016H Interrupt priority register PTM00, PTM01 Interrupt factor flag FTU0 Interrupt enable register ETU0 Interrupt priority level judgment circuit Interrupt factor flag FTC0 Timer 0 interrupt request Timer 1 interrupt request Interrupt enable register ETC0 16-bit programmable timer 0 16-bit programmable timer 1 Fig. 5.12.5.1 Configuration of 16-bit programmable timer interrupt circuit Table 5.12.5.1 Interrupt control registers Interrupt factor 16-bit Counter underflow programmable Compare match between counter and timer 0 compare data register CDR0 16-bit Counter underflow programmable Compare match between counter and timer 1 compare data register CDR1 S1C88409 TECHNICAL MANUAL Interrupt factor flag Interrupt enable register Interrupt priority register Name FTU0 FTC0 Address*Dx 00FF28H*D3 00FF28H*D4 Name ETU0 ETC0 Address*Dx 00FF24H*D3 00FF24H*D4 Name PTM00 PTM01 Address*Dx 00FF20H*D0 00FF20H*D1 FTU1 FTC1 00FF28H*D5 00FF28H*D6 ETU1 ETC1 00FF24H*D5 00FF24H*D6 PTM10 PTM11 00FF20H*D2 00FF20H*D3 EPSON 113 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) 5.12.6 Setting of TOUT output The 16-bit programmable timer can generate TOUT signals with the underflow and compare match signals of Timer 0 and Timer 1. The TOUT signal generated in the 16-bit programmable timer can be output from the output port terminal shown in Table 5.12.6.1 so that a programmable clock can be supplied for external devices. Table 5.12.6.1 TOUT output terminal Timer Timer 0 Timer 1 Output clock name Output terminal TOUT0 TOUT1 R40 R41 The TOUT signal rises at the falling edge of the underflow signal and falls at the falling edge of the compare match signal. Therefore, it is possible to change the frequency and duty ratio of the TOUT signal by setting the reload data register (RDR) and compare data register (CDR). However, it needs a condition setting: RDR>CDR, CDR 0. In the case of RDRCDR, TOUT signal is fixed at "1". The TOUT output can be controlled by the TOUT output control register of each timer (Timer 0: PTOUT0, Timer 1: PTOUT1). In the 16-bit mode, the output is controlled by the control register PTOUT1 for Timer 1. The clock is output from Timer 1. Figure 5.12.6.1 shows the output waveform of TOUT signal. Input clock RDR0(1) register 7 CDR0(1) register 6 Down counter 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 Compare match signal Underflow signal TOUT signal CDR register value RDR register value + 1 PTOUT0(1) Output from TOUT(R) terminal Fig. 5.12.6.1 Output waveform of TOUT signal Refer to Section 5.9, "Clock Output", for output control of TOUT signal to the outside. 114 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) 5.12.7 I/O memory of 16-bit programmable timer Table 5.12.7.1 shows the 16-bit programmable timer control bits. Table 5.12.7.1(a) 16-bit programmable timer control bits Address Bit Name Function 00FF10 D7 PRPRT1 16-bit programmable timer 1 clock control D6 PST12 16-bit programmable timer 1 division ratio PST12 PST11 PST10 (OSC3) (OSC1) 1 1 1 fOSC3 / 4096 fOSC1 / 128 fOSC3 / 1024 fOSC1 / 64 1 1 0 D5 PST11 fOSC3 / 256 fOSC1 / 32 1 0 1 fOSC3 / 128 fOSC1 / 16 1 0 0 fOSC3 / 64 fOSC1 / 8 0 1 1 D4 PST10 fOSC3 / 32 fOSC1 / 4 0 1 0 fOSC3 / 8 fOSC1 / 2 0 0 1 fOSC3 / 2 fOSC1 / 1 0 0 0 D3 PRPRT0 16-bit programmable timer 0 clock control D2 PST02 16-bit programmable timer 0 division ratio PST02 PST01 PST00 (OSC3) (OSC1) 1 1 1 fOSC3 / 4096 fOSC1 / 128 fOSC3 / 1024 fOSC1 / 64 1 1 0 D1 PST01 fOSC3 / 256 fOSC1 / 32 1 0 1 fOSC3 / 128 fOSC1 / 16 1 0 0 fOSC3 / 64 fOSC1 / 8 0 1 1 D0 PST00 fOSC3 / 32 fOSC1 / 4 0 1 0 fOSC3 / 8 fOSC1 / 2 0 0 1 fOSC3 / 2 fOSC1 / 1 0 0 0 00FF12 D7 - - D6 - - D5 - - D4 - - D3 - - D2 - - D1 PRTF1 16-bit programmable timer 1 source clock selection D0 PRTF0 16-bit programmable timer 0 source clock selection 00FF15 D7 - - D6 - - D5 - - D4 - - D3 - - D2 - - D1 PK11ON EXCL01 input clock ON/OFF control D0 PK10ON EXCL00 input clock ON/OFF control 00FF20 D7 PK11 K10-K13 D6 PK10 interrupt priority register D5 PK01 K00-K07 D4 PK00 interrupt priority register D3 PTM11 16-bit programmable timer 1 D2 PTM10 interrupt priority register D1 PTM01 16-bit programmable timer 0 D0 PTM00 interrupt priority register 00FF24 D7 ETU2 8-bit programmable timer underflow interrupt enable register D6 ETC1 16-bit programmable timer 1 compare match interrupt enable register D5 ETU1 16-bit programmable timer 1 underflow interrupt enable register D4 ETC0 16-bit programmable timer 0 compare match interrupt enable register D3 ETU0 16-bit programmable timer 0 underflow interrupt enable register D2 ESTX Serial interface transmit completion interrupt enable register D1 ESRX Serial interface receive completion interrupt enable register D0 ESERR Serial interface receive error interrupt enable register S1C88409 TECHNICAL MANUAL EPSON 1 On 0 Off Init R/W 0 R/W 0 R/W Comment 0 R/W 0 R/W On Off 0 R/W 0 R/W 0 R/W 0 R/W - - - - - - fOSC1 fOSC1 - - - - - - On On PK11 PK01 PTM11 PTM01 1 1 0 0 - - - - - - fOSC3 fOSC3 - - - - - - Off Off PK10 PK00 PTM10 PTM00 1 0 1 0 Priority level Level 3 Level 2 Level 1 Level 0 - - - - - - 0 0 - - - - - - 0 0 0 0 0 0 0 0 0 0 0 - "0" when being read - - - - - R/W R/W - "0" when being read - - - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 R/W 0 R/W 0 R/W Interrupt is enabled Interrupt is disabled 0 R/W 0 R/W 0 R/W 0 R/W 115 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) Table 5.12.7.1(b) 16-bit programmable timer control bits Address Bit 00FF28 D7 Name FTU2 D6 FTC1 D5 FTU1 D4 FTC0 D3 FTU0 D2 FSTX D1 FSRX D0 FSERR 00FF30 D7 D6 D5 D4 D3 D2 D1 D0 00FF31 D7 D6 D5 D4 D3 D2 D1 D0 00FF32 D7 D6 D5 D4 D3 D2 D1 D0 00FF33 D7 D6 D5 D4 D3 D2 D1 D0 00FF34 D7 D6 D5 D4 D3 D2 D1 D0 00FF35 D7 D6 D5 D4 D3 D2 D1 D0 116 MODE16 - - - PTOUT0 PTRUN0 PSET0 CKSEL0 - - - - PTOUT1 PTRUN1 PSET1 CKSEL1 RDR07 RDR06 RDR05 RDR04 RDR03 RDR02 RDR01 RDR00 RDR17 RDR16 RDR15 RDR14 RDR13 RDR12 RDR11 RDR10 CDR07 CDR06 CDR05 CDR04 CDR03 CDR02 CDR01 CDR00 CDR17 CDR16 CDR15 CDR14 CDR13 CDR12 CDR11 CDR10 Function 8-bit programmable timer underflow interrupt factor flag 16-bit programmable timer 1 compare match interrupt factor flag 16-bit programmable timer 1 underflow interrupt factor flag 16-bit programmable timer 0 compare match interrupt factor flag 16-bit programmable timer 0 underflow interrupt factor flag Serial interface transmit completion interrupt factor flag Serial interface receive completion interrupt factor flag Serial interface receive error interrupt factor flag 16-bit PTM 8-/16-bit mode selection - - - 16-bit PTM0 clock output control 16-bit PTM0 RUN/STOP control 16-bit PTM0 preset 16-bit PTM0 input clock selection - - - - 16-bit PTM1 clock output control 16-bit PTM1 RUN/STOP control 16-bit PTM1 preset 16-bit PTM1 input clock selection 16-bit programmable timer 0 reload data register 16-bit programmable timer 1 reload data register 16-bit programmable timer 0 compare data register 16-bit programmable timer 1 compare data register 1 0 Init R/W 0 R/(W) (R) Interrupt factor has generated (R) Interrupt factor has not generated 0 R/(W) Comment 0 R/(W) 0 R/(W) 0 R/(W) 0 R/(W) (W) Reset (W) Invalid 0 R/(W) 0 R/(W) 16-bit 8-bit x 2 - - - - - - On Off Run Stop Preset Invalid External clock Internal clock - - - - - - - - On Off Run Stop Preset Invalid External clock Internal clock D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) EPSON 0 - - - 0 0 0 0 - - - - 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W - - - R/W R/W W R/W - - - - R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W "0" when being read "0" when being read "0" when being read "0" when being read Low-order 8 bits data in 16-bit mode High-order 8 bits data in 16-bit mode Low-order 8 bits data in 16-bit mode High-order 8 bits data in 16-bit mode S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) Table 5.12.7.1(c) 16-bit programmable timer control bits Address Bit 00FF36 D7 D6 D5 D4 D3 D2 D1 D0 00FF37 D7 D6 D5 D4 D3 D2 D1 D0 00FFD4 D7 D6 D5 D4 D3 D2 D1 D0 00FFD9 D7 D6 D5 D4 D3 D2 D1 D0 Name PTM07 PTM06 PTM05 PTM04 PTM03 PTM02 PTM01 PTM00 PTM17 PTM16 PTM15 PTM14 PTM13 PTM12 PTM11 PTM10 - - - - - HZR42 HZR41 HZR40 - - - - - R42D R41D R40D Function 16-bit programmable timer 0 data register 1 0 D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) 16-bit programmable timer 1 data register - - - - - R42 high impedance control register R41 high impedance control register R40 high impedance control register - - - - - R42 output port data register R41 output port data register R40 output port data register - - - - - - - - - - High impedance Complementary - - - - - - - - - - High Low Init 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 R/W R R R R R R R R R R R R R R R R - - - - - R/W R/W R/W - - - - - R/W R/W R/W Comment Low-order 8 bits data in 16-bit mode High-order 8 bits data in 16-bit mode "0" when being read "0" when being read The clock to be input to each timer is selected from either the external clock (input signal of input port) or the internal clock (prescaler output clock). MODE16: 8-/16-bit mode selection register (00FF30H*D7) Selects either the 8-bit or 16-bit mode. When "1" is written: 16 bits x 1 channel When "0" is written: 8 bits x 2 channels Reading: Valid Select whether Timer 0 and Timer 1 are used as 2 channels independent 8-bit timers or as 1 channel combined 16-bit timer. When "0" is written to the MODE16 register, 8-bit x 2 channels is selected and when "1" is written, 16-bit x 1 channel is selected. At initial reset, the MODE16 register is set to "0" (8-bit x 2 channels). CKSEL0: Timer 0 input clock selection register (00FF30H*D0) CKSEL1: Timer 1 input clock selection register (00FF31H*D0) Selects the input clock for each timer. When "0" is written to the CKSEL0 register, the internal clock (prescaler output INCL00) is selected as the input clock for Timer 0. When "1" is written, the external clock (K10 input EXCL00) is selected and the timer functions as an event counter. Same as above, when "0" is written to the CKSEL1 register, the internal clock (prescaler output INCL01) is selected as the input clock for Timer 1. When "1" is written, the external clock (K11 input EXCL01) is selected. In the 16-bit mode, the setting of the CKSEL1 register is invalid. At initial reset, the CKSEL register is set to "0" (internal clock). When "1" is written: External clock When "0" is written: Internal clock Reading: Valid S1C88409 TECHNICAL MANUAL EPSON 117 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) PRTF1: 16-bit programmable timer 1 source clock selection register (00FF12H*D1) Selects the source clock for the 16-bit programmable timer 1. PRTF0: 16-bit programmable timer 0 source clock selection register (00FF12H*D0) Selects the source clock for the 16-bit programmable timer 0. When "1" is written: fOSC1 When "0" is written: fOSC3 Reading: Valid When "1" is written: fOSC1 When "0" is written: fOSC3 Reading: Valid When "1" is written to the PRTF0 register, the OSC1 clock is selected as the source clock for the 16-bit programmable timer 0. When "0" is written, the OSC3 clock is selected. At initial reset, the PRTF0 register is set to "0" (fOSC3). When "1" is written to the PRTF1 register, the OSC1 clock is selected as the source clock for the 16-bit programmable timer 1. When "0" is written, the OSC3 clock is selected. At initial reset, the PRTF1 register is set to "0" (fOSC3). PST00-PST02: 16-bit programmable timer 0 division ratio selection register (00FF10H*D0-D2) Selects the clock for the 16-bit programmable timer 0. It can be selected from 8 types of division ratio shown in Table 5.12.7.1(a). This register can also be read. At initial reset, the PST0 register is set to "0". PST10-PST12: 16-bit programmable timer 1 division ratio selection register (00FF10H*D4-D6) Selects the clock for the 16-bit programmable timer 1. It can be selected from 8 types of division ratio shown in Table 5.12.7.1(a). This register can also be read. At initial reset, the PST1 register is set to "0". PRPRT0: 16-bit programmable timer 0 clock control register (00FF10H*D3) Controls the clock supply of the 16-bit programmable timer 0. PRPRT1: 16-bit programmable timer 1 clock control register (00FF10H*D7) Controls the clock supply of the 16-bit programmable timer 1. When "1" is written: ON When "0" is written: OFF Reading: Valid When "1" is written: ON When "0" is written: OFF Reading: Valid By writing "1" to the PRPRT0 register, the clock that is selected with the PST0 register is output to the 16-bit programmable timer 0. When "0" is written, the clock is not output. At initial reset, the PRPRT0 register is set to "0" (OFF). By writing "1" to the PRPRT1 register, the clock that is selected with the PST1 register is output to the 16-bit programmable timer 1. When "0" is written, the clock is not output. At initial reset, the PRPRT1 register is set to "0" (OFF). PK10ON: EXCL00 clock control register (00FF15H*D0) Controls the event counter clock of the 16-bit programmable timer 0. PK11ON: EXCL01 clock control register (00FF15H*D1) Controls the event counter clock of the 16-bit programmable timer 1. When "1" is written: ON When "0" is written: OFF Reading: Valid When "1" is written: ON When "0" is written: OFF Reading: Valid By writing "1" to the PK10ON register, the EXCL00 (K10 input) clock is output to the 16-bit programmable timer 0. When "0" is written, the clock is not output. At initial reset, the PK10ON register is set to "0" (OFF). 118 By writing "1" to the PK11ON register, the EXCL01 (K11 input) clock is output to the 16-bit programmable timer 1. When "0" is written, the clock is not output. At initial reset, the PK11ON register is set to "0" (OFF). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) RDR00-RDR07: Timer 0 reload data register (00FF32H) RDR10-RDR17: Timer 1 reload data register (00FF33H) Sets the initial value for the counter of each timer. Each counter loads the reload data set in this register and counts using it as the initial value. The reload data set in this register is loaded into the counter when "1" is written to PSET0 or PSET1, or when a counter underflow occurs. This register can be read. At initial reset, the RDR register is set to "FFH". CDR00-CDR07: Timer 0 compare data register (00FF34H) CDR10-CDR17: Timer 1 compare data register (00FF35H) Sets the compare data for each timer. The timer compares the data set in this register with the corresponding counter data, and outputs the compare match signals when they are the same. The compare match signal controls the interrupt and the TOUT output waveform. This register can be read. At initial reset, the CDR register is set to "00H". PTM00-PTM07: Timer 0 counter data (00FF36H) PTM10-PTM17: Timer 1 counter data (00FF37H) The counter data of each timer can be read. Data can be read at any given time. However, in the 16-bit mode, reading PTM0 does not latch the timer 1 counter data in PTM1. To avoid generating a borrow from timer 0 to timer 1, read the counter data after stopping the timer by writing "0" to PTRUN0. PTM0 and PTM1 can only be read, so writing operation is invalid. At initial reset, PTM is set to "FFH". S1C88409 TECHNICAL MANUAL PSET0: Timer 0 preset (00FF30H*D1) PSET1: Timer 1 preset (00FF31H*D1) Presets the reload data to the counter. When "1" is written: Preset When "0" is written: Invalid Reading: Always "0" Writing "1" to PSET0 presets the reload data in the RDR0 register to the counter of Timer 0. When the counter of Timer 0 is in RUN status, the counter restarts immediately after presetting. In the case of STOP status, the counter maintains the preset data. No operation results when "0" is written. Same as above, PSET1 presets the reload data in the RDR1 register to the counter of Timer 1. In the 16-bit mode, writing "1" to PSET1 is invalid because 16-bit data is preset by PSET0 only. This bit is only for writing, and it is always "0" during reading. PTRUN0: Timer 0 RUN/STOP control register (00FF30H*D2) PTRUN1: Timer 1 RUN/STOP control register (00FF31H*D2) Controls the RUN/STOP of the counter. When "1" is written: RUN When "0" is written: STOP Reading: Valid The counter of Timer 0 starts down-counting by writing "1" to the PTRUN0 register and stops by writing "0". In STOP status, the counter data is maintained until it is preset or the counter restarts. When STOP status changes to RUN status, the counter resumes counting from the data maintained. Same as above, the PTRUN1 register controls the counter of Timer 1. In the 16-bit mode, both channels are controlled with the PTRUN0 register, and the PTRUN1 register is fixed at "0". At initial reset, the PTRUN register is set to "0" (STOP). EPSON 119 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) PTOUT0: Timer 0 clock output control register (00FF30H*D3) PTOUT1: Timer 1 clock output control register (00FF31H*D3) Controls the output of the TOUT signal. When "1" is written: ON When "0" is written: OFF Reading: Valid The PTOUT0 is the output control register for the TOUT0 signal (Timer 0 output clock). When "1" is written to this register, the TOUT0 signal is output from the R40 terminal. When "0" is written, the terminal goes high (VDD) level. However, the highimpedance control register HZR40 of the output port R40 must be set to "0" and the data register R40D must be set to "1". The TOUT0 clock cannot be output simultaneously with the FOUT3 clock. The PTOUT1 is the output control register for the TOUT1 signal (Timer 1 output clock). When "1" is written to this register, the TOUT1 signal is output from the R41 terminal. When "0" is written, the terminal goes high (VDD) level. However, the highimpedance control register HZR41 of the output port R41 must be set to "0" and the data register R41D must be set to "1". The TOUT1 clock cannot be output simultaneously with the FOUT1 clock. At initial reset, the PTOUT register is set to "0" (OFF). HZR40, HZR41: R4 port high impedance control register (00FFD4H*D0, D1) Sets the output terminals into a high impedance state. When "1" is written: High impedance When "0" is written: Complementary Reading: Valid The HZR40 and HZR41 registers are the high impedance control registers for the output ports R40 and R41 used for the clock output. Fix data of the port used for the TOUT output at "0". At initial reset, the HZR register is set to "1" (high impedance). 120 R40D, R41D: R4 port output data register (00FFD9H*D0, D1) They are the data registers for the output ports R40, R41 used for the clock output. When "1" is written: Clock output is possible When "0" is written: LOW (VSS) level is output Reading: Valid Fix data of the port used for the TOUT output at "1". At initial reset, the data bits are all set to "1". PTM00, PTM01: Timer 0 interrupt priority register (00FF20H*D0, D1) PTM10, PTM11: Timer 1 interrupt priority register (00FF20H*D2, D3) Sets the priority level of the 16-bit programmable timer interrupt. The PTM register is the interrupt priority register corresponding to each timer interrupt. Table 5.12.7.2 shows the interrupt priority level which can be set by this register. Table 5.12.7.2 Interrupt priority level settings PTM11 PTM01 PTM10 PTM00 1 1 0 0 1 0 1 0 Interrupt priority level Level 3 Level 2 Level 1 Level 0 (IRQ3) (IRQ2) (IRQ1) (None) At initial reset, the PTM register is set to "0" (level 0). ETU0: Timer 0 underflow interrupt enable register (00FF24H*D3) ETU1: Timer 1 underflow interrupt enable register (00FF24H*D5) Enables or disables the underflow interrupt generation to the CPU. When "1" is written: Interrupt is enabled When "0" is written: Interrupt is disabled Reading: Valid The ETU register is the interrupt enable register corresponding to the underflow interrupt factor of each timer. Interrupt in which the ETU register is set to "1" is enabled, and the others in which the ETU register is set to "0" are disabled. In the 16-bit mode, the setting of the ETU0 is invalid. At initial reset, the ETU register is set to "0" (interrupt is disabled). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) ETC0: Timer 0 compare match interrupt enable register (00FF24H*D4) ETC1: Timer 1 compare match interrupt enable register (00FF24H*D6) Enables or disables the compare match interrupt generation to the CPU. When "1" is written: Interrupt is enabled When "0" is written: Interrupt is disabled Reading: Valid FTC0: Timer 0 compare match interrupt factor flag (00FF28H*D4) FTC1: Timer 1 compare match interrupt factor flag (00FF28H*D6) Indicates the generation of compare match interrupt factor. The ETC register is the interrupt enable register corresponding to the compare match interrupt factor of each timer. Interrupt in which the ETC register is set to "1" is enabled, and the others in which the ETC register is set to "0" are disabled. In the 16-bit mode, the setting of the ETC0 is invalid. At initial reset, the ETC register is set to "0" (interrupt is disabled). When "1" is read: Int. factor has generated When "0" is read: Int. factor has not generated When "1" is written: Factor flag is reset When "0" is written: Invalid FTU0: Timer 0 underflow interrupt factor flag (00FF28H*D3) FTU1: Timer 1 underflow interrupt factor flag (00FF28H*D5) Indicates the generation of underflow interrupt factor. When "1" is read: Int. factor has generated When "0" is read: Int. factor has not generated When "1" is written: Factor flag is reset When "0" is written: Invalid FTU is the interrupt factor flag corresponding to interrupt of each timer, and is set to "1" due to the counter underflow. At this point, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I0 and I1), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "1" when the interrupt generation condition is met. To accept the subsequent interrupt after an interrupt generation, it is necessary to re-set the interrupt flags (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "0" by writing "1". S1C88409 TECHNICAL MANUAL In the 16-bit mode, the interrupt factor flag FTU0 is not set to "1" and Timer 0 interrupt is not generated. In this mode, the interrupt factor flag FTU1 is set to "1" by the underflow of the 16-bit counter. At initial reset, the FTU flag is reset to "0". FTC is the interrupt factor flag corresponding to interrupt of each timer, and is set to "1" due to the compare match signal. At this point, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I0 and I1), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "1" when the interrupt generation condition is met. To accept the subsequent interrupt after an interrupt generation, it is necessary to re-set the interrupt flags (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "0" by writing "1". In the 16-bit mode, the interrupt factor flag FTC0 is not set to "1" and Timer 0 interrupt is not generated. In this mode, the interrupt factor flag FTC1 is set to "1" by the compare match of the 16-bit counter. At initial reset, the FTC flag is reset to "0". EPSON 121 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer) 5.12.8 Programming notes (1) The 16-bit programmable timer actually enters into RUN or STOP status at the falling edge of the input clock after writing to the PTRUN0(1) register. Consequently, when "0" is written to PTRUN0(1), the timer stops after counting once more (+1). PTRUN0(1) is read as "1" until the timer actually stops. Figure 5.12.8.1 shows the timing chart at the RUN/STOP control. Input clock PTRUN0/PTRUN1(RD) PTRUN0/PTRUN1(WR) PTM0/PTM1 42H 41H 40H 3FH 3EH 3DH Fig. 5.12.8.1 Timing chart at RUN/STOP control (2) When the SLP instruction is executed while the 16-bit programmable timer is running (PTRUN0(1) = "1"), the timer stops counting during SLEEP status. When SLEEP status is canceled, the timer starts counting. However, the operation becomes unstable immediately after SLEEP status is canceled. Therefore, when shifting to SLEEP status, stop the 16-bit programmable timer (PTRUN0(1) = "0") prior to executing the SLP instruction. Same as above, the TOUT signal output should be disabled (PTOUT0(1) = "0") so that an unstable clock is not output to the clock output port terminal. (3) In the 16-bit mode, reading PTM0 does not latch the timer 1 counter data in PTM1. To avoid generating a borrow from timer 0 to timer 1, read the counter data after stopping the timer by writing "0" to PTRUN0. 122 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (8-bit Programmable Timer) 5.13 8-bit Programmable Timer 5.13.2 Setting of input clock 5.13.1 Configuration of 8-bit programmable timer The prescaler supplies the clocks to the timer. The prescaler generates the clocks for the timer by dividing the source clock supplied from the OSC3 oscillation circuit. The S1C88409 has a built-in 8-bit programmable timer. The timer consists of an 8-bit presettable down counter, and can be used as 8 bits x 1 channel of programmable timer. Figure 5.13.1.1 shows the configuration of the 8-bit programmable timer. The serial interface uses the underflow signal of the 8-bit programmable timer as the synchronous clock, so programmable setting of the transfer rate is possible. Division ratio of the prescaler can be individually selected by software. The division ratio can be selected from eight kinds using the prescaler division ratio selection register PST2. Further, it is necessary to control the prescaler output using the clock control register PRPRT2. Refer to Section 5.5, "Prescaler and Clock Control Circuit for Peripheral Circuits", or Section 5.13.6, "I/O memory of 8-bit programmable timer", for setting of the division ratio. Prescaler/clock control circuit 8-bit reload data register (RLD) Reload Serial I/F Clock output Underflow Data buffer (PTD) Control circuit Underflow interrupt 8-bit down counter Data bus fOSC3 Note: The prescaler, which supplies the clock to the 8-bit programmable timer, can operate only when the OSC3 oscillation has been set to ON. Be aware that the 8-bit programmable timer does not operate when the OSC3 oscillation circuit has been turned off. Control registers Interrupt circuit Fig. 5.13.1.1 Configuration of 8-bit programmable timer S1C88409 TECHNICAL MANUAL EPSON 123 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (8-bit Programmable Timer) Timer operation 5.13.3 Operation and control of timer Reload data register and setting of initial value The reload data register RLD is used to set the initial value of the down counter. The reload data register can be read and written, and is set to FFH at initial reset. Data written in this register is loaded into the down counter, and down counting starts from the value. A preset to down counter is done in the following two cases: 1) When software presets The software preset can be done using the preset control bit PSET. When the preset control bit is set to "1", the content of the reload data register is loaded into the down counter at that point. 2) When down counter has underflowed during a count Since the down counter presets the reload data by the underflow, the underflow period is decided according to the value set in the reload data register. This underflow generates an interrupt, and controls the clock output to the serial interface. The 8-bit programmable timer is equipped with the register PRUN which control the RUN/STOP of the timer. The programmable timer starts down counting by writing "1" to the PRUN register. However, it is necessary to control the input clock and to preset the reload data before starting a count. When "0" is written to the PRUN register, clock input is prohibited, and the count stops. This RUN/STOP control does not affect data in the counter. The data in the counter is maintained during count deactivation, so it is possible to resume counting from the data. The counter data can be read via the buffer PTD in optional timing. When the counter underflows, an underflow interrupt is generated, and the initial value set in the reload data register is loaded to the counter. This underflow signal controls supplying the clock to the serial interface. PRUN PSET RLD A6H F3H Input clock PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Preset Reload & Interrupt generation Fig. 5.13.3.1 Operation timing of counter 124 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (8-bit Programmable Timer) 5.13.4 Interrupt function The 8-bit programmable timer can generate an interrupt by the underflow signal of the counter. Figure 5.13.4.1 shows the configuration of the 8-bit programmable timer interrupt circuit. The underflow signal of the timer sets the interrupt factor flag FTU2 to "1". At that point, the interrupt is generated. The interrupt can also be prohibited by setting the interrupt enable register ETU2. The exception processing vector address for the 8bit programmable timer interrupt is set as follows: 8-bit programmable timer interrupt: 000018H Interrupt priority register PTM20, PTM21 Address Data bus Furthermore, the priority level of the interrupt for the CPU can be set to an optional level (0-3) using the interrupt priority register PTM2. Refer to Section 5.20, "Interrupt and Standby Mode", for details of the interrupt control registers and operations subsequent to interrupt generation. Timer underflow Interrupt factor flag FTU2 Address Interrupt enable register ETU2 Address Interrupt priority level judgment circuit Interrupt request Fig. 5.13.4.1 Configuration of 8-bit programmable timer interrupt circuit 5.13.5 Transfer rate setting for serial interface The 8-bit programmable timer can supply the clock, generated by dividing the underflow of the counter in 1/2, to the serial interface. The clock output control register PTOUT controls the clock output from the 8-bit programmable timer. Figure 5.13.5.1 shows the output waveform of the clock. The transfer rate of the serial interface is decided by the clock output from the prescaler and the value set in the reload register. The output clock is divided by 16 in the serial interface. Therefore, the setting value of the reload data register according to the transfer rate can be calculated with the expression below. RLD = fOSC3 dr / (32 bps) - 1 RLD: Setting value of the reload register fOSC3: OSC3 oscillation frequency bps: Transfer rate dr: Prescaler division ratio (1/2 to 1/256) (00H can be set to RLD) Underflow signal Underflow signal/2 PTOUT Clock output Fig. 5.13.5.1 Clock output waveform S1C88409 TECHNICAL MANUAL EPSON 125 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (8-bit Programmable Timer) 5.13.6 I/O memory of 8-bit programmable timer Table 5.13.6.1 shows the 8-bit programmable timer control bits. Table 5.13.6.1(a) 8-bit programmable timer control bits Address Bit Name Function 00FF11 D7 - - D6 - - D5 - - D4 - - D3 PRPRT2 8-bit programmable timer clock control D2 PST22 8-bit programmable timer division ratio PST22 PST21 PST20 Division ratio 1 1 1 fOSC3 / 256 fOSC3 / 128 1 1 0 D1 PST21 fOSC3 / 64 1 0 1 fOSC3 / 32 1 0 0 fOSC3 / 16 0 1 1 D0 PST20 fOSC3 / 8 0 1 0 fOSC3 / 4 0 0 1 fOSC3 / 2 0 0 0 00FF21 D7 PTM21 8-bit programmable timer D6 PTM20 interrupt priority register D5 PSI1 Serial interface D4 PSI0 interrupt priority register D3 PCTM1 Clock timer D2 PCTM0 interrupt priority register D1 PLCD1 LCD controller D0 PLCD0 interrupt priority register 00FF24 D7 ETU2 8-bit programmable timer underflow interrupt enable register D6 ETC1 16-bit programmable timer 1 compare match interrupt enable register D5 ETU1 16-bit programmable timer 1 underflow interrupt enable register D4 ETC0 16-bit programmable timer 0 compare match interrupt enable register D3 ETU0 16-bit programmable timer 0 underflow interrupt enable register D2 ESTX Serial interface transmit completion interrupt enable register D1 ESRX Serial interface receive completion interrupt enable register D0 ESERR Serial interface receive error interrupt enable register 00FF28 D7 FTU2 8-bit programmable timer underflow interrupt factor flag D6 FTC1 16-bit programmable timer 1 compare match interrupt factor flag D5 FTU1 16-bit programmable timer 1 underflow interrupt factor flag D4 FTC0 16-bit programmable timer 0 compare match interrupt factor flag D3 FTU0 16-bit programmable timer 0 underflow interrupt factor flag D2 FSTX Serial interface transmit completion interrupt factor flag D1 FSRX Serial interface receive completion interrupt factor flag D0 FSERR Serial interface receive error interrupt factor flag 126 EPSON 1 - - - - On 0 - - - - Off Init R/W Comment - - "0" when being read - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W PTM21 PTM20 PSI1 PSI0 PCTM1 PCTM0 Priority level PLCD1 PLCD0 Level 3 1 1 Level 2 1 0 Level 1 0 1 Level 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 R/W 0 R/W 0 R/W Interrupt is enabled Interrupt is disabled 0 R/W 0 R/W 0 R/W 0 R/W 0 R/(W) (R) Interrupt factor has generated (R) Interrupt factor has not generated 0 R/(W) 0 R/(W) 0 R/(W) 0 R/(W) 0 R/(W) (W) Reset (W) Invalid 0 R/(W) 0 R/(W) S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (8-bit Programmable Timer) Table 5.13.6.1(b) 8-bit programmable timer control bits Address Bit 00FF38 D7 D6 D5 D4 D3 D2 D1 D0 00FF39 D7 D6 D5 D4 D3 D2 D1 D0 00FF3A D7 D6 D5 D4 D3 D2 D1 D0 Name - - - - - PTOUT PSET PRUN RLD7 RLD6 RLD5 RLD4 RLD3 RLD2 RLD1 RLD0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Function - - - - - 8-bit programmable timer clock output control 8-bit programmable timer preset 8-bit programmable timer RUN/STOP control 8-bit programmable timer D7(MSB) reload data register D6 D5 D4 D3 D2 D1 D0(LSB) 8-bit programmable timer D7(MSB) data register D6 D5 D4 D3 D2 D1 D0(LSB) PST20-PST22: 8-bit programmable timer division ratio selection register (00FF11H*D0-D2) Selects the clock for the 8-bit programmable timer. It can be selected from 8 types of division ratio shown in Table 5.13.6.1(a). This register can also be read. At initial reset, the PST2 register is set to "0" (fOSC3/2). PRPRT2: 8-bit programmable timer clock control register (00FF11H*D3) Controls the clock supply of the 8-bit programmable timer. When "1" is written: ON When "0" is written: OFF Reading: Valid By writing "1" to the PRPRT2 register, the clock that is selected with the PST2 register is output to the 8-bit programmable timer. However, the OSC3 oscillation circuit must be used. When "0" is written, the clock is not output. At initial reset, the PRPRT2 register is set to "0" (OFF). 1 - - - - - On Preset Run 0 - - - - - Off Invalid Stop Init - - - - - 0 - 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W Comment - "0" when being read - - - - R/W W "0" when being read R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R RLD0-RLD7: Reload data register (00FF39H) Sets the initial value for the counter. The counter loads the reload data set in this register and counts using it as the initial value. The reload data set in this register is loaded into the counter when "1" is written to PSET, or when a counter underflow occurs. This register can be read. At initial reset, the RLD register is set to "FFH". PTD0-PTD7: Counter data (00FF3AH) The counter data of the 8-bit programmable timer can be read. PTD is a buffer to maintain the count data during reading, and the data can be read in optional timing. At initial reset, PTD is set to "FFH". PSET: Preset (00FF38H*D1 ) Presets the reload data to the counter. When "1" is written: Preset When "0" is written: Invalid Reading: Always "0" Writing "1" to PSET presets the reload data in the RLD register to the counter. When the counter is in RUN status, the counter restarts immediately after presetting. S1C88409 TECHNICAL MANUAL EPSON 127 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (8-bit Programmable Timer) In the case of STOP status, the counter maintains the preset data. No operation results when "0" is written. This bit is valid only for writing, and it is always "0" during reading. ETU2: Underflow interrupt enable register (00FF24H*D7) Enables or disables the underflow interrupt generation to the CPU. When "1" is written: Interrupt is enabled When "0" is written: Interrupt is disabled Reading: Valid PRUN: RUN/STOP control register (00FF38H*D0) Controls the RUN/STOP of the counter. When "1" is written: RUN When "0" is written: STOP Reading: Valid The counter starts down-counting by writing "1" to the PRUN register and stops by writing "0". In STOP status, the counter data is maintained until it is preset or the counter restarts. When STOP status changes to RUN status, the counter resumes counting from the data maintained. At initial reset, the PRUN register is set to "0" (STOP). When "1" is written: Factor flag is reset When "0" is written: Invalid When "1" is written: ON When "0" is written: OFF Reading: Valid The PTOUT register is the output control register. When "1" is written to this register, the clock (underflow 1/2) that is generated by the 8-bit programmable timer is output to the serial interface. When "0" is written, the clock is not output to the serial interface. At initial reset, the PTOUT register is set to "0" (OFF). PTM20, PTM21: Interrupt priority register (00FF21H*D6, D7) Sets the priority level of the 8-bit programmable timer interrupt. Table 5.13.6.2 shows the interrupt priority level which can be set by this register. Table 5.13.6.2 Interrupt priority level settings PTM20 1 1 0 0 1 0 1 0 FTU2: Underflow interrupt factor flag (00FF28H*D7) Indicates the generation of underflow interrupt factor. When "1" is read: Int. factor has generated When "0" is read: Int. factor has not generated PTOUT: Clock output control register (00FF38H*D2) Controls the clock output to the serial interface. PTM21 The ETU2 register is the interrupt enable register corresponding to the interrupt factor of the 8-bit programmable timer. Interrupt in which the ETU2 register is set to "1" is enabled, and the others in which the ETU2 register is set to "0" are disabled. At initial reset, the ETU2 register is set to "0" (interrupt is disabled). FTU2 is the interrupt factor flag corresponding to the 8-bit programmable timer interrupt, and is set to "1" due to the counter underflow. At this point, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I0 and I1), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "1" when the interrupt generation condition is met. To accept the subsequent interrupt after an interrupt generation, it is necessary to re-set the interrupt flags (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "0" by writing "1". At initial reset, the FTU2 flag is reset to "0". Interrupt priority level Level 3 Level 2 Level 1 Level 0 (IRQ3) (IRQ2) (IRQ1) (None) At initial reset, the PTM2 register is set to "0" (level 0). 128 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (8-bit Programmable Timer) 5.13.7 Programming notes (1) The 8-bit programmable timer actually enters into RUN or STOP status at the falling edge of the input clock after writing to the PRUN register. Consequently, when "0" is written to PRUN, the timer stops after counting once more (+1). PRUN is read as "1" until the timer actually stops. Figure 5.13.7.1 shows the timing chart of the RUN/STOP control. Input clock PRUN (RD) PRUN (WR) PTD 42H 41H 40H 3FH 3EH 3DH Fig. 5.13.7.1 Timing chart at RUN/STOP control (2) When the SLP instruction is executed while the 8-bit programmable timer is running (PRUN = "1"), the timer stops counting during SLEEP status. When SLEEP status is canceled, the timer starts counting. However, the operation becomes unstable immediately after SLEEP status is canceled. Therefore, when shifting to SLEEP status, stop the 8-bit programmable timer (PRUN = "0") prior to executing the SLP instruction. (3) The prescaler, which supplies the clock to the 8-bit programmable timer, can operate only when the OSC3 oscillation has been set to ON. Be aware that the 8-bit programmable timer does not operate when the OSC3 oscillation circuit has been turned off. S1C88409 TECHNICAL MANUAL EPSON 129 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 5.14 Serial Interface Figure 5.14.1.1 shows the configuration of the serial interface. 5.14.1 Configuration of serial interface The input/output port of the serial interface is shared with an I/O port, and it is set in the I/O port at initial reset. Therefore, when using the serial interface, enable the serial interface by writing "1" to the serial interface enable register (ESIF). The S1C88409 has a serial interface built-in. The following shows the features. * 8-bit clock synchronous system/8(7)-bit asynchronous system (full duplex) are switchable * Two systems of input/output terminals (P10-P13, P14-P17) are selectable * Data bit length, stop bit length and parity bit are selectable with software for the asynchronous system * IrDA interface compatible The serial interface in which the ESIF register is "0" cannot be used. Data bus Serial I/O control & status register SIN (P10/P14) Serial input control circuit Error detection circuit Received data shift register Start bit detection circuit SCLK (P12/P16) Received data buffer Clock control circuit Interrupt control circuit Transmitting data shift register Serial output control circuit READY output control circuit 8-bit programmable timer Interrupt request SOUT (P11/P15) SRDY (P13/P17) Fig. 5.14.1.1 Configuration of serial interface 130 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 5.14.2 Transfer mode and input/output terminals In this serial interface, the transfer mode can be selected by software. Transfer mode summary Clock synchronous transfer is the formula that transfers 8-bit data by synchronizing each bit to a clock common to transmitter and receiver. Asynchronous transfer is the formula that transfers the serial converted data in which a start bit is added to the front and a stop bit is added to the rear. In this formula, it is not necessary to use the same synchronous clock for transmitter and receiver. Data transfer is done by synchronizing the start/stop bit attached in front and rear of each data. The asynchronous interface has separate transmit and receive shift registers and is designed to permit full duplex transmission to be done simultaneously for transmitting and receiving. (2) Clock synchronous slave mode In this mode, clock synchronous 8-bit serial data transfer can be done. This serial interface becomes the slave and uses the synchronous clock supplied externally (the master side). The synchronous clock is input from the SCLK terminal and is used in this serial interface. Further, this mode can output the SRDY signal that indicates transmit/receive ready status from the SRDY terminal. Figure 5.14.2.2 shows a connection example of input/output terminals in clock synchronous slave mode. S1C88409 SIN (P10/P14) External serial device Data input SOUT (P11/P15) Data output SCLK (P12/P16) CLOCK output SRDY (P13/P17) READY input Four transfer modes shown below are available in this interface. Fig. 5.14.2.2 Connection example of clock synchronous slave mode (1) Clock synchronous master mode In this mode, clock synchronous 8-bit serial data transfer can be done. This serial interface becomes the master and uses the internal clock as the synchronous clock for the built-in shift register. The synchronous clock is output from the SCLK terminal and can control the external serial I/O device (the slave side). Figure 5.14.2.1 shows a connection example of input/output terminals in clock synchronous master mode. (3) 7-bit asynchronous mode In this mode, start stop synchronous transfer can be done. Data length is 7 bits. It is possible to select a stop bit length, addition of a parity bit and even/odd parity. Further, this mode works only with the internal clock. Figure 5.14.2.3 shows a connection example of input/output terminals in asynchronous mode. S1C88409 SIN (P10/P14) External serial device Data input SOUT (P11/P15) Data output SCLK (P12/P16) CLOCK input Input port (Kxx) (4) 8-bit asynchronous mode In this mode, start stop synchronous transfer can be done. Data length is 8 bits. It is possible to select a stop bit length, addition of a parity bit and even/odd parity. Further, this mode works only with the internal clock. Figure 5.14.2.3 shows a connection example of input/output terminals in asynchronous mode. READY output S1C88409 Fig. 5.14.2.1 Connection example of clock synchronous master mode SIN (P10/P14) SOUT (P11/P15) External serial device Data input Data output Fig. 5.14.2.3 Connection example of clock asynchronous mode S1C88409 TECHNICAL MANUAL EPSON 131 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Setting of serial interface The asynchronous mode does not use SCLK and SRDY, so P12 and P13 (P16 and P17) can be used as the I/O port. (1) Transfer mode The transfer mode is set with the SMD register (2 bits) as shown in Table 5.14.2.1. The I/O control registers and data registers of the I/O port which is used with the serial interface can be used as a general-purpose register. Table 5.14.2.1 Transfer mode SMD1 1 1 SMD0 1 0 0 0 1 0 Mode 8-bit asynchronous 7-bit asynchronous (2) Data format of clock synchronous transfer In the clock synchronous mode, data format is stationary as follows: Clock synchronous slave Clock synchronous master Data length: Start bit: Stop bit: Parity bit: It is set to the clock synchronous master mode at initial reset. In the clock synchronous mode, start/stop bit and parity bit cannot be added. The clock synchronous slave mode outputs the SRDY signal showing transmit/receive ready status from the SRDY terminal. SCLK LSB MSB D0 D1 D2 D3 D4 D5 D6 D7 Data When using the IR interface, set the 7-bit asynchronous mode or 8-bit asynchronous mode. Fig. 5.14.2.4 Clock synchronous transfer data format The input/output terminals of the serial interface can be assigned to P10-P13 or P14- P17. Select either one using the SIOSEL register. (3) Data format of asynchronous transfer The data format of asynchronous transfer is as follows: Data length: 7 bits or 8 bits Table 5.14.2.2 Input/output terminals Terminal SIN SOUT SCLK SRDY SIOSEL="0" P10 P11 P12 P13 8 bits none none none (decided by transfer mode selection) SIOSEL="1" P14 P15 P16 P17 Start bit: Stop bit: Parity bit: 1 bit stationary 1 bit or 2 bits even parity, odd parity or none The stop bit can be set with the STPB register, and the parity bit can be set with the EPR register and the PMD register shown in Table 5.14.2.4. (ESIF="1") It is set to P10-P13 at initial reset. When using the IR interface, select P14-P17. The ports which are not used in the serial interface can be used as the I/O port. Table 5.14.2.4 Setting of stop bit and parity bit Input/output configuration of the four lines differs depending on the transfer mode. Table 5.14.2.3 shows the terminal configuration of each mode. STPB EPR PMD 1 1 0 0 1 1 0 - 1 0 - The clock synchronous slave mode uses all four lines. 0 The clock synchronous master mode does not use SRDY, so P13 (P17) can be used as the I/O port. Setting Stop bit 2 bits 2 bits 2 bits 1 bit 1 bit 1 bit Parity bit Odd Even None Odd Even None At initial reset, they are set in 1 stop bit and no parity. Table 5.14.2.3 Terminal setting for each transfer mode Mode 8-bit asynchronous 7-bit asynchronous SIN Data input Data input SOUT Data output Data output SCLK P12/P16 P12/P16 SRDY P13/P17 P13/P17 Clock synchronous slave Clock synchronous master Data input Data input Data output Data output Clock input Clock output Ready output P13/P17 132 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Sampling clock (for transmission) 7-bit asynchronous mode (Stop bit: 1 bit, No parity) s1 D0 D1 D2 D3 D4 D5 D6 s2 (Stop bit: 1 bit, With parity) s1 D0 D1 D2 D3 D4 D5 D6 p s2 (Stop bit: 2 bits, No parity) s1 D0 D1 D2 D3 D4 D5 D6 s2 s3 (Stop bit: 2 bits, With parity) s1 D0 D1 D2 D3 D4 D5 D6 p s2 (Stop bit: 1 bit, No parity) s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 (Stop bit: 1 bit, With parity) s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 (Stop bit: 2 bits, No parity) s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 s3 (Stop bit: 2 bits, With parity) s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 8-bit asynchronous mode s3 s3 s1: start bit, s2 & s3: stop bit, p: parity bit Fig. 5.14.2.5 Asynchronous transfer data format 5.14.3 Mask option 5.14.4 Clock source The input/output terminals of the serial interface are shared with the I/O port terminals. Therefore, the terminal specification of the serial interface is decided by setting the I/O port mask option. The clock source of the serial interface is the 8-bit programmable timer. I/O port pull-up resistor P10 (SIN) With resistor P12 (SCLK) With resistor P14 (SIN) With resistor P16 (SCLK) With resistor Gate direct Gate direct Gate direct Gate direct Note: The configuration of the ports which are used for the serial interface input differs depending on the transfer mode setting. Synchronous clock in clock synchronous mode The I/O port has a built-in pull-up resistor that is activated during the input mode, and it can be individually selected for use or not by the mask option. This mask option (pull-up resistor) is effective for the input lines of the serial interface. When "Gate direct" is selected, take care that a floating status does not occur in the input terminal. 8-bit programmable timer output clock 1 2 3 When using the internal clock, it is necessary to output the clock from the 8-bit programmable timer beforehand. Refer to Section 5.13, "8-bit Programmable Timer", for control of the 8-bit programmable timer. Be aware that the serial interface does not operate when the OSC3 oscillation circuit has been turned off, because in this case the 8-bit programmable timer does not operate. The clock synchronous master mode divides the output clock of the 8-bit programmable timer in 1/ 16, and uses it as the synchronous clock SCLK. The clock synchronous slave mode uses an external clock input from the SCLK terminal. In this mode, it is not necessary to control the 8-bit programmable timer. ... 16 Synchronous clock SCLK Fig. 5.14.4.1 Synchronous clock SCLK S1C88409 TECHNICAL MANUAL EPSON 133 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Sampling clock of asynchronous mode the rising edge of the sampling clock. When the stop bit is sampled, the sampling signal is fixed at "1" until the next start bit is detected. If the serial input is not "0" at the time of start bit sampling with the eighth input clock because the baud rate set in this interface is different from the transmitter or noise is input to the SIN terminal, the following data sampling is stopped and the interface shifts into standby status for the next start bit detection. The asynchronous system in this interface generates a sampling clock on the basis of the output clock of the 8-bit programmable timer. However, it is necessary that the 8-bits programmable timer has output a clock of 16 times the baud rate. (1) At receiving As shown in Figure 5.14.4.2, duty of the internal sampling clock is not 50 %. The sampling clock changes from "1" to "0" with the second input clock after recognizing a start bit, and returns to "1" with the eighth clock so that sampling will be done at the middle of each bit data received. This sampling waveform is continuously output until sampling of the stop bit has completed. Each bit data is sampled at Start bit SIN 8-bit programmable timer output clock TCLK (2) At transmission In transmission, the serial interface generates a clock for transmission by dividing the output clock of the 8-bit programmable timer in 1/16 and outputs each bit in synchronization with the clock. 1 2 D0 8 16 1 2 8 Receive sampling clock 6xTCLK 10xTCLK Start bit sampling D0 bit sampling Fig. 5.14.4.2 Sampling clock for receiving in asynchronous system 8-bit programmable timer output clock 1 2 3 ... 16 Transmission sampling clock Fig. 5.14.4.3 Sampling clock for sending in asynchronous system 134 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 5.14.5 Control procedure to transmit/receive This section explains the control registers used to transmit and receive. Shift register and receive data buffer The serial interface is equipped with a shift register for serial/parallel conversion. Transmit data written in the transmit/receive data register TRXD is converted to serial data through the shift register and is output from the SOUT terminal. Besides the shift register, the receiver is equipped with a receive data buffer. At the time of receiving, data input from the SIN terminal is converted to parallel data through the shift register and loaded into the receive data buffer. However, the buffering function cannot be used in the clock synchronous mode. Therefore, it is necessary to read the received data before starting the next data receiving. Transmission enable register and transmission control bit The transmission enable register TXEN and the transmission control bit TXTRG are used to control transmissions. The transmission enable register TXEN enables and disables transmission. Writing "1" to this register enables transmission. In this status, clock input of the shift register is authorized, and the transmitter shifts into transmit standby status. In the clock synchronous mode, the synchronous clock input and output of the SCLK terminal is authorized, too. The transmission control bit TXTRG is used as a trigger for starting transmissions. To start a transmission, write "1" to TXTRG after a preparation to transmit has been completed by writing transmit data to the transmit/receive data register TRXD. When the transmission is completed, an interrupt is generated when the interrupt has been enabled. After the interrupt is generated, the next transmit data can be written. The receiving enable register RXEN and receiving control bit RXTRG are used to control receiving. The receiving enable register RXEN enables and disables receiving. Writing "1" to this register enables receiving. In this status, clock input of the shift register is authorized, and the receiver shifts into receive standby status. In the clock synchronous mode, the synchronous clock input and output of the SCLK terminal is authorized, too. When serial data is sent from the transmitter in this status, the data is loaded in the shift register. When receiving has completed, an interrupt is generated when the interrupt has been enabled. The operation of the receiving control bit RXTRG is slightly different depending on whether the clock synchronous mode or the asynchronous mode is being used. In the clock synchronous mode, RXTRG is used as a trigger to start receiving. When received data has been read and the preparation for the next data receiving is completed, write "1" in RXTRG to start receiving. (In the slave mode, the SRDY signal goes "0" when "1" is written to RXTRG.) In the asynchronous mode, RXTRG is used to prepare for the next data receiving. After reading the received data from the receive data buffer, write "1" in RXTRG to signify that the receive data buffer is empty. If "1" is not written in RXTRG, the overrun error flag OER will be set to "1" when the next receiving is completed. (An overrun error will be generated when the next receiving is completed between reading the previously received data and the writing of "1" to RXTRG.) RXTRG can also be read as a status. It goes "1" during receiving and goes "0" during standby (stopped) status. This function is the same in either the clock synchronous mode or the asynchronous mode. Refer to Section 5.14.9, "Timing charts", for timing of receiving. TXTRG can also be read as a status. It goes "1" during transmission and goes "0" during standby (stopped) status. Refer to Section 5.14.9, "Timing charts", for timing of transmission. Note: Do not set interface conditions, such as transfer mode, when the TXEN register is "1" (transmission authorize status). Setting except for transmission control must be done after writing "0" to the TXEN register. S1C88409 TECHNICAL MANUAL Receiving enable register and receiving control bit Note: Do not set interface conditions, such as transfer mode, when the RXEN register is "1" (receiving authorize status). Setting except for receiving control must be done after writing "0" to the RXEN register. EPSON 135 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 5.14.6 Receive error Overrun error During receiving the following three kinds of errors can be detected by an interrupt. In the asynchronous mode, an overrun error occurs when the next data is received before writing "1" to RXTRG. In the clock synchronous slave mode, an overrun error occurs when the next data is received before reading the received data. When an overrun error is generated, the overrun error flag OER and the error interrupt factor flag FSERR are set to "1". An error interrupt is generated at this point when the interrupt has been enabled. The OER flag is reset to "0" by writing "1". The received data is transferred to the receive data buffer even when an overrun error has generated, and the receiving operation also continues. Furthermore, when the received data is transferred to the receive data buffer at the same time "1" is written to RXTRG in the asynchronous mode, it is recognized as an overrun error. Parity error When the EPR register has been set to "1" (with parity), a parity check is executing during receiving (except for the clock synchronous mode). The parity check is done when data received in the shift register is transferred to the receive data buffer. It checks matching with the receive data and the setting of the PMD register (odd parity or even parity). If they are not matched, it is recognized as a parity error and the parity error flag PER and the error interrupt factor flag FSERR are set to "1". An error interrupt is generated at this point when the interrupt has been enabled. The PER flag is reset to "0" by writing "1". The received data is transferred to the receive data buffer even when a parity error has generated, and the receiving operation also continues. However, the received data cannot be assured. Framing error When the serial interface receives a stop bit as "0", it judges that the synchronization is deviated and generates a framing error. When a framing error is generated, the framing error flag FER and the error interrupt factor flag FSERR are set to "1". An error interrupt is generated at this point when the interrupt has been enabled. The FER flag is reset to "0" by writing "1". The received data is transferred to the receive data buffer even when a framing error has generated, and the receiving operation also continues. However, even when the following data receiving does not generate a framing error, the data cannot be assured. 136 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 5.14.7 Interrupt function Furthermore, the priority level of the interrupt for the CPU can be set to an optional level (0-3) using the interrupt priority register. Table 5.14.7.1 shows the interrupt control registers. The serial interface can generate the following three interrupts. * Transmit completion interrupt * Receive completion interrupt * Receive error interrupt The interrupt factor flag that indicates an interrupt factor generation and the interrupt enable register that enables and disables the interrupt are provided for each interrupt factor. Refer to Section 5.20 "Interrupt and Standby Mode", for details of the interrupt control registers and operations subsequent to interrupt generation. Figure 5.14.7.1 shows the configuration of the serial interface interrupt circuit. Table 5.14.7.1 Interrupt control registers Interrupt factor Receive error Receive completion Transmit completion Address Receive error Address Data bus Address Receive completion Address Address Transmit completion Address Address Interrupt factor flag Name Address*Dx FSERR 00FF28H*D0 FSRX 00FF28H*D1 FSTX 00FF28H*D2 Interrupt enable register Interrupt priority register Name Address*Dx Name Address*Dx ESERR 00FF24H*D0 PSI0 00FF21H*D4 ESRX 00FF24H*D1 PSI1 00FF21H*D5 ESTX 00FF24H*D2 Interrupt priority register PSI0, PSI1 Interrupt factor flag FSERR Interrupt enable register ESERR Interrupt factor flag FSRX Interrupt priority level judgment circuit Interrupt enable register ESRX Interrupt request Interrupt factor flag FSTX Interrupt enable register ESTX Fig. 5.14.7.1 Configuration of serial interface interrupt circuit S1C88409 TECHNICAL MANUAL EPSON 137 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Transmit completion interrupt Receive error interrupt This interrupt factor occurs when the transmission of the data written in the shift register has completed, and sets the interrupt factor flag FSTX to "1". It generates an interrupt to the CPU when the interrupt enable register ESTX has been set to "1" and the interrupt priority register PSI has been set to a higher level than the setting of the interrupt flag (I0, I1). When the interrupt is disabled by setting the ESTX register to "0", interrupt does not occur to the CPU. However, even in this case the FSTX flag is set to "1". The interrupt factor flag FSTX is reset to "0" by writing "1". This interrupt factor occurs when a parity error , a framing error or an overrun error is detected during receiving, and sets the interrupt factor flag FSERR to "1" at the same point of the receive completion interrupt generation. It generates an interrupt to the CPU when the interrupt enable register ESERR has been set to "1" and the interrupt priority register PSI has been set to a higher level than the setting of the interrupt flag (I0, I1). When the interrupt is disabled by setting the ESERR register to "0", interrupt does not occur to the CPU. However, even in this case the FSERR flag is set to "1". The interrupt factor flag FSERR is reset to "0" by writing "1". After the interrupt factor occurs, it is possible to write the next transmission data and to start the transmission (writing "1" to TXTRG). The exception processing vector addresses for the transmit completion interrupt are set as follows: Transmit completion interrupt: 00001EH Since all three kinds of errors result in the same interrupt factor, the error generated should be distinguished using the error flags PER (parity error), OER (overrun error) and FER (framing error). The exception processing vector addresses for the receive error interrupt are set as follows: Receive completion interrupt This interrupt factor occurs when the data received into the shift register is transferred to the receive data buffer after receiving is completed, and sets the interrupt factor flag FSRX to "1". It generates an interrupt to the CPU when the interrupt enable register ESRX has been set to "1" and the interrupt priority register PSI has been set to a higher level than the setting of the interrupt flag (I0, I1). When the interrupt is disabled by setting the ESRX register to "0", interrupt does not occur to the CPU. However, even in this case the FSRX flag is set to "1". The interrupt factor flag FSRX is reset to "0" by writing "1". After the interrupt factor occurs, it is possible to read the received data. The interrupt factor flag FSRX is set to "1" even when a parity error or a framing error has occurred. The exception processing vector addresses for the receive completion interrupt are set as follows: Receive error interrupt: 00001AH Note: When a parity error or a framing error occurs, both the receive error interrupt factor flag FSERR and the receive completion interrupt factor flag FSRX are simultaneously set to "1". However, since the receive error interrupt has priority over the receive completion interrupt, the receive error interrupt process is executed first. Therefore, it is necessary to reset the FSRX flag in the receive error handling routine. When a receive error interrupt occurs due to an overrun, receive completion interrupt does not occur. Receive completion interrupt: 00001CH 138 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 5.14.8 IR (Infrared-ray) interface IR communication module S1C88409 LED A SOUT (P15) PPM modulator LED TXD VP1N LED C Serial I/F SIN (P14) PPM modulator Photodiode RXD CX1 VDD Vcc CX2 VSS VP1N GND (Reference: HP HSDL-1000) Fig. 5.14.8.1 Configuration example of IR interface The serial interface has a built-in PPM modulator. Thus a circuit for infrared-ray communication based on IrDA (Infrared Data Association) standard can be configured by adding a simple external circuit. Setting of IR interface When IR interface function is set, the serial interface can reverse the logic polarity of the input/output signal according to the infrared-ray communication module to be connected to the outside. It is negative logic usually. Reverse the logic when inputting and outputting positive logic signal. The logic of the SIN input and SOUT output can be individually set by the IRIL register and the IRTL register. (See Tables 5.14.8.2 and 5.14.8.3.) The PPM modulator is only available when the P14-P17 terminals are selected and the asynchronous mode is set. When using the IR interface, change the function At initial reset, both the IRIL register and IRTL of the serial interface using the IRST register. (See register are set to "0" (logic not reversed). Table 5.14.8.1.) At initial reset, the serial interface is set as general interface. Table 5.14.8.1 Setting of IR interface IRST1 IRST0 1 1 0 1 0 1 Reserved (do not set) IR interface is used Reserved (do not set) Setting 0 0 IR interface is not used (normal interface is set) Table 5.14.8.2 Input logic of IR interface IRIL 1 0 Setting SIN input logic is reversed (HIGH active) SIN input logic is not reversed (LOW active) Table 5.14.8.3 Output logic of IR interface IRTL 1 0 S1C88409 TECHNICAL MANUAL Setting SOUT output logic is reversed (HIGH active) SOUT output logic is not reversed (LOW active) EPSON 139 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Control of IR interface The PPM modulator converts input/output signals so that an IR pulse width becomes 3/16 of the pulse width asynchronous input/output signal. 8-bit programmable timer output clock TCLK The control procedure of data transfer is the same as in case of the asynchronous mode. Refer to Section 5.14.5 "Control procedure to transmit/ receive". 1 2 3 8 9 10 11 16 PPM modulator input (SIF output) PPM modulator output (SOUT) 3xTCLK (1) During transmission 8-bit programmable timer output clock TCLK 1 2 3 4 16 17 18 19 20 PPM modulator input (SIN) PPM modulator output (SIF input) 16xTCLK (2) During receiving Fig. 5.14.8.2 Input/output signal 140 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 5.14.9 Timing charts Note: Do not write data to TXTRG, RXTRG and the TRXD register during transmission (while reading of TXTRG is "1"). The following shows the transmit/receive timing chart for each transfer mode. Clock synchronous master mode This mode uses a clock generated by dividing the 8-bit programmable timer output in 1/16 as the synchronous clock SCLK. (See Figure 5.14.4.1.) (1) Transmission timing in clock synchronous master mode Figure 5.14.9.1 shows the transmission timing in clock synchronous master mode. By writing "1" to the TXTRG bit, the synchronous clock is output from the SCLK terminal. Each bit of transmission data is output from the SOUT terminal at the falling edge of the synchronous clock. When the last bit is output, a transmit completion interrupt is generated at the rising edge of the synchronous clock. (2) Receiving timing in clock synchronous master mode Figure 5.14.9.2 shows the receiving timing in clock synchronous master mode. By writing "1" to the RXTRG bit, the synchronous clock is output from the SCLK terminal. The status of the SIN terminal is input at each rising edge of the synchronous clock. When the last bit is input, a receive completion interrupt is generated simultaneously. After the interrupt is generated, the received data can be read from the TRXD register. Note: Do not write data to TXTRG, RXTRG and the TRXD register during receiving (while reading of RXTRG is "1"). TXEN TXTRG (WR) SCLK SOUT D0 D1 D2 D3 D4 D5 D6 D7 TXTRG (RD) Transmit completion interrupt generation Fig. 5.14.9.1 Transmission timing (clock synchronous master mode) RXEN RXTRG (WR) SCLK SIN D0 D1 D2 D3 TRXD (RD) D4 D5 D6 D7 Received data RXTRG (RD) Receive completion interrupt generation Fig. 5.14.9.2 Receiving timing (clock synchronous master mode) S1C88409 TECHNICAL MANUAL EPSON 141 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Clock synchronous slave mode After the interrupt is generated, the received data can be read from the TRXD register. When a parity error or a framing error (stop bit = "0") occurs, the error interrupt is generated at the same time as the receive completion interrupt. An overrun error occurs when the next data is received before reading the previous received data. In this case, the interrupt generation timing is the same as other interrupts. This mode uses a clock input from the SCLK terminal (output from the master device) as the synchronous clock SCLK. (1) Transmission timing in clock synchronous slave mode Figure 5.14.9.3 shows the transmission timing in clock synchronous slave mode. After writing "1" to the TXTRG bit each bit of transmission data is output from the SOUT terminal at the falling edge of the synchronous clock input from the SCLK terminal. When the last bit is output, a transmit completion interrupt is generated at the rising edge of the synchronous clock. Note: Do not write data to TXTRG, RXTRG and the TRXD register during receiving (while reading of RXTRG is "1"). (3) Transmit/receive ready (SRDY) signal When the serial interface is used in the clock synchronous slave mode, it can output the SRDY signal that indicates whether the serial interface is ready to transmit/receive or not. The SRDY signal is output from the SRDY terminal as "0" (low level) when the serial interface is in ready status (ready to transmit/ receive) and as "1" (high level) when it is in busy status (during transmission/receiving). The SRDY signal changes from "1" to "0" immediately after writing "1" to TXTRG or RXTRG, and returns from "0" to "1" when the first synchronous clock is input (at rising edge). (See Figure 5.14.9.3, Figure 5.14.9.4.) Note: Do not write data to TXTRG, RXTRG and the TRXD register during transmission (while reading of TXTRG is "1"). (2) Receiving timing in clock synchronous slave mode Figure 5.14.9.4 shows the receiving timing in clock synchronous slave mode. After writing "1" to the RXTRG bit, the status of the SIN terminal is input at each rising edge of the synchronous clock input from the SCLK terminal. When the last bit is input, a receive completion interrupt is generated simultaneously. TXEN TXTRG (WR) SCLK SOUT D0 D1 D2 D3 D4 D5 D6 D7 TXTRG (RD) SRDY Transmit completion interrupt generation Fig. 5.14.9.3 Transmission timing (clock synchronous slave mode) RXEN RXTRG (WR) SCLK SIN D0 D1 D2 D3 TRXD (RD) D4 D5 D6 D7 Received data RXTRG (RD) SRDY Receive completion interrupt generation Fig. 5.14.9.4 Receiving timing (clock synchronous slave mode) 142 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) When receiving data in the asynchronous mode, it is necessary to write "1" to the RXTRG bit after reading received data. An internal signal OERCS checks overrun error. It goes "1" at the end of every data receiving (immediately after inputting the stop bit), and goes "0" by writing "1" to the RXTRG bit. An overrun error occurs if the OERCS signal has not returned to "0" when the stop bit is input. In this case, the error interrupt is generated at the same time as the receive completion interrupt. When the received data is transferred to the receive data buffer at the same time "1" is written to RXTRG, it is recognized as an overrun error. Pay attention to the write timing. Asynchronous mode (1) Transmission timing in asynchronous mode Figure 5.14.9.5 shows the transmission timing of the 8-bit asynchronous mode (stop bit = 2 bits, with parity). After writing "1" to the TXTRG bit, each bit of transmission data is output from the SOUT terminal at the falling edge of the sampling clock generated internally. When the last bit is output, a transmit completion interrupt is generated at the rising edge of the clock. The sampling clock is generated by dividing the 8-bit programmable timer output in 1/16. (See Figure 5.14.4.3.) (2) Receiving timing in asynchronous mode Figure 5.14.9.6 shows the receiving timing of the 8-bit asynchronous mode (stop bit = 1 bit, with parity). When a start bit is input from the SIN terminal, a sampling clock for data receiving is generated (see Figure 4.14.4.2). The status of the SIN terminal is input at each rising edge of the sampling clock. When the last stop bit is input, a receive completion interrupt is generated simultaneously. After the interrupt is generated, the received data can be read from the TRXD register. When a parity error or a framing error (stop bit = "0") occurs, the error interrupt is generated at the same time as the receive completion interrupt. Note: When a parity error or a framing error occurs, both the receive error interrupt factor flag FSERR and the receive completion interrupt factor flag FSRX are simultaneously set to "1". However, since the receive error interrupt has priority over the receive completion interrupt, the receive error interrupt process is executed first. Therefore, it is necessary to reset the FSRX flag in the receive error handling routine. When a receive error interrupt occurs due to an overrun, receive completion interrupt does not occur. TXEN TXTRG (WR) Sampling clock SOUT s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 s3 TXTRG (RD) s1: start bit, s2 & s3: stop bit, p: parity bit Transmit completion interrupt generation Fig. 5.14.9.5 Transmission timing (8-bit asynchronous mode, stop bit = 2 bits, with parity) RXEN RXTRG (WR) Sampling clock SIN s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 TRXD (RD) s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 1st data s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 2nd data RXTRG (RD) OERCS OER s1: start bit s2: stop bit p: parity bit Receive completion interrupt generation Interrupt is generated when parity error or framing error is detected Receive completion interrupt generation Interrupt is generated when parity error or framing error is detected Overrun error interrupt generation Fig. 5.14.9.6 Receiving timing (8-bit asynchronous mode, stop bit = 1 bit, with parity) S1C88409 TECHNICAL MANUAL EPSON 143 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 5.14.10 I/O memory of serial interface Table 5.14.10.1 shows the serial interface control bits. Table 5.14.10.1(a) Serial interface control bits Address Bit 00FF21 D7 D6 D5 D4 D3 D2 D1 D0 00FF24 D7 144 Name PTM21 PTM20 PSI1 PSI0 PCTM1 PCTM0 PLCD1 PLCD0 ETU2 D6 ETC1 D5 ETU1 D4 ETC0 D3 ETU0 D2 ESTX D1 ESRX D0 ESERR 00FF28 D7 FTU2 D6 FTC1 D5 FTU1 D4 FTC0 D3 FTU0 D2 FSTX D1 FSRX D0 FSERR 00FF38 D7 D6 D5 D4 D3 D2 D1 D0 00FF40 D7 D6 D5 D4 D3 D2 - - - - - PTOUT PSET PRUN SIOSEL EPR PMD STPB - SMD1 D1 SMD0 D0 ESIF Function 8-bit programmable timer interrupt priority register Serial interface interrupt priority register Clock timer interrupt priority register LCD controller interrupt priority register 8-bit programmable timer underflow interrupt enable register 16-bit programmable timer 1 compare match interrupt enable register 16-bit programmable timer 1 underflow interrupt enable register 16-bit programmable timer 0 compare match interrupt enable register 16-bit programmable timer 0 underflow interrupt enable register Serial interface transmit completion interrupt enable register Serial interface receive completion interrupt enable register Serial interface receive error interrupt enable register 8-bit programmable timer underflow interrupt factor flag 16-bit programmable timer 1 compare match interrupt factor flag 16-bit programmable timer 1 underflow interrupt factor flag 16-bit programmable timer 0 compare match interrupt factor flag 16-bit programmable timer 0 underflow interrupt factor flag Serial interface transmit completion interrupt factor flag Serial interface receive completion interrupt factor flag Serial interface receive error interrupt factor flag - - - - - 8-bit programmable timer clock output control 8-bit programmable timer preset 8-bit programmable timer RUN/STOP control Serial I/F terminal selection Serial I/F parity enable Serial I/F parity mode selection Serial I/F stop bit selection - Serial I/F mode selection SMD0 Mode SMD1 1 8-bit asynchronous 1 0 7-bit asynchronous 1 1 Clock synchronous slave 0 0 Clock synchronous master 0 Serial I/F enable EPSON 1 0 Init R/W PTM21 PTM20 0 R/W PSI1 PSI0 0 R/W PCTM1 PCTM0 Priority 0 R/W level PLCD1 PLCD0 0 R/W Level 3 0 R/W 1 1 Level 2 0 R/W 1 0 Level 1 0 R/W 0 1 Level 0 0 R/W 0 0 0 R/W Comment 0 R/W 0 R/W 0 R/W Interrupt is enabled Interrupt is disabled 0 R/W 0 R/W 0 R/W 0 R/W 0 R/(W) (R) Interrupt factor has generated (R) Interrupt factor has not generated 0 R/(W) 0 R/(W) 0 R/(W) 0 R/(W) 0 R/(W) (W) Reset (W) Invalid 0 R/(W) 0 R/(W) - - - - - On Preset Run P14-P17 With parity Odd 2 bits - - - - - - Off Invalid Stop P10-P13 No parity Even 1 bit - - - - - - 0 - 0 0 0 0 0 - 0 - "0" when being read - - - - R/W W "0" when being read R/W R/W R/W R/W R/W - "0" when being read R/W 0 R/W Serial I/F I/O port 0 R/W S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Table 5.14.10.1(b) Serial interface control bits Address Bit 00FF41 D7 D6 D5 D4 D3 D2 D1 D0 00FF42 D7 D6 D5 D4 D3 D2 D1 D0 00FF43 D7 D6 D5 D4 D3 D2 D1 D0 Name - FER Function - Serial I/F framing error flag PER Serial I/F parity error flag OER Serial I/F overrun error flag RXTRG Serial I/F receive trigger/status RXEN Serial I/F receive enable TXTRG Serial I/F transmit trigger/status TXEN Serial I/F transmit enable TRXD7 Serial I/F D7(MSB) TRXD6 transmit/receive data register D6 TRXD5 D5 TRXD4 D4 TRXD3 D3 TRXD2 D2 TRXD1 D1 TRXD0 D0(LSB) - - - - - - - - IRTL IrDA interface output logic inversion IRIL IrDA interface input logic inversion IRST1 IrDA interface setting IRST1 IRST0 Setting 1 1 Reserved (do not set) 1 0 IrDA interface IRST0 0 1 Reserved (do not set) 0 0 Normal interface ESIF: Serial interface enable register (00FF40H*D0) Sets the input/output terminals for serial interface. 0 - No error Invalid No error Invalid No error Invalid Stop Invalid Disable Stop Invalid Disable High Low - - - - Inverse Inverse - - - - Normal Normal Init R/W Comment - - "0" when being read 0 R W 0 R W 0 R W 0 R W 0 R/W 0 R W 0 R/W x R/W TRXD7 is invalid in x R/W 7-bit asynchronous x R/W mode x R/W x R/W x R/W x R/W x R/W - - "0" when being read - - - - - - 0 R/W 0 R/W 0 R/W Valid only when SIOSEL = "1" in asynchronous mode 0 R/W PTOUT: 8-bit programmable timer clock output control register (00FF38H*D2) Controls the clock output to the serial interface. When "1" is written: Serial I/F I/O terminal When "0" is written: I/O port terminal Reading: Valid When "1" is written: ON When "0" is written: OFF Reading: Valid The ESIF register is the serial interface enable register. When "1" is written to the register, specified I/O port terminals are set to the terminals for the serial interface. Refer to Section 5.14.2, "Transfer mode and input/output terminals", for the terminal configurations. When "0" is written, they become the I/O port terminals. At initial reset, the ESIF register is set to "0" (I/O port terminal). S1C88409 TECHNICAL MANUAL 1 - Error Reset (0) Error Reset (0) Error Reset (0) Run Trigger Enable Run Trigger Enable The PTOUT register is the output control register of the 8-bit programmable timer. When "1" is written to this register, the clock (underflow 1/2) that is generated by the 8-bit programmable timer is output to the serial interface. When "0" is written, the clock is not output to the serial interface. Refer to Section 5.13, "8-bit Programmable Timer", for control of the 8-bit programmable timer. At initial reset, the PTOUT register is set to "0" (OFF). EPSON 145 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) SIOSEL: Terminal selection register (00FF40H*D7) Selects the terminals to be used for the serial interface input/output. EPR: Parity enable register (00FF40H*D6) Selects the parity function. When "1" is written: With parity When "0" is written: No parity Reading: Valid When "1" is written: P14-P17 When "0" is written: P10-P13 Reading: Valid When "1" is written to the SIOSEL register, the input/output terminals of the serial interface are assigned to P14-P17. When "0" is written, they are assigned to P10-P13. However, the terminals which are actually used within four the terminals are decided by the transfer mode setting (SMD register). When using IR interface, be sure to set the SIOSEL register to "1" (P14-P17). At initial reset, the SIOSEL register is set to "0" (P10-P13). The EPR register is the parity enable register. By setting this register, parity check for received data and addition of a parity bit to transmission data can be enabled. When "1" is written to the register, the most significant bit of received data is regarded as a parity bit and a parity check is executed and a parity bit is added to transmission data. When "0" is written, neither a parity check nor adding a parity bit is done. This setting is valid only in the asynchronous mode. It is invalid in the clock synchronous mode. At initial reset, the EPR register is set to "0" (no parity). SMD0, SMD1: Mode selection register (00FF40H*D1, D2) Sets the transfer mode as shown in Table 5.14.10.2. PMD: Parity mode selection register (00FF40H*D5) Selects odd parity or even parity. When "1" is written: Odd parity When "0" is written: Even parity Reading: Valid Table 5.14.10.2 Transfer mode settings SMD1 1 SMD0 1 Mode 8-bit asynchronous 1 0 0 1 7-bit asynchronous Clock synchronous slave 0 0 Clock synchronous master The SMD register can also be read. When using IR interface, be sure to set in the asynchronous mode. At initial reset, the SMD register is set to "0" (clock synchronous master mode). STPB: Stop bit selection register (00FF40H*D4) Selects the stop bit length asynchronous transfer. When "1" is written: 2 bits When "0" is written: 1 bit Reading: Valid The STPB register is the stop bit selection register that is valid only for asynchronous transfer. When "1" is written to the register, the stop bit length is set in 2 bits. When "0" is written, it is set in 1 bit. The start bit length is fixed at 1 bit. The start/stop bit cannot be added for clock synchronous transfer. Therefore, the setting of the STPB register is invalid. At initial reset, the STPB register is set to "0" (1 bit). 146 The PMD register is the parity mode selection register. When "1" is written to the register, odd parity is selected. When "0" is written, even parity is selected. The parity check and addition of a parity bit are valid only when "1" has been written to the EPR register. When "0" has been written to the EPR register, parity setting by the PMD register is invalid. At initial reset, the PMD register is set to "0" (even parity). TXEN: Transmission enable register (00FF41H*D0) Sets the serial interface to the transmission authorize status. When "1" is written: Transmission is enabled When "0" is written: Transmission is disabled Reading: Valid The TXEN register is the transmission enable register. When "1" is written to the register, the serial interface shifts to a transmission authorize status. When "0" is written, it shifts to a transmission disabling status. Set the TXEN register to "0" when setting the transfer mode. At initial reset, the TXEN register is set to "0" (transmission is disabled). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) In the asynchronous mode, RXTRG is used to prepare for the next data receiving. After reading the received data from the receive data buffer, write "1" in RXTRG to signify that the receive data buffer is empty. If "1" is not written in RXTRG, the overrun error flag OER will be set to "1" when the next receiving is completed. (An overrun error will be generated when the next receiving is completed between reading the previous received data and the writing of "1" to RXTRG.) TXTRG: Transmission trigger/status (00FF41H*D1) This bit is used as the transmission start trigger and the operation status indicator (transmission/ stop status). When "1" is read: During transmission When "0" is read: During stop When "1" is written: Transmission trigger When "0" is written: Invalid TXTRG is the transmission control bits (trigger/ status). Transmission starts when "1" is written to TXTRG after writing the transmission data. TXTRG can be read as the status. When it is "1", it indicates transmission, and "0" indicates stoppage. At initial reset, TXTRG is set to "0" (during stop). RXTRG can also be read as a status. When it is "1", it indicates receiving, and "0" indicates stoppage. This function is the same in both the clock synchronous mode and the asynchronous mode. At initial reset, RXTRG is set to "0" (during stop). RXEN: Receiving enable register (00FF41H*D2) Sets the serial interface to the receiving authorize status. TRXD0-TRXD7: Transmit/receive data register (00FF42H) The TRXD register is the transmit/receive data register for the serial interface. When "1" is written: Receiving is enabled When "0" is written: Receiving is disabled Reading: Valid During transmission Write a transmission data to this register. The RXEN register is the receiving enable register. When "1" is written to the register, the serial interface shifts to a receiving authorize status. When "0" is written, it shifts to a receiving disabling status. Set the RXEN register to "0" when setting the transfer mode. At initial reset, the RXEN is set to "0" (receiving is disabled). RXTRG: Receiving trigger/status (00FF41H*D3) This bit is used as the receiving start trigger, ready to receive and the operation status indicator (receiving/stop status). When "1" is written: HIGH level When "0" is written: LOW level Write the transmitting data prior to start transmission. When transmitting data continuously, following data should be written after the transmit completion interrupt occurs. In the 7-bit asynchronous mode, TRXD7 is invalid. The data written in this register is converted into serial data, and output from the SOUT terminal as the bit set to "1" is a high (VDD) level and the bit set to "0" is a low (VSS) level. During receiving Received data can be read from this register. When "1" is read: During receiving When "0" is read: During stop When "1" is read: HIGH level When "0" is read: LOW level When "1" is written: Receiving trigger /Ready to receive When "0" is written: Invalid RXTRG is the receiving control bits (trigger/ status). In the clock synchronous mode, RXTRG is used as a trigger to start receiving. When received data has been read and the preparation for the next data receiving is completed, write "1" in RXTRG to start receiving. S1C88409 TECHNICAL MANUAL The data in the receive data buffer can be read. Received data should be read after the receive completion interrupt occurs. In the asynchronous mode, the received data can be read even while the next data is being received because the receive data buffer is provided separately from the shift register. (The buffer function is not used in the clock synchronous mode.) EPSON 147 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) In the 7-bit asynchronous mode, TRXD7 is always read as "0". The serial data input from the SIN terminal is loaded into this buffer after converting into parallel data as the bit of a high (VDD) level is "1" and the bit of a low (VSS) level is "0". At initial reset, the content of the TRXD register is undefined. OER: Overrun error flag (00FF41H*D4) Indicates the occurrence of an overrun error. When "1" is read: Error When "0" is read: No error When "1" is written: Reset to "0" When "0" is written: Invalid FER: Framing error flag (00FF41H*D6) Indicates the occurrence of a framing error. When "1" is read: Error When "0" is read: No error When "1" is written: Reset to "0" When "0" is written: Invalid FER is the error flag that indicates the occurrence of a framing error. The flag goes "1" when a framing error occurs. Framing error occurs when a stop bit is received as "0". The FER flag is reset to "0" by writing "1". At initial reset and when the RXEN register is "0", the FER flag is set to "0" (no error). OER is the error flag that indicates the occurrence of an overrun error. The flag goes "1" when an overrun error occurs. In the asynchronous mode, an overrun error occurs when the next data is received prior to writing "1" to RXTRG. In the clock synchronous slave mode, an overrun error occurs when the next data is received prior to reading the received data. In the clock synchronous master mode, overrun error does not occur. The OER flag is reset to "0" by writing "1". At initial reset and when the RXEN register is "0", the OER flag is set to "0" (no error). PSI0, PSI1: Interrupt priority register (00FF21H*D4, D5) Sets the priority level of the serial interface interrupt. The PSI register is the interrupt priority register corresponding to the serial interface interrupt. Table 5.14.10.3 shows the interrupt priority level which can be set by this register. PER: Parity error flag (00FF41H*D5) Indicates the occurrence of a parity error. At initial reset, the PSI register is set to "0" (level 0). Interrupt priority level PSI1 PSI0 1 1 1 0 Level 3 Level 2 (IRQ3) (IRQ2) 0 0 1 0 Level 1 Level 0 (IRQ1) (None) ESERR, ESRX, ESTX: Interrupt enable register (00FF24H*D0, D1, D2) Enables or disables the serial interface interrupt generation to the CPU. When "1" is read: Error When "0" is read: No error When "1" is written: Reset to "0" When "0" is written: Invalid PER is the error flag that indicates the occurrence of a parity error. The flag goes "1" when a parity error occurs. The PER flag is reset to "0" by writing "1". At initial reset and when the RXEN register is "0", the PER flag is set to "0" (no error). 148 Table 5.14.10.3 Interrupt priority level settings When "1" is written: Interrupt is enabled When "0" is written: Interrupt is disabled Reading: Valid The ESERR, ESRX and ESTX registers are interrupt enable registers corresponding to the receive error, receive completion and transmit completion interrupt factors, respectively. Interrupt in which the interrupt enable register is set to "1" is enabled, and the others in which the register is set to "0" are disabled. At initial reset, the interrupt enable registers are all set to "0" (interrupt is disabled). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 5.14.11 Programming notes FSERR, FSRX, FSTX: Interrupt factor flag (00FF28H*D0, D1, D2) Indicates the generation of the serial interface interrupt factor. (1) Setting of the serial interface mode must be done in the transmission/receiving disabling status (TXEN = RXEN = "0"). When "1" is read: Int. factor has generated When "0" is read: Int. factor has not generated When "1" is written: Factor flag is reset When "0" is written: Invalid The FSERR, FSRX and FSTX flags are interrupt factor flags corresponding to the receive error, receive completion and transmit completion interrupts, respectively. They are set to "1" by a generation of each factor. Transmit completion interrupt factor is generated when a transmission of the shift register data is completed. Receive completion interrupt factor is generated when the received data is transferred to the receive data buffer. Receive error interrupt factor is generated when a parity error, framing error or overrun error has been detected during data receiving. At this point, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I0 and I1), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "1" when the interrupt generation condition is met. To accept the subsequent interrupt after an interrupt generation, it is necessary to re-set the interrupt flags (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "0" by writing "1". At initial reset, the interrupt factor flags are all reset to "0". S1C88409 TECHNICAL MANUAL (2) Do not perform double trigger (writing "1") to TXTRG (RXTRG) during transmission (receiving). Furthermore, do not execute the SLP instruction. (When executing the SLP instruction, set TXEN and RXEN to "0".) (3) Transmission and receiving cannot be done simultaneously in the clock synchronous mode because the clock line (SCLK) is shared with transmit and receive operation. Therefore, do not write "1" to RXTRG (TXTRG) when TXTRG (RXTRG) is "1". (4) When a parity error or a framing error occurs, both the receive error interrupt factor flag FSERR and the receive completion interrupt factor flag FSRX are simultaneously set to "1". However, since the receive error interrupt has priority over the receive completion interrupt, the receive error interrupt process is executed first. Therefore, it is necessary to reset the FSRX flag in the receive error handling routine. When a receive error interrupt occurs due to an overrun, receive completion interrupt does not occur. EPSON 149 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 5.15.2 Control of buzzer output 5.15 Sound Generator 5.15.1 Configuration of sound generator The S1C88409 has a built-in sound generator for generating BZ (buzzer) signal. BZ signals generated from the sound generator can be output from the R42 output port terminal. Aside permitting the respective setting of the buzzer signal frequency and sound level (duty adjustment) to 8 stages, it permits the adding of a digital envelope by means of duty ratio control. It also has a one-shot output function for outputting key operated sounds. Figure 5.15.1.1 shows the configuration of the sound generator. BZFQ0-BZFQ2 fOSC1 OSC1 oscillation circuit Dividing circuit 256 Hz ENRTM Envelope addition circuit The output control for the BZ signal generated by the sound generator is done by the buzzer output control register BZON, one-shot buzzer trigger bit BZSHT and one-shot buzzer forced stop bit BZSTP. When "1" is set to BZON or BZSHT, the BZ signal is output from the R42 output port terminal and when "0" is set to BZON or "1" is set to BZSTP, the high (VDD) level is output. At this time, "1" must always be set for the output data register R42D. Figure 5.15.2.2 shows the output waveform of the BZ signal. Note: Since the BZ signal is generated asynchronously from the registers BZON, BZSHT and BZSTP, when the signal is turned ON or OFF by the register settings, a hazard of a 1/2 cycle or less is generated. Programmable dividing circuit ENRST BZ signal can be output from the R42 output port terminal. The configuration of the output port R42 is shown in Figure 5.15.2.1. Duty ratio control circuit DUTY0-DUTY2 Buzzer output control circuit Output port R42 ENON BZSHT One-shot buzzer control circuit BZSTP SHTPW BZ (R42) BZON Fig. 5.15.1.1 Configuration of sound generator Register R42D BZ signal Register BZSHT S Q Register BZSTP One-shot time up R42 output R Register BZON Fig. 5.15.2.1 Configuration of R42 BZON/BZSHT 0 1 BZ output (R42) Fig. 5.15.2.2 Output waveform of BZ signal 150 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 5.15.3 Setting of buzzer frequency and sound level The BZ signal is a divided signal using the OSC1 oscillation circuit (32.768 kHz) as the clock source and 8 frequencies can be selected. This selection is done by the buzzer frequency selection register BZFQ0-BZFQ2. The setting value and buzzer frequency correspondence is shown in Table 5.15.3.1. Table 5.15.3.1 Buzzer signal frequency settings BZFQ2 BZFQ1 BZFQ0 0 0 4096.0 0 0 1 1 0 3276.8 1 1 0 0 0 By selecting the duty ratio of the BZ signal from among 8 types, the buzzer sound level can be adjusted. This selection is made in the duty ratio selection register DUTY0-DUTY2. The setting value and duty ratio correspondence is shown in Table 5.15.3.2. Buzzer frequency (Hz) 0 1 1 0 0 1 1 1 1 2730.7 2340.6 2048.0 1638.4 1 0 1365.3 1170.3 1 Table 5.15.3.2 Duty ratio settings Duty ratio by buzzer frequencies (Hz) Level DUTY2 DUTY1 DUTY0 4096.0 2048.0 3276.8 1638.4 2730.7 1365.3 2340.6 1170.3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16 8/20 7/20 6/20 5/20 4/20 3/20 2/20 1/20 12/24 11/24 10/24 9/24 8/24 7/24 6/24 5/24 12/28 11/28 10/28 9/28 8/28 7/28 6/28 5/28 Level 1 (Max) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (Min) Duty ratio refers to the ratio of pulse width to the pulse cycle; given that HIGH level output time is TH, and low level output time is TL the BZ signal becomes TL/(TH+TL). When DUTY0-DUTY2 have all been set to "0", the duty ratio becomes maximum and the sound level also becomes maximum. Conversely, when DUTY0-DUTY2 have all been set to "1", the duty ratio becomes minimum and the sound level also becomes minimum. Note that the duty ratio setting differ depending on frequency. See Table 5.15.3.2. TH TL Level 1 (MAX) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (MIN) Fig. 5.15.3.1 Duty ratio of buzzer signal waveform Note: When using the digital envelope, the DUTY0-DUTY2 setting becomes invalid. S1C88409 TECHNICAL MANUAL 5.15.4 Digital envelope A digital envelope with duty control can be added to the BZ signal. The envelope can be realized by staged changing of the same duty ratio as detailed in Table 5.15.3.2 in the preceding section from level 1 (maximum) to level 8 (minimum). The addition of an envelope to the buzzer signal can be done by writing "1" to the envelope control register ENON. When "0" is written, the duty ratio is set at the level selected in DUTY0-DUTY2. By writing "1" to ENON and turning the buzzer output ON (writing "1" to BZON), a BZ signal with a level 1 duty ratio is output, and then the duty ratio can be attenuated in stages to level 8. The attenuated envelope can be returned to level 1 by writing "1" to the envelope reset bit ENRST. When attenuated to level 8, the duty level remains at level 8 until the buzzer output is turned OFF (writing "0" to BZON) or writing "1" to ENRST. The stage changing time for the envelope level can be selected either 125 msec or 62.5 msec by the envelope attenuation time selection register ENRTM. Figure 5.15.4.1 shows the timing chart of the digital envelope. EPSON 151 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) No change of duty level BZFQ0-2 ENON ENRST ENRTM BZON BZ signal duty ratio level 1 (MAX) 2 3 4 5 6 7 8 (MIN) t01 t02 t03 t04 t05 t06 t07 t11 t12 t01 +0 62.5 -4 t13 t14 t15 t16 t17 +0 125 -4 msec t01 = t02-07 = 62.5 msec t11 = msec t12-17 = 125 msec Fig. 5.15.4.1 Timing chart of digital envelope 5.15.5 One-shot output The sound generator has a built-in one-shot output function for outputting a short duration buzzer signal for key operation sounds and similar effects. Either 125 msec or 31.25 msec can be selected by the one-shot buzzer duration selection register SHTPW for buzzer signal output time. The output control of the one-shot buzzer is done by writing "1" to the one-shot buzzer trigger BZSHT, then the BZ signal is output in synchronization with the internal 256 Hz signal from the R42 output port terminal. Thereafter, when the set time has elapsed, the BZ signal in synchronization with the 256 Hz signal automatically goes OFF in the same manner. The BZSHT can be read to determine status. When BZSHT is "1", it indicates a BUSY status (during one-shot output) and when BZSHT is "0", it indicates a READY status (during stop). When you want to turn the BZ signal OFF prior to the elapse of the set time, the BZ signal can be immediately stopped (goes OFF in asynchonization with 256 Hz signal) by writing "1" to the one-shot forced stop bit BZSTP. The control for the one-shot output is invalid during normal buzzer output. Figure 5.15.5.1 shows the timing chart of the oneshot output. 256 Hz SHTPW BZSHT(W) BZSHT(R) BZSTP BZ output (R42) Fig. 5.15.5.1 Timing chart of one-shot output Since the one-shot output has a short duration, an envelope cannot be added. (When "1" is written to BZSHT, ENON is automatically reset to "0".) Consequently, only the frequency and sound level can be set for one-shot output. 152 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 5.15.6 I/O memory of sound generator Table 5.15.6.1 shows the sound generator control bits. Table 5.15.6.1 Sound generator control bits Address Bit 00FF54 D7 D6 D5 Name - BZSTP BZSHT D4 D3 D2 D1 D0 00FF55 D7 D6 SHTPW ENRTM ENRST ENON BZON - DUTY2 1 Function - One-shot buzzer forcibly stop One-shot buzzer trigger/status 1 0 Init R/W Comment - - - - "0" when being read Forcibly stop No operation - W Busy Ready 0 R Trigger No operation 0 W 125 msec 31.25 msec 0 R/W 1 sec 0.5 sec 0 R/W Reset No operation - W "0" when being read On Off 0 R/W 1 On Off 0 R/W - - - - "0" when being read 0 R/W One-shot buzzer duration width selection Envelope attenuation time Envelope reset Envelope On/Off control Buzzer output control - Buzzer signal duty ratio selection DUTY2-1 Buzzer frequency (Hz) 4096.0 3276.8 2730.7 2340.6 2 1 0 2048.8 1638.4 1365.3 1170.3 D5 DUTY1 0 0 0 8/16 8/20 12/24 12/28 0 0 1 7/16 7/20 11/24 11/28 0 1 0 6/16 6/20 10/24 10/28 0 1 1 5/16 5/20 9/24 9/28 1 0 0 4/16 4/20 8/24 8/28 D4 DUTY0 1 0 1 3/16 3/20 7/24 7/28 1 1 0 2/16 2/20 6/24 6/28 1 1 1 1/16 1/20 5/24 5/28 D3 - - D2 BZFQ2 Buzzer frequency selection BZFQ2 BZFQ1 BZFQ0 Frequency (Hz) 0 0 0 4096.0 0 0 1 3276.8 D1 BZFQ1 0 1 0 2730.7 0 1 1 2340.6 1 0 0 2048.0 D0 BZFQ0 1 0 1 1638.4 1 1 0 1365.3 1 1 1 1170.3 ENON is reset to "0" during one-shot output. 0 R/W - - - - "0" when being read 0 R/W 0 R/W 0 R/W BZFQ0-BZFQ2: Buzzer frequency selection register (00FF55H*D0-D2) Selects the BZ signal frequency. BZON: Buzzer output control register (00FF54H*D0) Controls the BZ signal output. When "1" is written: BZ signal output When "0" is written: HIGH level (DC) output Reading: Valid BZON is the output control register for BZ signal. When "1" is set, the BZ signal is output from the output port terminal R42 and when "0" is set, high (VDD) level is output. At this time, the highimpedance control register of the output port R42 must be set to "0" and the data register must be set to "1". At initial reset, BZON is set to "0" (high level output). S1C88409 TECHNICAL MANUAL 0 R/W Table 5.15.6.2 Buzzer frequency settings BZFQ2 BZFQ1 BZFQ0 Buzzer frequency (Hz) 0 0 1 1 0 0 1 1 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 The buzzer frequency can be selected from among the above 8 types that have divided the OSC1 clock. At initial reset, the BZFQ register is set to "0" (4096.0 Hz). EPSON 153 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) DUTY0-DUTY2: Duty ratio selection register (00FF55H*D4-D6) Selects the duty ratio of the BZ signal. Table 5.15.6.3 Duty ratio settings Level Level 1 (Max) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (Min) DUTY2 DUTY1 DUTY0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Duty ratio by buzzer frequencies (Hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3 8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16 8/20 7/20 6/20 5/20 4/20 3/20 2/20 1/20 12/24 11/24 10/24 9/24 8/24 7/24 6/24 5/24 12/28 11/28 10/28 9/28 8/28 7/28 6/28 5/28 The buzzer sound level can be adjusted by selecting the duty ratio from among the above 8 types. However, when the envelope has been set to ON (ENON = "1"), this setting becomes invalid. At initial reset, the DUTY register is set to "0" (level 1). ENRTM: Envelope attenuation time selection register (00FF54H*D3) Selects the envelope attenuation time that is added to the BZ signal. ENRST: Envelope reset (00FF54H*D2) Resets the envelope. When "1" is written: Reset When "0" is written: No operation Reading: Always "0" The envelope is reset by writing "1" to ENRST and the duty ratio returns to level 1 (maximum). Writing "0" to ENRST and writing "1" when an envelope has not been added become invalid. Since ENRST is exclusively for writing, it always becomes "0" during reading. ENON: Envelope ON/OFF control register (00FF54H*D1) Controls the addition of an envelope to the BZ signal. When "1" is written: ON When "0" is written: OFF Reading: Valid By writing "1" to ENON, an envelope can be added to BZ signal output. When "0" is written, an envelope is not added and the BZ signal is fixed at the duty ratio selected in DUTY0-DUTY2. At initial reset and when "1" is written to BZSHT, the ENON register is set to "0" (OFF). When "1" is written: 1.0 sec (125 msec x 7 = 875 msec) When "0" is written: 0.5 sec (62.5 msec x 7 = 437.5 msec) Reading: Valid The attenuation time of the digital envelope is determined by the time for changing the duty ratio. The duty ratio is changed in 125 msec (8 Hz) units when "1" is written to ENRTM and in 62.5 msec (16 Hz) units, when "0" is written. This setting becomes invalid when an envelope has been set to OFF (ENON = "0"). At initial reset, the ENRTM register is set to "0" (0.5 sec). SHTPW: One-shot buzzer output duration width selection register (00FF54H*D4) Selects the output duration width of the one-shot buzzer. When "1" is written: 125 msec When "0" is written: 31.25 msec Reading: Valid The one-shot buzzer output duration width is set to 125 msec when "1" is written to SHTPW and 31.25 msec, when "0" is written. At initial reset, the SHTPW register is set to "0" (31.25 msec). 154 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 5.15.7 Programming notes BZSHT: One-shot buzzer trigger/status (00FF54H*D5) Controls the one-shot buzzer output. (1) Since the BZ signal is generated asynchronously from the register BZON, when the signal is turned ON or OFF by the register setting, a hazard of a 1/2 cycle or less is generated. When "1" is written: Trigger When "0" is written: No operation When "1" is read: Busy When "0" is read: Ready Writing "1" into BZSHT causes the one-shot output circuit to operate and the BZ signal to be output. The buzzer output is automatically turned OFF after the time set by SHTPW has elapsed. At this time, the high-impedance control register of the output port R42 must be set to "0" and the data register must be "1". The one-shot output is only valid when the normal buzzer output is OFF (BZON = "0") status. The trigger is invalid during ON (BZON = "1") status. When a re-trigger is assigned during a one-shot output, the one-shot output time set with SHTPW is measured again from that point. (time extension) The operation status of the one-shot output circuit can be confirmed by reading BZSHT, when the one-shot output is ON (busy), BZSHT is read as "1" and when the output is OFF (ready), it is read as "0". At initial reset, BZSHT is set to "0" (ready). (2) The SLP instruction has executed when the BZ signal is in the enable status (BZON = "1" or BZSHT = "1"), an unstable clock is output from the R42 output port terminal at the time of return from the SLEEP status. Consequently, when shifting to the SLEEP status, you should set the BZ signal to the disable status (BZON = BZSHT = "0") prior to executing the SLP instruction. (3) The one-shot output is only valid when the normal buzzer output is OFF (BZON = "0") status. The trigger is invalid during ON (BZON = "1") status. BZSTP: One-shot buzzer forcibly stop (00FF54H*D6) Forcibly stops the one-shot buzzer output. When "1" is written: Forcibly stop When "0" is written: No operation Reading: Constantly "0" By writing "1" into BZSTP, the one-shot buzzer output can be stopped prior to the elapsing of the time set with SHTPW. Writing "0" is invalid and writing "1" except during one-shot output is also invalid. When "1" is written to BZSHT and BZSTP simultaneously, BZSTP takes precedence and one-shot output becomes stop status. Since BZSTP is for writing only, during readout it is constantly set to "0". S1C88409 TECHNICAL MANUAL EPSON 155 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) 5.16 SVD (Supply Voltage Detection) Circuit The criteria voltage can be set for the 3 types shown in Table 5.16.2.1 by the SVD register. Table 5.16.2.1 Criteria voltage setting 5.16.1 Configuration of SVD circuit The S1C88409 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the source voltage lowers. Turning the SVD circuit ON/OFF and the SVD criteria voltage setting can be done with software. Figure 5.16.1.1 shows the configuration of the SVD circuit. VDD Detector output SVDDT SVDON VSS Criteria voltage setting circuit Data bus SVD circuit SVDS1 SVDS0 SVD1 1 SVD0 x Criteria voltage 3.4 V 0 0 1 0 2.8 V 1.9 V When the SVDON register is set to "1", source voltage detection by the SVD circuit is executed. As soon as the SVDON register is reset to "0", the result is loaded to the SVDDT latch and the SVD circuit goes OFF. To obtain a stable detection result, the SVD circuit must be ON for at least l00 sec. So, to obtain the SVD detection result, follow the programming sequence below. 1. 2. 3. 4. Set SVDON to "1" Maintain for 100 sec minimum Set SVDON to "0" Read SVDDT The SVD operation increases current consumption, so turn the SVD circuit off when voltage detection is unnecessary or executing the SLP instruction. Fig. 5.16.1.1 Configuration of SVD circuit 5.16.2 SVD operation The SVD circuit compares the criteria voltage set by software and the supply voltage (VDD-VSS) and sets its results into the SVDDT latch. By reading the data of this SVDDT latch, it can be determined by means of software whether the supply voltage is normal or has dropped. 156 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) 5.16.3 I/O memory of SVD circuit Table 5.16.3.1 shows the control bits for the SVD circuit. Table 5.16.3.1 SVD circuit control bits Address Bit 00FF56 D7 D6 D5 D4 D3 D2 D1 D0 Name - - - - SVD1 Function - - - - SVD criteria voltage setting SVD1 SVD0 Voltage (V) 1 x 3.4 V SVD0 0 1 2.8 V 0 0 1.9 V SVDDT SVD data SCDON SVD On/Off control 1 - - - - 0 - - - - Init R/W Comment - - "0" when being read - - - - - - 0 R/W 0 R/W Low On Normal Off 0 R 0 R/W 5.16.4 Programming notes SVD0, SVD1: SVD criteria voltage setting register (FF56H*D2, D3) Criteria voltage for SVD is set as shown in Table 5.16.3.1. At initial reset, this SVD register is set to "0" (1.9 V). (1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 sec. So, to obtain the SVD detection result, follow the programming sequence below. 1. 2. 3. 4. SVDON: SVD control (ON/OFF) register (FF56H*D0) Turns the SVD circuit ON and OFF. When "1" is written: SVD circuit ON When "0" is written: SVD circuit OFF Reading: Valid When the SVDON register is set to "1", a source voltage detection is executed by the SVD circuit. As soon as SVDON is reset to "0", the result is loaded to the SVDDT latch. To obtain a stable detection result, the SVD circuit must be ON for at least l00 sec. At initial reset, this SVD register is set to "0" (Off). Set SVDON to "1" Maintain for 100 sec minimum Set SVDON to "0" Read SVDDT (2) The SVD operation increases current consumption, so turn the SVD circuit off when voltage detection is unnecessary or executing the SLP instruction. SVDDT: SVD data (FF56H*D1) This is the result of supply voltage detection. When "0" is read: Supply voltage (VDD-VSS) Criteria voltage When "1" is read: Supply voltage (VDD-VSS) < Criteria voltage Writing: Invalid The result of supply voltage detection at time of SVDON is set to "0" can be read from this latch. At initial reset, SVDDT is set to "0" (Normal). S1C88409 TECHNICAL MANUAL EPSON 157 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) 5.17 Touch Panel Controller Table 5.17.2.1 Touch panel control signal output terminals Output signal BYH BYL BXH BXL 5.17.1 Configuration of touch panel controller The S1C88409 has a built-in touch panel controller. It can reduce external devices and load software for designing systems. This touch panel controller also features a capacity to resist noise. The touch panel controller detects the coordinates on a touch panel using two channels of the 10-bit A/D converter. Figure 5.17.1.1 shows the block diagram of the touch panel controller. 5.17.2 Terminal configuration The following signals are used to control a touch panel. BXH, BXL These signals control the supply voltage to the electrodes for detecting X coordinates. BXH is the positive electrode control signal and BXL is the negative electrode control signal. BYH, BYL These signals control the supply voltage to the electrodes for detecting Y coordinates. BYH is the positive electrode control signal and BYL is the negative electrode control signal. The output terminals for the signals are shared with the I/O port terminals and they can be set for controlling a touch panel by selecting the mask option. I/O port P20 P21 P22 P23 The following two options are available: 1) Touch panel is used (The P20 to P23 terminals are set as the touch panel control signal output terminals.) 2) Touch panel is not used (The P20 to P23 terminals are set as the I/O port terminals.) Note: When the touch panel function is selected by mask option, the P20-P23 terminals are configured as follows at initial reset: P20 (BYH) High level P21 (BYL) Low level P22 (BXH) High level P23 (BXL) Low level The P20-P23 terminals are disconnected from the I/O control and data registers, and are controlled from the touch panel controller. Thus it is unnecessary to configure these terminals by software. The I/O control and data registers for these ports can be used as general-purpose registers. Two channels of the A/D converter that is built into the S1C88409 are used to input coordinates from a touch panel. Two analog signal input terminals can be selected from among the I/O port terminals P30-P35 by mask option. Bus I/F Internal data bus Ch0 input Ch1 input Primary average circuit Secondary average circuit Noise judgment circuit Drawing speed judgment circuit Pen-up decision circuit Average control circuit A/D converter AVDD AVREF AGND AVSS BXH BXL BYH BYL A/D converter control circuit Panel control circuit Interrupt control circuit Interrupt request Fig. 5.17.1.1 Block diagram of touch panel controller 158 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) Connecting a touch panel A touch panel consists of two panels for X coordinate detection and Y coordinate detection that are equipped with two electrodes each. The BXH, BXL, BYH and BYL signals should be connected as shown in Figure 5.17.2.1 to control the electrodes individually. Further the negative electrodes should be connected to the analog input terminals selected by mask option to input the detection results. The capacitors to connect to Ch0 and Ch1 should be 1000 pF or less. BXH BXL X panel Y panel BYH BYL Ch0 Ch1 These capasitor should be 1000 pF or less. Fig. 5.17.2.1 Connecting touch panel 5.17.3 Operation of touch panel controller Control of A/D converter Since the touch panel controller controls A/D conversion for coordinate values, it is unnecessary to control with software. However, the clock to be supplied to the A/D converter must be controlled by software. Furthermore, since the A/D converter interrupt can occur even when used for the touch panel, mask the interrupt by software. Refer to Section 5.18, "A/D Converter", for details of the A/D converter. The pen-down check mode controls the signals as follows: BXH=HIGH (The positive electrode on the X panel goes off.) BXL=LOW (The negative electrode on the X panel goes on.) BYH=Pen-down check pulse (The positive electrode on the Y panel goes off.) BYL=HIGH (The negative electrode on the Y panel goes off.) In the pen-down check mode, the pen-down detection input is pulled up in the touch panel controller and it goes high in pen-up status. In pen-down status, the output becomes low level due to the pressurization on the X panel. The pen-down check starts by writing "1" to the PDC register and stops by writing "0". When the touch panel controller judges pen-down status due to a low level input, a pen-down interrupt occurs. The pen-down check by the PDC register uses the OSC1 clock and does not need the OSC3 clock. This makes it possible to reduce current consumption by controlling OSC3 and coordinate detection using the pen-down interrupt. Therefore, it is necessary to enable the pen-down interrupt before starting pen-down check. The pen-down check is invalid during coordinate detection (RST register = "1"). The pen-down detector has a built-in noise rejecter at the input line in order to prevent unnecessary pen-down detection due to noise. This circuit can detect a pen-down when a low-level pulse longer than one cycle of the OSC1 clock is input. Pen-down check Coordinate detection increases current consumption because it always operates in high speed. Therefore, coordinate detection should be stopped to suppress current consumption when the touch panel operation is not necessary. To detect a start of touch panel operation (pen down), the pendown check mode is provided. S1C88409 TECHNICAL MANUAL EPSON 159 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) Starting coordinate detection The touch panel controller starts coordinate detection by writing "1" to the RST register. When "1" is written to the RST register, the controller first performs a pen-down check and is on standby to touch panel driving and A/D conversion for coordinate detection similar to the pendown check by writing "1" to the PDC register. When a pen-down is detected, the controller starts coordinate detection. At the same time, a pendown interrupt occurs if the interrupt is enabled. However, the coordinate detection uses the clock generated by the prescaler with the OSC3 clock as the source clock. Therefore, it is necessary to turn the OSC3 oscillation circuit on and to control the prescaler so that the clock for the touch panel controller is output before writing "1" to the RST register. Refer to Section 5.4 "Oscillation Circuit" and Section 5.5 "Prescaler and Clock Control Circuit for Peripheral Circuits" for controlling the clock. The touch panel controller controls the signals as follows and detects an X coordinate and a Y coordinate separately. X coordinate detection BXH: LOW (Positive electrode on X panel: ON) BXL: HIGH (Negative electrode on X panel: ON) BYH: HIGH (Positive electrode on Y panel: OFF) BYL: LOW (Negative electrode on Y panel: OFF) A/D channel: Ch0 The touch panel controller performs A/D conversion at least 32 times (16 times each for X and Y coordinates) per one coordinate and stores the arithmetic mean to the coordinate data register as the detection result. Since the touch panel controller controls A/D conversion during coordinate detection, do not control the A/D converter with software. While the RST register is set to "1", coordinate detection is repeatedly performed as long as the pen is touching the panel. It can be stopped by writing "0" to the RST register. In this case, turn off the clock output from the prescaler to the touch panel controller and A/D converter. Deciding pen-up status during coordinate detection In pen-down status (the pen is touching the panel), the A/D conversion result indicates the coordinates on the touch panel. If the result is smaller than the value at the corner of the panel, it can be regarded as pen-up status (the pen is not touching the panel). In this touch panel controller, a threshold value for pen-up decision can be set according to the panel to be used. When the mean value of the A/D conversion result is smaller than the set value, the touch panel controller decides it as pen-up status. The threshold value for pen-up decision can be set using the PUD register. Table 5.17.3.1 Threshold value for pen-up decision Y coordinate detection BXH: HIGH (Positive electrode on X panel: OFF) BXL: LOW (Negative electrode on X panel: OFF) BYH: LOW (Positive electrode on Y panel: ON) BYL: HIGH (Negative electrode on Y panel: ON) A/D channel: Ch1 Selected by mask option. X panel A/D conversion Y panel A/D conversion Equivalent circuit Fig. 5.17.3.1 Coordinate detection (X coordinate) The touch panel is regarded as the equivalent circuit shown in Figure 5.17.3.1. It outputs the voltage to the A/D converter according to the pointed coordinate. 160 PUD3 PUD2 PUD1 PUD0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pen-up decision threshold value 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 The result of pen-up/down decision can be read from the PEN bit (00FFA7H*D0). The PEN bit goes "0" in pen-up status and goes "1" in pen-down status. During coordinate detection, a pen-up is judged based on the determined data that is not regarded as noise. If the input data is regarded as noise at pen-up, it is not judged as pen-up and the PEN bit maintains "1" (pen-down status). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) Deciding drawing speed and getting coordinates The touch panel controller performs A/D conversion for getting a coordinate at least 16 times (256 times maximum) each for X and Y, and takes the arithmetic mean. The mean result is written to the coordinate data register as the coordinate value. X coordinate data register: DX11-DX0 (00FFA8H*D7-D0, 00FFA9H*D3-D0) Y coordinate data register: DY11-DY0 (00FFAAH*D7-D0, 00FFABH*D3-D0) The touch panel controller can generate an interrupt when the detected coordinate values are written to both the X and Y coordinate data registers. Thus coordinate values can be read and processed using the interrupt. (2) Normal mode The normal mode is set by writing "0" to the CONST register. It is also set at initial reset. In the normal mode, the hardware changes the number of A/D conversions according to the drawing speed. A low-speed drawing increases the number of A/D conversions, it raises coordinate detection precision. A high-speed drawing decreases the number of A/D conversion, it makes it easy to track the pen. The drawing speed is detected by the addersubtracter shown in Figure 5.17.3.2 as the approximation expression. |(previous X coordinate) - (current X coordinate)| + |(previous Y coordinate) - (current Y coordinate)| Previous coordinate The number of A/D conversions for getting a coordinate differs depending on the mode described below. Current coordinate (1) Constant-speed mode The constant-speed mode is set by writing "1" to the CONST (00FFA0H*D4) register. This mode always performs the same number of A/D conversions regardless of drawing speed and takes the mean for detecting one coordinate. Consequently, the coordinate detection speed is always constant. The number of A/D conversions for averaging can be selected from the five types shown in Table 5.17.3.2 using the AVN register. Table 5.17.3.2 Number of A/D conversion in constantspeed mode AVN2 AVN1 AVN0 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Number of A/D conversion 16x16 16x8 16x4 16x2 16x1 The set number of A/D conversions are performed for both the X and Y coordinates. S1C88409 TECHNICAL MANUAL Addersubtracter MVH MVMH MVML MVL Comparator Comparator Comparator Comparator MV3 MV2 MV1 MV0 Fig. 5.17.3.2 Drawing speed judgment circuit The drawing speed judgment circuit compares the output from the adder-subtracter with the following four threshold values to decide the number of A/D conversions for the next coordinate detection. MVH (00FFA5H*D7-D4): Threshold value for high-speed judgment MVMH (00FFA5H*D3-D0): Threshold value for middle-high-speed judgment MVML (00FFA4H*D7-D4): Threshold value for middle-low-speed judgment MVL (00FFA4H*D3-D0): Threshold value for low-speed judgment EPSON 161 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) Table 5.17.3.4 Threshold value for noise judgment Table 5.17.3.3 Threshold value setting for drawing speed judgment MVH3 MVMH3 MVML3 MVL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MVH2 MVMH2 MVML2 MVL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MVH1 MVMH1 MVML1 MVL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MVH0 MVMH0 MVML0 MVL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 High-speed Middle-high-speed Middle-low-speed Low-speed 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 The settings must meet the following conditions: MVH MVMH MVML MVL Figure 5.17.3.3 shows the relation between the comparison results and the number of A/D conversions for the next detection. Next number of A/D conversion (times) Drawing speed 256 128 64 32 Big Threshold value MVL setting value MVML setting value MVMH setting value MVH setting value Fig. 5.17.3.3 Drawing speed and number of A/D conversions The set number of A/D conversions are performed for both the X and Y coordinates. CND1 CND0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Noise judgment threshold value 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 At initial reset, threshold value for noise judgment is set to 36 (CND=1000B). Increase the threshold value if pen speed is important, or decrease if noise rejection is important. (1) Waiting time for voltage stabilization It is possible to set a waiting time for voltage stabilization between supplying a voltage to the electrode of the panel to be detected a coordinate and starting an A/D conversion. The waiting time can be selected from 16 types as shown in Table 5.17.3.5 using the WAIT register. Table 5.17.3.5 Waiting time setting for voltage stabilization WAIT3 WAIT2 WAIT1 WAIT0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Noise judgment In order to avoid unnecessary coordinate detection due to noise, the threshold value for noise judgment can be set. This controller performs at least 16 A/D conversions for getting coordinate data for each X and Y. At this time, the controller also finds the difference between the maximum conversion data and minimum conversion data. When the difference is larger than the threshold value set for noise judgment, it is regarded as noise and the result is not written to the coordinate data register. When the difference is smaller than the threshold value, the arithmetic mean of the A/D conversion data is written to the register as coordinate data. The threshold value for noise judgment can be set using the CND register. 162 CND2 Waiting time setting for stable detection result 16 0 CND3 Voltage stabilization waiting time 16x1/f 16x2/f 16x3/f 16x4/f 16x5/f 16x6/f 16x7/f 16x8/f 16x9/f 16x10/f 16x11/f 16x12/f 16x13/f 16x14/f 16x15/f 16x16/f f: Frequency of the clock input from the prescaler EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) Note: The waiting time to be set using the WAIT register must be longer than 3 cycles of the OSC1 clock. 16 x n/f > 3/fOSC1 (f: Input clock frequency from the prescaler) At initial reset, it is set to 16 x 5/f (WAIT="0100B"). (2) Interval time It is possible to set an interval after an A/D conversion processing for noise resistance improvement, saving power and setting the number of points to be detected for 1 second. The interval can be selected from 16 types as shown in Table 5.17.3.6 using the INV register. The A/D conversion processing for coordinate detection performs four A/D conversions at a time. The set interval is inserted after the processing (four A/D conversions have finished) and no voltage is supplied to the touch panel during this period. At initial reset, the interval is set to 128 x 3/f (INV="0010B"). When setting the interval shorter, current consumption will increase and coordinate values unnecessary for drawing will be detected. Set an appropriate interval according to the drawing contents. Operation of coordinate detection When "1" is written to the RST register, the touch panel controller starts operating for coordinate detection and continues a process as shown in Figure 5.17.3.4 until "0" is written to the RST register. The number of conversions per second while the pen is tracing on the panel is calculated as an approximate value by the expression below: N = 1 / (AV x 8 (CNT + WAIT + 4 AD + IVL)) AV: Number of A/D conversions CNT: 10 x input clock cycle time (prescaler output clock) WAIT: WAIT register setting time AD: 22 x A/D conversion clock cycle [00FF17H*D3-D0] IVL: IVL register setting time Table 5.17.3.6 Interval time setting IVL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IVL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IVL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IVL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interval time 128x1/f 128x2/f 128x3/f 128x4/f 128x5/f 128x6/f 128x7/f 128x8/f 128x9/f 128x10/f 128x11/f 128x12/f 128x13/f 128x14/f 128x15/f 128x16/f Figure 5.17.3.4 shows the operation when the number of conversions is set to 16 x 1. When a pen-up is detected in the coordinate conversion period, the following cycle starts from (1) after finishing the current cycle. When no pen-up is detected, the following cycle starts from (2). If the detected data is regarded as noise, the data register is not updated. f: Input clock frequency from the prescaler RST = "1" Pen-down interrupt Data update interrupt (1) Pen-down (2) Coordinate Coordinate Coordinate Coordinate Coordinate Coordinate Coordinate Coordinate check detection 1 detection 2 detection 3 detection 4 detection 5 detection 6 detection 7 detection 8 Pen-down detection Charge/discharge Voltage stabilization A/D A/D A/D A/D time waiting time conversion 1 conversion 2 conversion 3 conversion 4 Interval time Fig. 5.17.3.4 Coordinate detection operation S1C88409 TECHNICAL MANUAL EPSON 163 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) 5.17.4 Interrupt function The interrupts can be disabled using the interrupt enable registers ETPPD and ETPDR corresponding to each interrupt factor flag. In addition, a priority level of the touch panel controller interrupt for the CPU can be optionally set at levels 0 to 3 by the interrupt priority register PTP. The touch panel controller can generate an interrupt when a pen-down is detected during pendown check and converted coordinate data is updated. Figure 5.17.4.1 shows the configuration of the touch panel controller interrupt circuit. When a pen-down status is detected during pendown check using the PDC register or RST register, the interrupt factor flag FTPPD is set to "1" and an interrupt is generated. When the coordinate data register is updated after finishing A/D conversions for a coordinate detection, the interrupt factor flag FTPDR is set to "1" and an interrupt is generated. Address Pen-down Data bus Address Address Converted data update For details on the above mentioned interrupt control registers and the operation following an interrupt generation, see Section 5.20, "Interrupt and Standby Status". The exception processing vector address of each interrupt factor is set as below. Pen-down interrupt: 000020H Converted data update interrupt: 000022H Interrupt priority register PTP0, PTP1 Interrupt factor flag FTPPD Interrupt enable register ETPPD Address Interrupt factor flag FTPDR Address Interrupt enable register ETPDR Interrupt priority level judgment circuit Interrupt request Fig. 5.17.4.1 Configuration of touch panel controller interrupt circuit 164 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) 5.17.5 Touch panel controller control flow Initial setting Figure 5.17.5.1 shows the control flow for the touch panel controller Set the following registers. Initial setting Turn the pen-down check on (PDC = 1). Enable the pen-down interrupt. NO Pen-down interrupt YES Disable the pen-down interrupt. Turn the pen-down check off (PDC = 0). Start clock input to the A/D converter, and touch panel controller. Start coordinate detection by the touch panel controller (RST = 1). Enable the data update interrupt. NO Data update interrupt YES Read the coordinate data, and perform drawing process etc. NO End YES Disable the data update interrupt. Turn the touch panel controller off (RST = 0). Turn clock input to the A/D converter, and touch panel controller off. Fig. 5.17.5.1 Touch panel controller control flow S1C88409 TECHNICAL MANUAL Setting other circuits OSCC: Write "1" to turn the OSC3 oscillation circuit on. PSAD: Select an A/D converter operating clock. PSTP: Select a touch panel controller operating clock. VRC: Write "1" to enable the AVREF control by the touch panel controller. IOC30-IOC37, P30D-P37D: Configure the terminal for switching the AVREF voltage of the A/D converter on and off. Any I/O port frpm P30 to P37 which is not used for inputting analog signals can be used for this control. Set the I/O port in the output mode and write "1" to the data register. Setting touch panel controller CONST: Select either constant speed mode or normal mode. AVN: Set a number of A/D conversions for an arithmetic mean when the controller is used in the constant speed mode. WAIT: Set a waiting time for voltage stabilization. CND: Set a threshold value for noise judgment. PUD: Set a threshold value for pen-up decision. MVH, MVMH, MVML, MVL: Set threshold values for drawing speed judgment when the controller is used in the normal mode. IVL: Set an interval time. Setting for interrupt PTP: Set a priority level of the touch panel controller interrupt. FTPPD, FTPDR: Write "1" to reset the touch panel controller interrupt factor flags. ETPPD, ETPDR: Write "1" to enable the touch panel controller interrupt. To avoid unnecessary interrupts during coordinate detection, disable the A/D converter interrupt. EPSON 165 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) Pen-down check Reading coordinate values Write "1" to the PDC register to start pen-down check. When checking a pen-down after turning OSC3 off, the internal power supply circuit, OSCC and stabilization waiting time must be controlled after a pen-down is detected. To increase the response time until the coordinate detection starts, the pendown should be checked when OSC3 is on or using the RST register not the PDC register. However, this method increases current consumption. An interrupt occurs when coordinate values for a point are written to the coordinate data registers (DX, DY). Read coordinate data using the interrupt and then execute the necessary processing. Starting coordinate detection Coordinate detection should be started using a pen-down interrupt. Write "1" to the PRAD and PRTP registers so that the prescaler supplies the clocks to the A/D converter and the touch panel controller. Then write "1" to the RST register to start coordinate detection. 166 Coordinate data varies according to the panel to be used and operating environment. Therefore, first get data of the panel origin point and used area to make a correction value for converting the register data into an actual coordinate. Drawing processing should be done by correcting coordinate data using the correction value. Be sure to read all the coordinate data registers (00FFA8, 00FFA9, 00FFAA, 00FFAB) after a data update interrupt is generated. This process is required if the coordinate data at that point is unnecessary because the next data update interrupt cannot be generated if all the register data are not read. EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) 5.17.6 I/O memory of touch panel controller Table 5.17.6.1 shows the control bits of the touch panel controller. Table 5.17.6.1(a) Touch panel controller control bits Address Bit 00FF13 D7 D6 D5 D4 D3 D2 D1 D0 00FF16 D7 D6 D5 D4 D3 D2 D1 D0 00FF22 D7 D6 D5 D4 D3 D2 D1 D0 00FF26 D7 D6 D5 D4 D3 D2 D1 D0 00FF2A D7 D6 D5 D4 D3 D2 D1 D0 Name - - - - PRAD PSAD2 Function - - - - A/D converter clock control A/D converter division ratio PSAD2 PSAD1 PSAD0 Division ratio 1 x x fOSC3 / 16 PSAD1 0 1 1 fOSC3 / 8 fOSC3 / 4 0 1 0 PSAD0 fOSC3 / 2 0 0 1 fOSC3 / 1 0 0 0 - - - - - - - - PRTP Touch panel controller clock control PSTP2 Touch panel controller clock ratio PSTP2 PSTP1 PSTP0 Division ratio 1 x x fOSC3 / 16 PSTP1 1 1 0 fOSC3 / 8 1 0 fOSC3 / 4 0 PSTP0 fOSC3 / 2 0 1 0 fOSC3 / 1 0 0 0 PAD1 A/D converter PAD0 interrupt priority register PTP1 Touch panel controller PTP0 interrupt priority register - - - - - - - - EAD A/D converter conversion completion interrupt enable register ETPPD Touch panel controller pen-down interrupt enable register ETPDR Touch panel controller converted data update interrupt enable register - - - - - - - - - - FAD A/D converter conversion completion interrupt factor flag FTPPD Touch panel controller pen-down interrupt factor flag FTPDR Touch panel controller converted data update interrupt factor flag - - - - - - - - - - S1C88409 TECHNICAL MANUAL EPSON 1 - - - - On 0 - - - - Off Init R/W Comment - - "0" when being read - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W - - - - On - - - - Off - - "0" when being read - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W PAD1 PTP1 1 1 0 0 PAD0 PTP0 1 0 1 0 Priority level Level 3 Level 2 Level 1 Level 0 0 0 0 0 - - - - 0 R/W R/W R/W R/W - "0" when being read - - - R/W 0 R/W Interrupt is enabled Interrupt is disabled (R) Interrupt factor has generated (R) Interrupt factor has not generated (W) Reset (W) Invalid 0 R/W - - "0" when being read - - - - - - - - 0 R/W 0 R/W 0 R/W - - - - - - - - - - "0" when being read 167 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) Table 5.17.6.1(b) Touch panel controller control bits Address Bit 00FF80 D7 D6 D5 D4 D3 D2 D1 D0 00FFA0 D7 D6 D5 D4 D3 D2 D1 D0 00FFA1 D7 D6 D5 D4 D3 Name ADRUN - - VRC VRO CHS2 Function A/D conversion start control register - - AVREF control (Touch pamel controller) AVREF swich Analog input channel selection CHS2 CHS1 CHS0 Input channel 1 1 1 AD7 1 1 0 AD6 CHS1 1 0 1 AD5 1 0 0 AD4 0 1 1 AD3 CHS0 0 1 0 AD2 0 0 1 AD1 0 0 0 AD0 - - PDC Pen-down check control RST TPC circuit reset control CONST Mode setting - - AVN2 Mean count setting Mean count AVN2 AVN1 AVN0 0 0 16 x 16 0 AVN1 0 1 16 x 8 0 1 0 16 x 4 0 AVN0 1 1 16 x 2 0 x x 16 x 1 1 - - - - - - - - WAIT3 Voltage stabilization waiting time setting D2 WAIT2 D1 WAIT1 D0 WAIT0 00FFA2 D7 D6 D5 D4 D3 - - - - CND3 168 D2 CND2 D1 CND1 D0 CND0 WAIT3 WAIT2 WAIT1 WAIT0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 CND2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CND1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CND0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - Check Cancel Constant-speed - - - - - 0 Invalid - - Invalid Off - Cancel Reset Normal - - - - - Waiting time 16 x 1/f 16 x 2/f 16 x 3/f 16 x 4/f 16 x 5/f 16 x 6/f 16 x 7/f 16 x 8/f 16 x 9/f 16 x 10/f 16 x 11/f 16 x 12/f 16 x 13/f 16 x 14/f 16 x 15/f 16 x 16/f - - - - Noise judgment threshold value setting CND3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Start - - Enable On - - - - Value 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 EPSON - - - - Init 0 - - 0 0 0 R/W Comment W "0" when being read - - R/W R/W R/W 0 R/W 0 R/W - 0 0 0 - 0 - R/W R/W R/W - R/W 0 R/W 0 R/W - - - - 0 - "0" when being read - - - R/W 1 R/W 0 R/W 0 R/W - - - - 1 - "0" when being read - - - R/W 0 R/W 0 R/W 0 R/W "0" when being read Valid when "RST=0" "0" when being read Invalid when Normal mode S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) Table 5.17.6.1(c) Touch panel controller control bits Address Bit 00FFA3 D7 D6 D5 D4 D3 Name - - - - PUD3 D2 PUD2 D1 PUD1 D0 PUD0 00FFA4 D7 Function - - - - Pen-up decision threshold value setting PUD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PUD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PUD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PUD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 - - - - Value 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 MVML3 Middle-low-speed judgment threshold value setting D6 MVML2 D5 MVML1 D4 MVML0 D3 MVL3 D2 MVL2 D1 MVL1 D0 MVL0 MVML3 MVML2 MVML1 MVML0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Value 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Low-speed judgment threshold value setting MVL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S1C88409 TECHNICAL MANUAL MVL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MVL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MVL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Value 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 EPSON 0 - - - - Init R/W Comment - - "0" when being read - - - - - - 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 1 R/W MVMLMVL 0 R/W 0 R/W 0 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 0 R/W MVMLMVL 1 R/W 0 R/W 169 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) Table 5.17.6.1(d) Touch panel controller control bits Address Bit 00FFA5 D7 D6 MVH2 D5 MVH1 D4 MVH0 D3 D2 D1 D0 00FFA6 D7 D6 D5 D4 D3 170 Name MVH3 Function High-speed judgment threshold value setting MVH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MVH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MVH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MVH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 Value 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 R/W 0 R/W MVMH3 Middle-high-speed judgment threshold value setting 0 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 1 R/W MVMLMVL MVMH3 MVMH2 MVMH1 MVMH0 Value 0 0 0 2 0 0 0 1 4 0 0 1 0 6 0 MVMH2 0 1 1 8 0 1 0 0 10 0 1 0 1 12 0 1 1 0 14 0 1 1 1 16 0 MVMH1 0 0 0 18 1 0 0 1 20 1 0 1 0 22 1 0 1 1 24 1 1 0 0 26 1 MVMH0 1 0 1 28 1 1 1 0 30 1 1 1 1 32 1 - - - - IVL3 D2 IVL2 D1 IVL1 D0 IVL0 - - - - IVL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IVL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IVL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 R/W 0 R/W - - - - Interval time setting IVL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interval time 128 x 1 x2 x3 x4 x5 x6 x7 x8 x9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 EPSON Init R/W Comment 1 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 0 R/W MVMLMVL - - - - - - "0" when being read - - - - - - 0 R/W 0 R/W 1 R/W 0 R/W S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) Table 5.17.6.1(e) Touch panel controller control bits Address Bit 00FFA7 D7 D6 D5 D4 D3 D2 D1 D0 00FFA8 D7 D6 D5 D4 D3 D2 D1 D0 00FFA9 D7 D6 D5 D4 D3 D2 D1 D0 00FFAA D7 D6 D5 D4 D3 D2 D1 D0 00FFAB D7 D6 D5 D4 D3 D2 D1 D0 Name - - - - - - - PEN DX11 DX10 DX9 DX8 DX7 DX6 DX5 DX4 - - - - DX3 DX2 DX1 DX0 DY11 DY10 DY9 DY8 DY7 DY6 DY5 DY4 - - - - DY3 DY2 DY1 DY0 Function - - - - - - - Pen-up/pen-down status X coordinate data 1 - - - - - - - Pen-down D11(MSB) D10 D9 D8 D7 D6 D5 D4 - - - - D3 D2 D1 D0(LSB) D11(MSB) D10 D9 D8 D7 D6 D5 D4 X coordinate data Y coordinate data - - - - Y coordinate data PSAD0-PSAD2: A/D converter clock division ratio selection register (00FF13H*D0-D2) Selects the clock for the A/D converter. It can be selected from 5 types of division ratio as shown in Table 5.17.6.1(a). This register can also be read. At initial reset, the PSAD register is set to "0" (fOSC3/1). PRAD: A/D converter clock control register (00FF13H*D3) Controls the clock supply of the A/D converter. When "1" is written: ON When "0" is written: OFF Reading: Valid S1C88409 TECHNICAL MANUAL D3 D2 D1 D0(LSB) 0 - - - - - - - Pen-up Init R/W Comment - - "0" when being read - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R - - "0" when being read - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R - - "0" when being read - - - - - - 0 R 0 R 0 R 0 R By writing "1" to the PRAD register, the clock that is selected with the PSAD register is output to the A/D converter. When "0" is written, the clock is not output. At initial reset, the PRAD register is set to "0" (OFF). PSTP0-PSTP2: Touch panel controller clock division ratio selection register (00FF16H*D0-D2) Selects the clock for the touch panel controller. It can be selected from 5 types of division ratio as shown in Table 5.17.6.1(a). This register can also be read. At initial reset, the PSTP register is set to "0" (fOSC3/1). EPSON 171 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) RST: TPC circuit reset control register (00FFA0H*D5) Controls coordinate detection. PRTP: Touch panel controller clock control register (00FF16H*D3) Controls the clock supply of the touch panel controller. When "1" is written: Cancel When "0" is written: Reset Reading: Valid When "1" is written: ON When "0" is written: OFF Reading: Valid By writing "1" to the PRTP register, the clock that is selected with the PSTP register is output to the touch panel controller. When "0" is written, the clock is not output. At initial reset, the PRTP register is set to "0" (OFF). VRC: AVREF control register (00FF80H*D4) Enables the AVREF control function. CONST: Mode setting register (00FFA0H*D4) Sets the operating mode of the touch panel controller. When "1" is written: Enabled When "0" is written: Disabled Reading: Valid Writing "1" to the VRC register enables the AVREF control function. An I/O port (P30-P37) which is not used for inputting analog signals can be used to switch the external AVREF input. Set the I/O port in the output mode and write "1" to the data register. When the touch panel controller needs A/D conversion, it turns the I/O port terminal to low. The signal drives the external transistor to supply AVREF to the A/D converter. PDC: Pen-down check control register (00FFA0H*D6) Controls the pen-down check operation. When "1" is written: Check When "0" is written: Cancel Reading: Valid When "1" is written to the PDC register, the pendown check starts. The pen-down check generates an interrupt when a pen-down is detected. Start coordinate detection using the interrupt. It is necessary to enable the pen-down interrupt before starting pen-down check. When "0" is written to the PDC register, the pendown check stops. The pen-down function is effective only when the touch panel controller is in reset status (RST="0"). At initial reset, the PDC register is set to "0" (cancel). 172 When "1" is written to the RST register, the touch panel controller circuit starts coordinate detection. When "0" is written, the circuit stops coordinate detection and goes into reset status. Set the touch panel controller circuit to reset status to reduce current consumption when the touch panel operation is not necessary. At initial reset, the RST register is set to "0" (reset). When "1" is written: Constant-speed mode When "0" is written: Normal mode Reading: Valid When "1" is written to the CONST register, the touch panel controller is set in the constant-speed mode. When "0" is written. It is set in the normal mode. The constant-speed mode does not judge drawing speed and gets coordinate values by constant arithmetic mean set with the AVN register. The coordinate detection speed is always constant in this mode. In the normal mode, the hardware changes the number of A/D conversions for arithmetic mean in five stages according to the drawing speed. At initial reset, the CONST register is set to "0" (normal mode). AVN0-AVN2: Mean count setting register for constant-speed mode (00FFA0H*D0-D2) Sets the arithmetic mean count (number of A/D conversion) for constant-speed mode. Table 5.17.6.2 Mean count for constant-speed mode AVN2 AVN1 AVN0 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Number of A/D conversion 16x16 16x8 16x4 16x2 16x1 The setting in this register is invalid in the normal mode. The set number of A/D conversions are performed for both the X and Y coordinates. At initial reset, the AVN register is set to "0" (256 times). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) WAIT0-WAIT3: Voltage stabilization waiting time setting register (00FFA1H*D0-D3) Sets a waiting time for voltage stabilization between supplying a voltage to the electrode of the panel to be detected a coordinate and starting an A/D conversion. PUD0-PUD3: Pen-up decision threshold value setting register (00FFA3H*D0-D3) Sets the threshold value for pen-up decision. Table 5.17.6.5 Threshold value for pen-up decision Table 5.17.6.3 Waiting time for voltage stabilization WAIT3 WAIT2 WAIT1 WAIT0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Voltage stabilization waiting time 16x1/f 16x2/f 16x3/f 16x4/f 16x5/f 16x6/f 16x7/f 16x8/f 16x9/f 16x10/f 16x11/f 16x12/f 16x13/f 16x14/f 16x15/f 16x16/f At initial reset, the WAIT register is set to "0100B" (16 x 5/f). CND0-CND3: Noise judgment threshold value setting register (00FFA2H*D0-D3) Sets a threshold value for noise judgment. Table 5.17.6.4 Threshold value for noise judgment CND3 CND2 CND1 CND0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Noise judgment threshold value 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 When the difference between the maximum value and minimum value of the A/D conversions for a coordinate detection is bigger than the set threshold value, it is regarded as a noise and the result is not written to the coordinate data register. Increase the threshold value if high drawing speed is important, or decrease if noise rejection is important. At initial reset, the CND register is set to "1000B" (36). S1C88409 TECHNICAL MANUAL PUD3 PUD2 PUD1 PUD0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pen-up decision threshold value 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 By setting a smaller value than the minimum detection result (A/D conversion data) on the touch panel, pen-up status can be detected. At initial reset, the PUD register is set to "1010B" (44). MVL0-MVL3: Low-speed judgment threshold value setting register (00FFA4H*D0-D3) MVML0-MVML3: Middle-low-speed judgment threshold value setting register (00FFA4H*D4-D7) MVMH0-MVMH3: Middle-high-speed judgment threshold value setting register (00FFA5H*D0-D3) MVH0-MVH3: High-speed judgment threshold value setting register (00FFA5H*D4-D7) Sets the threshold value for judging drawing speed in the normal mode. Table 5.17.6.6 Threshold value for speed judgment MVH3 MVMH3 MVML3 MVL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 EPSON MVH2 MVMH2 MVML2 MVL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MVH1 MVMH1 MVML1 MVL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MVH0 MVMH0 MVML0 MVL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 High-speed Middle-high-speed Middle-low-speed Low-speed 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 173 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) The setting must meet following conditions. MVH MVMH MVML MVL In the normal mode, the controller gets the drawing speed from the difference between the previous coordinate values and current coordinate values, and decides the next arithmetic mean count according to the threshold values set in these registers. Table 5.17.6.7 shows the mean count that will be set. Table 5.17.6.7 Arithmetic mean count in normal mode Judgment speed ~MVL MVL MVML MVML MVMH MVMH MVH MVH~ Next number of A/D conversion 256 times 128 times 64 times 32 times 16 times The set number of A/D conversions are performed for both the X and Y coordinates. The settings of these registers are invalid in the constant-speed mode. At initial reset, the registers are set as follows: MVH: 1000B (18) MVMH: 0110B (14) MVML: 0100B (10) MVL: 0010B (6) IVL0-IVL3: Interval time setting register (00FFA6H*D0-D3) Sets the interval time after A/D conversion. Table 5.17.6.8 Interval time IVL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IVL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IVL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IVL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interval time 128x1/f 128x2/f 128x3/f 128x4/f 128x5/f 128x6/f 128x7/f 128x8/f 128x9/f 128x10/f 128x11/f 128x12/f 128x13/f 128x14/f 128x15/f 128x16/f The selected interval is inserted after four A/D conversions are finished. At initial reset, the IVL register is set to "0010B" (128 x 3). 174 PEN: Pen-up/pen-down status (00FFA7H*D0) Indicates pen-up status and pen-down status. When "1" is read: Pen-down When "0" is read: Pen-up Writing: Invalid The pen status during coordinate detection can be found by reading the PEN bit. When the controller detects a value bigger than the threshold value for pen-up judgment set with the PUD register, the PEN bit goes "1" and when a smaller value is detected goes "0". Writing operation is invalid because PEN is a readonly bit. At initial reset, PEN is set to "0" (pen-up). DX0-DX11: X coordinate data register (00FFA9H*D0-D3, 00FFA8) DY0-DY11: Y coordinate data register (00FFABH*D0-D3, 00FFAA) The A/D conversion result is written to this register through arithmetic mean. Data is not written if it is judged as a noise. Be sure to read all the coordinate data registers (00FFA8, 00FFA9, 00FFAA, 00FFAB) after a data update interrupt is generated. This process is required if the coordinate data at that point is unnecessary because the next data update interrupt cannot be generated if all the register data are not read. Writing operation is invalid because they are readonly registers. At initial reset, both the DX and DY registers are set to "0". PTP0, PTP1: Interrupt priority register (00FF22H*D4, D5) Sets the priority level of the touch panel controller interrupt. Table 5.17.6.9 shows the interrupt priority level which can be set by the PTP register. Table 5.17.6.9 Interrupt priority level settings PTP1 PTP0 1 1 0 0 1 0 1 0 Interrupt priority level Level 3 Level 2 Level 1 Level 0 (IRQ3) (IRQ2) (IRQ1) (None) At initial reset, the PTPD register is set to "0" (level 0). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller) 5.17.7 Programming notes ETPPD, ETPDR: Interrupt enable register (00FF26H*D6, D5) Enables or disables the touch panel controller interrupt generation to the CPU. (1) The setting of the threshold value for drawing speed judgment in the normal mode must meet following conditions. MVH MVMH MVML MVL When "1" is written: Interrupt is enabled When "0" is written: Interrupt is disabled Reading: Valid The ETPPD and ETPDR registers are the interrupt enable registers corresponding to the pen-down interrupt and conversion data update interrupt factors, respectively. When the register is set to "1", the interrupt is enabled, and when it is set to "0", the interrupt is disabled. At initial reset, the EPD and EDLP registers are set to "0" (interrupt is disabled). (2) Do not stop the clocks output from the OSC3 oscillation circuit and prescaler during coordinate detection. (3) Do not operate the A/D converter independently while the touch panel controller is used. (4) The waiting time to be set using the WAIT register must be longer than 3 cycles of the OSC1 clock. 16 x n/f > 3/fOSC1 (f: Input clock frequency from the prescaler) FTPPD, FTPDR: Interrupt factor flag (00F2AH*D6, D5) Indicates the generation of touch panel controller interrupt factor. When the A/D converter reference voltage control function is used (VRC = "1"), the time set in the WAIT register also applies to the reference voltage setup time. Therefore, design the peripheral circuit taking the charge time into consideration. If the reference voltage (AVREF) cannot be set up within the time set in the WAIT register, the reference voltage should be switched on and off by software so that the setup time is secured. When "1" is read: Int. factor has generated When "0" is read: Int. factor has not generated When "1" is written: Factor flag is reset When "0" is written: Invalid FTPPD and FTPDR are the interrupt factor flags corresponding to the pen-down interrupt and conversion data update interrupt, respectively. They are set to "1" when the corresponding factor occurs. The pen-down interrupt factor occurs when a pendown status is detected during pen-down check. The conversion data update interrupt factor occurs when the coordinate values (result of arithmetic mean) after A/D conversions are written to the coordinate data registers. At this point, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I0 and I1), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "1" when the interrupt generation conditions are met. To accept the subsequent interrupt after an interrupt generation, it is necessary to reset the interrupt flag (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "0" by writing "1". At initial reset, the FPD and FDLP flags are reset to "0". S1C88409 TECHNICAL MANUAL (5) The capacitors connected to Ch0 and Ch1 of the touch panel controller (see Figure 5.17.2.1) affect the pen-down judgement time. They must be 1000 pF or less. EPSON 175 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) 5.18 A/D Converter 5.18.2 Terminal configuration of A/D converter 5.18.1 Characteristics and configuration of A/D converter The terminals used with the A/D converter are as follows: The S1C88409 has a built-in A/D converter with the following characteristics. AVDD, AGND, AVSS (power supply input terminal) * Conversion formula: Successive-approximation type * Resolution: 10 bits * Input channel: Maximum 8 channels * Conversion time: Minimum 11 sec (in 2 MHz operation) * Setting of analog conversion voltage range is possible with reference voltage terminal (AVREF) * A/D conversion result is possible to read from 10-bit data register * Sample & hold circuit built-in * A/D conversion completion generates an interrupt The AVDD, AGND and AVSS terminals are power supply terminals for the A/D converter. The voltage should be input as AVDD VDD and AGND AVSS = VSS. These power supply terminals are common with the D/A converter. AVREF (reference voltage input terminal) The AVREF terminal is the reference voltage terminal of the analog block. Input voltage range of the A/D conversion is decided by this input (AGND-AVREF). The voltage should be input as AVREF AVDD. This terminal is used as the reference voltage input of the D/A converter. Figure 5.18.1.1 shows the configuration of the A/D converter. AD0-AD7 (analog input terminal) The analog input terminals AD0-AD7 are shared with the I/O port terminals P30-P37. Further, the AD6 (P36) and AD7 (P37) terminals can be used as the analog output terminals DA0 and DA1 of the D/A converter. Therefore, it is necessary to set them for the A/D converter by software when using them as analog input terminals. This setting can be done for each terminal. (Refer to Section 5.18.4 for setting.) At initial reset, all the terminals are set in the I/O port terminal. Analog voltage value AVIN that can be input is in the range of AVSS AGND AVIN AVREF. AD0 (P30) AD1 (P31) AD2 (P32) AD3 (P33) AD4 (P34) AD5 (P35) AD6 (P36) AD7 (P37) 10-bit D/A converter Successive conversion register Converted data (ADDR) Comparator + - Analog multiplexer Control circuit Sample/hold circuit Interrupt circuit Data bus AVDD AVREF AGND AVSS fOSC3/1 to fOSC3/16 OSC3 oscillation circuit fOSC3 Prescaler Fig. 5.18.1.1 Configuration of A/D converter 176 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) 5.18.3 Mask option Table 5.18.4.1 Correspondence between A/D input terminal and PAD register Pull-up resistor I/O port pull-up resistor P30 (AD0) With resistor P31 (AD1) With resistor P32 (AD2) With resistor P33 (AD3) With resistor P34 (AD4) With resistor P35 (AD5) With resistor P36 (AD6) With resistor P37 (AD7) With resistor Terminal A/D input control register PAD0 P30 (AD0) PAD1 P31 (AD1) PAD2 P32 (AD2) PAD3 P33 (AD3) PAD4 P34 (AD4) PAD5 P35 (AD5) PAD6 P36 (AD6) PAD7 P37 (AD7) Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct Gate direct The input terminals of the A/D converter are shared with the I/O port terminals P30-P37. Therefore, the terminal specification of the A/D converter is decided by setting the I/O port mask option. Select "Gate direct" for the port corresponding to the channel to be used to obtain the conversion precision. 5.18.4 Control of A/D converter Setting of A/D input terminal When using the A/D converter, it is necessary to set up the terminals used for analog input from the P30-P37 initialized as the I/O port terminals. Eight terminals can all be used as analog input terminals. However, one of the AD6 (P36) and AD7 (P37) terminals or both cannot be used as the analog input terminal of the A/D converter when the D/A converter is used, because it is used as the analog output terminal. The PAD (PAD0-PAD7) register is used to set analog input terminals. When the PAD register bits are set to "1", the corresponding terminals function as the analog input terminals. When using the P36 terminal as an analog input terminal, write "1" to PAD6 and write "0" to PDA6 (for setting an analog output terminal of the D/A converter) to disable the analog output. When both the PAD6 and PDA6 registers are set to "1", the P36 terminal is set for analog output, and it cannot be used with the A/D converter. It is the same for the P37 terminal. Set PAD7 to "1" and PDA7 to "0". Remarks Set PDA6 to "0" Set PDA7 to "0" The touch panel controller uses two terminals from P30 to P35 for inputting coordinate signals. These two terminals are selected by mask option and fixed as the analog signal input terminals. Thus the above software settings are unnecessary. At initial reset, the terminal except for 2 channels of the touch panel controller are set as I/O ports and goes to high-impedance status. Setting of input clock As explained in Section 5.5, "Prescaler and Clock Control Circuit for Peripheral Circuits", the A/D conversion clock can be selected from 5 types shown in Table 5.18.4.2. The selection is done using the PSAD register. Table 5.18.4.2 Input clock selection Selection register PSAD2 PSAD1 PSAD0 1 x x 0 1 1 0 1 0 0 0 1 0 0 0 Division ratio fOSC3/16 fOSC3/8 fOSC3/4 fOSC3/2 fOSC3/1 Output control PRAD register "1": ON "0": OFF The prescaler outputs the selected clock to the A/D converter by writing "1" to the PRAD register. Note: * The prescaler can output a clock to the A/D converter only when the OSC3 oscillation goes on. (Refer to Section 5.5, "Prescaler and Clock Control Circuit for Peripheral Circuits".) * The frequency of the input clock should be lower than the maximum value shown in Section 8.7, "A/D Converter Characteristics". * The input clock should be set when the A/D converter stops. Changing in the A/D converter operation may cause a malfunction. * To prevent malfunction, do not start A/D conversion (writing to the CHS register) when the A/D conversion clock is not being output from the prescaler, and do not turn the prescaler output clock off during A/D conversion. S1C88409 TECHNICAL MANUAL EPSON 177 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) AVREF control A/D conversion operation VRO The VRO register is used to turn the reference voltage AVREF for the A/D converter on and off. AVREF is turned on and off by an external transistor. An I/O port (P30-P37) which is not used for inputting analog signals (including two terminals used with the touch panel controller) is used to drive the transistor using the VRO register value. To set an I/O port for this function, set the I/O port in the output mode and write "1" to the data register. When "1" is written to the VRO register, the I/O port terminal goes low. When "0" is written, the terminal returns to high. If two or more I/O ports are set in this status, all the terminals are controlled with the VRO register. Therefore, P30-P37 cannot be used as generalpurpose output ports. When using P30 to P37 as general-purpose I/O ports, the VRO and VRC registers must be set to "0". An A/D conversion starts by writing data to the ADRUN register. For example, when performing A/D conversion using AD1 as the analog input, write "1" (0, 0, 1) to the CHS register (CHS2, CHS1, CHS0) and then write "1" to the ADRUN register. The A/D input channel is selected and the A/D conversion starts. However, it is necessary that the P31 terminal has been set as an analog input terminal. The built-in sample/hold circuit starts sampling of the analog input specified from tAD after writing. When the sampling is completed, the held analog input voltage is converted into a 10-bit digital value in successive-approximation architecture. VRC The VRC register enables the AVREF to be controlled by the touch panel controller. The touch panel controller controls the A/D converter during its operation. By writing "1" to the VRC register, the touch panel controller also controls AVREF in the same way as the VRO register. Thus it is unnecessary to change the VRO register while the touch panel controller operates. The conversion result is loaded into the ADDR (ADDR0-ADDR9) register. ADDR0 is the LSB and ADDR9 is the MSB. Note: If the CHS register selects an input channel which is not included in the analog input terminals set by the PAD register (the PAD register can select several terminals simultaneously), the A/D conversion does not result in a correct converted value. Input signal selection The analog signals from the AD0 (P30)-AD7 (P37) terminals are input to the multiplexer, and the analog input channel for A/D conversion is selected by software. This selection can be done using the CHS register as shown in Table 5.18.4.3. Example) Terminal setting: PAD5=1, PAD7=PAD6=PAD4-PAD0=0 (AD5 terminal is used) Selection of input channel: CHS2=1, CHS1=0, CHS0=0 (AD4 is selected) In a setting like this, the A/D conversion result will be invalid because the contents of the settings are not matched. Table 5.18.4.3 Selection of analog input channel 178 CHS2 CHS1 CHS0 Input channel 1 1 1 1 1 0 AD7 AD6 1 1 0 0 0 1 1 0 1 AD5 AD4 AD3 0 0 0 1 0 0 0 1 0 AD2 AD1 AD0 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) 5.18.5 Interrupt function Setting of analog input terminals (PAD) The A/D converter can generate an interrupt when an A/D conversion has completed. Figure 5.18.5.1 shows the configuration of the A/D converter interrupt circuit. Setting of input clock (PSAD) Turning clock output ON (PRAD) Writing to CHS register =selection of analog input channel Writing to ADRUN register =starting A/D conversion Fig. 5.18.4.1 Flowchart for starting A/D conversion An A/D conversion is completed when the conversion result is loaded into the ADDR register. At that point, the A/D converter generates an interrupt (explained in the next section). Figure 5.18.4.2 shows the timing chart of A/D conversion. The A/D converter sets the interrupt factor flag FAD to "1" when it stores the conversion. At this time, if the interrupt enable register EAD is "1" and the interrupt priority register PAD (2 bits) is set to a higher level than the setting of the interrupt flags (I0 and I1), an interrupt is generated to the CPU. By setting the EAD register to "0", the interrupt to the CPU can also be disabled. However, the interrupt factor flag is set to "1" when an A/D conversion has completed regardless of the interrupt enable register and interrupt priority register settings. The interrupt factor flag set in "1" is reset to "0" by writing "1". Refer to Section 5.20, "Interrupt and Standby Mode", for details of the interrupt control registers and operations subsequent to interrupt generation. The exception processing vector address for the A/ D conversion completion interrupt has been set in 000026H. Writing to ADRUN register Input sampling Successive conversion ADDR register Conversion result Interrupt request tAD Sampling time 8tCLK A/D conversion time 21tCLK+tAD tAD: 0 to 1tCLK tCLK: Input clock cycle Fig. 5.18.4.2 Timing chart of A/D conversion A/D conversion completion Data bus Address Address Address Interrupt factor flag FAD Interrupt enable register EAD Interrupt priority level judgment circuit Interrupt request Interrupt priority register PAD0, PAD1 Fig. 5.18.5.1 Configuration of A/D converter interrupt circuit S1C88409 TECHNICAL MANUAL EPSON 179 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) 5.18.6 I/O memory of A/D converter Table 5.18.6.1 shows the A/D converter control bits. Table 5.18.6.1(a) A/D converter control bits Address Bit 00FF13 D7 D6 D5 D4 D3 D2 Name - - - - PRAD PSAD2 D1 PSAD1 D0 PSAD0 00FF22 D7 D6 D5 D4 D3 D2 D1 D0 00FF26 D7 PAD1 PAD0 PTP1 PTP0 - - - - EAD D6 ETPPD D5 ETPDR D4 D3 D2 D1 D0 00FF2A D7 - - - - - FAD D6 FTPPD D5 FTPDR D4 D3 D2 D1 D0 00FF80 D7 D6 D5 D4 D3 D2 - - - - - ADRUN - - VRC VRO CHS2 180 D1 CHS1 D0 CHS0 Function - - - - A/D converter clock control A/D converter division ratio PSAD2 PSAD1 PSAD0 Division ratio 1 x x fOSC3 / 16 0 1 1 fOSC3 / 8 fOSC3 / 4 0 1 0 fOSC3 / 2 0 0 1 fOSC3 / 1 0 0 0 A/D converter interrupt priority register Touch panel controller interrupt priority register - - - - A/D converter conversion completion interrupt enable register Touch panel controller pen-down interrupt enable register Touch panel controller converted data update interrupt enable register - - - - - A/D converter conversion completion interrupt factor flag Touch panel controller pen-down interrupt factor flag Touch panel controller converted data update interrupt factor flag - - - - - A/D conversion start control register - - AVREF control (Touch pamel controller) AVREF swich Analog input channel selection CHS2 CHS1 CHS0 Input channel 1 1 1 AD7 1 1 0 AD6 1 0 1 AD5 1 0 0 AD4 0 1 1 AD3 0 1 0 AD2 0 0 1 AD1 0 0 0 AD0 EPSON 1 - - - - On 0 - - - - Off Init R/W Comment - - "0" when being read - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W PAD1 PTP1 1 1 0 0 PAD0 PTP0 1 0 1 0 Priority level Level 3 Level 2 Level 1 Level 0 0 0 0 0 - - - - 0 R/W R/W R/W R/W - "0" when being read - - - R/W 0 R/W Interrupt is enabled Interrupt is disabled (R) Interrupt factor has generated (R) Interrupt factor has not generated (W) Reset (W) Invalid Start - - Enable On Invalid - - Invalid Off 0 R/W - - "0" when being read - - - - - - - - 0 R/W 0 R/W 0 R/W - - "0" when being read - - - - - - - - 0 W "0" when being read - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Table 5.18.6.1(b) A/D converter control bits Address Bit 00FF81 D7 D6 D5 D4 D3 D2 D1 D0 00FF82 D7 D6 D5 D4 D3 D2 D1 D0 00FFE8 D7 D6 D5 D4 D3 D2 D1 D0 00FFE9 D7 D6 D5 D4 D3 D2 D1 D0 Name ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 - - - - - - ADDR1 ADDR0 PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 PDA7 PDA6 - - - - - - Function A/D conversion result - - - - - - 0 - - - - - - - - - - - - A/D converter input I/O port D1 D0(LSB) A/D conversion result P37 A/D converter input control P36 A/D converter input control P35 A/D converter input control P34 A/D converter input control P33 A/D converter input control P32 A/D converter input control P31 A/D converter input control P30 A/D converter input control P37 D/A converter output control P36 D/A converter output control - - - - - - D/A converter output - - - - - - I/O port - - - - - - Init - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 - - - - - - R/W Comment R R R R R R R R - "0" when being read - - - - - R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - - - Therefore, when using the P36 terminal (P37 terminal) as the analog input for the A/D converter, fix the PDA6 (PDA7) register at "0". At initial reset, the PDA register is set to "0" (I/O port). PAD0-PAD7: A/D converter input control register (00FFE8H) Sets the P30-P37 terminals as the analog input terminals for the A/D converter. When "1" is written: A/D converter input When "0" is written: I/O port Reading: Valid PSAD0-PSAD2: A/D converter division ratio selection register (00FF13H*D0-D2) Selects the clock for the A/D converter. When "1" is written to PADn, the P3n terminal is set to the analog input terminal ADn. (n=0-7) When "0" is written, the terminal is used with the I/O port. At initial reset, the PAD register is set to "0" (I/O port). Table 5.18.6.2 Input clock selection PDA6, PDA7: D/A converter output control register (00FFE9H*D6, D7) The PDA6 and PDA7 registers set the P36 and P37 terminals to the analog output terminal of the D/A converter, respectively. Those register settings have priority over the PAD6 and PAD7 settings. S1C88409 TECHNICAL MANUAL 1 D9(MSB) D8 D7 D6 D5 D4 D3 D2 PSAD2 PSAD1 PSAD0 1 x x 0 1 1 0 1 0 0 0 1 0 0 0 Division ratio fOSC3/16 fOSC3/8 fOSC3/4 fOSC3/2 fOSC3/1 This setting controls the division ratio of the prescaler. At initial reset, the PSAD register is set to "0" (fOSC3/1). EPSON 181 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) PRAD: A/D converter clock control register (00FF13H*D3) Controls the clock supply to the A/D converter. VRC: AVREF control register (00FF80H*D4) Enables the AVREF to be controlled by the touch panel controller. When "1" is written: ON When "0" is written: OFF Reading: Invalid When "1" is written: Enabled When "0" is written: Disabled Reading: Valid By writing "1" to the PRAD register, the prescaler outputs the clock selected with the PSAD register to the A/D converter. However, it is necessary that the CPU operating clock be set to OSC3. When "0" is written, the clock is not output to the A/D converter. At initial reset, the PRAD register is set to "0" (OFF). Writing "1" to the VRC register sets the touch panel controller so that it controls the AVREF without the VRO register. At initial reset, the VRC register is set to "0" (disabled). CHS0-CHS2: Analog input channel selection register (00FF80H*D0-D2) Selects an analog input channel. ADRUN: A/D conversion start trigger (00FF80H*D7) Starts A/D conversion. Table 5.18.6.3 Selection of analog input channel CHS2 1 1 1 1 0 0 0 0 When "1" is written: Start A/D conversion When "0" is written: Invalid Reading: Always "0" By writing "1" to this register, the A/D converter starts A/D conversion of the channel selected by the CHS register, and stores the conversion result to the ADDR register. CHS1 1 1 0 0 1 1 0 0 CHS0 1 0 1 0 1 0 1 0 Input channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 At initial reset, the CHS register is set to "0" (AD0). VRO: AVREF switch (00FF80H*D3) Turns AVREF on and off. ADDR0-ADDR9: A/D conversion result (00FF82H/low-order 2 bits, 00FF81H/high-order 8 bits) When "1" is written: On When "0" is written: Off Reading: Valid When "1" is written to the VRO register, AVREF turns on and when "0" is written turns off. An I/O port (P30-P37) which is not used for inputting analog signals can be used to switch the external AVREF input. Set the I/O port in the output mode and write "1" to the data register. Writing "1" to the VRO register in this status turns the I/O port terminal to low. The signal drives the external transistor to supply AVREF to the A/D converter. At initial reset, the VRO register is set to "0" (OFF). A/D conversion result is stored. ADDR0 is the LSB and ADDR9 is the MSB. ADDR0 and ADDR1 are assigned in D0 bit and D1 bit of the address 00FF82H. D2-D7 bits in this address are always "0" when being read. At initial reset, data is set to "0". PAD0, PAD1: A/D converter interrupt priority register (00FF22H*D6, D7) Sets the priority level of the A/D conversion completion interrupt. Table 5.18.6.4 shows the interrupt priority level which can be set by the PAD register. Table 5.18.6.4 Interrupt priority level settings Interrupt priority level PAD1 PAD0 1 1 0 Level 3 Level 2 1 0 Level 1 Level 0 1 0 0 (IRQ3) (IRQ2) (IRQ1) (None) At initial reset, the PAD register is set to "0" (level 0). 182 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) 5.18.7 Programming notes EAD: A/D conversion completion interrupt enable register (00FF26H*D7) Enables or disables the A/D conversion completion interrupt generation to the CPU. When "1" is written: Interrupt is enabled When "0" is written: Interrupt is disabled Reading: Valid The EAD register is the interrupt enable register corresponding to the A/D conversion completion interrupt factor. When this register is set to "1", the interrupt is enabled, and when it is set to "0", the interrupt is disabled. At initial reset, the EAD register is set to "0" (interrupt is disabled). FAD: A/D conversion completion interrupt factor flag (00FF2AH*D7) Indicates the generation of A/D conversion completion interrupt factor. When "1" is read: Int. factor has generated When "0" is read: Int. factor has not generated When "1" is written: Factor flag is reset When "0" is written: Invalid FAD is the interrupt factor flag corresponding to the A/D conversion completion interrupt. It is set to "1" when an A/D conversion is completed. At this point, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of the interrupt flags (I0 and I1), an interrupt is generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag is set to "1" when the interrupt generation condition is met. To accept the subsequent interrupt after an interrupt generation, it is necessary to re-set the interrupt flags (set the interrupt flag to a lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and to reset the interrupt factor flag. The interrupt factor flag is reset to "0" by writing "1". At initial reset, the FAD flag is reset to "0". S1C88409 TECHNICAL MANUAL (1) The A/D converter can operate by inputting the clock from the prescaler. Therefore, it is necessary to set the division ratio of the prescaler and to turn the clock output on before starting A/D conversion. Furthermore, it is also necessary that the OSC3 oscillation circuit is operating because the prescaler can operate only when the OSC3 is set as the CPU clock. (Refer to Section 5.5, "Prescaler and Clock Control Circuit for Peripheral Circuits".) (2) When SLEEP mode is set during A/D conversion, correct A/D conversion result cannot be obtained because the OSC3 oscillation circuit stops. Do not set in SLEEP mode during A/D conversion. (3) The input clock and analog input terminals should be set when the A/D converter stops. Changing in the A/D converter operation may cause a malfunction. (4) The frequency of the input clock should be lower than the maximum value shown in Section 8.7, "A/D Converter Characteristics". (5) To prevent malfunction, do not start A/D conversion (writing to the CHS register) when the A/D conversion clock is not being output from the prescaler, and do not turn the prescaler output clock off during A/D conversion. (6) If the CHS register selects an input channel which is not included in the analog input terminals set by the PAD register (the PAD register can select several terminals simultaneously), the A/D conversion does not result in a correct converted value. (7) During A/D conversion, do not operate the P3n terminals which are not used for analog inputs of the A/D converter (for input/output of digital signal and for D/A conversion). It affects the A/D conversion precision. EPSON 183 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (D/A Converter) AVREF (reference voltage input terminal) 5.19 D/A Converter 5.19.1 Characteristics and configuration of D/A converter The S1C88409 has built-in two channels of D/A converter with the following characteristics. * Conversion formula: * Resolution: * Output channel: * Conversion time: R-2R ladder type 8 bits 2 channels Minimum 30 sec (load capacitance: 100 pF) * Output voltage range: 0 V to AVREF (AVREF/256 steps) Figure 5.19.1.1 shows the configuration of the D/A converter. 5.19.2 Terminal configuration of D/A converter The terminals used with the D/A converter are as follows: The AVDD, AGND and AVSS terminals are power supply terminals for the A/D converter. The voltage should be input as AVDD VDD and AGND AVSS = VSS. These power supply terminals are common with the A/D converter. AVDD AVREF AGND AVSS DA0, DA1 (analog output terminal) The analog output terminals DA0 and DA1 are shared with the I/O port terminals P36 and P37. Further, those terminals can be used as the analog input terminals AD6 and AD7 of the A/D converter. Therefore, it is necessary to set them for the D/A converter by software when using them as an analog output terminal. This setting can be done for each terminal. (Refer to Section 5.19.4 for setting.) At initial reset, both the terminals are set in the I/O port terminals. 5.19.3 Mask option I/O port pull-up resistor P36 (DA0) With resistor P37 (DA1) With resistor Gate direct Gate direct The output terminals of the D/A converter are shared with the I/O port terminals P36 and P37. Therefore, the terminal specification of the D/A converter is decided by setting the I/O port mask option. Select "Gate direct" for the port corresponding to the channel to be used to obtain the conversion precision. Conversion data register (DADR) 8-bit D/A converter Data bus AVDD, AGND, AVSS (power supply input terminal) The AVREF terminal is the reference voltage terminal of the analog block. Output voltage range of the D/A conversion is decided by this input (AGND-AVREF). The voltage should be input as AVREFAVDD. This terminal is used as the reference voltage input of the A/D converter. It is possible to turn AVREF on and off by software. Refer to Section 5.18, "A/D Converter", for details. Control circuit DA0 (P36)/DA1 (P37) Fig. 5.19.1.1 Configuration of D/A converter 184 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (D/A Converter) 5.19.4 Control of D/A converter Initial settings When using the D/A converter, it is necessary to set up the terminals used for analog output from the P36 and P37 initialized as the I/O port terminals. When using DA0 (P36) as the analog output terminal, write "1" to the PDA6 register and "0" to the PAD6 register. When using DA1 (P37) as the analog output terminal, write "1" to the PDA7 register and "0" to the PAD7 register. Do not set both the terminals as analog outputs simultaneously. The analog output terminal goes to AGND level until the D/A conversion result is output. D/A conversion operation The DADR (DADR0-DADR7) register is used to write 8-bit data to be D/A converted. To start D/A conversion, write "1" to the DAE register. By this writing, data set in the DADR register is converted into analog value and the conversion result is output from the corresponding analog output terminal. The D/A converter takes a maximum 30 sec of D/A conversion time until it outputs the conversion result to the analog output terminal after starting D/A conversion with the DAE register. When "0" is written to the DAE register, the corresponding analog output terminal goes to AGND level. Table 5.19.4.1 Analog output level on DA0 and DA1 DA0 DA1 DAE 0 1 AGND D/A conversion output Furthermore, when new data is written to the DADR register keeping "1" of the DAE register, the data is converted by this writing and the result is output to the analog output terminal after a maximum 30 sec have passed after the writing. The following shows the analog output voltage according to the data written in the DADR register (0-255). Output voltage = AVREF [Value set in DADR register] / 256 (V) Note: When the status of the P37 (P36) terminal is changed while DA0 (1) is outputting the D/A conversion result, the DA0 (1) terminal may change its output level. The D/A converter has no built-in output buffer, so use an external amplifier to drive loads. In this case, make sure that the amplifier input current is 1 A or less. Writing to output data register (DADR) DAE Analog output Conversion result max. 30 sec Conversion result max. 30 sec Fig. 5.19.4.1 Timing chart of D/A conversion S1C88409 TECHNICAL MANUAL EPSON 185 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (D/A Converter) 5.19.5 I/O memory of D/A converter Table 5.19.5.1 shows the D/A converter control bits. Table 5.19.5.1 D/A converter control bits Address Bit 00FF90 D7 D6 D5 D4 D3 D2 D1 D0 00FF91 D7 D6 D5 D4 D3 D2 D1 D0 00FFE8 D7 D6 D5 D4 D3 D2 D1 D0 00FFE9 D7 D6 D5 D4 D3 D2 D1 D0 Name - - - - - - - DAE DADR7 DADR6 DADR5 DADR4 DADR3 DADR2 DADR1 DADR0 PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 PDA7 PDA6 - - - - - - Function - - - - - - - D/A conversion result output control D/A converter D/A conversion output data register When "1" is written: D/A converter output When "0" is written: I/O port Reading: Valid When "1" is written to the PDA6 register, the P36 terminal is set as the analog output terminal DA0 for the D/A converter. When "1" is written to the PDA7 register, the P37 terminal is set as the analog output terminal DA1 for the D/A converter. When "0" is written, the terminal is used with the I/O port. 186 0 - - - - - - - Disable A/D converter input I/O port D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) P37 A/D converter input control P36 A/D converter input control P35 A/D converter input control P34 A/D converter input control P33 A/D converter input control P32 A/D converter input control P31 A/D converter input control P30 A/D converter input control P37 D/A converter output control P36 D/A converter output control - - - - - - PDA6, PDA7: D/A converter output control register (00FFE9H*D6, D7) Sets the P36 and P37 terminals as the analog output terminals for the D/A converter. 1 - - - - - - - Enable D/A converter output - - - - - - I/O port - - - - - - Init - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - - - R/W Comment - "0" when being read - - - - - - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - - - Both terminals output the same signal, however, do not set them as analog output terminals at the same time. At initial reset, the PDA register is set to "0" (I/O port). PAD6, PAD7: A/D converter input control register (00FFE8H*D6, D7) The PAD6 and PAD7 registers set the P36 and P37 terminals to the analog input terminal of the A/D converter, respectively. The setting of the PDA6 and PDA7 registers have priority over those registers' settings. However, fix the PAD6 (PAD7) register at "0". At initial reset, the PAD register is set to "0" (I/O port). EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (D/A Converter) 5.19.6 Programming note DAE: D/A conversion result output enable register (00FF90H*D0) Enables D/A conversion output. The D/A converter should be operated only when it is necessary in order to reduce current consumption. Stop D/A conversion by writing "0" to the DAE register if unnecessary. When "1" is written: D/A conversion output is enabled When "0" is written: D/A conversion output is disabled Reading: Valid When "1" is written to the DAE register, D/A conversion is enabled. When "0" is written, it is disabled. At initial reset, the DAE register is set to "0" (D/A conversion output is disabled). DADR0-DADR7: D/A conversion output data register (00FF91H) Data for D/A conversion is set in this register. The data written in this register is converted to the analog value and is output to the corresponding analog output terminal when the DAE register is set to "1". The analog voltage value output will be AVREF[setting value in DADR register]/256. When "1" is written to the DAE register after writing data to this register, a delay for a D/A conversion time (30 sec max.) occurs from writing of the DAE register until the conversion result is actually output. Also when this register is changed keeping the DAE register at "1", the new data is converted by this writing and the result is output to the analog output terminal after the D/A conversion time has passed. S1C88409 TECHNICAL MANUAL EPSON 187 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode) 5.20 Interrupt and Standby Mode Hardware interrupts 5.20.1 Types of interrupts External interrupts * K00-K07 input interrupt * K10-K13 input interrupt (1 type) (4 types) Internal interrupts * 16-bit programmable timer 0 interrupt * 16-bit programmable timer 1 interrupt * 8-bit programmable timer interrupt * Serial interface interrupt * Touch panel controller interrupt * LCD controller interrupt * A/D converter interrupt * Clock timer interrupt (2 types) (2 types) (1 type) (3 types) (2 types) (1 type) (1 type) (5 types) The S1C88409 allows one line of non-maskable interrupt, and 10 systems (22 types) of hardware interrupts. Non-maskable interrupts (NMI) * Watchdog timer interrupt (1 type) NMI is the interrupt that cannot be masked with software. It is accepted prior to all hardware interrupts. However, the watchdog timer can be set by software so that it does not generate NMI. Refer to Section 5.3, "Watchdog Timer", for the control of the watchdog timer. NMI is exceptionally masked at initial reset and it is not input to the CPU in order to prevent malfunction caused by an NMI generation before setting the system configuration. The masking is released when data is written to the addresses 00FF00H and 00FF01H in the I/O memory. An interrupt factor flag that indicates a generation of the interrupt factor and an interrupt enable register to enable/disable the interrupt request have been provided for each interrupt. By using those, interrupt generation can be controlled by each factor. In addition, an interrupt priority register has been provided for each system of interrupts and the priority of interrupt processing can be set to 3 levels in each system. Figure 5.20.1.1 shows the configuration of the interrupt circuit. Refer to the explanations of the respective peripheral circuits for details of each interrupt. 188 EPSON S1C88409 TECHNICAL MANUAL Interrupt vector address generation circuit Input port K1 Input port K0 K10 FK10 EK10 IRK10 K11 FK11 EK11 IRK11 K12 FK12 EK12 IRK12 K13 FK13 EK13 IRK13 K00-K07 FK0 EK0 IRK0 Timer 1 underflow 16-bit programmable timer Timer 1 compare match Timer 0 underflow Timer 0 compare match 8-bit programmable Underflow timer Serial interface Receive completion Receive error Transmit completion Pen-down Touch panel controller LCD controller A/D converter Clock timer Converted data update Data transfer completion Conversion completion FTU1 ETU1 IRTU1 FTC1 ETC1 IRTC1 FTU0 ETU0 IRTU0 FTC0 ETC0 IRTC0 FTU2 ETU2 IRTU2 FSERR ESER IRSER Data bus CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode) PK11 PK10 PK01 PK00 PTM11 PTM10 PTM01 PTM00 PTM41 PTM40 NMI Interrupt priority level judgment circuit IRQ3 IRQ2 IRQ1 IRQ0 FSRX ESRX IRSRX FSTX ESTX IRSTX FTPPD ETPPD IRTP1 FTPDR ETPDR IRTP2 FLCD ELCD PTP1 PTP0 IRLCD PLCD1 PLCD0 FAD EAD 32 Hz FCTM32 ECTM32 8 Hz FCTM8 ECTM8 2 Hz FCTM2 ECTM2 1 Hz FCTM1 ECTM1 60 seconds FT60S ET60S PSI1 PSI0 IRAD PAD1 PAD0 IRRTC PCTM1 PCTM0 Fig. 5.20.1.1 Configuration of interrupt circuit S1C88409 TECHNICAL MANUAL EPSON 189 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode) 5.20.2 Standby mode 5.20.3 Interrupt generation conditions The S1C88409 has two standby modes, HALT mode and SLEEP mode, for saving power. The following explains each standby mode. For all interrupts (10 systems, 22 types) except for NMI, interrupt factor flags that indicate the generation of the interrupt factors are provided. They are set to "1" when the corresponding interrupt factor is generated. In addition, interrupt enable registers corresponding to the interrupt factor flags are provided. Writing "1" to the interrupt enable register enables the interrupt to the CPU, and writing "0" disables the interrupt. The CPU controls interrupt requests with the interrupt priority level. The priority level of each interrupt can be set with the interrupt priority registers, and the CPU accepts only the interrupts which have a level higher than the setting of the interrupt flags (I0 and I1). Therefore, it is necessary to meet the following three conditions so that the CPU accepts the interrupt. HALT mode The S1C88409 enters into HALT mode by executing the HALT instruction. In HALT mode, the peripheral circuits operate but the CPU stops operating. Thus, saving power can be realized. HALT mode is canceled by initial reset or an optional interrupt request, and the CPU resumes program execution from the exception processing routine. Refer to the "S1C88 Core CPU Manual" for HALT status and reactivating sequence. SLEEP mode The S1C88409 enters into SLEEP mode by executing the SLP instruction. In SLEEP mode, the CPU and the oscillation circuits (OSC1 and OSC3) stop operating. Consequently, a greater power saving than HALT mode can be realized. SLEEP status is canceled by initial reset, NMI or an input interrupt from the input port. The oscillation circuit, that has stopped by shifting to SLEEP mode, resumes oscillating when SLEEP mode is canceled. The CPU resumes program execution from the exception processing routine. (1) The interrupt factor flag has been set to "1" by generation of an interrupt factor. (2) The interrupt enable register corresponding to the interrupt factor has been set to "1". (3) The interrupt priority register corresponding to the interrupt factor has been set to a priority level higher than the interrupt flag (I0 and I1) setting. The CPU samples interrupt requests in the first opcode fetch cycle for every instruction, and shifts to exception processing when the above mentioned conditions have been met. Refer to the "S1C88 Core CPU Manual" for the exception processing sequence. Table 5.20.3.1 shows the interrupt factors, interrupt enable registers and interrupt priority registers corresponding to the interrupt factors. 190 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode) Table 5.20.3.1 Interrupt factors and control registers Interrupt factor Input port K1 No match between K10 input and input comparison register KCP10 No match between K11 input and input comparison register KCP11 No match between K12 input and input comparison register KCP12 No match between K13 input and input comparison register KCP13 Input port K0 No match between K0 input (8 bits) and input comparison register KCP0 16-bit Timer 0 underflow programmable Compare match between timer 0 and timer compare data register CDR0 Timer 1 underflow Compare match between timer 1 and compare data register CDR1 8-bit programmable Counter underflow timer Serial I/F Receive error Receive completion Transmit completion Touch panel Pen-down controller Converted data update LCD controller Data transfer completion A/D converter A/D conversion completion Clock timer Falling edge of 32 Hz signal Falling edge of 8 Hz signal Falling edge of 2 Hz signal Falling edge of 1 Hz signal 60S counter overflow S1C88409 TECHNICAL MANUAL Interrupt factor flag Interrupt enable register Interrupt priority register Name Address*Dx Name Address*Dx Name Address*Dx FK10 00FF27H*D4 EK10 00FF23H*D4 PK10 00FF20H*D6 PK11 00FF20H*D7 FK11 00FF27H*D5 EK11 00FF23H*D5 FK12 00FF27H*D6 EK12 00FF23H*D6 FK13 00FF27H*D7 EK13 00FF23H*D7 FK0 00FF27H*D3 EK0 FTU0 FTC0 00FF28H*D3 ETU0 00FF28H*D4 ETC0 00FF23H*D3 PK00 PK01 00FF24H*D3 PTM00 00FF24H*D4 PTM01 00FF20H*D4 00FF20H*D5 00FF20H*D0 00FF20H*D1 FTU1 FTC1 00FF28H*D5 ETU1 00FF28H*D6 ETC1 00FF24H*D5 PTM10 00FF24H*D6 PTM11 00FF20H*D2 00FF20H*D3 FTU2 00FF28H*D7 ETU2 00FF24H*D7 PTM20 PTM21 FSERR 00FF28H*D0 ESERR 00FF24H*D0 PSI0 FSRX 00FF28H*D1 ESRX 00FF24H*D1 PSI1 FSTX 00FF28H*D2 ESTX 00FF24H*D2 FTPPD 00FF2AH*D6 ETPPD 00FF26H*D6 PTP0 FTPDR 00FF2AH*D5 ETPDR 00FF26H*D5 PTP1 FLCD 00FF29H*D2 ELCD 00FF25H*D2 PLCD0 PLCD1 FAD 00FF2AH*D7 EAD 00FF26H*D7 PAD0 PAD1 FCTM32 00FF29H*D3 ECTM32 00FF25H*D3 PCTM0 FCTM8 00FF29H*D4 ECTM8 00FF25H*D4 PCTM1 FCTM2 00FF29H*D5 ECTM2 00FF25H*D5 FCTM1 00FF29H*D6 ECTM1 00FF25H*D6 FT60S 00FF29H*D7 ET60S 00FF25H*D7 00FF21H*D6 00FF21H*D7 00FF21H*D4 00FF21H*D5 EPSON 00FF22H*D4 00FF22H*D5 00FF21H*D0 00FF21H*D1 00FF22H*D6 00FF22H*D7 00FF21H*D2 00FF21H*D3 191 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode) 5.20.4 Interrupt factor flag The interrupt factor flag is set to "1" when the corresponding interrupt factor generates. By reading the interrupt factor flag, it is possible to confirm the interrupt factor that has been generated. Interrupt factor flag that has been set to "1" is reset to "0" by writing "1". At initial reset, all the interrupt factor flags are reset to "0". Note: When the RETE instruction is executed without resetting the interrupt factor flag after an interrupt has been generated, the same interrupt is generated again. Therefore, the interrupt factor flag must be reset (writing "1") in the interrupt handler routine. At initial reset, all the interrupt priority registers are set to "0" and all interrupts are set to level 0. Furthermore, the priorities inside of each system have been previously decided and they cannot be changed. The CPU can mask each interrupt by setting the interrupt flags (I0 and I1). The relation between the interrupt priority level of each system and interrupt flags is shown in Table 5.20.6.2. The CPU accepts only interrupts set in a higher level than the interrupt flag setting. The priority level of NMI (watchdog timer) is set in level 4, so it is always accepted regardless of the interrupt flag setting. Table 5.20.6.2 Interrupt mask setting for CPU 5.20.5 Interrupt enable register The interrupt enable registers corresponding to all interrupt factor flags are provided to enable/ disable the interrupt requests to the CPU. When "1" is written to the interrupt enable register, the interrupt request is enabled and when "0" is written, it is disabled. This register can also be read, thus making it possible to confirm the setting status. At initial reset, all the interrupt enable registers are set to "0" and all the interrupts except for NMI are disabled. The priority level of each interrupt system can be optionally set to four levels (0 to 3) by the interrupt priority register. However, when two or more systems are set to the same priority level, they are processed according to the default priority level. Table 5.20.6.1 Setting of interrupt priority level 192 P*1 P*0 1 1 0 0 1 0 1 0 Interrupt priority level Level 3 Level 2 Level 1 Level 0 (IRQ3) (IRQ2) (IRQ1) I0 1 1 1 0 Level 4 (NMI) Level 4, Level 3 (IRQ3) 0 0 1 0 Level 4, Level 3, Level 2 (IRQ2) Level 4, Level 3, Level 2, Level 1 (IRQ1) After an interrupt is accepted, the interrupt flags are changed to the same level of the interrupt accepted as shown in Table 5.20.6.3 in order to mask interrupt requests with the same priority level or less. However, it is set to level 3 after an NMI is accepted. Table 5.20.6.3 Interrupt flags after acceptance of interrupt Accepted interrupt priority level 5.20.6 Interrupt priority register and interrupt priority level Each interrupt system provides the interrupt priority register shown in Table 5.20.3.1. By using the interrupt priority register, the priority of each interrupt can be changed so that the CPU can process interrupt in order of priority. Consequently, it is possible to make a multiple interrupt system that meets the demand of the application. Acceptable interrupt I1 I1 I0 Level 4 Level 3 (NMI) (IRQ3) 1 1 1 1 Level 2 Level 1 (IRQ2) (IRQ1) 1 0 0 1 The interrupt flags changed are returned to the previous value at return from the interrupt handler routine. Multiple interrupts up to 3 levels can be controlled by only setting the interrupt priority registers. Multiple interrupts exceeding 3 levels can be realized by rewriting the interrupt flags and interrupt enable register in the interrupt handler routine. Note: Be aware if the interrupt flags are rewritten (set to lower priority) prior to resetting the interrupt factor flag after an interrupt is generated, the same interrupt will be generated again. (None) EPSON S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode) 5.20.7 Exception processing vectors Exception processing vector is a 2-byte data to address the top of each exception (interrupt) handler routine. The vector addresses correspond to the exception processing factors as shown in Table 5.20.7.1. When the CPU accepts an interrupt request, it starts exception processing immediately after completing the instruction being executed. The CPU executes the following sequence as an exception processing for branching the program. (1) In the minimum mode, the program counter (PC) and system condition flag (SC) are saved in the stack. In the maximum mode, the code bank register (CB), PC and SC are saved. (2) The branch destination address is read from the exception processing vector corresponding to each exception processing (interrupt) factor and is set in the PC. Note: An exception processing vector is fixed at 2 bytes, so it cannot specify a branch destination bank address. Therefore, to branch from two or more banks to a common exception handler routine, the top portion of the exception handler routine must be described within the common area (000000H-007FFFH). Table 5.20.7.1 Vector address and exception processing vector Vector address 000000H 000002H 000004H 000006H 000008H 00000AH 00000CH 00000EH 000010H 000012H 000014H 000016H 000018H 00001AH 00001CH 00001EH 000020H 000022H 000024H 000026H 000028H 000032H 000034H 0000FEH Symbol RESET ZDIV NMI IRK10 IRK11 IRK12 IRK13 IRK0 IRTU0 IRTC0 IRTU1 IRTC1 IRTU2 IRSER IRSRX IRSTX IRTP1 IRTP2 IRLCD IRAD IRRTC - - S1C88409 TECHNICAL MANUAL Exception processing factor Reset Zero division NMI (Watchdog timer) Input port K1 K10 input interrupt K11 input interrup K12 input interrup K13 input interrup Input port K0 K00-K07 input interrup 16-bit programmable timer 0 Underflow interrupt Compare match interrupt 16-bit programmable timer 1 Underflow interrupt Compare match interrupt 8-bit programmable timer Underflow interrupt Serial interface Receive error interrupt Receive completion interrupt Receive error interrupt Touch panel controller Pen-down interrupt Converted data update interrupt LCD controller Data transfer completion interrupt A/D converter A/D conversion completion interrupt Clock timer 32Hz/8Hz/2Hz/1Hz/60S interrupt System reserved (cannot be used) Software interrupt EPSON Priority High Low No Priority rating 193 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode) 5.20.8 I/O memory of interrupt Table 5.20.8.1 shows the interrupt control bits. Table 5.20.8.1(a) Interrupt control bits Address Bit 00FF20 D7 D6 D5 D4 D3 D2 D1 D0 00FF21 D7 D6 D5 D4 D3 D2 D1 D0 00FF22 D7 D6 D5 D4 D3 D2 D1 D0 00FF23 D7 D6 D5 D4 D3 D2 D1 D0 00FF24 D7 Name PK11 PK10 PK01 PK00 PTM11 PTM10 PTM01 PTM00 PTM21 PTM20 PSI1 PSI0 PCTM1 PCTM0 PLCD1 PLCD0 PAD1 PAD0 PTP1 PTP0 - - - - EK13 EK12 EK11 EK10 EK0 - - - ETU2 D6 ETC1 D5 ETU1 D4 ETC0 D3 ETU0 D2 ESTX D1 ESRX D0 ESERR 00FF25 D7 ET60S D6 ECTM1 D5 ECTM2 D4 ECTM8 D3 ECTM32 D2 ELCD D1 - D0 - 194 Function K10-K13 interrupt priority register K00-K07 interrupt priority register 16-bit programmable timer 1 interrupt priority register 16-bit programmable timer 0 interrupt priority register 8-bit programmable timer interrupt priority register Serial interface interrupt priority register Clock timer interrupt priority register LCD controller interrupt priority register A/D converter interrupt priority register Touch panel controller interrupt priority register - - - - K13 interrupt enable register K12 interrupt enable register K11 interrupt enable register K10 interrupt enable register K00-K07 interrupt enable register - - - 8-bit programmable timer underflow interrupt enable register 16-bit programmable timer 1 compare match interrupt enable register 16-bit programmable timer 1 underflow interrupt enable register 16-bit programmable timer 0 compare match interrupt enable register 16-bit programmable timer 0 underflow interrupt enable register Serial interface transmit completion interrupt enable register Serial interface receive completion interrupt enable register Serial interface receive error interrupt enable register Clock timer 60 S interrupt enable register Clock timer 1 Hz interrupt enable register Clock timer 2 Hz interrupt enable register Clock timer 8 Hz interrupt enable register Clock timer 32 Hz interrupt enable register LCD controller interrupt enable register - - EPSON 1 PK11 PK01 PTM11 PTM01 1 1 0 0 PTM21 PSI1 PCTM1 PLCD1 1 1 0 0 PAD1 PTP1 1 1 0 0 0 PK10 PK00 PTM10 PTM00 1 0 1 0 PTM20 PSI0 PCTM0 PLCD0 1 0 1 0 PAD0 PTP0 1 0 1 0 Interrupt is enabled Priority level Level 3 Level 2 Level 1 Level 0 Priority level Level 3 Level 2 Level 1 Level 0 Priority level Level 3 Level 2 Level 1 Level 0 Interrupt is disabled Init 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - 0 0 0 0 0 - - - 0 R/W Comment R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - R/W R/W R/W R/W R/W - "0" when being read - - R/W 0 R/W 0 R/W 0 R/W Interrupt is enabled Interrupt is disabled 0 R/W 0 R/W 0 R/W 0 R/W Interrupt is enabled Interrupt is disabled 0 0 0 0 0 0 - - R/W R/W R/W R/W R/W R/W - "0" when being read - S1C88409 TECHNICAL MANUAL CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode) Table 5.20.8.1(b) Interrupt control bits Address Bit 00FF26 D7 Name EAD Function 1 0 Init R/W Comment A/D converter 0 R/W conversion completion interrupt enable register D6 ETPPD Touch panel controller 0 R/W pen-down interrupt enable register D5 ETPDR Touch panel controller 0 R/W Interrupt is Interrupt is converted data update interrupt enable register enabled disabled D4 - - - "0" when being read - D3 - - - - D2 - - - - D1 - - - - D0 - - - - 00FF27 D7 FK13 K13 interrupt factor flag (R) (R) 0 R/(W) D6 FK12 K12 interrupt factor flag Interrupt Interrupt 0 R/(W) D5 FK11 K11 interrupt factor flag factor has factor has not 0 R/(W) D4 FK10 K10 interrupt factor flag generated generated 0 R/(W) D3 FK0 K00-K07 interrupt factor flag 0 R/(W) (W) (W) D2 - - - - "0" when being read Reset Invalid D1 - - - - D0 - - - - 00FF28 D7 FTU2 8-bit programmable timer 0 R/(W) underflow interrupt factor flag D6 FTC1 16-bit programmable timer 1 0 R/(W) (R) (R) Interrupt Interrupt compare match interrupt factor flag D5 FTU1 16-bit programmable timer 1 factor has factor has not 0 R/(W) generated generated underflow interrupt factor flag D4 FTC0 16-bit programmable timer 0 0 R/(W) compare match interrupt factor flag D3 FTU0 16-bit programmable timer 0 0 R/(W) underflow interrupt factor flag D2 FSTX Serial interface 0 R/(W) (W) (W) transmit completion interrupt factor flag D1 FSRX Serial interface 0 R/(W) Reset Invalid receive completion interrupt factor flag D0 FSERR Serial interface 0 R/(W) receive error interrupt factor flag 00FF29 D7 FT60S Clock timer 60 S interrupt factor flag (R) (R) 0 R/(W) D6 FCTM1 Clock timer 1 Hz interrupt factor flag Interrupt Interrupt 0 R/(W) D5 FCTM2 Clock timer 2 Hz interrupt factor flag factor has factor has not 0 R/(W) D4 FCTM8 Clock timer 8 Hz interrupt factor flag generated generated 0 R/(W) D3 FCTM32 Clock timer 32 Hz interrupt factor flag 0 R/(W) (W) (W) D2 FLCD LCD controller interrupt factor flag 0 R/(W) Reset Invalid D1 - - - - "0" when being read D0 - - - - 00FF2A D7 FAD A/D converter 0 R/W (R) (R) conversion completion interrupt factor flag D6 FTPPD Touch panel controller 0 R/W Interrupt Interrupt factor has factor has not pen-down interrupt factor flag D5 FTPDR Touch panel controller 0 R/W generated generated converted data update interrupt factor flag D4 - - - "0" when being read - D3 - - - - (W) (W) D2 - - - - Reset Invalid D1 - - - - D0 - - - - 00FF53 D7 WRWD EWD, WDCL write enable Write enable Write disable 0 R/W 1 D6 EWD Watchdog timer NMI enable NMI enable NMI disable 1 R/W 1 D5 WDCL Watchdog timer input clock selection fOSC3/16 fOSC1/16 0 R/W 1 - - D4 - - - - "0" when being read - - D3 - - - - - - D2 - - - - - - D1 - - - - Reset Invalid D0 WDRST Watchdog timer reset - W 1 Writing to EWD or WDCL is valid after "1" is written to WRWD. WRWD is automatically returns to "0" after writing to EWD or WDCL. S1C88409 TECHNICAL MANUAL EPSON 195 CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode) Table 5.20.8.1(c) Interrupt control bits Address Bit 00FFC0 D7 D6 D5 D4 D3 D2 D1 D0 00FFC1 D7 D6 D5 D4 D3 D2 D1 D0 00FFC2 D7 D6 D5 D4 D3 D2 D1 D0 Name SIK07 SIK06 SIK05 SIK04 SIK03 SIK02 SIK01 SIK00 KCP07 KCP06 KCP05 KCP04 KCP03 KCP02 KCP01 KCP00 - - - - KCP13 KCP12 KCP11 KCP10 Function K07 interrupt selection register K06 interrupt selection register K05 interrupt selection register K04 interrupt selection register K03 interrupt selection register K02 interrupt selection register K01 interrupt selection register K00 interrupt selection register K07 input comparison register K06 input comparison register K05 input comparison register K04 input comparison register K03 input comparison register K02 input comparison register K01 input comparison register K00 input comparison register - - - - K13 input comparison register K12 input comparison register K11 input comparison register K10 input comparison register Refer to the explanations on the respective peripheral circuits for the setting contents and control for each bit. 1 0 Interrupt is enabled Interrupt is disabled Falling edge generates interrupt Rising edge generates interrupt - - - - - - - - Falling edge generates interrupt Rising edge generates interrupt Init 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 R/W Comment R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - "0" when being read - - - R/W R/W R/W R/W 5.20.9 Programming notes (1) When the RETE instruction is executed without resetting the interrupt factor flag after an interrupt has been generated, the same interrupt is generated again. Therefore, the interrupt factor flag must be reset (writing "1") in the interrupt handler routine. (2) Be aware if the interrupt flags (I0, I1) are rewritten (set to lower priority) prior to resetting the interrupt factor flag after an interrupt is generated, the same interrupt will be generated again. (3) An exception processing vector is fixed at 2 bytes, so it cannot specify a branch destination bank address. Therefore, to branch from two or more banks to a common exception handler routine, the top portion of the exception handler routine must be described within the common area (000000H-007FFFH). 196 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 6: SUMMARY OF NOTES CHAPTER 6 SUMMARY OF NOTES 6.1 Notes for Low Current Consumption The S1C88409 can turn circuits, which consume a large amount of power, ON or OFF by the control registers. These control registers lower the current consumption through programs that operate the circuits at the minimum levels. Table 6.1.1 shows the circuits and the control registers (instructions). Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS" for the current consumption. Table 6.1.1 Circuits and control registers Control register/instruction Status at initial reset CPU Oscillation circuit HALT and SLP instructions CLKCHG, OSCC Operating OSC1 clock (CLKCHG="0") Operating voltage VD1 SVD circuit A/D converter D/A converter Touch panel controller VD1C SVDON ADRUN DAE RST OSC3 oscillation OFF (OSCC="0") 2.4 V (VD1C="00B") OFF status (SVDON="0") OFF status (ADRUN="0") OFF status (DAE="0") OFF status (RST="0") Circuit 6.2 Summary of Notes by Function Here, the cautionary notes are summed up by function category. Keep these notes well in mind when programming. System controller and bus control After initial reset, all the interrupts including NMI are masked until the appropriate values are written to the I/O memory addresses "00FF00H" and "00FF01H" to prevent malfunctions that may occur before setting the system configuration. Therefore, write data to the addresses in the initial routine even though the initial settings are used. Furthermore, set the stack pointer SP prior to writing so that interrupt processing will operate normally. Watchdog timer (1) When the watchdog timer NMI is authorized, it is necessary to reset the counter by software before an overflow is generated. (2) At initial reset, the watchdog timer starts counting by inputting the fOSC1/16 clock and is set to generate NMI. When the watchdog timer is not used, write "0" to the EWD register before the first overflow is generated. (3) The count operation is continued even when the EWD register is set to "0" if the clock is input. Therefore, when NMI is invalidated temporarily, reset the watchdog timer before changing back the EWD register to "1". S1C88409 TECHNICAL MANUAL (4) The oscillation clock becomes unstable immediately after SLEEP is canceled. Therefore, reset the watchdog timer before shifting to SLEEP status and after SLEEP status is canceled so that an unnecessary NMI will not be generated. Oscillation circuit (1) The VD1 level must be switched while the OSC3 oscillation circuit is off (before turning on and after turning off). Switching during operation may cause malfunction. Furthermore, the VD1 voltage required at least 5 msec of voltage stabilizing time after switching. Do not turn the OSC3 oscillation circuit on during this period. (2) VD1 cannot be switched directly to a level that is two or three levels different from the current level. The middle level must be set between the switching. To switch from 1,6 (3.2) V to 3.2 (1.6) V: 1.6 V 2.4 V 3.2 V 1.6 V 2.4 V 3.2 V To switch from 1.6 (4.2) V to 4.2 (1.6) V: 1.6 V 2.4 V 3.2 V 4.2 V 1.6 V 2.4 V 3.2 V 4.2 V EPSON 197 CHAPTER 6: SUMMARY OF NOTES To switch from 2.4 (4.2) V to 4.2 (2.4) V: 2.4 V 3.2 V 4.2 V 2.4 V 3.2 V 4.2 V A 5 msec interval is required for each switching steps. (3) To generate VD1 with specified voltage, the supply voltage must be higher than the specified voltage. To prevent malfunction, make sure that the supply voltage is not lowered under the VD1 value to be set using the SVD circuit before switching VD1. Do not switch VD1 to a voltage higher than the supply voltage if the supply voltage drops. (4) The OSC3 oscillation circuit takes a maximum 20 msec for stabilizing oscillation after turning the OSC3 oscillation circuit on. Therefore, take an enough interval after the OSC3 oscillation goes on before starting control of the peripheral circuit, such as the programmable timer, serial interface and A/D converter, that uses the OSC3 oscillation circuit as the clock source. (The oscillation start time varies depending on the oscillator and external component to be used. Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS", in which an example of oscillation start time is indicated.) (5) Use a separate instruction for switching the clock from OSC3 to OSC1 and turning the OSC3 oscillation off. Handling with one instruction may cause malfunction of the CPU. (6) To prevent malfunction, before stopping the OSC3 oscillation, stop the operation of the peripheral circuits that use the OSC3 oscillation circuit as the clock source, such as programmable timer, serial interface and A/D converter. (7) Do not turn the OSC3 oscillation circuit on to reduce current consumption when the OSC3 clock is not necessary. Prescaler When using an output clock from the OSC3 prescaler, it is necessary to turn the OSC3 oscillation circuit on. Furthermore, the OSC3 oscillation circuit takes a maximum 20 msec for stabilizing oscillation after turning the OSC3 oscillation circuit on. Therefore, wait a long enough interval after the OSC3 oscillation goes on before turning the clock output of the OSC3 prescaler on. (The oscillation start time varies depending on the oscillator and external components to be used. 198 Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS", in which an example of oscillation start time is indicated.) Input port (K port) I/O port (P port) When the input terminal is changed from a low level to a high level by the built-in pull-up resistor, the rise of the waveform is delayed on account of the time constant of the pull-up resistor and load capacitance of the terminal. Hence, when reading the input port, it is necessary to wait an appropriate amount of time. Particular care must be taken of the key scan for the key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression. Waiting time = RIN x (CIN + CL) x 1.6 [sec] RIN: Pull-up resistance Max. value CIN: Terminal capacitance Max. value CL: Load capacitance on the board Clock output (1) The FOUT3 clock and TOUT0 clock cannot be output simultaneously, because they use the same port, similar to the FOUT1 clock and TOUT1 clock. (2) Be aware that the output is fixed at low (VSS) level when the data register of the output port used for the clock output is set to "0". (3) A hazard may occur on the output signal when the clock output control register is changed. (4) Since the output clock becomes unstable when SLEEP mode is canceled, stop the output before shifting to SLEEP mode. LCD controller (1) Do not write "0" to the LCDEN register while the LCD panel is ON. The LCD panel may be damaged. (2) Only the 4-bit continuous data refresh mode is available in the gray-scale mode. Do not use 8bit data transfer or another transfer mode. (3) The data transfer uses the OSC3 clock. Therefore, turn the OSC3 oscillation on before writing "1" to the LCDEN register. Furthermore, wait 20 msec or more after turning the OSC3 oscillation on for stabilizing oscillation. In the one-shot transfer mode or hardware auto-transfer mode, do not turn the OSC3 oscillation off before finishing data transfer. EPSON S1C88409 TECHNICAL MANUAL CHAPTER 6: SUMMARY OF NOTES When the segment driver is in self-refresh status, the OSC3 oscillation can be stopped to reduce current consumption. (4) When setting the CPU in SLEEP status, be sure to turn the LCD panel power off and stop operation of the LCD controller. Clock timer (1) The clock timer actually entqzs into RUN or STOP status at the falling edge of the 256 Hz signal after writing to the TMRUN register. Consequently, when "0" is written to TMRUN, the timer stops after counting once more (+1). TMRUN is read as "1" until the timer actually stops. Figure 6.2.1 shows the timing chart at the RUN/STOP control. 256 Hz TMRUN (RD) (3) In the 16-bit mode, reading PTM0 does not latch the timer 1 counter data in PTM1. To avoid generating a borrow from timer 0 to timer 1, read the counter data after stopping the timer by writing "0" to PTRUN0. 8-bit programmable timer TMRUN (WR) TMDX (2) When the SLP instruction is executed while the 16-bit programmable timer is running (PTRUN0(1) = "1"), the timer stops counting during SLEEP status. When SLEEP status is canceled, the timer starts counting. However, the operation becomes unstable immediately after SLEEP status is canceled. Therefore, when shifting to SLEEP status, stop the 16-bit programmable timer (PTRUN0(1) = "0") prior to executing the SLP instruction. Same as above, the TOUT signal output should be disabled (PTOUT0(1) = "0") so that an unstable clock is not output to the clock output port terminal. 57H 58H 59H 5AH 5BH 5CH Fig. 6.2.1 Timing chart at RUN/STOP control (2) The 60-second counter is preset only when data is written to the TMMD register. The register does not maintain the preset data and returns to 0-second when the counter overflows. To prevent the counter from abnormal operation, do not preset data without a range of 0 to 59 (BCD). (1) The 8-bit programmable timer actually enters into RUN or STOP status at the falling edge of the input clock after writing to the PRUN register. Consequently, when "0" is written to PRUN, the timer stops after counting once more (+1). PRUN is read as "1" until the timer actually stops. Figure 6.2.3 shows the timing chart of the RUN/STOP control. Input clock PRUN (RD) 16-bit programmable timer PRUN (WR) (1) The 16-bit programmable timer actually enters into RUN or STOP status at the falling edge of the input clock after writing to the PTRUN0(1) register. Consequently, when "0" is written to PTRUN0(1), the timer stops after counting once more (+1). PTRUN0(1) is read as "1" until the timer actually stops. Figure 6.2.2 shows the timing chart at the RUN/STOP control. Input clock PTRUN0/PTRUN1(RD) PTRUN0/PTRUN1(WR) PTM0/PTM1 42H 41H 40H 3FH 3EH 3DH Fig. 6.2.2 Timing chart at RUN/STOP control S1C88409 TECHNICAL MANUAL PTD 42H 41H 40H 3FH 3EH 3DH Fig. 6.2.3 Timing chart at RUN/STOP control (2) When the SLP instruction is executed while the 8-bit programmable timer is running (PRUN = "1"), the timer stops counting during SLEEP status. When SLEEP status is canceled, the timer starts counting. However, the operation becomes unstable immediately after SLEEP status is canceled. Therefore, when shifting to SLEEP status, stop the 8-bit programmable timer (PRUN = "0") prior to executing the SLP instruction. (3) The prescaler, which supplies the clock to the 8-bit programmable timer, can operate only when the OSC3 oscillation has been set to ON. Be aware that the 8-bit programmable timer does not operate when the OSC3 oscillation circuit has been turned off. EPSON 199 CHAPTER 6: SUMMARY OF NOTES Serial interface SVD circuit (1) Setting of the serial interface mode must be done in the transmission/receiving disabling status (TXEN = RXEN = "0"). (1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 sec. So, to obtain the SVD detection result, follow the programming sequence below. (2) Do not perform double trigger (writing "1") to TXTRG (RXTRG) during transmission (receiving). Furthermore, do not execute the SLP instruction. (When executing the SLP instruction, set TXEN and RXEN to "0".) 1. 2. 3. 4. Set SVDON to "1" Maintain for 100 sec minimum Set SVDON to "0" Read SVDDT (3) Transmission and receiving cannot be done simultaneously in the clock synchronous mode because the clock line (SCLK) is shared with transmit and receive operation. Therefore, do not write "1" to RXTRG (TXTRG) when TXTRG (RXTRG) is "1". (2) The SVD operation increases current consumption, so turn the SVD circuit off when voltage detection is unnecessary or executing the SLP instruction. (4) When a parity error or a framing error occurs, both the receive error interrupt factor flag FSERR and the receive completion interrupt factor flag FSRX are simultaneously set to "1". However, since the receive error interrupt has priority over the receive completion interrupt, the receive error interrupt process is executed first. Therefore, it is necessary to reset the FSRX flag in the receive error handling routine. When a receive error interrupt occurs due to an overrun, receive completion interrupt does not occur. (1) The setting of the threshold value for drawing speed judgment in the normal mode must meet following conditions. MVH MVMH MVML MVL Sound generator (1) Since the BZ signal is generated asynchronously from the register BZON, when the signal is turned ON or OFF by the register setting, a hazard of a 1/2 cycle or less is generated. (2) The SLP instruction has executed when the BZ signal is in the enable status (BZON = "1" or BZSHT = "1"), an unstable clock is output from the R42 output port terminal at the time of return from the SLEEP status. Consequently, when shifting to the SLEEP status, you should set the BZ signal to the disable status (BZON = BZSHT = "0") prior to executing the SLP instruction. (3) The one-shot output is only valid when the normal buzzer output is OFF (BZON = "0") status. The trigger is invalid during ON (BZON = "1") status. 200 Touch panel controller (2) Do not stop the clocks output from the OSC3 oscillation circuit and prescaler during coordinate detection. (3) Do not operate the A/D converter independently while the touch panel controller is used. (4) The waiting time to be set using the WAIT register must be longer than 3 cycles of the OSC1 clock. 16 x n/f > 3/fOSC1 (f: Input clock frequency from the prescaler) When the A/D converter reference voltage control function is used (VRC = "1"), the time set in the WAIT register also applies to the reference voltage setup time. Therefore, design the peripheral circuit taking the charge time into consideration. If the reference voltage (AVREF) cannot be set up within the time set in the WAIT register, the reference voltage should be switched on and off by software so that the setup time is secured. (5) The capacitors connected to Ch0 and Ch1 of the touch panel controller (see Figure 5.17.2.1) affect the pen-down judgement time. They must be 1000 pF or less. EPSON S1C88409 TECHNICAL MANUAL CHAPTER 6: SUMMARY OF NOTES A/D converter Interrupt (1) The A/D converter can operate by inputting the clock from the prescaler. Therefore, it is necessary to set the division ratio of the prescaler and to turn the clock output on before starting A/D conversion. Furthermore, it is also necessary that the OSC3 oscillation circuit is operating because the prescaler can operate only when the OSC3 is set as the CPU clock. (Refer to Section 5.5, "Prescaler and Clock Control Circuit for Peripheral Circuits".) (1) When the RETE instruction is executed without resetting the interrupt factor flag after an interrupt has been generated, the same interrupt is generated again. Therefore, the interrupt factor flag must be reset (writing "1") in the interrupt handler routine. (2) When SLEEP mode is set during A/D conversion, correct A/D conversion result cannot be obtained because the OSC3 oscillation circuit stops. Do not set in SLEEP mode during A/D conversion. (3) The input clock and analog input terminals should be set when the A/D converter stops. Changing in the A/D converter operation may cause a malfunction. (2) Be aware if the interrupt flags (I0, I1) are rewritten (set to lower priority) prior to resetting the interrupt factor flag after an interrupt is generated, the same interrupt will be generated again. (3) An exception processing vector is fixed at 2 bytes, so it cannot specify a branch destination bank address. Therefore, to branch from two or more banks to a common exception handler routine, the top portion of the exception handler routine must be described within the common area (000000H-007FFFH). (4) The frequency of the input clock should be lower than the maximum value shown in Section 8.7, "A/D Converter Characteristics". (5) To prevent malfunction, do not start A/D conversion (writing to the CHS register) when the A/D conversion clock is not being output from the prescaler, and do not turn the prescaler output clock off during A/D conversion. (6) If the CHS register selects an input channel which is not included in the analog input terminals set by the PAD register (the PAD register can select several terminals simultaneously), the A/D conversion does not result in a correct converted value. (7) During A/D conversion, do not operate the P3n terminals which are not used for analog inputs of the A/D converter (for input/output of digital signal and for D/A conversion). It affects the A/D conversion precision. D/A converter The D/A converter should be operated only when it is necessary in order to reduce current consumption. Stop D/A conversion by writing "0" to the DAE register if unnecessary. S1C88409 TECHNICAL MANUAL EPSON 201 CHAPTER 6: SUMMARY OF NOTES <Reset Circuit> 6.3 Precautions on Mounting The power-on reset signal which is input to the RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When the built-in pull-up resistor is added to the RESET terminal by mask option, take into consideration dispersion of the resistance for setting the constant. <Oscillation Circuit> Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the RESET terminal in the shortest line. (1) Components which are connected to the OSC1, OSC2, OSC3, OSC4 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the right hand figure, make a VSS pattern as large as possible at circumscription of the OSC1, OSC2, OSC3, OSC4 terminals and the components connected to these terminals. Furthermore, do not use this VSS pattern for any purpose other than the oscillation system. Sample VSS pattern <Power Supply Circuit> Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD, VSS, AVDD, AVSS and AGND, AVREF terminals with patterns as short and large as possible. In particular, the power supply for AVDD, AVSS, AGND and AVREF affects A/D conversion and D/A conversion accuracy. (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. OSC4 OSC3 Bypass capacitor connection example VSS (3) When supplying an external clock to the OSC1 (OSC3) terminal, the clock source should be connected to the OSC1 (OSC3) terminal in the shortest line. Furthermore, do not connect anything else to the OSC2 (OSC4) terminal. VDD VDD VSS VSS In order to prevent unstable operation of the oscillation circuit due to current leak between OSC3 and VDD, please keep enough distance between OSC3 and VDD or other signals on the board pattern. 202 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 6: SUMMARY OF NOTES <A/D Converter, D/A Converter> <Precautions for Visible Radiation (when bare chip is mounted)> When the A/D converter and D/A converter are not used, the power supply terminals for the analog system should be connected as shown below. AVDD VDD AVSS VSS AVREF VSS AGND VSS Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this IC, consider the following precautions to prevent malfunctions caused by visible radiations. <Arrangement of Signal Lines> In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit. When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit. (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. Prohibited pattern OSC4 P30 (AD0) OSC3 Large current signal line High-speed signal line VSS Large current signal line High-speed signal line S1C88409 TECHNICAL MANUAL EPSON 203 CHAPTER 7: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 7 BASIC EXTERNAL WIRING DIAGRAM VSS AGND SD0-SD7 LCDEN DOFF YD FR XSCL LP LCD panel/driver AVSS K00-K07 K10-K13 CG1 Input OSC1 RCR X'tal1 OSC2 CG2 OSC3 X'tal2 or CR Rf OSC4 CD2 - C1 + S1C88409 VD1 RESET (D0-D7) P00-P07 (SIN) P10 (SOUT) P11 (SCLK) P12 (SRDY) P13 (SIN/IRI) P14 (SOUT/IRO) P15 (SCLK) P16 (SRDY) P17 (BYH, BYL, BXH, BXL) P20-P23 (AD0-AD5) P30-P35 (AD6/DA0, AD7/DA1) P36, P37 Cres + CP3 + CP2 + CP1 1.8-5.5 V VDD MCU/MPU TEST AVDD Coil (A00-A07) R00-R07 (A08-A15) R10-R17 (A16-A21) R20-R25 (RD) R26 (WR) R27 (CE0) R30 (CE1) R31 (CE2) R32 (TOUT0/FOUT3) R40 (TOUT1/FOUT1) R41 Output I/O BZ (R42) Piezo [The potential of the substrate (back of the chip) is VSS] AVREF Recommended values for external parts Symbol X'tal1 RCR X'tal2 CR Rf CG1 CG2 CD2 C 1-3 CP Cres 204 Name Crystal oscillator Resistor for CR oscillation Crystal oscillator Ceramic oscillator Feedback resistor Trimmer capacitor Gate capacitor Drain capacitor Capacitor between VSS and VD1 Capacitor for power supply Capacitor for RESET terminal Recommended value 32.768 kHz, CI(Max.) = 35 k 1.8 M 4, 6, 8 MHz 4, 6, 8 MHz 1 M 5-25 pF 15 pF 15 pF 0.1 F 3.3 F 0.47 F EPSON S1C88409 TECHNICAL MANUAL CHAPTER 8: ELECTRICAL CHARACTERISTICS CHAPTER 8 ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Rating Item Supply voltage Analog supply voltage Reference supply voltage Input voltage Output voltage High-level output current Symbol Condition VDD AVDD AVREF VI VO IOH 1 terminal Total of all terminals Low-level output current IOL 1 terminal Total of all terminals Operating temperature Topr Storage temperature Tstg Permissible disspation Ta=25C PD Note) 1. In case of plastic package. Rated value -0.3 to +7.0 -0.3 to +7.0 -0.3 to AVDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -5 -20 -5 -20 -20 to +70 -65 to +150 200 (VSS=0 V) Unit Note V V V V V mA mA mA mA C C mW 1 8.2 Recommended Operating Conditions (VSS=0 V) Symbol Condition Min. Typ. Max. Unit Note VDD 1.8 5.5 V AVDD AVDD2.7 V VDD-0.05 VDD+0.05 V fOSC1 VDD=1.8 to 5.5 V 30.000 32.768 50.000 kHz 1 fOSC3 VDD=1.8 to 5.5 V 0.03 1.1 MHz 1 VDD=2.6 to 5.5 V 0.03 4.4 MHz 1 VDD=3.5 to 5.5 V 0.03 6.6 MHz 1 VDD=4.5 to 5.5 V 0.03 8.8 MHz 1 Operating temperature Topr -20 +70 C Capacitor between VSS and VD1 C1 0.1 F Note) 1. When an external clock is input from the OSC1 terminal by setting the mask option, do not connect anything to the OSC2 terminal. When an external clock is input from the OSC3 terminal, do not connect anything to the OSC4 terminal. Item Supply voltage Analog supply voltage Clock frequency S1C88409 TECHNICAL MANUAL EPSON 205 CHAPTER 8: ELECTRICAL CHARACTERISTICS 8.3 DC Characteristics Unless otherwise specified: VDD=1.8 to 5.5 V, VSS=0 V, Ta=-20 to 70C Item High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level schmitt trigger input voltage Low-level schmitt trigger input voltage Schmitt trigger hysteresis voltage High-level output current Low-level output current Input leak current Input leak current Output leak current Input pull-up resistance Input terminal capacitance Note) 1. 2. 3. 4. 5. 6. 7. Symbol Condition VIH1 Pxx, MCU/MPU, Kxx VIL1 Pxx, MCU/MPU, Kxx VIH2 OSC1, OSC3, VD1 = 1.6V OSC1, OSC3, VD1 = 2.4V OSC1, OSC3, VD1 = 3.2V OSC1, OSC3, VD1 = 4.2V VIL2 OSC1, OSC3, VD1 = 1.6V OSC1, OSC3, VD1 = 2.4V OSC1, OSC3, VD1 = 3.2V OSC1, OSC3, VD1 = 4.2V VT+ RESET VT- Min. 0.8VDD 0 1.3 1.8 2.4 3.2 0 0 0 0 0.5VDD 0.1VDD RESET Typ. Max. VDD 0.2VDD VDD VDD VDD VDD 0.3 0.6 0.8 1.0 0.9VDD Unit V V V V V V V V V V V 0.5VDD V Note 1,3 1,4 1,5 1,6 1,3 1,4 1,5 1,6 VHS 0.2 RESET V VHS=VT+-VTIOH Pxx, Rxx, VOH=VDD-0.2 V -0.5 mA 7 Pxx, Rxx, VOL=0.2 V IOL 0.5 mA 7 ILI1 Kxx, Pxx, MCU/MPU, RESET 1 -1 A ILI2 OSC1, OSC3 1 -1 A 1 ILO Pxx, Rxx 1 -1 A RIN Kxx, Pxx, MCU/MPU, RESET 500 100 k 2 CIN Kxx, Pxx 15 pF VIN=0 V, =1 MHz, Ta=25C When external clock is selected by mask option. When pull-up resistor is added by mask option. Low-power mode (VD1C1 = "0", VD1C0 = "1") Normal mode (VD1C1 = "0", VD1C0 = "0") High-speed mode 1 (VD1C1 = "1", VD1C0 = "0") High-speed mode 2 (VD1C1 = "1", VD1C0 = "1") Characteristics when only one terminal is driven. If two or more terminals are driven simultaneously, the characteristics had happen to reduced because the VOH and VOL voltages drop due to the parasitic resistance on the power line in the IC. VOUT [V] VDD 0 VT- VT+ VDD VIN [V] 206 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 8: ELECTRICAL CHARACTERISTICS 8.4 Analog Circuit Characteristics and Current Consumption Unless otherwise specified: VDD=1.8 to 5.5 V, VSS=0 V, Ta=25C, OSC1=32.768 kHz crystal oscillation, OSC3=external clock input Symbol Condition Min. SVD voltage VSVD SVD1="1", SVD0=X 3.05 SVD1="0", SVD0="1" 2.55 SVD1="0", SVD0="0" 1.7 SVD circuit response time tSVD Power current In SLEEP status IDD1 Low-power mode IDD2 In HALT status VD1C1="0", VD1C0="1" CPU is in operating (32.768 kHz) IDD3 IDD4 CPU is in operating (1 MHz) Power current In SLEEP status IDD1 IDD2 Normal mode In HALT status VD1C1="0", VD1C0="0" CPU is in operating (32.768 kHz) IDD3 IDD4 CPU is in operating (1 MHz) Power current In SLEEP status IDD1 IDD2 High-speed mode 1 In HALT status VD1C1="1", VD1C0="0" CPU is in operating (32.768 kHz) IDD3 IDD4 CPU is in operating (1 MHz) Power current In SLEEP status IDD1 IDD2 High-speed mode 2 In HALT status VD1C1="1", VD1C0="1" CPU is in operating (32.768 kHz) IDD3 IDD4 CPU is in operating (1 MHz) SVD circuit current ISVDN VDD=5.0 V ICR1 OSC1 CR oscillation current RCR=1.5 M, normal mode Note) 1. OSC1: Stop OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Stop 2. OSC1: On OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Run 3. OSC1: On OSC3: Stop CPU, ROM, RAM: Run Clock Timer: Run 4. OSC1: On OSC3: On CPU, ROM, RAM: Run Clock Timer: Run 5. OSC1: On OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Run 6. When the OSC1 CR oscillation circuit is selected by mask option. Item S1C88409 TECHNICAL MANUAL EPSON Typ. 3.4 2.8 1.9 0.45 1.8 9.0 0.3 0.55 3.0 14.0 0.45 0.65 5.0 21.0 0.65 0.75 9.0 32.0 0.9 7 20 SVD: Off SVD: Off SVD: Off SVD: Off SVD: On Max. Unit Note 3.75 V 3.05 V 2.1 V 100 s 1.0 A 1 5.0 A 2 20.0 A 3 0.5 mA 4 1.5 A 1 7.0 A 2 25.0 A 3 0.7 mA 4 2.0 A 1 12.0 A 2 35.0 A 3 1.0 mA 4 3.0 A 1 20.0 A 2 50.0 A 3 1.4 mA 4 15 A 5 50 A 6 Others: Stop Others: Stop Others: Stop Others: Stop Others: Stop 207 CHAPTER 8: ELECTRICAL CHARACTERISTICS 8.5 AC Characteristics 8.5.1 External memory access Read cycle Unless otherwise specified: VDD=5.5 V, VSS=0 V, fOSC1=32.768 kHz, fOSC3=1.0 MHz, Ta=-20 to 70C, CL=100 pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD Item Symbol Condition Min. tras VDD=1.8 to 5.5 V tc+tl-200+n*tc/2 Address set-up time in read cycle trah VD1=1.6 V th-160 Address hold time in read cycle trp tc-40+n*tc/2 Read signal pulse width 600 Data input set-up time in read cycle trds trdh 0 Data input hold time in read cycle tras VDD=2.6 to 5.5 V tc+tl-100+n*tc/2 Address set-up time in read cycle trah VD1=2.4 V th-80 Address hold time in read cycle trp tc-20+n*tc/2 Read signal pulse width 300 Data input set-up time in read cycle trds trdh 0 Data input hold time in read cycle tras VDD=3.5 to 5.5 V tc+tl-50+n*tc/2 Address set-up time in read cycle trah VD1=3.2 V th-40 Address hold time in read cycle trp tc-10+n*tc/2 Read signal pulse width 150 Data input set-up time in read cycle trds trdh 0 Data input hold time in read cycle tras VDD=4.5 to 5.5 V tc+tl-50+n*tc/2 Address set-up time in read cycle trah VD1=4.2 V th-40 Address hold time in read cycle trp tc-10+n*tc/2 Read signal pulse width 150 Data input set-up time in read cycle trds trdh 0 Data input hold time in read cycle tc=input clock cycle time, th=input clock H pulse width, tl=input clock L pulse width Note) 1. Substitute the number of states for wait insertion in n. Typ. - - - - - - - - - - - - - - - - - - - - Max. - - - - - - - - - - - - - - - - - - - - Unit Note ns 1 ns ns 1 ns ns ns 1 ns ns 1 ns ns ns 1 ns ns 1 ns ns ns 1 ns ns 1 ns ns tc * VIH ICLK VIL th * A00-A21 CE tl * VOH VOL tras RD trah VOH VOL trp trds trdh VIH VIL DIN In the case of crystal or ceramic oscillation: th=0.5tc0.05tc, tl=tc-th In the case of CR oscillation: th=0.5tc0.10tc, tl=tc-th (1/tc: oscillation frequency) 208 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 8: ELECTRICAL CHARACTERISTICS Write cycle Unless otherwise specified: VDD=5.5 V, VSS=0 V, fOSC1=32.768 kHz, fOSC3=1.0 MHz, Ta=-20 to 70C, CL=100 pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD Item Symbol Condition Min. Address set-up time in write cycle twas VDD=1.8 to 5.5 V tc-360 Address hold time in write cycle twah VD1=1.6 V th-160 twp tl-80+n*tc/2 Write signal pulse width Data output set-up time in write cycle twds tc-360+n*tc/2 Data output hold time in write cycle twdh th-160 Address set-up time in write cycle twas VDD=2.6 to 5.5 V tc-180 Address hold time in write cycle twah VD1=2.4 V th-80 twp tl-40+n*tc/2 Write signal pulse width Data output set-up time in write cycle twds tc-180+n*tc/2 Data output hold time in write cycle twdh th-160 Address set-up time in write cycle twas VDD=3.5 to 5.5 V tc-90 Address hold time in write cycle twah VD1=3.2 V th-40 Write signal pulse width twp tl-20+n*tc/2 Data output set-up time in write cycle twds tc-90+n*tc/2 Data output hold time in write cycle twdh th-160 Address set-up time in write cycle twas VDD=4.5 to 5.5 V tc-90 Address hold time in write cycle twah VD1=4.2 V th-40 Write signal pulse width twp tl-20+n*tc/2 Data output set-up time in write cycle twds tc-90+n*tc/2 Data output hold time in write cycle twdh th-160 tc=input clock cycle time, th=input clock H pulse width, tl=input clock L pulse width Note) 1. Substitute the number of states for wait insertion in n. Typ. - - - - - - - - - - - - - - - - - - - - Max. - - - - th+160 - - - - th+160 - - - - th+160 - - - - th+160 Unit Note ns ns ns 1 ns 1 ns ns ns ns 1 ns 1 ns ns ns ns 1 ns 1 ns ns ns ns 1 ns 1 ns tc * VIH ICLK VIL th * A00-A21 CE tl * VOH VOL twas twah VOH VOL WR twp twdh twds DIN VIH VIL In the case of crystal or ceramic oscillation: th=0.5tc0.05tc, tl=tc-th In the case of CR oscillation: th=0.5tc0.10tc, tl=tc-th (1/tc: oscillation frequency) S1C88409 TECHNICAL MANUAL EPSON 209 CHAPTER 8: ELECTRICAL CHARACTERISTICS 8.5.2 Serial interface Clock synchronous master mode Unless otherwise specified: VDD=5.5 V, VSS=0 V, fOSC1=32.768 kHz, fOSC3=100 kHz, Ta=-20 to 70C, CL=100 pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD Item Symbol Condition Min. Transmit data output delay time tsmd VDD=1.8 to 5.5 V - Receive data input set-up time tsms VD1=1.6 V 1000 Receive data input hold time tsmh 400 Transmit data output delay time - tsmd VDD=2.6 to 5.5 V Receive data input set-up time tsms VD1=2.4 V 500 Receive data input hold time 200 tsmh Transmit data output delay time tsmd VDD=3.5 to 5.5 V - Receive data input set-up time 250 tsms VD1=3.2 V Receive data input hold time 100 tsmh Transmit data output delay time - tsmd VDD=4.5 to 5.5 V Receive data input set-up time 250 tsms VD1=4.2 V tsmh Receive data input hold time 100 SCLK OUT Typ. - - - - - - - - - - - - Max. 400 - - 200 - - 100 - - 100 - - Unit Note ns ns ns ns ns ns ns ns ns ns ns ns VOH VOL tsmd SOUT VOH VOL tsms SIN tsmh VIH VIL OSC3 SCLK OUT VOH VOL tscd tscd Clock synchronous slave mode Unless otherwise specified: VDD=5.5 V, VSS=0 V, fOSC1=32.768 kHz, fOSC3=100 kHz, Ta=-20 to 70C, CL=100 pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD Item Symbol Condition Min. Transmit data output delay time tssd VDD=1.8 to 5.5 V - Receive data input set-up time 400 tsss VD1=1.6 V Receive data input hold time 400 tssh SCKIN=100 kHz Transmit data output delay time tssd VDD=2.6 to 5.5 V - Receive data input set-up time tsss VD1=2.4 V 200 Receive data input hold time tssh SCKIN=100 kHz 200 Transmit data output delay time - tssd VDD=3.5 to 5.5 V Receive data input set-up time 100 tsss VD1=3.2 V Receive data input hold time 100 tssh SCKIN=100 kHz Transmit data output delay time - tssd VDD=4.5 to 5.5 V Receive data input set-up time 100 tsss VD1=4.2 V Receive data input hold time tssh SCKIN=100 kHz 100 210 EPSON Typ. - - - - - - - - - - - - Max. 1000 - - 500 - - 250 - - 250 - - Unit Note ns ns ns ns ns ns ns ns ns ns ns ns S1C88409 TECHNICAL MANUAL CHAPTER 8: ELECTRICAL CHARACTERISTICS SCLK IN VIH VIL tssd VOH VOL SOUT tsss tssh VIH VIL SIN tsccy SCLK IN tsch tckf VIH VIL tckr tscl Asynchronous mode Unless otherwise specified: VDD=1.8 to 5.5 V, VSS=0 V, Ta=-20 to 70C, VIH=0.7VDD, VIL=0.3VDD, VOH=0.7VDD, VOL=0.3VDD Item Start bit detection error time Erroneous start bit detection range time Symbol Condition tsa1 tsa2 Min. Typ. Max. 0 - t/16 Unit Note s 1 8t/16 - 9t/16 s 2 Note) 1. Start bit detection error time is a logical delay time from inputting a start bit until the internal sampling starts operating. (AC time is not included.) 2. Erroneous start bit detection range time is a logical time from starting sampling clock (detecting a start bit) until the start bit is detected again whether a low level (start bit) has still been input. When a high level is detected, the start bit detection circuit is reset and goes into a start bit waiting status. (AC time is not included.) Start bit Stop bit SIN tsa1 Sampling clock t Erroneous start bit detection signal S1C88409 TECHNICAL MANUAL tsa2 EPSON 211 CHAPTER 8: ELECTRICAL CHARACTERISTICS 8.5.3 Input clock OSC1, OSC3 external clock Unless otherwise specified: VSS=0 V, Ta=-20 to 70C Item OSC1 input clock time Cycle time "H" pulse width "L" pulse width OSC3 input clock time Cycle time "H" pulse width "L" pulse width Input clock rising time Input clock falling time OSC1 input clock time Cycle time "H" pulse width "L" pulse width OSC3 input clock time Cycle time "H" pulse width "L" pulse width Input clock rising time Input clock falling time OSC1 input clock time Cycle time "H" pulse width "L" pulse width OSC3 input clock time Cycle time "H" pulse width "L" pulse width Input clock rising time Input clock falling time OSC1 input clock time Cycle time "H" pulse width "L" pulse width OSC3 input clock time Cycle time "H" pulse width "L" pulse width Input clock rising time Input clock falling time Symbol to1cy to1h to1l to3cy to3h to3l tosr tosf to1cy to1h to1l to3cy to3h to3l tosr tosf to1cy to1h to1l to3cy to3h to3l tosr tosf to1cy to1h to1l to3cy to3h to3l tosr tosf Condition VDD=1.8 to 5.5 V VD1=1.6 V VIH=1.3 V VIL=0.3 V VDD=2.6 to 5.5 V VD1=2.4 V VIH=1.8 V VIL=0.6 V VDD=3.5 to 5.5 V VD1=3.2 V VIH=2.4 V VIL=0.8 V VDD=4.5 to 5.5 V VD1=4.2 V VIH=3.2 V VIL=1.0 V Min. 20 10 10 1000 500 500 - - 20 10 10 240 120 120 - - 20 10 10 155 77.5 77.5 - - 20 10 10 115 57.5 57.5 - - Typ. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Max. 32 16 16 32000 16000 16000 25 25 32 16 16 32000 16000 16000 25 25 32 16 16 32000 16000 16000 25 25 32 16 16 32000 16000 16000 25 25 Unit Note s s s ns ns ns ns ns s s s ns ns ns ns ns s s s ns ns ns ns ns s s s ns ns ns ns ns Max. - Unit Note s to1cy OSC1 to1h tosf VIH VIL tosr to1l to3cy OSC3 to3h tosf VIH VIL tosr to3l RESET input clock Unless otherwise specified: VDD=1.8 to 5.5 V, VSS=0 V, Ta=-20 to 70C, VIH=0.5VDD, VIL=0.1VDD Item RESET pulse width Symbol Condition Min. 100 tsr Typ. - tsr RESET 212 VIH VIL EPSON S1C88409 TECHNICAL MANUAL CHAPTER 8: ELECTRICAL CHARACTERISTICS 8.5.4 LCD controller Unless otherwise specified: VDD=5.5 V, VSS=0 V, fOSC1=32.768 kHz, fOSC3=2.0 MHz, Ta=-20 to 70C, CL=100 pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD Item Symbol Condition Min. Typ. Max. Unit Note tc-360 XSCL H-level pulse width (B&W, 4 bits) tHXS(1) VDD=1.8 to 5.5 V - - ns tc-tl-360 XSCL H-level pulse width (gray, 4 bits) tHXS(2) VD1=1.6 V - - ns tLPXS 6*tc-360 LP falling edge to XSCL rising edge - - ns LCD data setup time tDS tc-360 - - ns tDH tc-360 LCD data hold time - - ns YD H-level pulse width - - s tHYD tc(fOSC1)-3 tHLP tl(fOSC1)-1.5 LP H-level pulse width - - s tYDLPL tl(fOSC1)-1.5 YD setup time - - s tLPYD th(fOSC1)-1.5 YD hold time - - s tLPFR -300 FR change from LP falling edge - 300 ns XSCL H-level pulse width (B&W, 4 bits) tHXS(1) VDD=2.6 to 5.5 V - - ns tc-180 XSCL H-level pulse width (gray, 4 bits) tHXS(2) VD1=2.4 V tc-tl-180 - - ns tLPXS LP falling edge to XSCL rising edge 6*tc-180 - - ns LCD data setup time - - ns tDS tc-180 LCD data hold time - - ns tDH tc-180 YD H-level pulse width - - s tHYD tc(fOSC1)-3 tHLP tl(fOSC1)-1.5 LP H-level pulse width - - s YD setup time - - s tYDLPL tl(fOSC1)-1.5 YD hold time - - s tLPYD th(fOSC1)-1.5 FR change from LP falling edge tLPFR - 200 ns -200 XSCL H-level pulse width (B&W, 4 bits) tHXS(1) VDD=3.5 to 5.5 V - - ns tc-90 XSCL H-level pulse width (gray, 4 bits) tHXS(2) VD1=3.2 V - - ns tc-tl-90 LP falling edge to XSCL rising edge - - ns 6*tc-90 tLPXS LCD data setup time tDS tc-90 - - ns LCD data hold time - - ns tDH tc-90 YD H-level pulse width - - s tHYD tc(fOSC1)-3 LP H-level pulse width - - s tHLP tl(fOSC1)-1.5 YD setup time - - s tYDLPL tl(fOSC1)-1.5 YD hold time - - s tLPYD th(fOSC1)-1.5 FR change from LP falling edge - 100 ns tLPFR -100 XSCL H-level pulse width (B&W, 4 bits) tHXS(1) VDD=4.5 to 5.5 V - - ns tc-90 XSCL H-level pulse width (gray, 4 bits) tHXS(2) VD1=4.2 V - - ns tc-tl-90 LP falling edge to XSCL rising edge - ns tLPXS 6*tc-90 LCD data setup time - ns tDS tc-90 LCD data hold time - ns tDH tc-90 YD H-level pulse width - s tHYD tc(fOSC1)-3 LP H-level pulse width - s tHLP tl(fOSC1)-1.5 YD setup time - s tYDLPL tl(fOSC1)-1.5 YD hold time - s tLPYD th(fOSC1)-1.5 FR change from LP falling edge 100 ns -100 tLPFR tc=OSC3 clock cycle time, th=OSC3 clock H pulse width, tl=OSC3 clock L pulse width, tc(fOSC1)=OSC1 clock cycle time th(fOSC1)=OSC1 clock H pulse width, tl(fOSC1)=OSC1 clock L pulse width FR tHYD YD tYDLPL tHLP tLPYD tLPFR LP tLPXS tHXS XSCL tDS tDH SD0-SD3 S1C88409 TECHNICAL MANUAL EPSON 213 CHAPTER 8: ELECTRICAL CHARACTERISTICS 8.5.5 Power-on reset Unless otherwise specified: VSS=0 V, Ta=-20 to 70C Item Operating voltage RESET input width Symbol Vsr Condition Min. 2.6 10 tpsr Typ. - - Max. - - Unit Note V ms Vsr VDD tpsr 0.5VDD RESET 0.1VDD Power ON VDD *2 *1 RESET VSS *1 When the built-in pull up resistor is not used. *2 Because the potential of the RESET terminal not reached VDD level or higher. 8.5.6 Switching operating mode Unless otherwise specified: VDD=1.8 to 5.5 V, VSS=0 V, Ta=-20 to 70C Item Symbol Condition Min. Typ. Max. Unit Note Stabilization time tvdc 5 - - ms 1 Note) 1. Stabilization time is the time from switching on the operating mode until operating mode is stabilized. For example, when turning the OSC3 oscillation circuit on, stabilization time is needed after the operating mode is switched on. 214 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 8: ELECTRICAL CHARACTERISTICS 8.6 Oscillation Characteristics Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following characteristics as reference values. In particular, when a ceramic oscillator or crystal oscillator is used for OSC3, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. The oscillation start time is important because it becomes the waiting time when OSC3 clock is used. (If OSC3 is used as CPU clock before oscillation stabilizes, the CPU may malfunction.) OSC1 crystal oscillation Unless otherwise specified: VDD=1.8 to 5.5 V, VSS=0 V, Ta=25C, Crystal oscillator=Q12C2(made by Seiko Epson corporation), CG1=25 pF(External), CD1=Built-in Item Symbol Condition Min. Typ. Max. Unit Note Oscillation start time 3 s tsta External gate capacitance Including board capacitance 5 25 pF 1 CG1 Built-in drain capacitance In case of the chip 15 pF CD1 Frequency/IC deviation -10 10 ppm f/IC VDD=constant 1 Frequency/supply voltage deviation f/V ppm/V 25 Frequency adjustment range ppm f/CG VDD=constant, CG=5 to 25 pF 20 ppm Frequency/operating mode deviation f/MD VDD=constant Note) 1. When crystal oscillation is selected by mask option. OSC1 CR oscillation Unless otherwise specified: VDD=1.8 to 5.5 V, VSS=0 V, Ta=25C, RCR=1.8 M Item Oscillation start time Frequenct/IC deviation Symbol Condition Min. Typ. tsta f/IC RCR=constant -25 Max. 3 25 Unit Note ms % OSC3 crystal oscillation Unless otherwise specified: VDD=2.6/3.5/4.5 to 5.5 V, VSS=0 V, Ta=25C, Crystal oscillator=Q21CA301xxx(made by Seiko Epson corporation), RF=1 M, CG2=CD2=15 pF Item Symbol Condition Min. Typ. Oscillation start time tsta Note) 1. The crystal oscillation start time changes by the crystal oscillator to be used, CG2 and CD2. Max. 20 Unit Note ms 1 OSC3 ceramic oscillation Unless otherwise specified: VDD=2.6/3.5/4.5 to 5.5 V, VSS=0 V, Ta=25C, Ceramic oscillator=CSA4.00MG/CSA8.00MTZ(made Item Oscillation start time by Murata Mfg. corporation), RF=1 M, CG2=CD2=30 pF Symbol Condition Min. Typ. Max. 5 Unit Note ms Typ. Max. 1 25 Unit Note ms % tsta OSC3 CR oscillation Unless otherwise specified: VDD=2.6/3.5/4.5 to 5.5 V, VSS=0 V, Ta=25C Item Oscillation start time Frequenct/IC deviation S1C88409 TECHNICAL MANUAL Symbol Condition Min. tsta f/IC RCR=constant -25 EPSON 215 CHAPTER 8: ELECTRICAL CHARACTERISTICS OSC1 CR oscillation characteristics (for reference) CRoscillation frequency fOSC1 [kHz] 100 VD1 = 4.2V VD1 = 3.2V VD1 = 2.4V VD1 = 1.6V 10 1 100 1000 10000 CR oscillatiing resistor value RCR [k] OSC3 CR oscillation characteristics (for reference) 100000 VD1 = 4.2V VD1 = 3.2V VD1 = 2.4V VD1 = 1.6V CR oscillation frequency fOSC3 [kHz] 10000 1000 100 10 1 1 10 100 1000 10000 CR oscillatiing resistor value RCR [k] 216 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 8: ELECTRICAL CHARACTERISTICS 8.7 A/D Converter Characteristics The following characteristics apply to the plastic package model only. Unless otherwise specified: VDD=AVDD=AVREF=5.0 V, VSS=AVSS=AGND=0 V, fOSC1=32.768 kHz, fOSC3=4.0 MHz, Ta=25C Item Zero-scale error Full-scale error Non-linearity error Total error A/D converter current consumption Symbol Condition Min. Typ. Max. Unit Note Ezs VDD=AVDD=AVREF=2.7 to 5.5V, AVSS=0V, -1.50 - 1.50 LSB Efs -1.50 - 1.50 LSB ADCLK=2MHz, Ta=25C El -1.50 - 1.50 LSB Et -3.00 - 3.00 LSB IAD - 0.50 1.00 mA VDD=AVDD=AVREF=3.0V, ADCLK=2MHz, Ta=25C AVREF and ADCLK divider current not included VDD=AVDD=AVREF=5.0V, ADCLK=2MHz, Ta=25C - 1.80 3.50 mA AVREF and ADCLK divider current not included VDD=AVDD=AVREF=2.7 to 5.5 V, Ta=25C Input clock frequency f - 2 4 MHz * Zero-scale error: Ezs = deviation from the ideal value at zero point * Full-scale error: Efs = deviation from the ideal value at the full scale point * Non-linearity error: El = deviation of the real conversion curve from the end point line * Total error: Et = max(Ezs, Efs, Eabs), Eabs = deviation from the ideal line (including quantization error) 8.8 D/A Converter Characteristics The following characteristics apply to the plastic package model only. Unless otherwise specified: VDD=AVDD=AVREF=5.0 V, VSS=AVSS=AGND=0 V, fOSC1=32.768 kHz, fOSC3=1.0 MHz, Ta=25C Item D/A conversion speed Condition Min. Typ. Max. VDD=AVDD=AVREF=VD1=5.5 V - - 10 Load capacitance=parasitic capacitance only VDD=AVDD=AVREF=VD1=5.5 V - - 30 Load capacitance=100 pF+parasitic capacitance Integral linearity error ElDA VDD=AVDD=VD1=AVREF=3.0 V, -1.50 - 1.50 IL=1 A, Ta=-20 to 70C VDD=AVDD=VD1=AVREF=5.0 V, -1.50 - 1.50 IL=1 A, Ta=-20 to 70C Differential linearity error EdDA VDD=AVDD=VD1=AVREF=3.0 V, -1.00 - 1.00 IL=1 A, Ta=-20 to 70C VDD=AVDD=VD1=AVREF=5.0 V, -1.00 - 1.00 IL=1 A, Ta=-20 to 70C Total error EtDA VDD=AVDD=VD1=AVREF=3.0V, -2.50 - 2.50 IL=1A, Ta=-20 to 70C VDD=AVDD=VD1=AVREF=5.0V, -2.50 - 2.50 IL=1A, Ta=-20 to 70C D/A converter IDA VDD=AVDD=AVREF=3.0V, Ta=25C, 55H output - 0.35 1 current consumption Reference resistor current not included VDD=AVDD=AVREF=5.5V, Ta=25C, 55H output - 0.7 2 Reference resistor current not included * Integral linearity error: ElDA = difference between the real conversion characteristic and the end point line * Differential linearity error: EdDA = difference between the real step width and the ideal step width * Total error: EtDA = max(Ezs, Efs, Eabs) Eabs = deviation from the ideal line (including quantization error) Ezs = deviation from the ideal value at zero point (zero-scale error) Efs = deviation from the ideal value at the full scale point (full-scale error) S1C88409 TECHNICAL MANUAL Symbol tDA EPSON Unit Note s s LSB LSB LSB LSB LSB LSB mA mA 217 CHAPTER 9: PACKAGE CHAPTER 9 PACKAGE 9.1 Plastic Package QFP15-100pin (Unit: mm) 160.4 140.1 75 51 160.4 50 140.1 76 INDEX 100 26 1.40.1 25 0.5 +0.1 0.18 -0.05 +0.05 0.125 -0.025 0 10 0.50.2 0.1 1.7max 1 1 Note: The dimensions are subject to change without notice. 218 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 9: PACKAGE 9.2 Ceramic Package for Test Samples (Unit: mm) 17.00 0.30 12.00Typ. 100 76 75 25 51 13.97 0.15 1 26 50 0.50Typ. GLASS S1C88409 TECHNICAL MANUAL 0.20 0.38 0.08 0.95 0.08 2.54Max. 0.76 0.13 0.50 EPSON CERAMIC 0.82 0.30 219 CHAPTER 10: PAD LAYOUT CHAPTER 10 PAD LAYOUT 10.1 Diagram of Pad Layout 30 25 20 15 10 1 5 108 31 105 35 100 X (0, 0) 7.58 mm Y 40 45 95 50 90 55 85 56 60 65 70 75 81 80 Die No. 6.47 mm Chip thickness: 400 m Pad opening: 100 m (PAD No. 1-80, 84-108) 60 m (PAD No. 81-83) 220 EPSON S1C88409 TECHNICAL MANUAL CHAPTER 10: PAD LAYOUT 10.2 Pad Coordinates Table 10.2.1 Pad coordinate No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Pad name MCU/MPU K00 K01 K02 K03 K04 K05 K06 K07 K10/EXCL00 K11/EXCL11 K12 K13 RESET P00/D0 P01/D1 P02/D2 P03/D3 P04/D4 P05/D5 P06/D6 P07/D7 R00/A0 R01/A1 R02/A2 N.C. N.C. N.C. N.C. N.C. R03/A3 R04/A4 R05/A5 R06/A6 R07/A7 R10/A8 R11/A9 R12/A10 R13/A11 R14/A12 R15/A13 R16/A14 R17/A15 R20/A16 R21/A17 R22/A18 R23/A19 R24/A20 R25/A21 R26/RD R27/WR R30/CE0 R31/CE1 R32/CE2 X 2,143 1,943 1,793 1,593 1,443 1,293 1,143 993 843 693 543 393 243 93 -80 -230 -380 -530 -680 -830 -990 -1,150 -1,330 -1,530 -1,790 -2,146 -2,306 -2,466 -2,616 -2,776 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 Y 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 2,131 1,865 1,412 1,259 1,106 953 800 647 494 341 188 35 -118 -271 -424 -577 -730 -883 -1,036 -1,189 -1,342 -1,495 -1,648 -1,798 No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pad name R40/TOUT0/FOUT3 R41/TOUT1/FOUT1 R42/BZ P10/SIN P11/SOUT P12/SCLK P13/SRDY P14/SIN/IRI P15/SOUT/IRO P16/SCLK P17/SRDY P20/BYH P21/BYL P22/BXH P23/BXL TEST P37/AD7/DA1 P36/AD6/DA0 P35/AD5 P34/AD4 P33/AD3 P32/AD2 P31/AD1 P30/AD0 AVDD AVSS N.C. N.C. N.C. AVREF AGND N.C. N.C. SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 LP XSCL FR YD DOFF LCDEN VDD OSC4 OSC3 VD1 OSC2 OSC1 VSS X -3,107 -2,069 -1,869 -1,689 -1,519 -1,369 -1,219 -1,069 -919 -769 -619 -469 -319 -169 -19 131 281 431 582 732 882 1,032 1,232 1,432 1,632 1,882 3,127 3,127 3,127 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 Y -2,100 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,390 -3,137 -2,870 -2,600 -2,400 -2,173 -2,018 -1,863 -1,708 -1,553 -1,398 -1,243 -1,088 -933 -774 -610 -463 -259 -88 92 262 1,313 1,495 1,650 1,805 1,987 2,148 2,318 (Unit: m) S1C88409 TECHNICAL MANUAL EPSON 221 APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER APPENDIX CONTROLLING THE TOUCH PANEL CONTROLLER A.1 I/O Map Table A.1.1(a) Touch panel I/O map Address Bit 00FF13 D7 D6 D5 D4 D3 D2 D1 D0 00FF16 D7 D6 D5 D4 D3 D2 D1 D0 00FF22 D7 D6 D5 D4 D3 D2 D1 D0 00FF26 D7 D6 D5 D4 D3 D2 D1 D0 00FF2A D7 D6 D5 D4 D3 D2 D1 D0 222 Name - - - - PRAD PSAD2 Function - - - - A/D converter clock control A/D converter division ratio PSAD2 PSAD1 PSAD0 Division ratio 1 x x fOSC3 / 16 PSAD1 0 1 1 fOSC3 / 8 fOSC3 / 4 0 1 0 PSAD0 fOSC3 / 2 0 0 1 fOSC3 / 1 0 0 0 - - - - - - - - PRTP Touch panel controller clock control PSTP2 Touch panel controller clock ratio PSTP2 PSTP1 PSTP0 Division ratio 1 x x fOSC3 / 16 PSTP1 1 1 0 fOSC3 / 8 1 0 fOSC3 / 4 0 PSTP0 fOSC3 / 2 0 1 0 fOSC3 / 1 0 0 0 PAD1 A/D converter PAD0 interrupt priority register PTP1 Touch panel controller PTP0 interrupt priority register - - - - - - - - EAD A/D converter conversion completion interrupt enable register ETPPD Touch panel controller pen-down interrupt enable register ETPDR Touch panel controller converted data update interrupt enable register - - - - - - - - - - FAD A/D converter conversion completion interrupt factor flag FTPPD Touch panel controller pen-down interrupt factor flag FTPDR Touch panel controller converted data update interrupt factor flag - - - - - - - - - - EPSON 1 - - - - On 0 - - - - Off Init R/W Comment - - "0" when being read - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W - - - - On - - - - Off - - "0" when being read - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W PAD1 PTP1 1 1 0 0 PAD0 PTP0 1 0 1 0 Priority level Level 3 Level 2 Level 1 Level 0 0 0 0 0 - - - - 0 R/W R/W R/W R/W - "0" when being read - - - R/W 0 R/W Interrupt is enabled Interrupt is disabled (R) Interrupt factor has generated (R) Interrupt factor has not generated (W) Reset (W) Invalid 0 R/W - - "0" when being read - - - - - - - - 0 R/W 0 R/W 0 R/W - - - - - - - - - - "0" when being read S1C88409 TECHNICAL MANUAL APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER Table A.1.1(b) Touch panel I/O map Address Bit 00FF80 D7 D6 D5 D4 D3 D2 D1 D0 00FFA0 D7 D6 D5 D4 D3 D2 D1 D0 00FFA1 D7 D6 D5 D4 D3 Name ADRUN - - VRC VRO CHS2 Function A/D conversion start control register - - AVREF control (Touch pamel controller) AVREF swich Analog input channel selection CHS2 CHS1 CHS0 Input channel 1 1 1 AD7 1 1 0 AD6 CHS1 1 0 1 AD5 1 0 0 AD4 0 1 1 AD3 CHS0 0 1 0 AD2 0 0 1 AD1 0 0 0 AD0 - - PDC Pen-down check control RST TPC circuit reset control CONST Mode setting - - AVN2 Mean count setting Mean count AVN2 AVN1 AVN0 0 0 16 x 16 0 AVN1 0 1 16 x 8 0 1 0 16 x 4 0 AVN0 1 1 16 x 2 0 x x 16 x 1 1 - - - - - - - - WAIT3 Voltage stabilization waiting time setting D2 WAIT2 D1 WAIT1 D0 WAIT0 00FFA2 D7 D6 D5 D4 D3 - - - - CND3 D2 CND2 D1 CND1 D0 CND0 WAIT3 WAIT2 WAIT1 WAIT0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 S1C88409 TECHNICAL MANUAL CND2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CND1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CND0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - Check Cancel Constant-speed - - - - - 0 Invalid - - Invalid Off - Cancel Reset Normal - - - - - Waiting time 16 x 1/f 16 x 2/f 16 x 3/f 16 x 4/f 16 x 5/f 16 x 6/f 16 x 7/f 16 x 8/f 16 x 9/f 16 x 10/f 16 x 11/f 16 x 12/f 16 x 13/f 16 x 14/f 16 x 15/f 16 x 16/f - - - - Noise judgment threshold value setting CND3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Start - - Enable On - - - - Value 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 EPSON - - - - Init 0 - - 0 0 0 R/W Comment W "0" when being read - - R/W R/W R/W 0 R/W 0 R/W - 0 0 0 - 0 - R/W R/W R/W - R/W 0 R/W 0 R/W - - - - 0 - "0" when being read - - - R/W 1 R/W 0 R/W 0 R/W - - - - 1 - "0" when being read - - - R/W 0 R/W 0 R/W 0 R/W "0" when being read Valid when "RST=0" "0" when being read Invalid when Normal mode 223 APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER Table A.1.1(c) Touch panel I/O map Address Bit 00FFA3 D7 D6 D5 D4 D3 D2 PUD2 D1 PUD1 D0 PUD0 00FFA4 D7 224 Name - - - - PUD3 Function - - - - Pen-up decision threshold value setting PUD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PUD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PUD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PUD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 - - - - Value 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 MVML3 Middle-low-speed judgment threshold value setting D6 MVML2 D5 MVML1 D4 MVML0 D3 MVL3 D2 MVL2 D1 MVL1 D0 MVL0 MVML3 MVML2 MVML1 MVML0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Value 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Low-speed judgment threshold value setting MVL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MVL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MVL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MVL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Value 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 EPSON 0 - - - - Init R/W Comment - - "0" when being read - - - - - - 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 1 R/W MVMLMVL 0 R/W 0 R/W 0 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 0 R/W MVMLMVL 1 R/W 0 R/W S1C88409 TECHNICAL MANUAL APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER Table A.1.1(d) Touch panel I/O map Address Bit 00FFA5 D7 Name MVH3 D6 MVH2 D5 MVH1 D4 MVH0 D3 D2 D1 D0 00FFA6 D7 D6 D5 D4 D3 Function High-speed judgment threshold value setting MVH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MVH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MVH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MVH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 Value 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 R/W 0 R/W MVMH3 Middle-high-speed judgment threshold value setting 0 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 1 R/W MVMLMVL MVMH3 MVMH2 MVMH1 MVMH0 Value 0 0 0 2 0 0 0 1 4 0 0 1 0 6 0 MVMH2 0 1 1 8 0 1 0 0 10 0 1 0 1 12 0 1 1 0 14 0 1 1 1 16 0 MVMH1 0 0 0 18 1 0 0 1 20 1 0 1 0 22 1 0 1 1 24 1 1 0 0 26 1 MVMH0 1 0 1 28 1 1 1 0 30 1 1 1 1 32 1 - - - - IVL3 D2 IVL2 D1 IVL1 D0 IVL0 - - - - IVL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S1C88409 TECHNICAL MANUAL IVL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IVL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 R/W 0 R/W - - - - Interval time setting IVL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interval time 128 x 1 x2 x3 x4 x5 x6 x7 x8 x9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 EPSON Init R/W Comment 1 R/W Invalid in constant-speed mode MVHMVMH MVMHMVML 0 R/W MVMLMVL - - - - - - "0" when being read - - - - - - 0 R/W 0 R/W 1 R/W 0 R/W 225 APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER Table A.1.1(e) Touch panel I/O map Address Bit 00FFA7 D7 D6 D5 D4 D3 D2 D1 D0 00FFA8 D7 D6 D5 D4 D3 D2 D1 D0 00FFA9 D7 D6 D5 D4 D3 D2 D1 D0 00FFAA D7 D6 D5 D4 D3 D2 D1 D0 00FFAB D7 D6 D5 D4 D3 D2 D1 D0 226 Name - - - - - - - PEN DX11 DX10 DX9 DX8 DX7 DX6 DX5 DX4 - - - - DX3 DX2 DX1 DX0 DY11 DY10 DY9 DY8 DY7 DY6 DY5 DY4 - - - - DY3 DY2 DY1 DY0 Function - - - - - - - Pen-up/pen-down status X coordinate data 1 - - - - - - - Pen-down D11(MSB) D10 D9 D8 D7 D6 D5 D4 - - - - D3 D2 D1 D0(LSB) D11(MSB) D10 D9 D8 D7 D6 D5 D4 X coordinate data Y coordinate data - - - - Y coordinate data D3 D2 D1 D0(LSB) EPSON 0 - - - - - - - Pen-up Init R/W Comment - - "0" when being read - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R - - "0" when being read - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R - - "0" when being read - - - - - - 0 R 0 R 0 R 0 R S1C88409 TECHNICAL MANUAL APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER (2) How to improve the response against user's operation A.2 Description To improve the response against user's operation, always activate the TPC with the highspeed clock (OSC3). The pen-down check control and pen-down interrupt should be disabled (PDC = "0", ETPPD = "0"). Set the operating clock to the high-speed clock (OSC3), turn on the clock supply to the A/D converter and TPC (PRAD = "1", PRTP = "1") and activate the TPC (RST = "1"). The coordinate update interrupt should be enabled after resetting the coordinate update interrupt factor flag. After that read the detected coordinate data every time a coordinate update interrupt has occurred due to the user's pen-trace operation. A.2.1 Circuit connection Refer to Section 5.17, "Touch Panel Controller". A.2.2 Mask option configuration Refer to Section 5.17, "Touch Panel Controller". A.2.3 Reducing power consumption and improving response (1) How to reduce power consumption To reduce current consumption, the high-speed clock (OSC3) should be used to operate the touch panel controller (TPC) only while the touch panel is being used. The coordinate update interrupt should be enabled (ETPDR = "1"). When the touch panel is not being used, set the operating clock to the low-speed clock (OSC1), turn off the clock supply to the A/D converter and TPC (PRAD = "0", PRTP = "0"), and reset the TPC circuit (RST = "0"). Furthermore, enable the pen-down check circuit (PDC = "1") to check a pen-down, then reset the pen-down interrupt factor flag (FTPPD = "1") a set period of time, and then enable the pen-down interrupt (ETPDR = "1"). When a pen-down interrupt has occurred due to the first pen-down, switch the operating clock to the high-speed clock (OSC3) and turn on the clock supply to the A/D converter and TPC (PRAD = "1", PRTP = "1"). Then reset the pen-down check circuit (PDC = "0") and activate the TPC (RST = "1"). The pen-down interrupt should be disabled (ETPDR = "0"). After that read the detected coordinate data every time a coordinate update interrupt has occurred. If coordinate data is not updated for a set period of time, assume that the touch panel is not being used, and return the configuration to the standby status for *awaiting the next pendown. Note, however, that this method increases power consumption because the TPC has to always operate with the high-speed clock. The sample program described later uses this method. (3) How to obtain the intermediate characteristics To obtain the intermediate characteristics between methods (1) and (2), the operating clock should be always set to the high-speed clock (OSC3) and the TPC and A/D converter should be activated after a pen-down is detected by the pen-down check. A.2.4 Reading coordinate data from the TPC (1) Method 1 Note, however, that the user's first operation may not be detected in this method because there is a time lag of several hundred msec between the first pen-down detection and when the TPC becomes ready to detect coordinates. S1C88409 TECHNICAL MANUAL EPSON Read the detected coordinate data and the switch status information (DX0-DX11, DY0- DY11, PEN) and store them in the temporary area, then set a flag indicating that coordinate data is updated. The detected coordinate data and the switch status information is guaranteed against change by the hardware until they are read by software after a coordinate update interrupt has occurred (they are not rewritten during read). These processes should be performed in the coordinate update interrupt service routine. Monitor the above flag in the main routine to check if coordinate data is updated. If the flag has been set, disable the interrupt and read the data stored in the temporary area. 227 APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER In this method, the coordinate data and switch status information in the temporary area are not rewritten while they are being read, so the values can be guaranteed. (2) Method 2 Set only a flag indicating that coordinate data is updated in the coordinate update interrupt service routine. The coordinate data and switch status information (DX0-DX11, DY0-DY11, PEN) are read in the main routine. A.2.5 Calculating the LCD dot position (1) Initial setting The first process needs registration of dot position between the touch panel and the LCD panel. The following explains the X axis only as the same applies to the Y axis. It assumes that the origin of both the LCD and touch panels are located at the left edge (in other words, the leftmost dot on the LCD is dot 0; the touch panel's A/D conversion value increase at the right side). First pen down at the leftmost dot position on the LCD, and the touch-panel A/D converted value is stored as x_min. Then pen down at the rightmost dot position on the LCD, and the touch-panel A/D converted value is stored as x_max. (2) LCD dot position calculation The LCD dot position corresponding to the pen-down position within the LCD display area is calculated by the following expressions: For x axis: DXMAX x_dot = (x_addat - x_min) x (x_max - x_min) For y axis: DYMAX y_dot = (y_addat - y_min) x (y_max - y_min) A.3 Precautions A.3.1 Interrupt processing (1) Only a pen-down interrupt may be generated when only the pen-down check circuit is activated (PDC = "1" and RST = "0"). When the TPC circuit is activated, both the pen-down and coordinate data update interrupts may be generated. Therefore, disable the pen-down interrupt when the TPC circuit is activated. (2) The coordinate data registers DX0-DX11 and DY0-DY11 (0FFA8h-0FFABh) must all be read regardless of the TPC operating status (RST = "1" or "0"). If only a part of the data, for example address 0FFA8h, is read leaving other addresses, the next coordinate update interrupt will not be generated. (3) When a coordinate update interrupt is generated, the coordinate data registers DX0-DX11 and DY0-DY11 (0FFA8h-0FFABh) must be read. If the set data is not read, the next coordinate update interrupt will not be generated. A.3.2 Others (1) A part of or all of the reference flowcharts and programs may be used freely. However, they cannot be guaranteed to work. Therefore Seiko Epson does not assume liability of any kind arising out of partial or complete use of the reference flowcharts and programs. (2) The reference program is a part of an executable program. To execute as a completed executable program, other processing routines such as a system initialization are necessary. Where x_addat (y_addat) is the A/D converted value and DXMAX (DYMAX) is the LCD resolution (number of dots). 228 EPSON S1C88409 TECHNICAL MANUAL APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER A.4 Reference Flowchart A.4.1 Initializing the TPC A.4.2 TPC data update interrupt processing TOUCH_INI INT_PMOVE Save register values into stack Save register values into stack CLK_LtoH (Set OSC3 clock) Set A/D clock division ratio (PSAD set) A/D clock on (PRAD 1) Set TPC clock division ratio (PSTP set) TPC clock on (PRTP 1) Configure TPC modes CONST, AVN, PRNR PSNR, WAIT, CND PUD, MVL, MVML MVMH, MVH, IVL Set TPC interrupt priority (PTP setting) Cancel TPC reset (RST 1) PEN ? (Pen-up/down status) 0 (Pen-up) 1 (Pen-down) Switch data 0 on (TC_SWITCH0 1) Switch data 0 off (TC_SWITCH0 0) Read/store X coordinate [tc_xior] DX11...DX0 X coordinate dummy read (DX11...DX0) Read/store Y coordinate [tc_yior] DY11...DY0 Y coordinate dummy read (DY11...DY0) Set coordinate update flag (TCDT_RCV 1) Reset coordinate update interrupt factor flag (FTPDR 1) Restore register values from stack Reset TPC interrupt factor flags (FTPPD, FTPDR 1) RETE Enable TPC data update interrupt (ETPDR 1) Restore register values from stack RET S1C88409 TECHNICAL MANUAL EPSON 229 APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER A.4.3 TP initial data configuration A.4.3.1 Pen-down standby TCDATA_INI WAIT_PEN_DOWN Save register values into stack Draw X origin check point Draw Y origin check point Pen-down standby (WAIT_PEN_DOWN) Pen-down standby (WAIT_PEN_DOWN) Read and store X origin A/D data [tc_xorg] [tc_xior] Read and store Y origin A/D data [tc_yorg] [tc_yior] Pen-up standby (WAIT_PEN_UP) Pen-up standby (WAIT_PEN_UP) Erase X origin check point Erase Y origin check point Draw max. X position check point Draw max. Y position check point Pen-down standby (WAIT_PEN_DOWN) Pen-down standby (WAIT_PEN_DOWN) Read max. X position A/D data and calculate span [tc_xspn] = [tc_xior] - [tc_xorg] Read max. Y position A/D data and calculate span [tc_yspn] = [tc_yior] - [tc_yorg] Pen-up standby (WAIT_PEN_UP) Pen-up standby (WAIT_PEN_UP) Erase max. X position check point Erase max. Y position check point Reset coordinate receive flag (TCDT_RCV 0) TCDT_RCV ? (Wait data receive) 0 1 (received) TC_SWITCH0 ? (Wait pen-down) 0 (pen-up) 1 (pen-down) Reset coordinate receive flag (TCDT_RCV 0) RET Restore register values from stack RET A.4.3.2 Pen-up standby WAIT_PEN_UP TCDT_RCV ? (Wait data receive) 0 1 (received) TC_SWITCH0 ? (Wait pen-up) 0 (pen-down) 1 (pen-up) Reset coordinate receive flag (TCDT_RCV 0) RET 230 EPSON S1C88409 TECHNICAL MANUAL APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER A.4.4 Coordinate data calculation TC_GETCOORD Save register values into stack DXMAX TCDT_RCV ? (Wait data receive) 0 LCD 1 (received) Reset coordinate receive flag (TCDT_RCV 0) Disable interrupt (SC: I1, I0 = 11) [tc_xspn] Read coordinate data Register [tc_xior] Register [tc_yior] Register TC_SWITCH0 Touch Panel Enable interrupt (SC: I1, I0 = 00) [tc_xorg] [tc_xior] Calculate switch data TC_SWITCH1 TC_SWITCH0 Calculate X coordinate x = ([tc_xior] - [tc_xorg] DXMAX / [tc_xspn] Calculate Y coordinate y = ([tc_yior] - [tc_yorg] DYMAX / [tc_yspn] Restore register values from stack RET S1C88409 TECHNICAL MANUAL EPSON 231 APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER A.5 Reference Program A.5.1 Setting constants and macros (include file) ;******************************************************************************* ; SYS_CONST.INC system constant data ; -------------------------------------------; Copyright(C) 1997 Seiko Epson Co.,Ltd ;******************************************************************************* (1) Set flags ;============= tpc_flg0 ====================================================== TCDT_RCV EQU 00000001B ;1: coordinate calculation is finished TC_SWITCH0 EQU 00000010B ;switch detected in pen-move interrupt TC_SWITCH1 EQU 00000100B ;switch translated in coordinate calc.loutine WAITTIMER EQU 00001000B ;wait timer for pen down setting (2) Define Macros ;------------- macro declaration ------------------------;<bit set macro> M_BSET MACRO DATA,DBIT,REG LD REG,[DATA] OR REG,#DBIT LD [DATA],REG ENDM M_BCLR M_IO_BCLR M_IO_BSET ;<bit clear macro> MACRO DATA,DBIT,REG LD REG,#DBIT XOR REG,#0FFH AND REG,[DATA] LD [DATA],REG ENDM ;<I/O register bit clear macro> MACRO DATA,DBIT AND [BR:@LOW(DATA)],#DBIT0FFH ENDM ;<I/O register bit set macro> MACRO DATA,DBIT OR [BR:@LOW(DATA)],#DBIT ENDM A.5.2 TPC initialization ;############################################################################### ; touch panel controller initialize ; input none ; output none ; destroyed none ;############################################################################### GLOBAL TOUCH_INI TOUCH_INI: ;ETPPD,ETPDR,PDC,RST is initial 0 ;TP interrupt priority PTP* is set in other previous routine (1) Save the register values into the stack PUSH PUSH SC A (2) Switch to the high-speed clock CARL CLK_LtoH ;change the clock to high (3) Supply clocks to the A/D converter and TPC LD 232 [BR:@LOW(IO_PRE3)],#00001010B EPSON ;A/D clock = fOSC3/4 ;A/D clock is turned on S1C88409 TECHNICAL MANUAL APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER LD [BR:@LOW(IO_PRE6)],#00001100B ;TPC clock = fOSC3/16 ;TPC clock is turned on LD [BR:@LOW(IO_PRE7)],#00000000B LD [BR:@LOW(IO_TPCR0)],#00010011B LD [BR:@LOW(IO_TPCR1)],#00001111B LD [BR:@LOW(IO_TPCR2)],#00001111B LD [BR:@LOW(IO_TPCR3)],#00001111B LD [BR:@LOW(IO_TPCR4)],#01000010B LD [BR:@LOW(IO_TPCR5)],#10000110B LD [BR:@LOW(IO_TPCR6)],#00000010B ;TPC noise rejection on ;TPC noise rejection ;f.ratio = fOSC1/1 ;CONST moving average ;average times = 16 * 2 ;voltage stability wait ;time = 16 * 16/f ;noise detection threshold ;= 64 ;pen up detection threshold ;= 64 ;setting speed detection ;threshold ; SSDT = 6 ;MSSDT = 10 ;MFSDT = 14 ; FSDT = 18 ;wait time after A/D conv. ;= 128 * 3 (4) Set the TPC modes (5) Activate the TPC circuit OR [BR:@LOW(IO_TPCR0)],#00100000B ;lift a reset of TPC circuit (8) Reset the coordinate update interrupt flag and enable the interrupt LD [BR:@LOW(IO_INTFA3)],#01100000B OR [BR:@LOW(IO_INTEA3)],#00100000B ;TP pen down interrupt ;factor flag reset ;TP data renewal interrupt ;enable (9) Restore the saved registers POP POP A SC RET A.5.3 TPC data update interrupt processing ;############################################################################### ; pen move interrupt loutine ; input none ; output none ; destroyed none ;############################################################################### GLOBAL INT_PMOVE INT_PMOVE: (1) Save the registers PUSH PUSH BA L (2) Pen-down check BIT JRS [BR:@LOW(IO_TPCR7)],#00000001B Z,INTPMOVE10 ;if pen down is detected ;then read the coordinate ;data (3) Process when a pen-down is detected Set the switch data to "1" M_BSET tpc_flg0,TC_SWITCH0,A ;switch0 = 1 Load X coordinate data LD LD PACK LD LD S1C88409 TECHNICAL MANUAL B,[BR:@LOW(IO_TPCR8)] A,[BR:@LOW(IO_TPCR9)] L,A A,B EPSON ;B ;A ;A ;L ;A = = = = = x11 - x04 x03 - x00 x07 - x00 A B 233 APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER UPCK LD LD ;B = x11 - x08 ;A = x07 - x00 ;data save A,L [tc_xior],BA Load Y coordinate data LD LD PACK LD LD UPCK LD LD JRS B,[BR:@LOW(IO_TPCRA)] A,[BR:@LOW(IO_TPCRB)] L,A A,B A,L [tc_yior],BA INTPMOVE20 ;B = x11 ;A = x03 ;A = x07 ;L = A ;A = B ;B = x11 ;A = x07 ;data save x04 x00 x00 x08 x00 (4) Process when no pen-down is detected INTPMOVE10: Set the switch data to "1" M_BCLR tpc_flg0,TC_SWITCH0,A ;switch0 = 0 Dummy read of coordinate data LD LD LD LD A,[BR:@LOW(IO_TPCR8)] A,[BR:@LOW(IO_TPCR9)] A,[BR:@LOW(IO_TPCRA)] A,[BR:@LOW(IO_TPCRB)] ;dummy ;dummy ;dummy ;dummy read read read read (5) Set the coordinate data update flag INTPMOVE20: M_BSET tpc_flg0,TCDT_RCV,A ;set the coordinate data ;receive flag (6) Reset the coordinate update interrupt factor flag LD [BR:@LOW(IO_INTFA3)],#00100000B (7) Restore the saved register POP POP L BA RETE A.5.4 TP initial data setting ;############################################################################### ; set the base data for coordinate calculation ; input none ; output none ; destroyed none ;############################################################################### GLOBAL TCDATA_INI TCDATA_INI: (1) Save the registers PUSH PUSH PUSH SC BA HL ;SC register is stored ;BA register is stored ;HL register is stored (2) Obtain the X origin reference coordinate Draw check point <omitted> Pen-down standby CARL WAIT_PEN_DOWN Load TP data LD LD 234 BA,[tc_xior] [tc_xorg],BA ;save x origin data EPSON S1C88409 TECHNICAL MANUAL APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER Pen-up standby CARL WAIT_PEN_UP Erase check point <omitted> (3) Obtain the max. X reference coordinate Draw check point <omitted> Pen-down standby CARL WAIT_PEN_DOWN Load TP data LD LD SUB BA,[tc_xior] HL,[tc_xorg] BA,HL ;BA = x max data ;HL = x org data ;BA = x span data LD L,#0 ;shift counter = tc_xsft CP JRS SRL RR INC JRS B,#0 Z,TCDTI_210 B A L TCDTI_LP20 ;if B = 0 (data is included ;in 8 bit) then out of loop LD LD [tc_xspn],A [tc_xsft],L ;x span data ;x bit shift times TCDTI_LP20: ;bit shift ;shift counter increment TCDTI_210: Pen-up standby CARL WAIT_PEN_UP Erase check point <omitted> (4) Obtain the Y origin reference coordinate <omitted. similar to the process to obtain the X origin reference coordinate> (5) Obtain the max. Y reference coordinate <omitted. similar to the process to obtain the Y origin reference coordinate> (6) Restore the saved registers POP POP POP HL BA SC ;HL = register is returned ;BA = register is returned ;SC = register is returned RET (7) <Subroutine> Pen-down standby processing ;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ; Wait Pen Down ; (A register is destroyed) ;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% WAIT_PEN_DOWN: M_BCLR tpc_flg0,TCDT_RCV,A ;reset the coordinate receive flag WTPNDNLP: LD BIT JRS A,[tpc_flg0] A,#TCDT_RCV Z,WTPNDNLP LD BIT JRS A,[tpc_flg0] A,#TC_SWITCH0 Z,WTPNDNLP S1C88409 TECHNICAL MANUAL ;check the coordinate receive flag ;check pen is down EPSON 235 APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER M_BCLR tpc_flg0,TCDT_RCV,A ;reset the coordinate receive flag RET (8) <Subroutine> Pen-up standby processing ;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ; Wait Pen UP ; (A,B register is destroyed) ;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% WAIT_PEN_UP: LD A,[tpc_flg0] ;check the coordinate receive flag BIT A,#TCDT_RCV JRS Z,WAIT_PEN_UP LD BIT JRS A,[tpc_flg0] A,#TC_SWITCH0 NZ,WAIT_PEN_UP ;check pen is up M_BCLR tpc_flg0,TCDT_RCV,A ;reset the coordinate receive flag RET A.5.5 Coordinate data calculation ;############################################################################### ; get coordinate data from touch panel ; ; input output none A:y axis coordinate B:x axis coordinate ; destroyed (A,B) ;############################################################################### GLOBAL TC_GETCOORD TC_GETCOORD: (1) Save registers and reserve work area PUSH PUSH PUSH SUB SC IX HL SP,#2 LD IX,SP ;SC register is stored ;IX register is stored ;HL register is stored ;2 byte reserved for work in stack ;area ;stack pointer address (2) Wait for receiving coordinate data TCGETCD10: LD A,[tpc_flg0] BIT JRS A,#TCDT_RCV Z,TCGETCD10 ;check the coordinate ;receive flag (3) Reset the coordinate data receive flag M_BCLR tpc_flg0,TCDT_RCV,A ;reset the coordinate receive flag SC,#11000000B ;interrupt disenable BA,[tc_yior] [IX],BA HL,[tc_xior] A,[tpc_flg0] ;wk0, wk1 = y data (ytgt) ;HL = x axis data (xtgt) ;switch data SC,#00111111B ;interrupt enable A,#TC_SWITCH0 NZ,TCGETCD12 tpc_flg0,TC_SWITCH1,A ;if switch0 = 0 then ; switch1 = 0 (4) Disable the interrupt OR (5) Read coordinate data LD LD LD LD (6) Enable the interrupt AND (7) Calculate switch data BIT JRS M_BCLR 236 EPSON S1C88409 TECHNICAL MANUAL APPENDIX: CONTROLLING THE TOUCH PANEL CONTROLLER JRS TCGETCD14 M_BSET tpc_flg0,TC_SWITCH1,A ;else (switch = 1) then ; switch1 = 1 LD LD SUB JRS LD BA,HL HL,[tc_xorg] BA,HL NC,TCGETCD20 BA,#0 ;BA = x axis data (xtgt) ;HL = x axis origin data (xorg) ;BA=xtgt - xorg ;if xtgt - xorg < 0 then ; xtgt - xorg = 0 LD INC L,[tc_xsft] L ;L = shift counter DEC JRS SRL RR JRS L Z,TCGETCD40 B A TCGETCD30 SRL JRS LD MLT LD DIV CP JRS B C,TCGETCD45 L,#D_PXL_X LD L,#D_PXL_X-1 ; LD LD BA,[IX] [IX],L ;BA = y axis data (ytgt) ;wk0 = x axis coordinate LD SUB JRS LD HL,[tc_yorg] BA,HL NC,TCGETCD60 BA,#0 ;BA ;HL ;BA ;if ; LD INC L,[tc_ysft] L DEC JRS SRL RR JRS L Z,TCGETCD80 B A TCGETCD70 SRL JRS LD MLT LD DIV CP JRS B C,TCGETCD85 L,#D_PXL_Y LD L,#D_PXL_Y-1 ; LD LD A,L B,[IX] ;A = y axis coordinate ;A = x axis coordinate TCGETCD12: TCGETCD14: (8) Calculate X coordinate TCGETCD20: TCGETCD30: ;shift 1 bit to right TCGETCD40: ;if B reg is not 0 then over flow ;L = display dot number (DMAX) ;HL = DMAX * (xtgt - xorg) ;A = x axis coordinate span (xspn) ;L = DMAX * (xtgt - xorg) / xspn ;if x coord MAX then A,[tc_xspn] L,#D_PXL_X C,TCGETCD50 TCGETCD45: x coord = MAX-1 TCGETCD50: (9) Calculate Y coordinate = y axis data (ytgt) = y axis origin data (yorg) = ytgt - yorg ytgt - yorg < 0 then ytgt - yorg = 0 TCGETCD60: ;L = shift counter TCGETCD70: ;shift 1 bit to right TCGETCD80: ;if B reg is not 0 then over flow ;L = display dot number (DMAX) ;HL = DMAX * (ytgt - yorg) ;A = y axis coordinate span (yspn) ;L = DMAX * (ytgt - yorg) / yspn ;if y coord MAX then A,[tc_yspn] L,#D_PXL_Y C,TCGETCD90 TCGETCD85: y coord = MAX - 1 TCGETCD90: (10) Restore the saved register and release the work area ADD POP POP POP SP,#2 HL IX SC ;2 byte returned ;HL register is returned ;IX register is returned ;SC register is returned RET S1C88409 TECHNICAL MANUAL EPSON 237 International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. 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FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Prima Sant Cugat Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 Fax: +34-93-544-2491 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. S1C88409 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue August, 1998 Printed February, 2001 in Japan M B