INTEGRATED CIRCUITS DATA SHEET 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) Product specification Supersedes data of 1998 Mar 17 2002 Oct 02 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A FEATURES DESCRIPTION * 5 V tolerant inputs/outputs for interfacing with 5V logic The 74LVC(H)16373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment. * Wide supply voltage range from 1.2 to 3.6 V * Complies with JEDEC standard no. 8-1A * CMOS low power consumption * MULTIBYTETM flow-through standard pin-out architecture * Low inductance multiple power and ground pins for minimum noise and ground bounce The 74LVC(H)16373A consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. * Direct interface with TTL levels * All data inputs have bus hold (74LVCH16373A only) * High-impedance when VCC = 0 V. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74LVCH16373A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns SYMBOL tPHL/tPLH PARAMETER propagation delay: CONDITIONS UNIT CL = 50 pF; VCC = 3.3 V Dn to Qn 3.0 ns LE to Qn 3.4 ns CI input capacitance CPD power dissipation per latch VCC = 3.3 V; note 1 Note 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacity in pF; VCC = supply voltage in Volts; (CL x VCC2 x fo) = sum of the outputs. 2002 Oct 02 TYPICAL 2 5.0 pF 26 pF Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74LVC16373ADL -40 to +85 C 48 TSSOP-48 plastic SOT370-1 74LVC16373ADGG -40 to +85 C 48 TSSOP-48 plastic SOT362-1 74LVCH16373ADL -40 to +85 C 48 TSSOP-48 plastic SOT370-1 74LVCH16373ADGG -40 to +85 C 48 TSSOP-48 plastic SOT362-1 PINNING PIN 1 SYMBOL 1OE DESCRIPTION output enable input (active LOW) handbook, halfpage 2, 3, 5, 6, 8, 1Q0 to 1Q7 data inputs/outputs 9, 11, 12 4, 10, 15, 21, 28, 34, 39, 45 GND ground (0 V) 7, 18, 31, 42 VCC 13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7 data inputs/outputs 24 2OE output enable input (active LOW) 25 2LE latch enable input (active HIGH) supply voltage 36, 35, 33, 32, 30, 29, 27, 26 2D0 to 2D7 data inputs 47, 46, 44, 43, 41, 40, 38, 37 1D0 to 1D7 data inputs 48 1LE latch enable input (active HIGH) 1OE 1 48 1LE 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2LE MGU767 Fig.1 Pin configuration. 2002 Oct 02 3 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A handbook, full pagewidth 1D0 D 1Q0 Q 2D0 D LATCH 1 LE 2Q0 Q LATCH 9 LE LE 1LE 2LE 1OE 2OE to 7 other channels LE to 7 other channels MGU769 Fig.2 Logic diagram. 1 handbook, halfpage handbook, halfpage 24 1OE 1LE 1OE 2OE 2OE 47 1D0 1Q0 2 46 1D1 1Q1 3 44 1D2 1Q2 5 2LE 1D0 43 1D3 1Q3 6 1D1 41 1D4 1Q4 8 1D2 40 1D5 1Q5 9 1D3 38 1D6 1Q6 11 1D4 37 1D7 1Q7 12 1D5 36 2D0 2Q0 13 1D6 35 2D1 2Q1 14 1D7 33 2D2 2Q2 16 2D0 32 2D3 2Q3 17 2D1 30 2D4 2Q4 19 2D2 29 2D5 2Q5 20 2D3 27 2D6 2Q6 22 2D4 23 2D5 26 2D7 2Q7 1LE 2LE 48 25 2D6 2D7 MGU768 48 24 25 47 1EN C3 2EN C4 3D 1 2 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 4D 2 13 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 MGU770 Fig.3 Logic symbol. 2002 Oct 02 1 Fig.4 Logic symbol (IEEE/IEC). 4 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) handbook, halfpage 74LVC16373A; 74LVCH16373A VCC data input to internal circuit MGU771 Fig.5 Bus hold circuit. FUNCTION TABLE Per section of eight bits; note 1 INPUT OE LE Dn INTERNAL LATCHES OUTPUTS Q0 TO Q7 L H L L L L H H H H OPERATING MODES Enable and read register (transparent mode) Latch and read register Latch register and disable outputs L L l L L L L h H H H L l L Z H L h H Z Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. 2002 Oct 02 5 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage VI input voltage VO output voltage Tamb operating ambient temperature tr, tf input rise and fall times CONDITIONS MIN. MAX. UNIT for maximum speed performance 2.7 3.6 V for low voltage applications 1.2 3.6 V 0 5.5 V output HIGH or LOW state 0 VCC V output 3-state 0 5.5 V in free-air -40 +85 C VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V); note 1. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage -0.5 - +6.5 V IIK input diode current VI < 0 - -50 - V VI input voltage note 2 -0.5 - +6.5 V IOK output diode current VO > VCC or VO < 0 - 50 - V VO output voltage output HIGH or LOW state; -0.5 note 2 - VCC + 0.5 V output 3-state; note 2 -0.5 - +6.5 V VO = 0 to VCC IO output source or sink current - 50 - mA ICC, IGND VCC or GND current - 100 - mA Tstg storage temperature -65 - +150 C Ptot power dissipation per package SO above 70 C derates linearly with 8 mW/K - 500 - mW SSOP and TSSOP above 60 C derates linearly with 8 mW/K - 500 - mW Notes 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2002 Oct 02 6 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb (C) TEST CONDITIONS SYMBOL VCC (V) OTHER VIH VIL VOH VOL -40 to +85 PARAMETER HIGH-level input voltage MIN. UNIT TYP.(1) MAX. 1.2 VCC - - V 2.7 to 3.6 2.0 - - V 1.2 - - GND V 2.7 to 3.6 - - 0.8 V VI = VIH or VIL; IO = -12 mA 2.7 VCC - 0.5 - - V VI = VIH or VIL; IO = -100 A 3.0 VCC - 0.2 VCC - V VI = VIH or VIL; IO = -18 mA 3.0 VCC - 0.6 - - V VI = VIH or VIL; IO = -24 mA 3.0 VCC - 0.8 - - V LOW-level output voltage VI = VIH or VIL; IO = 12 mA 2.7 - - 0.40 V LOW-level input voltage HIGH-level output voltage VI = VIH or VIL; IO = 100 A 3.0 - - 0.20 V VI = VIH or VIL; IO = 24 mA 3.0 - - 0.55 V ILI input leakage current VI = 5.5 V or GND; note 2 3.6 - 0.1 5 A IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND 3.6 - 0.1 5 A Ioff power off leakage current Vi or VO = 5.5 V 0 - - 10 A ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - 0.1 20 A ICC additional quiescent supply current per input pin VI = VCC - 0.6 V; IO = 0 2.7 to 3.6 - 5 500 A IBHL bus hold LOW sustaining current VI = 0.8 V; notes 3 and 4 3.0 75 - - A IBHH bus hold HIGH sustaining VI = 2.0 V; notes 3 and 4 current 3.0 -75 - - A IBHLO bus hold LOW overdrive current notes 3 and 5 3.6 500 - - A IBHHO bus hold HIGH overdrive current notes 3 and 5 3.6 -500 - - A Notes 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2. For bus hold parts, the bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal. 3. Valid for data inputs of bus hold parts (LVCH16373A) only. 4. The specified sustaining current at the data input holds the input below the specified VI level. 5. The specified overdrive current at the data input forces the data input to the opposite logic input state. 2002 Oct 02 7 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A AC CHARACTERISTICS GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 . Tamb (C) SYMBOL PARAMETER -40 to +85 WAVEFORMS MIN. UNIT TYP. MAX. VCC = 1.2 V tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 - 12 - ns tPHL/tPLH propagation delay LE to Qn see Figs 7 and 10 - 14 - ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 9 and 10 - 18 - ns tPHZ/tPLZ 3-state output enable time OE to Qn see Figs 9 and 10 - 11 - ns tW LE pulse width HIGH see Fig.7 - - - ns tsu set-up time Dn to LE see Fig.8 - - - ns th hold time Dn to LE see Fig.8 - - - ns tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 1.5 - 5.7 ns tPHL/tPLH propagation delay LE to Qn see Figs 7 and 10 1.5 - 5.8 ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 9 and 10 1.5 - 6.5 ns tPHZ/tPLZ 3-state output enable time OE to Qn see Figs 9 and 10 1.5 - 6.4 ns VCC = 2.7 V tW LE pulse width HIGH see Fig.7 3 - - ns tsu set-up time Dn to LE see Fig.8 1.7 - - ns th hold time Dn to LE see Fig.8 1.2 - - ns VCC = 3.3 0.3 V; note1 tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 1.5 3.0 4.7 ns tPHL/tPLH propagation delay LE to Qn see Figs 7 and 10 1.5 3.4 4.8 ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 9 and 10 1.5 3.5 5.5 ns tPHZ/tPLZ 3-state output enable time OE to Qn see Figs 9 and 10 1.5 3.9 5.4 ns tW LE pulse width HIGH see Fig.7 3 2.0 - ns tsu set-up time Dn to LE see Fig.8 +1.7 -0.1 - ns th hold time Dn to LE see Fig.8 1.2 0.1 - ns Note 1. Typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2002 Oct 02 8 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A AC WAVEFORMS VI handbook, halfpage Dn input VM VM t PHL t PLH GND VOH VM Qn output VOL MGU772 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. Fig.6 Input (Dn) to output (Qn) propagation delays. VI handbook, halfpage LE input VM VM VM GND tW t PHL t PLH VOH Qn output VM VM VOL MGU773 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. Fig.7 Latch enable input (LE) pulse width, and the latch enable input to output (Qn) propagation delays. 2002 Oct 02 9 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A VI handbook, full pagewidth VM Dn input GND th th t su t su VI VM LE input GND MGU774 The shaded areas indicate when the input is permitted to change for predictable performance. VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. Fig.8 Data set-up and hold times for the Dn input to the LE input. VI handbook, full pagewidth OE input VM VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND outputs enabled outputs disabled outputs enabled MGU775 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VX = VOL + 0.3 V at VCC 2.7 V. VX = VOL + 0.1VCC at VCC < 2.7 V. VY = VOH - 0.3 V at VCC 2.7 V. VY = VOH - 0.1VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. Fig.9 3-state enable and disable times. 2002 Oct 02 10 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A S1 handbook, full pagewidth VCC PULSE GENERATOR VIN RL 500 VOUT 2 x VCC open GND D.U.T. CL RT RL 500 MGU776 VCC VI <2.7 V VCC 2.7 to 3.6 2.7 V TEST S1 tPLH/tPHL open tPLZ/tPZL 2 x VCC tPHZ/tPZH GND Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.10 Load circuitry for switching times. 2002 Oct 02 11 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A PACKAGE OUTLINES SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3) pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 2002 Oct 02 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-118 12 o Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 2002 Oct 02 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-10 99-12-27 MO-153 13 o Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. To overcome these problems the double-wave soldering method was specifically developed. 2002 Oct 02 74LVC16373A; 74LVCH16373A 14 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Oct 02 15 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) 74LVC16373A; 74LVCH16373A DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 Oct 02 16 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) NOTES 2002 Oct 02 17 74LVC16373A; 74LVCH16373A Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) NOTES 2002 Oct 02 18 74LVC16373A; 74LVCH16373A Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V tolerant inputs/outputs (3-state) NOTES 2002 Oct 02 19 74LVC16373A; 74LVCH16373A Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA74 (c) Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/05/pp20 Date of release: 2002 Oct 02 Document order number: 9397 750 10037