QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1317A-E
ACTIVE RESET ISOLATED DC/DC POWER CONVERTER
4
Figure 5. The LT4430 opto coupler driver pro-
duces monotonic output voltage rise at startup
without output voltage overshoot.
DEBUGGING AND TESTING
The DC1317 can easily be tested and debugged by
powering the bias circuit separately from the main
power circuit. To place DC1317 into debug mode
remove the resistor R1 and connect 48V, 100mA
power source to +Vb node (right side of R1). By
doing this, the primary PWM controller LT1952
can be activated without the main primary power
being applied to +Vin.
To activate the secondary side feedback circuit
LT4430 diode OR a 10V, 100mA power source
into collector of Q9.
Once the primary and secondary controllers are
running the MOSFET gate timing can be checked.
If the MOSFET gate timing is correct the main
power input can be applied to +Vin. By slowly in-
creasing the +Vin from 0V to 48V the output volt-
age and input current can be monitored. The input
current should not exceeded 100mA without the
output load. If one of the MOSFETs is damaged,
the input current will exceed 100mA.
PCB LAYOUT
The pcb layout should be carefully planned to avoid
potential noise problems. The PCB layout for
DC1317A can be used as a guide. Since demo board
DC1317A has 8 versions the PCB layout has optional
components that can be removed. Also, the PCB lay-
out has a common schematic that is used just for the
layout. The actual circuit schematic shows compo-
nent values. In some cases, a resistor is used inplace
holder for a capacitor as in case of C4. Please modify
the reference designators in your schematic to reflect
the actual component used. The following simple
PCB layout rules should be helpful.
If possible use solid ground planes on layers 2 and N-
The ground planes will prevent the switching noise
from coupling into sensitive lines.
Place sensitive lines on the inner layers that will be
shielded by grounds on layers 2 and N-1.
Keep the loop formed by Q1, RCS1, Cin and T1
tight.
Keep the loop formed by Q2, Q3 and T1 tight.
Keep noise sensitive nodes like SD/VSEC, ROSC,
FB, COMP, ISENSE, BLANK and DELAY as small
as posible by placing the associated components
close to the LT1952 and LT4430 chips.
Use local vias for all components that connect to
ground planes.
Do not place any traces on the layers 2 and N-1 to
avoid ground planes from being compromised.
If the PCB layout has to be done on 2 or 4-layer PCB
use the same guidelines as outlined above. Also,
maximize the ground connections between compo-
nents by placing the components tight together.
Please contact LT factory for additional assistance.