ee FAIRCHILD ee SEMICONDUCTOR 100350 Low Power Hex D-Latch General Description The 100350 contains six D-type latches with true and complement outputs, a pair of common Enables (Eq and E,), and a common Master Reset (MR). A Q output follows its D input when both E, and &, are LOW. When either E, or E, March 1998 Features @ 20% power reduction of the 100150 @ 2000V ESD protection w Pin/function compatible with 100150 w Voltage compensated operating range = MR Qo Qy TTT Titi iit DS009884-10 Connection Diagrams 24-Pin DIP = Wd Qf! 24-05 G2 23 EDs, Q-43 22;Dy Os-44 21 E, 45 20;-E, Voo] 6 19 FMR Voca]7 187- Veg a%-48 17}Ds 48 16D, Q-710 15}D, Qi 14.-Dy A412 13-5 bso0sss4-1 (or both) are HIGH, a latch stores the last valid data present -4.2V to -5.7V on its D input before E, or E, went HIGH. The MR input over- rides all other inputs and makes the Q outputs LOW. All in- puts have 50 kQ pull-down resistors. Ordering Code: Logic Symbol Pin Names Description z z DoDs Data Inputs : E,, Ep Common Enable Inputs (Active LOW) MR Asynchronous Master Reset Input E Do Dy Dp Dg Dy Ds Qo-Qs Data Outputs Qo-Qs5 Complementary Data Outputs 24-Pin Quad Cerpak E, Ey MR Ver Ds Dp Jj jj jt 24 23 22 21 20 19 byt 18 Dy Dg 42 17 F Dy OQ, 43 16 FQ Q, 44 15F= a,-5 14 Q, Qy-46 13 4, 8 9 10 11 12 7 TrTTT. Q3 Q3 Voc Voca Q2 bso09884-2 1998 Fairchild Semiconductor Corporation Dsoogse4 www fairchildsemi.com Yo}e1-d X9H J8M0d MO] OSEOOLConnection Diagrams (Continued) 28-Pin PCC Dy Dy QqVeEs Mp 0 0 HOoOEABAeS Vers MR E, e een a fe Dg Ds O5 Vers Qs Q4 Oy DS009884-3 Logic Diagram Do D, Dp Ds Ds MR Eq ER Ds T | | T | T | T | T | Q % Q, QQ Q; Q3 Q % Q 5 DS009884-4 Truth Tables (Each Latch) Asynchronous Operation Inputs Outputs Latch Operation Dz, E, E, MR Q, Inputs Outputs x x x A L D, E, E, MR Q, L L L L L H L L L H x H x L Latched (Note 1} x x H L Latched (Note 1} H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Note 1: Retains data present before E positive transition www fairchildsemi.com 2Absolute Maximum Ratings (note 2) Recommended Operating Conditions Storage Temperature (Tgt) -65C to +150C Maximum Junction Temperature (Ty) ; Case Temperature (T,) Ceramic 175C Commercial O'C to +85C Plastic +150C Military 55C to +125C Vee Pin Potential to Ground Pin -7.0V to +0.5V Supply Voltage (Veg) _5.7V to -4.2V Input Voltage (DC) Vee to +0.5V Note 2: Absolute maximum ratings are those values beyond which the de- Output Current (DC Output HIGH) 50 mA vice may be damaged or have its useful life impaired. Functional operation ESD (Note 3) >2000V under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (note 4) Vee = -4.5V to -5.7V, Voo = Veca = GND, Tg = 0C to +85C Symbol Parameter Min Typ Max Units Conditions Vou Output HIGH Voltage -1025 -955 -870 mV Vin =Vin (Max) Loading with Voi Output LOW Voltage -1830 -1705 -1620 or Vit (min) 50Q to -2.0V Voue Output HIGH Voltage -1035 mV Vin = Vin (min) Loading with Vote Output LOW Voltage -1610 or Vit (max) 50Q to -2.0V Vie Input HIGH Voltage -1165 -870 mV Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage -1830 -1475 mV Guaranteed LOW Signal for All Inputs lit Input LOW Current 0.50 HA Vin = Vic aminy liq Input HIGH Current MR 240 Dn 240 HA Vin = Vin (max) E, E, 240 lee Power Supply Inputs Open Current -89 44 mA Vee = -4.2V to -4.8V -93 -44 Vee = -4.2V to -5.7V Note 4: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. DIP AC Electrical Characteristics Vee = -4.2V to -5.7V, Voo = Veca = GND Symbol Parameter To = OC To = +25C To = +85C Units Conditions Min Max Min Max Min Max TeLH Propagation Delay Figures 1, 2 TPHL D, to Output 0.50 1.40 0.50 1.40 0.50 1.50 ns (Transparent Mode) teLy Propagation Delay 0.75 1.85 0.75 1.85 0.75 2.05 ns teHL E,, E, to Output teLy Propagation Delay 0.90 2.10 0.90 2.10 0.90 2.10 | ns Figures 1, 3 teu MR to Output toy Transition Time 0.35 1.30 0.35 1.30 0.35 1.30 ns Figures 1, 2 tra 20% to 80%, 80% to 20% ts Setup Time Figures 3, 4 Do-Ds 1.00 1.00 1.00 ns MR (Release Time) 1.60 1.60 1.60 th Hold Time, DyDs 0.40 0.40 0.40 ns Figure 4 3 www fairchildsemi.comDIP AC Electrical Characteristics (continued) Vee = -4.2V to -5.7V, Veo = Veca = GND Symbol Parameter To = 0'C To = +25C To = +85C Units Conditions Min Max Min Max Min Max tow(L) Pulse Width LOW 2.00 2.00 2.00 ns Figure 2 E. Eo tow(H) Pulse Width HIGH, MR 2.00 2.00 2.00 ns Figure 3 PCC and Cerpak AC Electrical Characteristics Vee = -4.2V to -5.7V, Veco = Veca = GND Symbol Parameter To = OC To = +25C To = +85C Units | Conditions Min Max Min Max Min Max teLy Propagation Delay Figures 1, 2 tout D, to Output 0.50 120 | 050 1.20 | 050 1.30 ns (Transparent Mode) teLH Propagation Delay 0.75 1.65 0.75 1.65 0.75 1.85 ns teHL E,, E, to Output teLy Propagation Delay 0.90 1.90 0.90 1.90 0.90 1.90 ns Figures 1, 3 teu MR to Output tH Transition Time 0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1, 2 true 20% to 80%, 80% to 20% ts Setup Time Figures 3, 4 Do-Ds 0.90 0.90 0.90 ns MR (Release Time) 1.50 1.50 1.50 th Hold Time, DyDs 0.30 0.30 0.30 ns Figure 4 tow(L) Pulse Width LOW 2.00 2.00 2.00 ns Figure 2 E. E, tow(H) Pulse Width HIGH, MR 2.00 2.00 2.00 ns Figure 3 Military VersionPreliminary DC Electrical Characteristics Vee = -4.2V to -5.7V, Voc = Veca = GND, Te = -55C to +125C Symbol Parameter Min | Max | Units Te Conditions Notes Vou Output HIGH Voltage |-1025 | -870 | mV 0C to +125C (Notes 5, 6, 7) 1085 | -870 | mV -55C Vin = Vin(Max) Loading with VoL Output LOW Voltage [|-1830 +1620] mV 0C to +125C or Vi_(Min) 50Q to -2.0V 1830 +1555 | mV -55C Vonc | Output HIGH Voltage |-1035 mV 0C to +125C (Notes 5, 6, 7) 1085 mV -55C Vin = Vin(Min) Loading with Voie Output LOW Voltage L1610} mV 0C to +125C or Vi_(Min) 50Q to -2.0V +1555 | mV -55C Vin Input HIGH Voltage +1165 | -870 | mV | -55C to +125C | Guaranteed HIGH Signal (Notes 5, 6, 7, for All Inputs 8) Vit Input LOW Voltage 1830 +1475 | mV | -55C to +125C | Guaranteed LOW Signal (Notes 5, 6, 7, for All Inputs 8) lit Input LOW Current 0.50 HA -58C to +125C | Veg = -4.2V (Notes 5, 6, 7) Vin = Vic (Min) www fairchildsemi.comDC Electrical Characteristics (continued) Vee = -4.2V to -5.7V, Veo = Veca = GND, To = -85C to +125C Symbol Parameter Min | Max | Units Te Conditions Notes la Input HIGH Current (Notes 5, 6, 7) MR 300 Dn 250 HA 0C to +125C Ez, Ep 520 Vee = -5.7V MR 450 Vin = Vin (Max) Dn 350 HA -55C Ea, Ey 750 lee Power Supply Current | -138 | -64 mA | -55C to +125C | Inputs Open (Notes 5, 6, 7) Note 5: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55'C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 6: Screen tested 100% on each device at -55C, +25C, and +125C, Subgroups 1, 2, 3, 7, and 8. Note 7: Sample tested (Method 5005, Table |) on each manufactured lot at -55C, +25C, and +125C, Subgroups A1, 2, 3, 7, and 8. Note 8: Guaranteed by applying specified input condition and testing VoH/VoL. AC Electrical Characteristics Vee = -4.2V to -5.7V, Veo = Veca = GND Symbol Parameter BS Se Te = +125C Units Conditions Notes Min Max | Min Max | Min Max teLy Propagation Delay TpHL D, to Output 0.45 1.50]0.50 140/050 1.50 ns (Transparent Mode) Figures 1, 2 teLy Propagation Delay 0.75 2.051075 185/075 2.05 ns (Notes 9, 10, 11) teu E,, E, to Output teLy Propagation Delay 0.80 240/090 240/090 2.60 ns Figures 1, 3 TPH MR to Output tty Transition Time 0.45 1.701)045 1.60] 0.45 1.60 ns . Figures 1, 2 tra 20% to 80%, 80% to 20% ts Setup Time Do-Ds 0.70 0.70 0.70 ns Figures 1, 2 MR (Release Time) 2.10 2.10 2.10 ty Hold Time, Do-Ds 0.70 0.70 0.70 ns Figure 4 (Note 12) tow(L) Pulse Width LOW 2.00 2.00 2.00 ns Figure 2 Ea, Ep tow(L) Pulse Width HIGH, MR 2.00 2.00 2.00 ns Figure 3 Note 9: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 10: Screen tested 100% on each device at +25'C, temperature only, Subgroup AQ. Note 11: Sample tested (Method 5005, Table |) on each Mfg. lot at +25C, Subgroup AQ, and at +125C, and -55C temp., Subgroups A10 and A11. Note 12: Not tested at +25C, +125C, and -55C temperature (design characterization data). 5 www fairchildsemi.comTest Circuit |_-+ 50 0 VEE Notes: Voc. Voca = +2V, Veg = -2.5V L1 and L2 = equal length 50Q impedance lines Ry = 50Q terminator internal to scope Decoupling 0.1 HF from GND to Veg and Veg All unused outputs are loaded with 500 to GND C, = Fixture and stray capacitance < 3 pF FIGURE 1. AC Test Circuit Switching Waveforms ENABLE TRANSPARENT LATCHED ~ n PULSE i\ i\ ., SCOPE GENERATOR UT Veo Vi CHAN A I I Rr MR Q E 20 = A a PULSE i\ 0 im SCOPE GENERATOR | \ 7 D @ LS CHAN B Rr Dso0g8s4- 0.7+0.1 ns +1.05 V TRANSPARENT {PHL {PLH teHL OUTPUT FIGURE 2. Enable Timing tTHL tTLH mee eee +0.31V +1.05V +0.31V jag PHL | tPLH ---s4 bso088s4-6 www fairchildsemi.com 6Switching Waveforms (continued) pom rn ee eee DATA ENABLE TRANSPARENT LATCHED TRANSPARENT t,(RELEASE TIME} MASTER RESET OUTPUT wow DS009884-7 FIGURE 3. Reset Timing DATA . ts th ENABLE DS009884-8 Notes: ts is the minimum time before the transition of the enable that information must be present at the data input. th is the minimum time after the transition of the enable that information must remain unchanged at the data input. FIGURE 4. Data Setup and Hold Time www fairchildsemi.comOrdering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 100350 D C QB TL Special Variation QB = Military grade device with Device Type environmental processing (Basic) Package Code . A D = Ceramic DIP shipped in tubes F = Flatpak Temperature Range P = Plastic DIP C = Commercial (0C to + 85C) Q = Plastic Leaded Chip Cartier (PCC) M = Military (55C to + 125C) bso0s8e4-11 Physical DimeNnSiONS inches (millimeters) unless otherwise noted 1.215 . {30.86} 0.025 MAX 0.030 0.055 (0.64) 24 13 (0.76 1.40) w F PAI PIP il RAD TYP 0.390 (9.91) MAX | ] It GAGA CA CI GA GA Gd God Ge a] 1 2 >| [> arte 0.005 GLASS 0.0500.060 B11. 0.400 0.430 0.180 oa) SEALANT \(1.271.62) P| [| [0.015 0.055, fr0.1610.92) (4.57) MIN TYP (0.38 1.40) Z ae T [ + 0.225 = rH y 8 ff MAX TYP | ; i \ 8694 A 109 ' so 100 __iat 0.008 0.012 NP TP =~ (0.20-0.30) 0.125 Tye 0.055 0.0900.110 _, | 0.0150.021 | (3.18) 0.435 0.535 (1.40) > (2.29 2.79) (0.38 -0.53) MIN (11.05 - 13.59) MAX TYP TYP TYP BOTH ENDS J24E (REV J) 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) Package Number J24E www fairchildsemi.com1.194-1.214 [30.33-30.84] 0.202 oA [5.13] 13 ee ee ee ee ee Physical DimensiON$ inches (millimeters) unless otherwise noted (Continued) g 0:035-0.045 [0,891.14] ND 0.337-0.347 [8.56-8.81] Q u LICL ULI UU U 1 12 PIN NO. 1 IDENT 9 0-125 [3.18] 0.125-0.135 4 0.060 0.039 [5.18-3.43] TYP me] pee 4X | be 0.390-0.410 [1.52] [0.99] 0.065 [9.91-10.41] pte 0.145-0.200 | | } g0-100 [3.68-5.08] | 86-94 0.020 0.125-0.140 , 4 [af meee MIN MIN L_ 9. . P [9.65] [0.51] [3.18-3.56] 1 0.047-0.087 0.040 047-0. 0.428 *0- 9.050 typ >| [1.19-1.45] =0.015 [1.27] [10.87 *1-02) 0.015-0.021 0.090-0.110 0.009-0.015 -0.38] : el TYP - [0.23-0.38] [0.38-0.53] [2.29-2.79] N24E (REV A) 24-Lead Plastic Dual-In-Line Package (P) Package Number N24E www fairchildsemi.comPhysical DimMeNnSiONS inches (millimeters) unless otherwise noted (Continued) +0.006 0.450 "hoo +0.15 ee IDENT 450 x 7 04e [1.14] 0.017#0.004 TYP 4 1 26 9.02940.003 ryp [0.43+0.10] a} [0.7440.08] | -| _ []25 a n f + H 0.4100.020 L [10.410.51] L] L] L]19 12 18 SEATING PLANE 1 0.050 typ | ne ja [1.27] | fa 9-020 in Typ 0.300 yyp [0.51] [7.62] 0.10540.015 ago y 0-045 [2.6740.38] [1.14] 0.165-0.180 TYP [4.19-4.57] a 0.490#0.005 [12.4540.13] TYP V2BA (REV K) 28-Lead Plastic Chip Carrier (Q) Package Number V28A aml www fairchildsemi.com100350 Low Power Hex D-Latch Physical DimensiON$ inches (millimeters) unless otherwise noted (Continued) 0.360 ~ 9.250 TYP > PIN ND. 1 N (MOLDED BODY) 0.370 MIN 0.360 TYP 9959 TYP {24 19 111 18 fz __ | 1 _ J 6 3> 7 12 0.018 | 0.075 MAX o.o1g TYP 8 PLCS 0.050 + 0.005 , TYP LIFE SUPPORT POLICY 0.400 MAX ___,,. | TYP GLASS 0.007 * I~ o.o04 TYP 0.050 Pl 01035 -~t 0.085 MAX W248 (REV Di 24-Lead Quad Cerpak (F) Package Number W24B FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, failure to perform when properly used with instructions for use provided in th be reasonably expected to result inas and (c) whose in accordance e labeling, can ignificant injury 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. to the user. Fairchild Semiconductor Fairchild Corporation Europe Semiconductor Americas Fax: +49 (0) 1 80-530 85 86 Customer Response Center Tel: 1-888-522-5372 Deutsch English Italy www fairchildsemi.com Email: europe.support@nsc.com Tel: +49 (0) 8 141-35-0 Tel: +44 (0) 1 793-85-68-56 Tel: +39 (0) 2 57 5631 Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, & Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: +852 2737-7200 Fax: +852 2314-0061 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.