CYPRESS SEMICONDUCTOR CbE D T4623 -52. we 258%bbe 0003433 1 CY7C132/CY7C136 CY7C142/CY7C146 RESS = SEMICONDUCTOR Features Functional Description @ 0.8 micron CMOS for optimum The CY7C132/CY7C136/CY7C142/ speed/power CY7C146 are high-speed CMOS 2K by 8 Automatic power-down dual-port static RAMS. Two ports are pro- TTL-compatible vided permitting independent access to any @ MASTER CY7C132/CY7C136 easily location in memory. The CY7C132/ CY7C136 can be utilized as either a stand- alone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7C142/CY7C146 SLAVE dual- port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit- slice, or multiprocessor designs. Each port has independent control pins; Chip Enable (CE), Write Enable (WE), and Capable of withstanding greater than 2001V electrostatic discharge Fully asynchronous operation expands data bus width to 16 or more bits using SLAVE CY7C142/CY7C146 BUSY output flag on CY7C132/ CY7C136; BUSY input on C7C142/CY7C142 INT flag for port-to-port communi- cation (LCC/PLCC versions) 2048 x 8 Dual-Port Static RAM Output Enable (OE). BUSY flags are. pro- vided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin LCC or PLCC versions. BUSY signals that the port is trying to access the same loca- tion currently be accessed by the other port. On the LCC/PLCC versions, INT is an inter- rupt flag indicating that data has been placed in a unique location by the other port. An automatic power-down feature is con- trolled independently on each port by the Chip Enable (CE) pin. The CY7C132/CY7C142 are available in both 48-pin DIP and 48-pin LCC, The CY7C136/CY7C146 are available in both 52-pin LCC and 52-pin PLCC. A die coat is used to insure alpha immunity. Logic Block Diagram Pin Configuration RA, RNa CE, CER OB BE, Ata Aton BUSYA(1} ars ARBITRATION e INTERRUPT Loalo CYCLE 132/0YCLE 136 ONLY INTu2, & INTa(2, 6) 0132-1 Notes: 1, CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor. CY77C142/CY7C146 (Slave): BUSY is input. 2. Open drain outputs; pull-up resitor required. Fant A ri az popPpSpRTTTTITTT 0132-2 2-66CYPRESS SEMICONDUCTOR 2bE D MM 2586%bbe p003434 3 __ CY7C132/CY7C136 Ss occ CY7C142/CY7C146 Ss & SEMICONDUCTOR Pin Configurations (continued) T-46-23-12 LCC Lcc Top View Top View 70132/70136 10142770148 SPeyPPresy ze sl S 3 132-3 Selection Guide Maximum Access Time (ns) Maximum O Commerical rating Current (mA Military Commerical Maximum Standby Current (mA) Military Shaded area contains preliminary information. Maximum Ratings c ee ooo ag sees as 7C132-35 7136-35 70142-35 7C0142-48 7C146-35 71C146-45 35 45 120 90 120 45 35 65 45 7132-45 710136-45 (Above which the useful life may be impaired. For user guidelines, not tested. ) Storage Temperature .......+004. teeee ~ 65C to + 150C Ambient Temperature with Power Applied ....cccccsseeesreneeaes - 55C to + 125C Supply Voltage to Ground Potential (Pin 48 to Pin 24) wicccssserseeeneeceenee -0.5V to + 7.0V DC Voltage Applied to Outputs in High Z State....... teceee eeeereseene -0.5V to + 7.0V DC Input Voltage... . cee cee eens eeeeees -3.5V to + 7.0V Output Current into Outputs (Low) .......eeecereeee 20 mA 132-4 7C132-55 70136-55 7C0142-55 7C146~55 55 90 120 35 45 Static Discharge Voltage ... sc. seccceene eee n ones >2001V (per MIL-STD-883, Method 3015) Latch-Up Current... scccescreeeeer sere sennees >200 mA Operating Range Ambient Range Temperature Veco Commercial 0C to + 70C SV + 10% Military) - 55C to + 125C SV + 10% 2-67CYPRESS SEMICONDUCTOR 2hE D MM 2589bb2 0003435 5 mm = CY7C132/CY7C136 Sse & SEMICONDUCTOR : : Electrical Characteristics Over the Operating Rangel4l T~46-23. 12 70132-35 | 7C132-45, 55 7C136-35 | 7C136-45, 55 7C142-35 | 7C142-45, 55 70146-35 | 70146-45, 55 Parameters Description Test Conditions Min. | Max. | Min. | Max. | Units Vou Output HIGH Voltage | Vcc = Min. lon = - 4.0 mA 2.4 2.4 Vv Vou Output LOW Voltage To, = 4.0 mA 04 0.4 Vv Tot = 16.0 mAb 0.5 0.5 Vint Input HIGH Voltage 2.2 2.2 Vv Vin Input LOW Voltage 08 0.8 Vv Ix Input Load Current GND <. Vi < Vcc -5 | #5 4} -5 +5 1 WA Toz Output Leakage GND. < Vo.s. Vcc; - +5 -5 +5 pA Current Output Disabled Tos Output Short Vec = Max, ~350 1-350 | mA Circuit Current! Vour = GND : Tee Vee Operating CE = Vin Com'l 120 90 | mA Supply Current Outputs Open, Mil 170 0 | mA Isa Standby Current CE, and CEp > Vin, Com'l 45 35 [mA Both Ports, TTL Inputs = fatax Mil 65 45 mA Isn2 Standby Current CE, and Cy > Vin Com! 90 75 | mA One Port, TTL Inputs putive Port Outputs Open, Mil iis 90 | mA Isp3 Standby Current Both Ports CE, and Com'l 15 18 | A Bac | REVO nputs in = Veco ~ 0.2V or ; Vin <.0.2V, f = 0 Mil 6 6 | ma Tspq Standby Current One Port CE, or Com! 85 7 | mA One Port, CMOS Inputs | CEg > Vee - 0.2V, Vin = Vec - 0.2V or - = Vin <.0.2V Mil 105 85 Active Ports Outputs Open mA . = ftax Shaded area contains preliminary information. Capacitancel Parameters Description Test Conditions Max. Units Cin Input Capacitance Ta = 25C, f = 1 MHz 10 pF Cour Output Capacitance Veo = 5.0V 10 pF Notes: 3. Ta is the instant on" cas temperature 9. tuzoe, tuzce, and tyzwe are tested with Cy = SpF as in part (b) of 4, See the last page of this specification for Group A subgroup testing AC Test Loads. Transition is measured + 500 mV form steady sfate oe AM information. BUSY and INT pins only. Duration of the short circuit should not exceed 30 seconds. Tested initially and after any design or process changes that may affect these parameters. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified Toy/To:, and 30-pF load capacitance. 10. 11. voltage. At any given temperature and voltage condition, tuzce is less than tuzce for any given device. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set- up and hold timing should be referencd to the rising edge of the signal that terminates the wrife.CYPRESS SEMICONDUCTOR ebE D MM 258%bbe 0003436 7 =>, CY7C132/CY7C136 iS Srreese CY7C142/CY7C146 == musa T-46-23-12 AC Test Loads and Waveforms . A14610 R1L4819, 5Y BY av i ve | 2800, $ R2 R2 oR 30 pF 3 265. 5 pF 2550. INT rune neue LE To SCOPE SCOPE 0192-8 = (a) (b) BUSY Output Load Equivalent to: THEVENIN EQUIVALENT 187: OUTPUT OW 9 1.73 Switching Characteristics Over the Operating Rangel**l Parameters Description READ CYCLE tre Read Cycle Time taa Address to Data Valid Data Hold from Address Change LOW to Data Valid LOW to Data Valid LOW to Low Z HIGH to High LOW to Low HIGH to High LOW to Power-Up HIGH to Power-Down Write Cycle Time LOW to Write End Address Set-Up to Write End | ta Address Hold from Write End | tsa Address Set-Up to Write Start tews Pulse Width tsp Data Set-Up to Write End tub Data Hold from Write End tuzwe LOW to High Z tezwe HIGH to Low Z Shaded area contains preliminary information. 2-69 ALL INPUT PULSES 7C132-35 7132-45 7C132-55 7C136-35 * 7C136-45 7C0136-55 7C142-35 7C142-45 7C0142-85 70146-35 71C146-45 7146-55 Min, | Max. | Min. | Max. | Min. | Max. 35 45 55 (CY7C130/CY7C131 ONLY) 0132-6CYPRESS SEMICONDUCTOR an PH itiec ebE D me 2549bbe 0003437 7 CY7C132/CY7C136 CY7C142/CY7C146 Switching Characteristics Over the Operating Range!*! (continued) Parameters Description BUSY/INTERRUPT TIMING LOW from Address Match HIGH from Address LOW from CE LOW HIGH from CE HI Port Set Up for Priority LOW after LOW HIGH after HIGH HIGH to Valid Data tala tana taic tac tes twa tano topo Write Data Valid to Read Data Valid Write Pulse to Data Delay twop INTERRUPT TIMING Set Time Set Time Set Time Reset Time!!! Reset 12] Reset to to Address to to to Address to Shaded area contains preliminary information. twins teins tins toinr taine tine Notes: 12, These parameters are measured from the input signal changing, until 15. the output pin goes to a high-impedance state. 16, 13, CY7C142/CY7C146 only. 17. 14, Awrite operation on Port A, where Port A has priority, leavesthedata 18, on Port Bs outputs undisturbed until one access time after one of the follwoing: 19. A. BUSY on Port B goes HIGH. B. Port B's address toggled, C. CE for Port B is toggted. D. WE for Port B is toggled, Switching Waveforms Read Cycle No, 1!5: 161 Either Port--Address Access T-46-23-12 7132-45 70136-45 7C142-45 10146-45 Min. | Max, 7C132-35 7C136-35 7142-35 7C146-35 Min. | Max. 70136-55 7C0142-55 7C146-55 Min. | Max. | Units 30 30 30 30 RApPRpRpaya WE is HIGH for read cycle, __ Device is continuously selected, CS = Vy, and OB = Vir, Address valid prior to or coincident with CE transition LOW. Data I/O pins enter high-impedance state, as shown when OB is held LOW during write. LCC version only. ! tae ADDRESS x ta b toa >| DATAOUT PREVIOUS DATA VALID > DATA VALID 2-70 0132-7CYPRESS SEMICONDUCTOR 2bE D MM 254%bbe 00034348 0 = an CY7C132/CY7C136 Sa iy Crores CY7C142/CY7C146 SS SEMICONDUCTOR Switching Waveforms (Continued) T-46-23-12 9{15, 17] Read Cycle No. Either PortCE/OE Access ts ff CE - tace He tizce > aS s KE tess Nae ESI LL LL LL x 2 DATA OUT CEE EEEL DATA VALID + ere) Ise 0132-8 Read Cycle No, 315 READ with BUSY : ADDRESS, ADDRESS MATCH RAWa Dina ADDRESS, ADDRESS MATCH 132-9 Write Cyle No.1! 18) Either Port two ADDRESS cs tewe RAV tsp DATAN DATA-IN VALID CE << thzoe HIGH IMPEDANCE Dour 2-71 132-10CYPRESS SEMICONDUCTOR PLE D MM 2589662 0003439 c = CY7C132/CY7C136 Bas 75 Cieness | _CY7C142/C7C146 Sear & SEMICONDUCTOR Switching Waveforms (Continued) T-46-23-12 Write Cycle No, 2{tt 18) Either Port two ADDRESS CE AW tsp tup DATA DATA VALID tLawe HIGH IMPENDANCE Dour 0132-11 Busy Timing Diagram No. 1 (CE Arbitration) CE, Valid First: ADDRESS, LAND R x ADDRESS MATCH x CEL tes CEa teLc i tayo 0132-12 CEg Valid First: ADDRESS, LAND R XxX CEa bs > ___ YF ADDRESS MATCH >.< CE, N tac - tee ~ =- 0132-13 2-72CYPRESS SEMICONDUCTOR SLE D mm@ 2589bb2 0003440 4 = -_ . CY7C132/CY7C136 = CYPRESS CY7C142/CY7C146 T-46-23-12 Switching Waveforms (Continued) Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: tac OR twe ADDRESS, ADDRESS MATCH ADDRESS MISMATCH KX ADDRESS, * >< {BLA tena BUSY, : 0132-14 Right Address Valid First: tac OR two ADDRESS, ADDRESS MATCH ADDRESS MISMATCH x at tos ADDRESS, x faa tana . BUSY, 132-15 Busy Timing Diagram No. 3 Write with BUSY (Slave: CY7C142/CY7C146) ! oe tw BUSY 132-16 2-73CYPRESS SEMICONDUCTOR See CY7C132/CY7C136 * See & CYPRESS => SEMICONDUCTOR _ Switching Waveforms (continued) T=46-23-12 Interrupt Timing Diagrams(! Left Side Sets INTa! two ADDRESS, WRITE 7FF oe, tins RAL INT Right Side Clears INTp: 0192-17 tec ADDRESS, READ 7FF ina CEA RW OER INTR 6132-48 Right Side Sets INT: two ADDRESS, WRITE 7FE tins CE, Wit Left Side Clears INTi: tao ADDRESS, READ 7FE CE, ft ta tun Sf tens wm. SITILI ILL LL 0132-19 7, CRQRRN AMMO / f town | 6132-20 2-74 2bE D MM 258%bbe oo03441 0 CY7C142/CY7C146CYPRESS SEMICONDUCTOR a = a Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 4 12 5 1.0 0.8 loo 06 0.4 NORMALIZED Ig, 0.2 Isa 40 45 5.0 5.6 SUPPLY VOLTAGE (V) 6.0 NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE NORMALIZED tag 5 2 8b BOR Ss 2 ao wo 6.0 > o 5.0 5.5 SUPPLY VOLTAGE (V) TYPICAL POWER-ON CURRENT vs, SUPPLY VOLTAGE NORMALIZED tec ys ep YY VY o wm oOo _ M7 8 2 a 0 1.0 SUPPLY VOLTAGE (V) 20 30 40 50 2bE D MM 258%bbe oo0344e c CY7C132/CY7C136 | CY7C142/CY7C146 T-46-23-12 NORMALIZED ACCESS TIME OUTPUT SOURCE CURRENT vs. AMBIENT TEMPERATURE 12 \ 310 < 8 o8 a 3 0.6 zz 04 Go =z 0.2 Ss 06 55 25 425 AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs, AMBIENT TEMPERATURE 16 $ 14 9 q 12 a = & 1.0 . 9 Veo = 5.0V 0.8 0.6 55 25 425 AMBIENT TEMPERATURE (C) TYPICAL ACCESS TIME CHANGE vs, OUTPUT LOADING 30.0 25,0 e 200 3 fE 160 410.0 50 Voc = 45.0 Ta = 25C 0 0 200 400 600 800 1000 CAPACITANCE (PF) 2-75 v3, OUTPUT VOLTAGE @ 120 ae % 100 & 5 80 oO We 60 ec 3 2 40 E 20 0 Oo "oC 1020 3.0 0 OUTPUT VOLTAGE (VY) OUTPUT SINK CURRENT ys, OUTPUT VOLTAGE z 140 = 120 Ke G i 100 a BQ 80 Z 60 n 5 40 5 Veg = 5.0V 3 2 Th = 25C 0 00. 10 20 OUTPUT VOLTAGE (V) NORMALIZED Icc vs. CYCLE TIME 1.25 T Voo = 45.0V Ta = 28C 8 Vin = 0.5V a 4.0 5 ea = - c 9075 - 0.50 10 20 30 40 CYCLE FREQUENCY (MHZ)CYPRESS SEMICONDUCTOR ebE D MM e589bbe 0003443 4 me =~ CY7C132/CY7C136 Sees 9 Fecse CY7C142/CY7C146 Ss F SEMICONDUCTOR : Ordering Information T-46~-23-12 Speed Package | Operating Speed Package | Operating (ns) Ordering Code Type Range (ns) Ordering Code Type Range 35 CY7C132-35PC P25 Commerical 35 CY7C142-35PC P25 Commerical CY7C132-35DC D26 CY7C142-35DC D26 CY7C132-35LC 168 CY7C142-35LC L68 CY7C132-35DMB D6 Military -CY7C142-35DMB D26 Military CY7C132-35LMB L68 CY7C142-35LMB L68 45 CY7C132-45PC P25 Commerical 45 CY7C142-45PC P25 Commerical CY7C132-45DC D26 CY7C142-45DC D26 CY7C132-45LC 168 CY7C142-45LC L68 CY7C132-45DMB D26__| Military CY7C142-45DMB D26 | Military CY7C132-4S5LMB L68 CY7C142-45LMB L68 55 CY7C132-5SPC P25 Commerical 55 CY7C142-55PC P25 Commerical CY7C132-55DC D26 CY7C142-55DC D26 CY7C132-55LC L68 CY7C142-55LC L68 CY7C132-55DMB D6 Military CY7C142-5SDMB D26 Military CY7C132-5SLMB L68 CY7Ci42-5SLMB 168 Speed Package | Operating Speed Package | Operating (ns) Ordering Code Type Range (ns) Ordering Code Type Range 35 | CY7C136-35LC L69 | Commerical 35 | CY7C146-35LC 169 | Commerical CY7C136-35C 169 CY71C146-351C 169 CY7C136-35LMB L69 | Military CY7C146-35LMB 169 _| Military 45 | CYIC136-45LC L69 | Commerical 45. | CY7C146-45LC 169 | Commerical CY7C136-451C 369 CY7C146-451C 369 CY7C136-45LMB L69 | Military CY7C146-45LMB L69 | Military 35 | CY7C136-S5LC L69 | Commerical 55 | CY7CI46-SSLC L69 | Commerical CY7C136-55C 169 CY7C146-S5IC L69 CY7C136-SSLMB 169 | Military CY7C146-55LMB L69 | Military Shaded area contains preliminary information. 2-76CYPRESS SEMICONDUCTOR ChE D MM 254%bbc DOO3444 & __ CY7C132/CY7C136 at ens - SSS 9 Crouss CY7C142/CY7C146 MILITARY SPECIFICATIONS T-46-23-12 Group A Subgroup Testing DC Characteristics Parameters Subgroups Vou 1,2,3 Vou 1,2,3 Vin 1, 2,3 Vit Max. 1,2,3 Tix 1,2,3 loz 1,2,3 Tos 1,2,3 - Tce 1, 2,3 Tsai 1, 2,3 Isn2 1, 2,3 Isa 1, 2,3 Tsps 1, 2,3 Switching Characteristics Parameters Subgroups Parameters Subgroups. READ CYCLE BUSY/INTERRUPT TIMING tre 7, 8,9, 10, 11 tata 7, 8, 9, 10, 11 taa 7,8, 9, 10, 11 toHa 7, 8,9, 10, 12 tona 7, 8, 9, 10, 11 tate 7, 8, 9, 10, 11 tacs 7, 8, 9, 10, 11 tauc 7, 8, 9, 10, 11 tpor 7, 8, 9, 10, 11 tes 7, 8, 9, 10, 11 WRITE CYCLE twins 7, 8,9, 10, 11 twe 7, 8,9, 10, 11 teins 7, 8, 9, 10, 11 tscH 7, 8, 9, 10, 11 tins 7,8, 9, 10, 1 taw 7, 8, 9, 10, 14 toinr 7, 8, 9, 10, 11 tua 7, 8,9, 10, 11 tenn 7,8, 9, 10, 11 tsa 7,8, 9, 10, 11 tinr 7, 8,9, 10, 11 tpwe 7,8, 9, 10, 14 BUSY TIMING tsp 7,8, 9, 10, 11 twat?! 7,8, 9, 10, 11 tuo 7,8, 9, 10, 11 twit 7,8, 9, 10, 11 tapp 7,8, 9, 10, 11 topp 7, 8,9, 10, 11 twop 7, 8,9, 10, 11 Note: . Document #: 38-00061-C 20. CY7C142 only.