FDS3992 Dual N-Channel PowerTrench(R) MOSFET 100V, 4.5A, 62m Features Applications * rDS(ON) = 54m (Typ.), VGS = 10V, ID = 4.5A * DC/DC converters and Off-Line UPS * Qg(tot) = 11nC (Typ.), VGS = 10V * Distributed Power Architectures and VRMs * Low Miller Charge * Primary Switch for 24V and 48V Systems * Low QRR Body Diode * High Voltage Synchronous Rectifier * Optimized efficiency at high frequencies * Direct Injection / Diesel Injection Systems * UIS Capability (Single Pulse and Repetitive Pulse) * 42V Automotive Load Control * Electronic Valve Train Systems Formerly developmental type 82745 Branding Dash (1) (8) (2) (7) (3) (6) (4) (5) 5 1 2 3 4 SO-8 MOSFET Maximum Ratings TA = 25C unless otherwise noted Symbol VDSS Drain to Source Voltage Parameter Ratings 100 Units V VGS Gate to Source Voltage 20 V Drain Current ID Continuous (TA = 25oC, VGS = 10V, RJA = 50oC/W) 4.5 A Continuous (TA = 100oC, VGS = 10V, RJA = 50oC/W) 2.8 A Pulsed EAS PD TJ, TSTG Figure 4 A Single Pulse Avalanche Energy (Note 1) 167 mJ Total Package Power Dissipation 2.5 W Derate above 25oC 20 mW/oC Operating and Storage Temperature o -55 to 150 C Thermal Characteristics RJA Thermal Resistance, Junction to Ambient at 10 seconds (Note 3) 50 o C/W RJA Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3) 85 oC/W RJC Thermal Resistance, Junction to Case (Note 2) 25 o C/W Package Marking and Ordering Information Device Marking FDS3992 (c)2004 Fairchild Semiconductor Corporation Device FDS3992 Package SO-8 Reel Size 330mm Tape Width 12mm Quantity 2500 units FDS3992 Rev. B1 FDS3992 August 2004 Symbol Parameter Test Conditions Min Typ Max Units V Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250A, VGS = 0V 100 - - - - 1 - - 250 VGS = 20V - - 100 nA V VDS = 80V VGS = 0V TC = 150oC A On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A 2 - 4 ID = 4.5A, VGS = 10V - 0.054 0.062 ID = 2A, VGS = 6V - 0.072 0.108 ID = 4.5A, VGS = 10V, TC = 150oC - 0.107 0.123 - 750 - pF - 118 - pF - 27 - pF - 11 15 nC - 1.4 1.9 nC - 3.5 - nC - 2.1 - nC - 2.8 - nC ns Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V VGS = 0V to 2V Qg(TH) Threshold Gate Charge Qgs Gate to Source Gate Charge Qgs2 Gate Charge Threshold to Plateau Qgd Gate to Drain "Miller" Charge Switching Characteristics VDS = 25V, VGS = 0V, f = 1MHz VDD = 50V ID = 4.5A Ig = 1.0mA (VGS = 10V) tON Turn-On Time - - 47 td(ON) Turn-On Delay Time - 8 - ns tr Rise Time - 23 - ns td(OFF) Turn-Off Delay Time - 28 - ns tf Fall Time - 26 - ns tOFF Turn-Off Time - - 81 ns V VDD = 50V, ID = 4.5A VGS = 10V, RGS = 27 Drain-Source Diode Characteristics ISD = 4.5A - - 1.25 ISD = 2A - - 1.0 V Reverse Recovery Time ISD= 4.5A, dISD/dt= 100A/s - - 48 ns Reverse Recovery Charge ISD= 4.5A, dISD/dt= 100A/s - - 65 nC VSD Source to Drain Diode Voltage trr QRR Notes: 1: Starting TJ = 25C, L = 37mH, IAS = 3A. 2: RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design. 3: RJA is measured with 1.0 in2 copper on FR-4 board (c)2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1 FDS3992 Electrical Characteristics TA = 25C unless otherwise noted 5 1.2 1.0 4 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER VGS = 10V 0.8 0.6 0.4 3 2 1 0.2 0 0 0 25 50 75 100 125 150 25 50 Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 100 125 0.1 150 Figure 2. Maximum Continuous Drain Current vs Ambient Temperature DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 1 ZJA, NORMALIZED THERMAL IMPEDANCE 75 TA , AMBIENT TEMPERATURE (oC) TA , AMBIENT TEMPERATURE (oC) RJA=50oC/W PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 0.001 10-5 10-4 10-3 10-2 10-1 100 t, RECTANGULAR PULSE DURATION (s) 101 102 103 Figure 3. Normalized Maximum Transient Thermal Impedance 200 IDM, PEAK CURRENT (A) TA = 25oC TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 100 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = 10V 150 - TC 125 10 1 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103 Figure 4. Peak Current Capability (c)2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1 FDS3992 Typical Characteristics TA = 25C unless otherwise noted FDS3992 Typical Characteristics TA = 25C unless otherwise noted 7 10s 10 100s 1 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms 100ms 0.1 SINGLE PULSE TJ = MAX RATED TC = 25oC IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 200 100 STARTING TJ = 25oC STARTING TJ = 150oC 1 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1s 0.01 0.1 1 0.1 10 100 300 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 5. Forward Bias Safe Operating Area 30 Figure 6. Unclamped Inductive Switching Capability 30 TA = 25oC 20 15 TJ = 10 VGS = 10V 25 ID, DRAIN CURRENT (A) ID , DRAIN CURRENT (A) NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 25 100 150oC TJ = 25oC TJ = -55oC 20 VGS = 7V 15 VGS = 6V 10 VGS = 5V 5 5 0 0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 3.5 4.0 4.5 5.0 5.5 6.0 VGS , GATE TO SOURCE VOLTAGE (V) 6.5 0 Figure 7. Transfer Characteristics 2.0 Figure 8. Saturation Characteristics 2.5 80 VGS = 6V NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE (m ) 0.5 1.0 1.5 VDS , DRAIN TO SOURCE VOLTAGE (V) 75 70 65 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 60 VGS = 10V 55 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 VGS = 10V, ID = 4.5A 0.5 50 1.0 1.5 2.0 2.5 3.0 3.5 ID, DRAIN CURRENT (A) 4.0 4.5 Figure 9. Drain to Source On Resistance vs Drain Current (c)2004 Fairchild Semiconductor Corporation -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature FDS3992 Rev. B1 FDS3992 Typical Characteristics TA = 25C unless otherwise noted 1.2 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250A 1.0 0.8 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) -80 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 CISS = CGS + CGD VGS , GATE TO SOURCE VOLTAGE (V) VDD = 50V 1000 C, CAPACITANCE (pF) 1.0 160 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature COSS CDS + CGD CRSS = CGD 100 1.1 0.9 0.6 2000 ID = 250A VGS = 0V, f = 1MHz 10 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 4.5A ID = 2A 2 0 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 13. Capacitance vs Drain to Source Voltage (c)2004 Fairchild Semiconductor Corporation 100 0 2 4 6 8 Qg, GATE CHARGE (nC) 10 12 Figure 14. Gate Charge Waveforms for Constant Gate Currents FDS3992 Rev. B1 FDS3992 Test Circuits and Waveforms BVDSS VDS tP VDS L IAS VDD VARY tP TO OBTAIN + RG REQUIRED PEAK IAS VDD - VGS DUT tP IAS 0V 0 0.01 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS = 10V VGS + VDD VGS - VGS = 2V DUT Qgs2 0 Ig(REF) Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 0 Figure 19. Switching Time Test Circuit (c)2004 Fairchild Semiconductor Corporation 10% Figure 20. Switching Time Waveforms FDS3992 Rev. B1 The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. (T -T ) JM A P DM = -----------------------------R JA maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. R 26 (EQ. 2) JA = 64 + ------------------------------0.23 + Area (EQ. 1) In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 4. The use of thermal vias. 200 5. Air flow and board orientation. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized ZJA, THERMAL IMPEDANCE (oC/W) 150 120 90 RJA = 64 + 26/(0.23+Area) RJA (oC/W) 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. 150 100 50 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) 10 Figure 21. Thermal Resistance vs Mounting Pad Area COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2 60 30 0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103 Figure 22. Thermal Impedance vs Mounting Pad Area (c)2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1 FDS3992 Thermal Resistance vs. Mounting Pad Area rev Aug 2002 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RSLC2 5 51 - Lgate 1 9 5.61e-9 Ldrain 2 5 1e-9 Lsource 3 7 1.98e-9 RLDRAIN RSLC1 51 Ebreak 11 7 17 18 108 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 DRAIN 2 5 EVTHRES + 19 8 + LGATE GATE 1 ESLC 11 50 RDRAIN 6 8 ESG DBREAK + .SUBCKT FDS3992 2 1 3 ; Ca 12 8 2.3e-10 Cb 15 14 3.5e-10 Cin 6 8 7.47e-10 EVTEMP RGATE + 18 22 9 20 21 EBREAK 16 + 17 18 - DBODY MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE RLSOURCE RLgate 1 9 56.1 RLdrain 2 5 10 RLsource 3 7 19.8 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD S1A 12 S2A 13 8 CA 17 18 RVTEMP S2B 13 CB 19 6 8 VBAT 5 8 EDS - IT 14 + + EGS Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 25.e-3 Rgate 9 20 3.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 20e-3 Rvthres 22 8 Rvthresmod 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD 15 14 13 S1B RBREAK - + 8 22 RVTHRES Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),2.5))} .MODEL DbodyMOD D (IS=2.4E-12 N=1.04 RS=13e-3 TRS1=2.1e-3 TRS2=4.7e-7 + CJO=5.5e-10 M=0.57 TT=3.25e-8 XTI=4.6) .MODEL DbreakMOD D (RS=1.6 TRS1=2.4e-3 TRS2=-1e-5) .MODEL DplcapMOD D (CJO=1.6e-10 IS=1e-30 N=10 M=0.54) .MODEL MmedMOD NMOS (VTO=3.8 KP=2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.7) .MODEL MstroMOD NMOS (VTO=4.35 KP=28 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3.26 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=37 RS=0.1) .MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1e-8) .MODEL RdrainMOD RES (TC1=1.15e-2 TC2=2.8e-5) .MODEL RSLCMOD RES (TC1=3.3e-3 TC2=1e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-4.8e-3 TC2=-1.1e-5) .MODEL RvtempMOD RES (TC1=-3e-3 TC2=1.5e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-3) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=1) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1 VOFF=-1.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1 FDS3992 PSPICE Electrical Model FDS3992 SABER Electrical Model REV Aug 2002 template FDS3992 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.4e-12,nl=1.04,rs=13e-3,trs1=2.1e-3,trs2=4.7e-7,cjo=5.5e-10,m=0.57,tt=3.25e-8,xti=4.6) dp..model dbreakmod = (rs=1.6,trs1=2.4e-3,trs2=-1.0e-5) dp..model dplcapmod = (cjo=1.6e-10,isl=10e-30,nl=10,m=0.54) m..model mmedmod = (type=_n,vto=3.8,kp=2.0,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.35,kp=28,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.26,kp=0.04,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-3.0,voff=-2.0) LDRAIN sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-3.0) DPLCAP 5 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=1.0) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.0,voff=-1.5) 10 RLDRAIN c.ca n12 n8 = 2.3e-10 RSLC1 51 c.cb n15 n14 = 3.5e-10 RSLC2 c.cin n6 n8 = 7.47e-10 DRAIN 2 ISCL dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod - RDRAIN 6 8 ESG EVTHRES + 19 8 + spe.ebreak n11 n7 n17 n18 = 108 spe.eds n14 n8 n5 n8 = 1 GATE spe.egs n13 n8 n6 n8 = 1 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 LGATE EVTEMP RGATE + 18 22 9 20 21 11 DBODY 16 MWEAK 6 EBREAK + 17 18 - MMED MSTRO RLGATE CIN 8 i.it n8 n17 = 1 LSOURCE SOURCE 3 7 RSOURCE RLSOURCE S1A l.lgate n1 n9 = 5.61e-9 l.ldrain n2 n5 = 1e-9 l.lsource n3 n7 = 1.98e-9 res.rlgate n1 n9 = 56.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 19.8 DBREAK 50 12 S2A 13 8 14 13 S1B CA m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS - 19 IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-1e-8 res.rdrain n50 n16 = 25e-3, tc1=1.15e-2,tc2=2.8e-5 res.rgate n9 n20 = 3.7 res.rslc1 n5 n51 = 1e-6, tc1=3.3e-3,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 20e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-4.8e-3,tc2=-1.1e-5 res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1.5e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/45))** 2.5)) } (c)2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1 JUNCTION th REV Aug 2002 FDS3992 Copper Area =1.0 in2 CTHERM1 TH 8 4e-4 CTHERM2 8 7 5e-3 CTHERM3 7 6 6e-2 CTHERM4 6 5 9e-2 CTHERM5 5 4 3e-1 CTHERM6 4 3 4e-1 CTHERM7 3 2 9e-1 CTHERM8 2 TL 2 FDS3992 SPICE Thermal Model RTHERM1 CTHERM1 8 RTHERM2 RTHERM1 TH 8 5e-1 RTHERM2 8 7 6e-1 RTHERM3 7 6 4 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 9 RTHERM7 3 2 15 RTHERM8 2 TL 23 RTHERM3 SABER Thermal Model RTHERM4 CTHERM2 7 CTHERM3 6 CTHERM4 2 Copper Area = 1.0 in template thermal_model th tl thermal_c th, tl { CTHERM1 TH 8 4e-4 CTHERM2 8 7 5e-3 CTHERM3 7 6 6e-2 CTHERM4 6 5 9e-2 CTHERM5 5 4 3e-1 CTHERM6 4 3 4e-1 CTHERM7 3 2 9e-1 CTHERM8 2 TL 2 5 RTHERM5 CTHERM5 4 RTHERM6 CTHERM6 3 RTHERM1 TH 8 5e-1 RTHERM2 8 7 6e-1 RTHERM3 7 6 4 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 9 RTHERM7 3 2 15 RTHERM8 2 TL 23 } RTHERM7 CTHERM7 2 CTHERM8 RTHERM8 tl CASE TABLE 1. THERMAL MODELS 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.0 in2 CTHERM6 3.2e-1 3.5e-1 4.0e-1 4.0e-1 4.0e-1 CTHERM7 8.5e-1 9.0e-1 9.0e-1 9.0e-1 9.0e-1 CTHERM8 0.3 1.8 2.0 2.0 2.0 RTHERM6 24 18 12 10 9 RTHERM7 36 21 18 16 15 RTHERM8 53 37 30 28 23 COMPONANT (c)2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM ActiveArrayTM BottomlessTM CoolFETTM CROSSVOLTTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM FPSTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM I2CTM i-LoTM Across the board. Around the world.TM The Power Franchise(R) Programmable Active DroopTM ImpliedDisconnectTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM POPTM Power247TM PowerSaverTM PowerTrench(R) QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TINYOPTOTM TruTranslationTM UHCTM UltraFET(R) VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I11