©2004 Fairchild Semiconductor Corporation
August 2004
FDS3992 Rev. B1
FDS3992
FDS3992
Dual N-Channel PowerTrench® MOSFET
100V, 4.5A, 62mΩ
Features
•r
DS(ON) = 54mΩ (Typ.), VGS = 10V, ID = 4.5A
•Q
g(tot) = 11nC (Typ.), VGS = 10V
• Low Miller Charge
•Low Q
RR Body Diode
• Optimized efficiency at high frequencies
• UIS Capability (Single Pulse and Repetitive Pulse)
Formerly developmental type 82745
Applications
• DC/DC converters and Off-Line UPS
• Distributed Power Architectures and VRMs
• Primary Switch for 24V and 48V Systems
• High Voltage Synchronous Rectifier
• Direct Injection / Diesel Injection Systems
• 42V Automotive Load Control
•Electronic Valve Train Systems
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDSS Drain to Source Voltage 100 V
VGS Gate to Source Voltage ±20 V
ID
Drain Current
4.5 A
Continuous (TA = 25oC, VGS = 10V, RθJA = 50oC/W)
Continuous (TA = 100oC, VGS = 10V, RθJA = 50oC/W) 2.8 A
Pulsed Figure 4 A
EAS Single Pulse Avalanche Energy (Note 1) 167 mJ
PD
Total Package Power Dissipation 2.5 W
Derate above 25oC20mW/
oC
TJ, TSTG Operating and Storage Temperature -55 to 150 oC
RθJA Thermal Resistance, Junction to Ambient at 10 seconds (Note 3) 50 oC/W
RθJA Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3) 85 oC/W
RθJC Thermal Resistance, Junction to Case (Note 2) 25 oC/W
Device Marking Device Package Reel Size Tape Width Quantity
FDS3992 FDS3992 SO-8 330mm 12mm 2500 units
SO-8
Branding Dash
1
5
2
3
4
(8)
(1)
(7)
(6)
(5)
(3)
(4)
(2)
©2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1
FDS3992
Electrical Characteristics TA = 25°C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics (VGS = 10V)
Drain-Source Diode Characteristics
Notes:
1: Starting TJ = 25°C, L = 37mH, IAS = 3A.
2: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. RθJC is guaranteed by design while RθCA is determined by the user’s board design.
3: RθJA is measured with 1.0 in2 copper on FR-4 board
Symbol Parameter Test Conditions Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 100 - - V
IDSS Zero Gate Voltage Drain Current VDS = 80V - - 1 µA
VGS = 0V TC = 150oC- - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V
rDS(ON) Drain to Source On Resistance
ID = 4.5A, VGS = 10V - 0.054 0.062
Ω
ID = 2A, VGS = 6V - 0.072 0.108
ID = 4.5A, VGS = 10V,
TC = 150oC- 0.107 0.123
CISS Input Capacitance VDS = 25V, VGS = 0V,
f = 1MHz
- 750 - pF
COSS Output Capacitance - 118 - pF
CRSS Reverse Transfer Capacitance - 27 - pF
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V
VDD = 50V
ID = 4.5A
Ig = 1.0mA
-1115nC
Qg(TH) Threshold Gate Charge VGS = 0V to 2V - 1.4 1.9 nC
Qgs Gate to Source Gate Charge - 3.5 - nC
Qgs2 Gate Charge Threshold to Plateau - 2.1 - nC
Qgd Gate to Drain “Miller” Charge - 2.8 - nC
tON Turn-On Time
VDD = 50V, ID = 4.5A
VGS = 10V, RGS = 27Ω
- - 47 ns
td(ON) Turn-On Delay Time - 8 - ns
trRise Time - 23 - ns
td(OFF) Turn-Off Delay Time - 28 - ns
tfFall Time - 26 - ns
tOFF Turn-Off Time - - 81 ns
VSD Source to Drain Diode Voltage ISD = 4.5A - - 1.25 V
ISD = 2A - - 1.0 V
trr Reverse Recovery Time ISD= 4.5A, dISD/dt= 100A/µs- - 48 ns
QRR Reverse Recovery Charge ISD= 4.5A, dISD/dt= 100A/µs- - 65nC
©2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1
FDS3992
Typical Characteristics TA = 25°C unless otherwise noted
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
0
1
2
3
4
5
25 50 75 100 125 150
ID, DRAIN CURRENT (A)
TA, AMBIENT TEMPERATURE (oC)
VGS = 10V
0.001
0.01
0.1
1
10-5 10-4 10-3 10-2 10-1 100101102103
2
t, RECTANGULAR PULSE DURATION (s)
ZθJA, NORMALIZED
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
PDM
t1
t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
THERMAL IMPEDANCE
RθJA=50oC/W
1
10
100
10-5 10-4 10-3 10-2 10-1 100101102103
200
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
VGS = 10V
TA = 25oC
I = I25 150 - TC
125
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
©2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1
FDS3992
Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics
Figure 9. Drain to Source On Resistance vs Drain
Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
Typical Characteristics TA = 25°C unless otherwise noted
0.01
0.1
1
10
100
1101003000.1
200
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
TJ = MAX RATED
TC = 25oC
SINGLE PULSE
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
10µs
100ms
10ms
1s
100µs
1ms
0.1
1
0.01 0.1 1 10 100
7
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
STARTING TJ = 150oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0
5
10
15
20
25
30
3.5 4.0 4.5 5.0 5.5 6.0 6.5
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = 150oC
TJ = 25oC
TJ = -55oC
0
5
10
15
20
25
30
0 0.5 1.0 1.5 2.0
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 6V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 5V
VGS = 7V
VGS = 10V
TA = 25oC
50
55
60
65
70
75
80
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
ID, DRAIN CURRENT (A)
VGS = 6V
VGS = 10V
DRAIN TO SOURCE ON RESISTANCE (m Ω)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.5
1.0
1.5
2.0
2.5
-80 -40 0 40 80 120 160
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 4.5A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
©2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1
FDS3992
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
Typical Characteristics TA = 25°C unless otherwise noted
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 160
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
THRESHOLD VOLTAGE
0.9
1.0
1.1
1.2
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ID = 250µA
BREAKDOWN VOLTAGE
10
100
1000
0.1 1 10 100
2000
C, CAPACITANCE (pF)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
2
4
6
8
10
024681012
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 50V
ID = 4.5A
ID = 2A
WAVEFORMS IN
DESCENDING ORDER:
©2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1
FDS3992
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS +
-
VDS
VDD
DUT
Ig(REF)
L
VDD
Qg(TH)
VGS = 2V
Qg(TOT)
VGS = 10V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
Qgs2
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
©2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1
FDS3992
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
(EQ. 1)
PDM
TJM TA
–()
RθJA
-------------------------------=
(EQ. 2)
RθJA 64 26
0.23 Area+
-------------------------------
+=
100
150
200
0.001 0.01 0.1 1 10
50
Figure 21. Thermal Resistance vs Mounting
Pad Area
RθJA = 64 + 26/(0.23+Area)
RθJA (oC/W)
AREA, TOP COPPER AREA (in2)
Figure 22. Thermal Impedance vs Mounting Pad Area
30
60
90
120
150
0
t, RECTANGULAR PULSE DURATION (s)
ZθJA, THERMAL
COPPER BOARD AREA - DESCENDING ORDER
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.00 in2
IMPEDANCE (oC/W)
10-1 100101102103
©2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1
FDS3992
PSPICE Electrical Model
.SUBCKT FDS3992 2 1 3 ; rev Aug 2002
Ca 12 8 2.3e-10
Cb 15 14 3.5e-10
Cin 6 8 7.47e-10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 108
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.61e-9
Ldrain 2 5 1e-9
Lsource 3 7 1.98e-9
RLgate 1 9 56.1
RLdrain 2 5 10
RLsource 3 7 19.8
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 25.e-3
Rgate 9 20 3.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 20e-3
Rvthres 22 8 Rvthresmod 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),2.5))}
.MODEL DbodyMOD D (IS=2.4E-12 N=1.04 RS=13e-3 TRS1=2.1e-3 TRS2=4.7e-7
+ CJO=5.5e-10 M=0.57 TT=3.25e-8 XTI=4.6)
.MODEL DbreakMOD D (RS=1.6 TRS1=2.4e-3 TRS2=-1e-5)
.MODEL DplcapMOD D (CJO=1.6e-10 IS=1e-30 N=10 M=0.54)
.MODEL MmedMOD NMOS (VTO=3.8 KP=2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.7)
.MODEL MstroMOD NMOS (VTO=4.35 KP=28 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.26 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=37 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1e-8)
.MODEL RdrainMOD RES (TC1=1.15e-2 TC2=2.8e-5)
.MODEL RSLCMOD RES (TC1=3.3e-3 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-4.8e-3 TC2=-1.1e-5)
.MODEL RvtempMOD RES (TC1=-3e-3 TC2=1.5e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-2)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-3)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=1)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1 VOFF=-1.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
©2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1
FDS3992
SABER Electrical Model
REV Aug 2002
template FDS3992 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.4e-12,nl=1.04,rs=13e-3,trs1=2.1e-3,trs2=4.7e-7,cjo=5.5e-10,m=0.57,tt=3.25e-8,xti=4.6)
dp..model dbreakmod = (rs=1.6,trs1=2.4e-3,trs2=-1.0e-5)
dp..model dplcapmod = (cjo=1.6e-10,isl=10e-30,nl=10,m=0.54)
m..model mmedmod = (type=_n,vto=3.8,kp=2.0,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.35,kp=28,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.26,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-3.0,voff=-2.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-3.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=1.0)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.0,voff=-1.5)
c.ca n12 n8 = 2.3e-10
c.cb n15 n14 = 3.5e-10
c.cin n6 n8 = 7.47e-10
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 108
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 5.61e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 1.98e-9
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 19.8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-1e-8
res.rdrain n50 n16 = 25e-3, tc1=1.15e-2,tc2=2.8e-5
res.rgate n9 n20 = 3.7
res.rslc1 n5 n51 = 1e-6, tc1=3.3e-3,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 20e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.8e-3,tc2=-1.1e-5
res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1.5e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/45))** 2.5))
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
©2004 Fairchild Semiconductor Corporation FDS3992 Rev. B1
FDS3992
SPICE Thermal Model
REV Aug 2002
FDS3992
Copper Area =1.0 in2
CTHERM1 TH 8 4e-4
CTHERM2 8 7 5e-3
CTHERM3 7 6 6e-2
CTHERM4 6 5 9e-2
CTHERM5 5 4 3e-1
CTHERM6 4 3 4e-1
CTHERM7 3 2 9e-1
CTHERM8 2 TL 2
RTHERM1 TH 8 5e-1
RTHERM2 8 7 6e-1
RTHERM3 7 6 4
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 9
RTHERM7 3 2 15
RTHERM8 2 TL 23
SABER Thermal Model
Copper Area = 1.0 in2
template thermal_model th tl
thermal_c th, tl
{
CTHERM1 TH 8 4e-4
CTHERM2 8 7 5e-3
CTHERM3 7 6 6e-2
CTHERM4 6 5 9e-2
CTHERM5 5 4 3e-1
CTHERM6 4 3 4e-1
CTHERM7 3 2 9e-1
CTHERM8 2 TL 2
RTHERM1 TH 8 5e-1
RTHERM2 8 7 6e-1
RTHERM3 7 6 4
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 9
RTHERM7 3 2 15
RTHERM8 2 TL 23
}
RTHERM6
RTHERM8
RTHERM7
RTHERM5
RTHERM4
RTHERM3
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
7
JUNCTION
CASE
8
th
RTHERM2
RTHERM1
CTHERM7
CTHERM8
TABLE 1. THERMAL MODELS
COMPONANT 0.04 in20.28 in20.52 in20.76 in21.0 in2
CTHERM6 3.2e-1 3.5e-1 4.0e-1 4.0e-1 4.0e-1
CTHERM7 8.5e-1 9.0e-1 9.0e-1 9.0e-1 9.0e-1
CTHERM8 0.3 1.8 2.0 2.0 2.0
RTHERM624181210 9
RTHERM73621181615
RTHERM85337302823
Rev. I11
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
ACEx™
ActiveArray™
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
EcoSPARK™
E2CMOS™
EnSigna™
FACT™
FACT Quiet Series™
FAST®
FASTr™
FPS™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
I2C™
i-Lo™
ImpliedDisconnect™
ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC®
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerSaver™
PowerTrench®
QFET®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
µSerDes™
SILENT SWITCHER®
SMART START™
SPM™
Stealth™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic®
TINYOPTO™
TruTranslation™
UHC™
UltraFET®
VCX™
Across the board. Around the world.™
The Power Franchise®
Programmable Active Droop™
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary First Production This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not In Production This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
