ANALOG DEVICES Ultrahigh Speed Pin Driver with Inhibit Mode AD1324 FEATURES 200 MHz Driver Operation Driver Inhibit Function 200 ps Edge Matching Guaranteed Industry Specifications 50 Output Impedance 2 V/ns Slew Rate Variable Output Voltages for ECL, TTL and CMOS High Speed Differential Inputs for Maximum Flexibility Hermetically Sealed Small Gull Wing Package APPLICATIONS Automatic Test Equipment Semiconductor Test Systems Board Test Systems Instrumentation & Characterization Equipment PRODUCT DESCRIPTION The AD1324 is a complete high speed pin driver designed for use in digital or mixed signal test systems. By combining a high speed monolithic process with a unique surface mount package, this product attains superb electrical performance while preserv- ing optimum packaging densities and long term reliability in an ultrasmall 16-lead, hermetically sealed gull wing package. Featuring unity gain programmable output levels of 2 V to +7 V with output swing capability of less than 100 mV to 9 V, the AD1324 is designed to stimulate ECL, TTL and CMOS logic families. The 200 MHz (2.5 ns pulsewidth) data rate capacity, and matched output impedance allows for real-time stimulation of these digital logic families. To test I/O devices, the pin driver can be switched into a high impedance state (inhibit mode) electrically removing the driver from the path, through the inhibit mode feature. The pin driver leakage cur- rent in inhibit is typically 50 nA, and output charge transfer. entering inhibit is typically less than 15 pC. The AD1324 transition from HI/LO or to inhibit is controlled through the data and inhibit inputs. The input circuitry is implemented utilizing high speed differential inputs with a common-mode range of 3 volts. This allows for direct interface FUNCTIONAL BLOCK DIAGRAM PACKAGE LID to the precision of differential ECL timing or the simplicity of stimulating the pin driver from a single ended TTL or CMOS logic source. The analog logic HI/LO inputs are equally easy to interface. Typically requiring 15 A of bias current, the AD1324 can be directly coupled to the output of a digital-to- analog converter. The AD1324 is available in a 16-lead, hermetically sealed gull wing package and is specified to operate over the ambient com- mercial temperature range from 0C to +70C.AD1324 SPECIFICATION (All measurements made in free air at +25C. Output load 10 k92/6 pF with +V, = +10 V, V, = 5.2 V unless otherwise specified) AD1324KZ Parameter Min Typ Max Units Comments DIFFERENTIAL INPUT CHARACTERISTICS _ D to D, INH to INH Input Voltage, Any Input 3.0 +5.5 Volts r Differential Input Range 0.4 ECL 3.0 Volts Bias Current 1350 +200 +500 pA REFERENCE INPUTS See Note 1 Vincu Range (Vy) 2.5 +75 Volts Viow Range (V,) 2.5 +7.5 Volts Bias Currents 40 +15 40 pA Bias Current Change 2 10 pA See Note 2 OUTPUT CHARACTERISTICS See Notes 1, 3 Logic High Range 1.6 +7.0 Volts Logic Low Range 2.0 +6.6 Volts Amplitude [VyV,]} 0.4 +9.0 Volts Accuracy Initial Offset 200 +200 mV Gain Error 3.0 -1.0 0.0 % of Vser Linearity Error See Note 4 -10Vto +5.6V (0.2% + 10) (0.2% + 10) % of Ven7 + mV] Vy. -1.0V to +6.0V (0.2% + 10) (0.2% + 10) % of Vere + mV! Vy -2.0V to -1.0V (0.2% + 40) (0.2% + 40) % of Venx + mV | V,, Viz +6.0 V to +7.0V (0.2% + 40) (0.2% + 40) % of Vopyp + mV | Vy +5.6Vt0 +7.0 V (0.2% + 40) (0.2% + 40) % of Veep + mV | VV, Output Voltage Drift 0.5 mV/C Current Drive Static 30 mA Dynamic 100 mA See Note 5 Current Limit 35 85 mA Output to GND Output Resistance 48.5 50.0 51.5 Q See Note 6 Leakage Current in Inhibit Mode -1Vto +6V 1 +0.25 +1 pA T, = 95C + SC; See Note 7 -2Vto+7V 10 +10 pA T, = 95C + 5C; See Note 7 DYNAMIC PERFORMANCE See Note 8 Driver Mode Delay Time 0.9 1.2 1.5 ns See Note 9 Prop Delay TC 1.0 ps/C Delay Time Matching Edge-to-Edge | 0 50 250 ps Rise & Fall Times See Note 10 1 V Swing 0.4 0.6 0.8 ns Measurement 20%-80% 2 V Swing 1.0 1.2 1.4 ns Measurement 10%-90% 3 V Swing 1.4 1.7 2.0 ns Measurement 10%-90% 5 V Swing 2.3 2.6 2.9 ns Measurement 10%-90% 9 V Swing 5.5 6.5 ns Measurement 10%-90% Toggle Rate 200 MHz ECL Output Large Signal Slew Rate 1.5 V/ns Minimum Pulsewidth, Vou = 2 V 2.0 ns See Figure 11 Overshoot & Preshoot 1Vtw7V (3% Vo) 50 +(3%Vo) +50 | mV % of Vout Swing; See Note 11 Settling Time 1Vto7 V, 0% X Vo) 15S ns See Note 11 Delay Time vs. PW 100 ps See Note 12 DYNAMIC PERFORMANCE Inhibit Mode Delay Time See Note 13 Drive-to-Inhibit 1.0 1.3 1.6 ns Inhibit-to-Drive 1.4 1.9 2.4 ns Delay Time Matching | Edge-to-Edge 0 100 400 ps 1 V Swing Overshoot & Preshoot 300 mV Output Capacitance 3.5 5 pF Output Charge Going into Inhibit Mode 5 pCAD1324 AD1324KZ Parameter Min Typ Max Units Comments POWER SUPPLIES Vz to + V, Range 18.2 15.6 Volts Supply Range See Note 14 Positive Supply +8.0 +10.0 +11.0 Volts Negative Supply 7.2 -5.2 -4.2 Volts Current Positive Supply 42 82 100 mA Negative Supply 100 82 42 mA PSRR 5 20 mvV/V +Vs, Vg = +2.5% NOTES 'The output voltage range is specified for 2 V to +7 V for typical power supply values of 5.2 V and +10.0 V but can be offset for different values of Vou such as 1 V to +8 V or 4 V to +5 V as long as the required headroom of 3 V is maintained between both V,, and +V, and V, and V,. 2V,, and V,, inputs have internal buffers which reduce the input bias current requirements. These buffers also reduce the amount of bias current change when the output switches logic levels. *V,, Must remain at least 400 mV more positive than V,, for specified performance. V,, may be as much as 5 V more negative than V,, with degraded performance. *Linearity testing is performed in 1 V increments over the following ranges: V, Linearity: V,, fixed at +7.0 V, V, = 2.0 V to +6.6 V; V,, Linearity: V, fixed at 2.0 V, Vy = 1.6 V to +7.0 V. Linearity error includes the error due to interaction for a minimum amplitude of 400 mV. Interaction error testing is performed with V,, = 0.6 V, V, = 1.0 V and with V,, = +6.0 V, V, = +5.6 V. *Transient output current can easily exceed the AD1324s steady-state current limit when driving capacitive loads. The transient output current capability can be increased by connecting 0.039 wF capacitors between Pin 5 and +V, and between Pin 6 and Vs. This will prevent the driver from current limiting by providing the edge current necessary when driving capacitive loads. These capacitors will not affect the drivers de current limit. Driver output impedance is 50 for a 3 V p-p signal into a 50 2 load. 7While in inhibit mode, the output voltage must not go more than 6 V above Ving or 6 V below V, ow. The driver output has 2 ns length of 50 2 coaxial cable attached with a 10 kO/6 pF probe, 1 GHz bandwidth or equivalent at the far end. *Delay times are measured from the crossing of differential ECL levels at the input to the 50% point of an 800 mV driver output with V,, and V, set at +400 mV, respectively. : 'ORise and fall time performance guaranteed over the output range of +V, 4 V to -~V, +4.2 V except for 9 V swing, which is measured over the output range of +V, 3 V to V, + 3.2 V. "Due to uncontrolled inductances in the test socket, overshoot, preshoot and settling time cannot be 100% tested. These characteristics are guaranteed by characterization data . Delay matching vs. PW is defined as the amount of change in propagation delay, with respect to the leading edge, due to change in pulsewidth of the input signal. The specification applies over the pulsewidth range of 2.5 ns to 100 ns. Inhibit mode delay times are measured from the crossing of differential (ECL) INH inputs to a 200 mV crossing at the pin drivers output connected to 2 ns length of 50 9 coaxial cable. The cable is terminated to ground through a 50 2 resistor. The measurement is made at the 50 resistor to GND with a 10 kQ/6 pF scope probe. 4A supply range of 15.2 V must be maintained to guarantee a 9 V output swing. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* NOTES Power Supply Voltage *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional +VstoGND 1.1. eee ete +13V operation of the device at these or any other conditions above those indicated ~V5 to GND 2... eee 8.2V in the operational sections of this specifications is not implied. Exposure to Difference from +V.5 to Vg oe ee es 16 V absolute maximum rating conditions for extended periods may affect device Inputs to eat lead 1 ity (+0.002 inches) and solderability handli ith : KR o ensure lead coplanarity (+0. inches) and solderability handling wi Difference from D toD os sees eee eee 4.75 V bare hands. should be avoided and the device should be stored in an Difference from INH toINH .....-.---.--++--- 4.75 V environment at 24C, +5C (75F, +10F) with relative humidity not to exceed D, D, INH, INH ......... +V, - 13 V, -Vs + 11.5 V 65%. Ve toVyE Coe ee eee -1V,+9V Vip VE ee +V_, 13.2 V, -Vs + 13.2 V Driver Output ORDERING GUIDE Voltage... 0.2... ee eee +V_, 13.2 V, -Vs + 13.2 V Short Circuit to GND .........0... 000002 Indefinite Temperature oo Package Operating Temperature Range............. 0C to +70C Model Range Description Option Storage Temperature Range ........... 65C to +125C AD1324KZ 0 to +70C 16-Lead Z-16A Lead Temperature Range (Soldering 20 sec)' ....... +300C Gull Wing *For outline information see Package Information section.AD1324 AD1324 TOP VIEW (Not To Scale) on oun &B wn = CONNECTION DIAGRAMS Dimensions shown in inches and (mm). PIN DESCRIPTION SUGGESTED LANDING PADS LOCATION Cc) cot 0.050 (1.27) Cc f a co co co L0.540 (13.71) >| | 0.710 (18.03) AD1324 0.025 (0.63) [uote Pin No. Symbol Function 1 GND Circuit Ground 2 N/C No Connection 3 Vout Driver Output 4 N/C No Connection 5 Cy. Positive Decouple 6 Cy_ Negative Decouple 7 VL Voltage Logic Low 8 GND Internal Ground* 9 LID Lid Connection* 10 Vu Voltage Logic High 1 D Driver Input 12 D Driver Input 13 INH Inhibit Input 14 INH Inhibit Input 15 -Vs Negative Supply 16 +V5 Positive Supply *It is recommended to connect Pins 8 and 9 to Circuit Ground.Definition of TermsAD1324 OFFSET ERROR The offset error for logic high is determined by holding the out- put of the driver at logic high, and applying zero volts to the logic high reference input. The driver output value represents the offset high error. The same approach is used to identify offset low error. Vincu orrseT = Vout where: Vy = 0V D = HIGH D = LOW INH = LOW INH = HIGH GAIN ERROR Defined as the ratio of the drivers output voltage to its logic set level voltage and is expressed in terms of percent of set level. The gain error is typically seen as 1.0% and is always in the negative direction with respect to the logic set level. Vour Va VuicH oFFsET Vuicy Gain (%) = rn x 100 where: Vy = 5.0 V+Vuicu oF set D = HIGH D = LOW INH = LOW INH = HIGH LINEARITY ERROR The deviation of the transfer function from a reference line. For the AD 1324, the linearity error is calculated by subtracting the worst case gain error from the best case gain error (for the speci- fied range) and dividing the result by two. This method guaran- tees that the maximum linearity error for any set level within the specified range will be within the specified limits. , ; Vaicu caw (max) Vic Gar (mun! Vaien uixearrry (%| = 2 09 DELAY TIME The amount of time it takes the input signal to propagate through the driver and be converted to the desired logic levels. The measurement technique is defined in the notes and is shown in Figure 2. EDGE-TO-EDGE MATCHING Edge-to-edge matching is the difference, in time, between the delay time of the rising edge and the falling edge. MINIMUM PULSEWIDTH Defined as the smallest pulse applied to the input of the driver which can maintain an output signal amplitude of 2 V. The minimum pulsewidth is measured at the 50% point of the waveform. OVERSHOOT AND PRESHOOT The amount by which the drivers output voltage exceeds the desired set voltage. Preshoot is similar to overshoot but is the amount by which the drivers output goes above or below the initial voltage when driving to the new set level (or inhibit mode). See Figure 3. IDEAL TRANSFER CURVE OFFSET & GAIN ERROR REMOVED 65V tee rrr GAIN OFFSET ERROR REMOVED CURVATURE = ERROR LINEARITY ERROR UNCOMPENSATED OUTPUT Vout v (NOT TO SCALE) OFFSET QZ ERROR 6.5V Vy (Vy = OV) WHERE Voyz = Veer = [OFFSET ERROR|- GAIN ERROR = LINEARITY ERROR Figure 1. Definition of Terms ,__X x D Von = +400mV Vo_= 400mVv _ / SN L INH ' Von = +1V z a INHIBIT MODE DELAY TIME Vot=-1V Figure 2. Timing Diagram for Driver and Inhibit Propagation Delay +3% (Voyr) +50mV* OT ~~} 41% Mayr) OVERSHOOT FINAL VALUE DX ERROR 7 OTS BAND -3% (Voy7 } -50mVv* r ew 7 Oe | -1% our) +3% (Vout ) +50mVv* f es See +1% (Vout) PRESHOOT || foo 0 UDR ERROR INITIAL VALUE BAND l o AV cenmys U(r LAA 73% our) 60m" 49% Wound <__ 15ns __> ra 500ns ad *LIMITS ARE =300mV FOR INHIBIT MODE OVERSHOOT AND PRESHOOT Figure 3. Definition of Waveform AberrationsAD1324Typical Performance 1.25 1.23 a RISING EDGE e 1.21 I % 1.19 wo4147 3 115 a 1.13 < a 4.41 9 FALLING EDGE a 4.09 . 1.07 1.05 0 25 70 AMBIENT TEMPERATURE - C Figure 4. Driver Propagation Delay vs. Temperature 30 TI Ty=0C + 20 ~ y | | > Ty = 25C ~ 10 - s WN | > b oO Pam =Tt= 4.5 2 bi oe = S | | IN \ #10 r_ 3 Ty = 70C > -20 -30 Vuien SET LEVEL - Volts Figure 7. Change in Vig over Temperature 75 a+ DRIVER OUTPUT VOLTAGE - Volts 1 Ld a 10ns/DIV Figure 10. Vou7 = 9 V as Seen at the End of a 50 ns, 50 2 Cable a ~ 8 A PROPAGATION DELAY (tpat -tpar) - PS wn o 2 Oo o 25 70 AMBIENT TEMPERATURE - C Figure 5. Propagation Delay Edge Matching vs. Temperature 70 50 40 Fs 30 20 10 Ta =70C I -4-5-6-7 Vout -VorrseT 15MV-Vger Viow SET LEVEL - Volts Figure 8. Change in V, ow over Temperature 25 DRIVER OUTPUT VOLTAGE - Volts 2.5 2ns/DIV Figure 11. Minimum (Data) Pulse- width as Defined by Vour = 2 V, 50% Crossing = 2ns 1.35 o L Cc 1 1.30 LJ > rh s ~~ Ww Oo 3 1.25 = 4 SG 2 o 2 1.20 a 1.15 65 ss_ | 2 20 40 60 80 100 1000 1500 DRIVER INPUT SIGNAL PULSEWIDTH - ns Figure 6. Propagation Delay vs. Input Signal Pulsewidth DRIVER OUTPUT VOLTAGE - Volts 2ns/DIV Figure 9. 10 ns Output Pulse at 1V,3Vand5V Vser Va ViNHIBIT Cp = TL Cparasitic + CproBE Q = (Cp + Copier) * Va Figure 12. Charge into Inhibit Test SetupAD1324 +7V TO -2V ADJ REF + @ out1 PP . = PULSE 10216 10216 GENERATOR a 100MHz OUT2) |ro216 10216 C d > > > % 3333 2322 x= 0.01 uF o = (8) 3300 J NOTES -52V 1, PULSE GENERATOR OUTPUT LEVELS TO BE -0.8V TO -2.0V. 2. ALL SCOPE PROBES TO BE 10k2, eee. 3pF, 300MHz BANDWIDTH. 3. SCOPE BANDWIDTH 300MHz. 4. FIXTURE REQUIRES GROUND PLANES. 5. SEE PARAGRAPH ON LAYOUT CONSIDERATIONS. Figure 13. AD1324 Test Setup FUNCTIONAL DESCRIPTION The AD1324 is a complete high speed pin driver designed for use in general purpose instrumentation and digital functional test equipment. The purpose of a pin driver is to accept digital, analog and timing information from a system source and com- bine these to drive the device to be tested. PACKAGE AD1324 Figure 14. AD1324 Block Diagram The circuit configuration for the AD1324 is outlined in Figure 14. Simply stated, a pin driver performs the function of a pre- cise, high speed level translator with an output which can be disabled. The AD 1324 accepts differential digital information utilizing a high speed differential design on the D and INH inputs providing precise timing at logic crossover and high noise immunity. The wide input voltage range allows for ECL opera- tion with power supplies at 0 to 5.2 V, +2 V to 3.2 V or +5 V to 0 V. Where timing is less critical TTL or CMOS logic levels may be used to toggle the AD1324. By biasing the D and INH inputs to approximately +1.3 V for TTL and 1/2 Ve for CMOS, the D and INH inputs can be directly driven from these single-ended output sources. The output of the pin driver will follow the logic state of the D input providing the INH input is low. When inhibit is asserted the output is disconnected and any activity on the input does not affect the output. Analog information is provided to the pin driver through the Vy and V, terminals as reference voltages. These analog voltages are buffered internally using unity gain followers. The resulting gain and linearity errors are provided in the specification table. System timing requirements are achieved through a specified 1.2 ns, +300 ps driver propagation delay, defined preshoot and overshoot, and a dynamically trimmed 50 2 output impedance.AD1324 LAYOUT CONSIDERATIONS While it is generally considered good engineering practice to capacitively decouple the power supplies of an active device, it is absolutely essential for a high power, high speed device such as the AD1324. The engineer merely has to consider the current pulse demand from the power supply when a dynamic current change of 100 mA to +100 mA is required in only a few nano- seconds. Therefore, a 470 pF high frequency decoupling capaci- tor must be located within 0.25 inches of the +V. and Vsz terminals to a low impedance ground. A 0.1 wF capacitor in parallel with a 10 pF tantalum capacitor should also be situated between the power supplies and ground. However, the proxim- ity to the device is less critical assuming low impedance power supply distribution techniques are employed. Circuit perform- ance will be similarly enhanced and noise minimized by locating a 470 pF capacitor as close as possible to Vz, V,, and connect- ed to ground. Bypass considerations have been summarized in Figure 15. Lot : 470pF = 0.1,F T 10uF @& T > T 470pF G) T # COMMON T 470pF @ 2 > Ve + 470pF T T O.1uF T 10UF (15) 4 > \G Figure 15. Basic Circuit Decoupling An equally important consideration is the use of microwave stripline techniques on the output of the AD1324. Failure to preserve the 50 output impedance of the pin driver will result in unwanted reflections, ringing and general corruption of the wave shape. Care should be exercised when selecting etch widths and routing, wire and cable to the device to be tested, and in choosing relays if they are required. THERMAL CONSIDERATIONS The AD1324 is provided in a 0.450" x 0.450", 16 lead (bottom brazed) gull wing, surface mount package with a typical junction- to-case thermal resistance of 17.5C/W. Thermal resistance 9.4 (case to ambient) vs. air flow for the AD1324 in this package is shown in Figure 16. The improvement in thermal resistance vs. air flow begins to flatten out just above 400 lfm! 2. NOTES ifm is air flow in Linear Feet/Minute. ?For convection cooled systems, the minimum recommended airflow is 400 lfm. 70 qt Oo = 60 wi Mm 3 AN < MN Ee NY 2 a> 50 a> a AD1324 PCB PY 3 rm z MOUNTED tL | z= 40 0 80 160 240 320 400 480 560 640 720 800 AIR FLOW - Linear Feet/Minute Figure 16. Case-to-Ambient Thermal Resistance vs. Air FlowAD1324 APPLICATIONS The AD1324 has been optimized to function as a pin driver in an ATE test system. Shown in Figure 18 is a block diagram illustrating the electronics behind a single pin of a high speed digital functional test system with the ability to test I/O pins on logic devices. The AD1324 pin driver, AD1317 high speed STORED DATA & INHIBIT PATTERN dual comparator, AD 1315 active load, and the AD75069 octal 12-bit voltage DAC would comprise the pin electronic portion of the test system. Such a system could operate at 200 MHz in a data mode or 100 MHz in the I/O mode, yet fit into a neat trim package. INH zs PERIOD GENERATION & OELAY TIMING Y DELAY VY WIDTH DELAY FORMATTER DC PARAMETRICS | Vu AD1324 INH a. K S < l"_ vy Zs STORED COMPARE DATA & DON'T CARE DATA WIDTH EXP DATA ZS A075069 OCTAL 12-BIT DAC MASK COMPARE REGISTER 4 AA VL A > Oo o _ N aN SYSTEM BUS > AD842 AD1315 Figure 17. High Speed Digital Test System Block DiagramAD1324 AD1324 EVALUATION BOARD Introduction The AD1324EB evaluation board was developed to aid in quickly evaluating the performance of the AD1324. Included is complete documentation of the evaluation board along with sug- gestions on equipment to use and measurement limitations. Overview The AD1324 is a high speed pin driver used in automatic test equipment The device has true differential inputs for both the drive and inhibit which can be driven from either TTL or ECL logic levels (ECL is recommended). Standard ECL design and layout techniques should be used. The device runs from dual power supplies +10 V and 5.2 V. It is very important that these power supplies are decoupled properly at the device pin. (High frequency oscillations will cou- ple through to the device output.) INHIBIT IN _ The reference input pins are dc inputs; therefore they also should be decoupled properly. The reference input range is -2Vt0+7V. The output slew rate is 2 V/ns for large signals and has a repeti- tion rate for an ECL level of 200 MHz minimum. Equipment The Drive and Inhibit inputs should be driven with standard ECL levels. If the full performance of the AD1324 needs to be evaluated, the generator must be able to supply an ECL level at frequencies greater than 200 MHz. Motorolas MC10216 is used on the evaluation board to simulate the actual application. Vg, is used on the MC10216 as the logic reference and the outputs have 330 ohm pulldowns to Vir. Five power supplies are required: DUT_Vc-c, DUT_Veg, Viricu Vow and ECL_Vypz. DUT_Vec requires +10 V at 100 mA minimum; DUT_Vgrr requires 5.2 V at 100 mA mini- mum; ECL _Vrp requires 5.2 V at 150 mA minimum. Ving and V,; ow require 2 V to +7 V at 5 mA (each). INHIBIT N >____4p > 4p > INHIBIT_COMP _]_ AA VV = MC10216 = < AAA v A Vv wn oe > CABLE_TERM rc [1] eno +Veg [16 } q DUT Voc > Vout SMA Nc - 15 | qo CABLE_TERM _L. @m~< oz} Ves [15] q DUT Vee SMA = GND p> ne [3] Vour inn [74] OUT a} NC apig2q iN [13}+ 0.039.F PIN DUT Vcc |] c:. river oRIVE [12H 0.039uF DUT_Veg >_{}_{E | Cy DRIVE 11} VLow VingH [10 GND LID fo}5 ECL_Vee P = ViiGH <s < . DATA IN I as S = 330-4 DATA_COMP 44 ~ 4> \- 4> > T eo Ves i Ly oa NOTES: HALF-MOON CONNECTORS CAN BE CONNECTED OR DISCONNECTED AS REQUIRED... 4> DECOUPLING CAPS ARE NOT SHOWN ON THIS SCHEMATIC, BUT THE BOARD USES 0.11.F AND 470pF CAPS TO DECOUPLE THE Voc. Veg. Vow AND Viigh SUPPLIES. SMA CONNECTORS @ PROBE JACKS > BNC CONNECTORS @ Figure 18. AD1324EB Evaluation Board Schematic -t0-AD1324 The output performance of the pin driver can only be measured properly with a scope which has the proper bandwidth for the required application. The input impedance and the bandwidth of the scope probe should be taken into consideration when evaluating the performance of the device. The resultant band- width of the system is the rms value of the components in the system. The characterizations performed by Analog Devices were per- formed using the following equipment: Tektronix 11402 main- frame (1 GHz BW), P6203 probe (1 GHz, 2 pF, 10 k), and 11A71 plug-in (1 GHz BW, 50 Q). The Hewlett-Packard 54120 and 54110 were also evaluated with 500 Q, 1.2 pF passive probes and the Data Precision 6100 with their model 640 FET probe (50 kQ., 4 pF). When measuring the performance of waveforms close to or exceeding the bandwidth of a scope, it is not uncommon for the results between scopes to be different because of aberrations and slew rates. DC POWER SUPPLIES (4) RANGE: RANGE: RANGE: RANGE: RANGE: -2V TO +7V AT -2V TO +7V AT -5.2V NOMINAL +10V NOMINAL, 100mA -5.2V NOMINAL <5mA <5mA 100mA MINIMUM MINIMUM 150mA MINIMUM -9 o+ -9 o+ -9 o+ -9 ot -9 O+ I \ 4 | 7 | 200MHz Vuieu Viow DUT_Veg OUTVoc GND ECL_Veg MINIMUM O DATA_IN RECOMMENDED Your O- 4 BANDWIDTH: 1GHz MINIMUM O 100MHz | INHIBIT_IN OSCILLOSCOPE MINIMUM PULSE GENERATORS CONNECTORS ON AD1324 EVALUATION BOARD: (2) 1. OC POWER SUPPLIES: FEMALE BANANA JACKS 2. PULSE GENERATORS: FEMALE BNC CONNECTORS 3. OSCILLOSCOPE: FEMALE PROBE SOCKET (TEKTRONIX p/n: 131-0258-00) Figure 19. AD1324EB Evaluation Board Connections -11-