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White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
GENERAL DESCRIPTION
The 256MByte (2Gb) SDRAM is a high-speed CMOS,
dy nam ic ran dom-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally confi gured as a
quad-bank DRAM with a syn chro nous interface. Each of
the chip’s 134,217,728-bit banks is or ga nized as 8,192
rows by 1,024 columns by 16 bits.
Read and write accesses to the SDRAM are burst ori-
ented; ac cess es start at a selected location and continue
for a pro grammed number of locations in a programmed
se quence. Ac cess es be gin with the registration of an
ACTIVE com mand, which is then fol lowed by a READ or
WRITE com mand. The address bits reg is tered coincident
with the AC TIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits reg is tered co in ci dent
with the READ or WRITE com mand are used to se lect the
starting col umn lo ca tion for the burst ac cess.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be en abled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 2Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is com pat i ble
with the 2n rule of prefetch architectures, but it also allows
the column ad dress to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging
one bank while ac cess ing one of the other three banks
will hide the precharge cycles and provide seam less, high-
speed, random-access op er a tion.
The 2Gb SDRAM is designed to operate at 3.3V. An auto
refresh mode is provided, along with a power-saving,
power-down mode.
32Mx72 Synchronous DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm
3.3V ±0.3V power supply for core and I/Os
Fully Synchronous; all signals registered on pos i tive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8192 refresh cycles
Commercial, Industrial and Military Temperature
Rang es
Organized as 32M x 72
Weight: W332M72V-XSBX - 2.0 grams typical
BENEFITS
73% SPACE SAV INGS
Re duced part count
Re duced I/O count
• 23% I/O Re duc tion
Re duced trace lengths for low er par a sit ic
ca pac i tance
Suitable for hi-re li abil i ty ap pli ca tions
Lami nate in ter pos er for op ti mum TCE match
* This product is subject to change without notice.
Discrete Approach ACTUAL SIZE S
A
V
I
N
G
S
Area 5 x 265mm2 = 1325mm2 352mm2 73%
I/O 5 x 54 pins = 270 pins 208 Balls 23%
Count
16
22
11.9 11.9 11.9 11.9 11.9
22.3 54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
White Electronic Designs
W332M72V-XSBX
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White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
FIGURE 1 – PIN CONFIGURATION
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally
Ball J10 is NC on this device; will be used as A13 for future density upgrades.
Top View
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
V
CC
V
SS
V
CCQ
V
CCQ
V
SS
V
CCQ
V
CCQ
V
SS
V
CC
V
SS
V
CCQ
V
SS
CS2# CS0# CKE2 CKE0 CAS2# RAS0# RAS2# V
SS
V
CCQ
V
SS
NC NC CLK0 CLK2 DQML0 DQML2 CAS0# WE0# WE2# V
SS
DQMH2 DQMH0 NC NC DQ8 DQ40 DQ5 DQ39 DQ7 NC NC
DQ41 DQ9 DQ10 DQ42 DQ43 DQ12 DQ3 DQ36 DQ4 DQ38 DQ6
DQ44 DQ11 DQ13 DQ45 DQ14 DQ33 DQ1 DQ34 DQ2 DQ37 DQ35
DQ64 DQ65 DQ15 DQ47 DQ46 V
SS
DQ32 DQ0 DQ77 DQ79 DQ78
DNU DQ66 DQ69 DNU DQ67 V
CC
DQ72 DQ73 DQ74 DQ75 DQ76
V
CCQ
A12 BA1 A0 V
CC
V
SS
V
CCQ
A7 A9 NC(A13) V
CC
V
SS
A10 A3 V
CCQ
V
SS
NC V
SS
V
CCQ
A4 A11 V
SS
V
CC
A2 BA0 A1 V
CCQ
V
SS
V
CC
A6 A8 A5 V
CCQ
DQ71 DQ70 NC DQML4 DQ68 V
CC
NC DQMH4 NC CLK4 DNU
WE4# CAS4# RAS4# DQ16 DQ48 V
SS
DQ63 DQ31 DQ62 CKE4 CS4#
DQ22 DQ52 DQ18 DQ50 DQ17 DQ49 DQ30 DQ61 DQ29 DQ59 DQ27
DQ23 DQ54 DQ21 DQ19 DQ51 DQ60 DQ28 DQ58 DQ26 DQ57 DQ25
NC NC DQ55 DQ53 DQ20 DQ56 DQ24 DQMH3 DQMH1 NC NC
V
SS
CAS3# WE3# WE1# DQML3 DQML1 NC NC CLK1 CLK3 V
SS
V
CCQ
V
SS
CAS1# RAS3# RAS1# CKE1 CKE3 CS1# CS3# V
SS
V
CCQ
V
SS
V
CC
V
SS
V
CCQ
V
CCQ
V
SS
V
CCQ
V
CCQ
V
SS
V
CC
V
SS
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Rev. 3
A
0-12
A
0-12
BA
0-1
BA
0-1
CLK
0
CLK
CAS#
DQ
0
DQ
15
CKE
0
CKE
CS
0
# CS#
DQML
0
DQML
DQMH
0
DQMH
RAS
1
#
WE
1
#
CAS
1
#
DQ
0
DQ
15
WE#
U1
RAS#
A
0-12
BA
0-1
CLK
1
CLK
CAS#
DQ
16
DQ
31
RAS
0
#
WE
0
#
CAS
0
#
DQ
0
DQ
15
WE#
U0
RAS#
CKE
1
CKE
CS
1
# CS#
DQML
1
DQML
DQMH
1
DQMH
RAS
2
#
WE
2
#
CAS
2
#
DQ
0
DQ
15
WE#
U2
RAS#
A
0-12
BA
0-1
CLK
2
CLK
CAS#
DQ
32
DQ
47
CKE
2
CKE
CS
2
# CS#
DQML
2
DQML
DQMH
2
DQMH
RAS
3
#
WE
3
#
CAS
3
#
DQ
0
DQ
15
WE#
U3
RAS#
A
0-12
BA
0-1
CLK
3
CLK
CAS#
DQ
48
DQ
63
CKE
3
CKE
CS
3
# CS#
DQML
3
DQML
DQMH
3
DQMH
RAS
4
#
WE
4
#
CAS
4
#
DQ
0
DQ
15
WE#
U4
RAS#
A
0-12
BA
0-1
CLK
4
CLK
CAS#
DQ
64
DQ
79
CKE
4
CKE
CS
4
# CS#
DQML
4
DQML
DQMH
4
DQMH
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
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Rev. 3
Register Defi nition
MODE REGISTER
The Mode Register is used to defi ne the specifi c mode
of op er a tion of the SDRAM. This defi nition includes the
selec-tion of a burst length, a burst type, a CAS latency,
an op er at ing mode and a write burst mode, as shown in
Figure 3. The Mode Register is programmed via the LOAD
MODE REG IS TER command and will retain the stored
in for ma tion until it is programmed again or the device
loses power.
Mode register bits M0-M2 specify the burst length, M3
spec i fi es the type of burst (sequential or in ter leaved),
M4-M6 specify the CAS latency, M7 and M8 specify the
op er at ing mode, M9 spec i fi es the WRITE burst mode,
and M10 and M11 are reserved for future use. Address
A12 (M12) is undefi ned but should be driven LOW during
loading of the mode register.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specifi ed time before
ini ti at ing the subsequent operation. Violating either of these
requirements will result in unspecifi ed operation.
Burst Length
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
Fig ure 3. The burst length determines the maximum
number of column lo ca tions that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are avail able for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown op er a tion
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
col umns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
mean ing that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-9 when the burst length is set to two; by A2-9 when
the burst length is set to four; and by A3-9 when the burst
length is set to eight. The remaining (least signifi cant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached
All inputs and outputs are L VTTL compatible. SDRAMs offer
sub stan tial ad vanc es in DRAM op er at ing per for mance,
in clud ing the ability to syn chro nous ly burst data at a high
data rate with au to mat ic column-ad dress gen er a tion,
the ability to in ter leave be tween in ter nal banks in order
to hide precharge time and the capability to ran dom ly
change col umn ad dress es on each clock cy cle dur ing a
burst ac cess.
FUNCTIONAL DE SCRIP TION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
pro grammed number of locations in a pro grammed
se quence. Ac cess es begin with the registration of an
ACTIVE com mand which is then followed by a READ or
WRITE com mand. The address bits registered coincident
with the AC TIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-12 select the row). The address bits (A0-9) reg is tered
coincident with the READ or WRITE com mand are used to
select the start ing column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
cov er ing device initialization, register defi nition, command
de scrip tions and de vice operation.
Initialization
SDRAMs must be pow ered up and initialized in a pre defi ned
manner . Operational pro ce dures other than those spec i fi ed
may result in undefi ned operation. Once power is ap plied
to VCC and VCCQ (si mul ta neous ly) and the clock is stable
(stable clock is de fi ned as a signal cycling within tim ing
constraints specified for the clock pin), the SDRAM
re quires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100µs period and continuing at
least through the end of this period, COMMAND INHIBIT
or NOP com mands should be applied.
Once the 100µs delay has been satisfi ed with at least
one COM MAND INHIBIT or NOP command having been
ap plied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
per formed. After the AUTO REFRESH cycles are complete,
the SDRAM is ready for Mode Register programming. Be cause
the Mode Register will power up in an unknown state, it should
be loaded prior to applying any operational command.
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Rev. 3
TABLE 1 – BURST DEFINITION
Burst
Length Starting Column
Address Order of Accesses Within a Burst
Type = Sequential Type = In ter leaved
2
A0
0 0-1 0-1
1 1-0 1-0
4
A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full
Page
(y)
n = A 0-9
(location 0-y)
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
Not Supported
FIGURE 3 – MODE REGISTER DEFINITION
NOTES:
1. For full-page accesses: y = 1,024.
2. For a burst length of two, A1-9 select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-9 select the block-of-four burst; A0-1 select the starting
column within the block.
4. For a burst length of eight, A3-9 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-9 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-9 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst LengthCAS Latency BT
A9A7A6A5A4A3
A8A2A1A0
Mode Register (Mx)
Address Bus
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8 M7
Op Mode
A10
A11
Reserved*
WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M12, M11, M10 = 0, 0
to ensure compatibility
with future devices.
A12
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FIGURE 4 – CAS LATENCY
OPERATING MODE
The nor mal operating mode is selected by setting M7and
M8 to zero; the other combinations of values for M7 and
M8 are re served for future use and/or test modes. The
pro grammed burst length applies to both READ and
WRITE bursts.
Test modes and reserved states should not be used
be cause unknown operation or incompatibility with future
versions may result.
TABLE 2 – CAS LATENCY
SPEED
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
LATENCY = 2 CAS
LATENCY = 3
-100 ≤ 75 ≤ 100
-125 ≤ 100 ≤ 125
-133 ≤ 100 ≤ 133
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
CLK
Command
I/O
CLK
Command
I/O
T0 T1 T2 T3
T0 T1 T2 T3 T4
READ NOP NOP
CAS Latency = 2
D
OUT
t
LZ
t
OH
t
AC
READ NOP NOP NOP
D
OUT
t
LZ
t
OH
t
AC
CAS Latency = 3
DON'T CARE
UNDEFINED
BURST TYPE
Accesses within a given burst may be pro grammed to be
either se quen tial or interleaved; this is re ferred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is de ter mined by
the burst length, the burst type and the start ing column
address, as shown in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the avail abil i ty
of the fi rst piece of output data. The latency can be set to
two or three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. The I/Os will start driving as a result of the clock
edge one cycle ear li er (n + m - 1), and provided that the
rel e vant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is pro grammed to two clocks, the I/Os will start driving
after T1 and the data will be valid by T2. Table 2 below
indicates the op er at ing fre quen cies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown op er a tion
or incompatibility with future versions may result.
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TRUTH TABLE - COMMANDS AND DQM OPERATION (NOTE 1)
NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR I/Os
COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (Select bank and activate row) ( 3) L L H H X Bank/Row X
READ (Select bank and column, and start READ burst) (4) L H L H L/H 8 Bank/Col X
WRITE (Select bank and column, and start WRITE burst) (4) L H L L L/H 8 Bank/Col Valid
BURST TERMINATE L H H L X X Active
PRECHARGE (Deactivate row in bank or banks) ( 5) L L H L X Code X
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7) L L L H X X X
LOAD MODE REGISTER (2) L L L L X Op-Code X
Write Enable/Output Enable (8) ––––L – Active
Write Inhibit/Output High-Z (8) –––– H – High-Z
command can only be issued when all banks are idle, and
a sub se quent ex e cut able com mand cannot be issued until
tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs se lects the bank, and the
address pro vid ed on inputs A0-12 selects the row. This row
remains active (or open) for ac cess es until a PRECHARGE
com mand is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.
READ
The READ command is used to initiate a burst read
access to an active row . The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-9
se lects the starting column location. The value on input
A10 de ter mines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ
burst; if AUTO PRECHARGE is not selected, the row will
remain open for subsequent ac cess es. Read data appears
on the I/Os sub ject to the logic level on the DQM inputs
COMMANDS
The Truth Table provides a quick reference of available
com mands. This is followed by a written de scrip tion of each
com mand. Three additional Truth Tables appear following
the Op er a tion section; these tables provide current state/
next state information.
COMMAND INHIBIT
The COMMAND INHIBIT function pre vents new commands
from being executed by the SDRAM, regardless of whether
the CLK signal is enabled. The SDRAM is effectively
de se lect ed. Op er a tions already in progress are not
affected.
NO OPERATION (NOP)
The NO OPERA TION (NOP) command is used to perform
a NOP to an SDRAM which is selected (CS# is LOW).
This pre vents unwanted commands from being registered
dur ing idle or wait states. Op er a tions already in progress
are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-11 (A12
should be driven low). See Mode Reg is ter heading in the
Register Defi ni tion sec tion. The LOAD MODE REGISTER
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 defi ne the op-code written to the Mode Register and A12 should be driven
low.
3. A0-12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-9 provide column address; A10 HIGH enables the auto precharge feature
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs
(two-clock delay).
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Rev. 3
two clocks earlier. If a given DQM signal was registered
HIGH, the cor re spond ing I/Os will be High-Z two clocks
later; if the DQM signal was registered LOW, the I/Os will
provide valid data.
WRITE
The WRITE command is used to initiate a burst write
access to an active row . The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-9
se lects the starting column location. The value on input A10
de ter mines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
sub se quent accesses. Input data appearing on the I/Os
is written to the memory array subject to the DQM input
logic level ap pear ing co in ci dent with the data. If a given
DQM signal is registered LOW, the cor re spond ing data
will be written to memory; if the DQM signal is registered
HIGH, the cor re spond ing data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specifi ed time (tRP) after the PRECHARGE command
is is sued. Input A10 determines wheth er one or all banks
are to be precharged, and in the case where only one
bank is to be precharged, inputs BA0, BA1 select the bank.
Oth er wise BA0, BA1 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated pri or to any READ or WRITE commands being
is sued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
in di vid u al-bank PRECHARGE function de scribed above,
with out re quir ing an explicit command. This is ac com plished
by using A10 to enable AUTO PRECHARGE in conjunction
with a spe cifi c READ or WRITE command. A precharge of
the bank/row that is ad dressed with the READ or WRITE
com mand is au to mat i cal ly performed upon com ple tion of
the READ or WRITE burst, except in the full-page burst
mode, where AUTO PRECHARGE does not ap ply. AUTO
PRECHARGE is non per sis tent in that it is either enabled or
disabled for each in di vid u al READ or WRITE com mand.
AUTO PRECHARGE ensures that the precharge is initiated
at the earliest valid stage within a burst. The user must not
is sue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit
PRECHARGE com mand was issued at the earliest possible
time.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
either fi xed-length or full-page bursts. The most recently
reg is tered READ or WRITE command prior to the BURST
TER MI NATE command will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal op er a tion of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) RE FRESH in con ven tion al DRAMs. This com mand
is nonpersistent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
con trol ler. This makes the address bits “Don’t Care”
during an AUTO RE FRESH command. Each 512Mb
SDRAM requires 8,192 AUTO RE FRESH cycles every
refresh period (tREF). Pro vid ing a dis trib ut ed AUTO
RE FRESH command will meet the refresh re quire ment
and ensure that each row is re freshed. Al ter na tive ly , 8,192
AUTO RE FRESH com mands can be is sued in a burst at
the minimum cycle rate (tRC), once every refresh period
(tREF).
SELF REFRESH*
The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data with out external clocking. The SELF RE FRESH
command is ini ti at ed like an AUTO REFRESH com mand
except CKE is dis abled (LOW). Once the SELF RE FRESH
command is reg is tered, all the inputs to the SDRAM
become “Don’t Care,” with the exception of CKE, which
must remain LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own
AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to tRAS and
may remain in self refresh mode for an indefi nite period
beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock is
defined as a signal cycling within timing con straints
* Self refresh available in commercial and industrial tem per a tures only.
9White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
ABSOLUTE MAXIMUM RATINGS
Parameter Unit
Voltage on VCC, VCCQ Supply relative to Vss -1 to 4.6 V
Voltage on NC or I/O pins relative to Vss -1 to 4.6 V
Operating Temperature TA (Mil) -55 to +125 °C
Operating Temperature TA (Ind) -40 to +85 °C
Storage Temperature, Plastic -55 to +125 °C
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause per ma nent damage to the device. This is a stress rating
only and func tion al op er a tion of the device at these or any other conditions greater than those in di cat ed in the operational sections of
this specifi cation is not implied. Exposure to ab so lute maximum rating con di tions for extended periods may affect reliability.
CAPACITANCE (NOTE 2)
Parameter Symbol Max Unit
Input Capacitance: CLK CI1 7 pF
Addresses, BA0-1 Input Capacitance CA 24 pF
Input Capacitance: All other input-only pins CI2 9 pF
Input/Output Capacitance: I/Os CIO 9 pF
BGA THERMAL RESISTANCE
Description Symbol Typical Unit Notes
Junction to Ambient (No Airfl ow) Theta JA 17.0 C/W 1
Junction to Ball Theta JB 16.6 C/W 1
Junction to Case (Top) Theta JC 7.4 C/W 1
NOTE:
Refer to Application Note “PBGA Thermal Resistance Correlation” at www.wedc.com in the
application notes section for modeling conditions.
spec i fied for the clock pin) prior to CKE going back
HIGH. Once CKE is HIGH, the SDRAM must have NOP
commands is sued (a minimum of two clocks) for tXSR,
because time is required for the com ple tion of any internal
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
com mands must be issued as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.
10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
VCC, VCCQ = +3.3V ± 0.3V; -55°C ≤ TA ≤ +125°C
Parameter/Condition Symbol Min Max Units
Supply Voltage VCC,VCCQ 3 3.6 V
Input High Voltage: Logic 1; All inputs (21) VIH 2 VCC + 0.3 V
Input Low Voltage: Logic 0; All inputs (21) VIL -0.3 0.8 V
Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V) II -5 5 µA
Input Leakage Address Current (All other pins not under test = 0V) II-25 25 µA
Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCCQ IOZ -5 5 µA
Output Levels:
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
VOH 2.4 – V
VOL – 0.4 V
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1,6,11,13)
VCC, VCCQ = +3.3V ± 0.3V; -55°C ≤ TA ≤ +125°C
Parameter/Condition Symbol Max Units
Operating Current: Active Mode;
Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (3, 18, 19)
ICC1 550 mA
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after tRCD met; No accesses in progress (3, 12, 19)
ICC3 225 mA
Operating Current: Burst Mode; Continuous burst;
Read or Write; All banks active; CAS latency = 3 (3, 18, 19)
ICC4 575 mA
Self Refresh Current: CKE 0.2V (Commercial and industrial temperature) (27) ICC7 30 mA
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11)
Parameter Symbol -100 -125 -133 Unit
Min Max Min Max Min Max
Access time from CLK (pos.
edge)
CL = 3 tAC 7 6 5.5 ns
CL = 2 tAC 766ns
Address hold time tAH 1 1 0.8 ns
Address setup time tAS 2 2 1.5 ns
CLK high-level width tCH 3 3 2.5 ns
CLK low-level width tCL 3 3 2.5 ns
Clock cycle time (22) CL = 3 tCK 10 8 7.5 ns
CL = 2 tCK 13 10 10 ns
CKE hold time tCKH 1 1 0.8 ns
CKE setup time tCKS 2 2 1.5 ns
CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 1 0.8 ns
CS#, RAS#, CAS#, WE#, DQM setup time tCMS 2 2 1.5 ns
Data-in hold time tDH 1 1 0.8 ns
Data-in setup time tDS 2 2 1.5 ns
Data-out high-impedance time CL = 3 (10) tHZ 7 6 5.5 ns
CL = 2 (10) tHZ 766ns
Data-out low-impedance time tLZ 1 1 1 ns
Data-out hold time (load) tOH 3 3 3 ns
Data-out hold time (no load) (26) tOHN 1.8 1.8 1.8 ns
ACTIVE to PRECHARGE command tRAS 50 120,000 50 120,000 50 120,000 ns
ACTIVE to ACTIVE command period tRC 70 68 68 ns
ACTIVE to READ or WRITE delay tRCD 20 20 20 ns
Refresh period (8,192 rows) – Commercial,
Industrial
tREF 64 64 64 ms
Refresh period (8,192 rows) – Military tREF 16 16 16 ms
AUTO REFRESH period tRFC 70 70 70 ns
PRECHARGE command period tRP 20 20 20 ns
ACTIVE bank A to ACTIVE bank B command tRRD 20 20 20 ns
Transition time (7) tT0.3 1.2 0.3 1.2 0.3 1.2 ns
WRITE recovery time
(23)
tWR
1 CLK + 7ns 1 CLK + 7ns 1 CLK +
7.5ns
—
(24) 15 15 15 ns
Exit SELF REFRESH to ACTIVE command tXSR 80 80 75 ns
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11)
Parameter/Condition Symbol -100 -125 -133 Units
READ/WRITE command to READ/WRITE command (17) tCCD 111t
CK
CKE to clock disable or power-down entry mode (14) tCKED 1 1 1 tCK
CKE to clock enable or power-down exit setup mode (14) tPED 111t
CK
DQM to input data delay (17) tDQD 0 0 0 tCK
DQM to data mask during WRITEs tDQM 0 0 0 tCK
DQM to data high-impedance during READs tDQZ 2 2 2 tCK
WRITE command to input data delay (17) tDWD 0 0 0 tCK
Data-in to ACTIVE command (15) tDAL 455t
CK
Data-in to PRECHARGE command (16) tDPL 2 2 2 tCK
Last data-in to burst STOP command (17) tBDL 111t
CK
Last data-in to new READ/WRITE command (17) tCDL 1 1 1 tCK
Last data-in to PRECHARGE command (16) tRDL 2 2 2 tCK
LOAD MODE REGISTER command to ACTIVE or REFRESH command (25) tMRD 222t
CK
Data-out to high-impedance from PRECHARGE command (17) CL = 3 tROH 333t
CK
CL = 2 tROH 2——t
CK
NOTES:
1. All voltages referenced to VSS.
2. This parameter is not tested but guaranteed by design. f = 1 MHz, TA = 25°C.
3. ICC is dependent on output loading and cycle rates. Specifi ed values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifi cations are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC and VCCQ
must be powered up simultaneously.) The two AUTO REFRESH command wake-
ups should be repeated any time the tREF refresh re quire ment is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specifi cation, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50p
F
10. tHZ defi nes the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and ICC tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V
crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are otherwise at valid VIH or VIL levels.
13. ICC spec i fi ca tions are tested after the device is properly initialized.
14. Timing actually specifi ed by tCKS; clock(s) specifi ed as a reference only at minimum
cycle rate.
15. Timing actually specifi ed by tWR plus tRP; clock(s) specifi ed as a reference only at
minimum cycle rate.
16. Timing actually specifi ed by tWR.
17. Required clocks are specifi ed by JEDEC functionality and are not de pen dent on
any timing parameter.
18. The ICC current will decrease as the CAS latency is reduced. This is due to the fact
that the maximum cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V
for a pulse width ≤ 3ns.
22. The clock frequency must remain constant (stable clock is defi ned as a signal
cycling within timing constraints specifi ed for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE com mands).
CKE may be used to reduce the data rate.
23. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns
after the fi rst clock delay, after the last WRITE is executed.
24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.
13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY (PBGA), 16mm x 22mm
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
Bottom View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
11 10 9 8 7 6 5 4 3 2 1
208 x Ø 0.51 (0.020) NOM
1.0 (0.039)NOM
10.0 (0.394) NOM
16.15 (0.636) MAX
22.15 (0.872) MAX
18.0 (0.709) NOM
1.0 (0.039) NOM
3.20 (0.126) MAX
0.43
(0.017)
NOM
14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
ORDERING INFORMATION
WHITE ELECTRONIC DESIGNS CORP.
SDRAM
CONFIGURATION, 32M x 72
3.3V Power Supply
FREQUENCY (MHz)
100 = 100MHz
125 = 125MHz
133 = 133MHz
PACKAGE:
SB = 208 Plastic Ball Grid Array (PBGA), 16mm x 22mm
DEVICE GRADE:
M = Mil i tary -55°C to +125°C
I = In dus tri al -40°C to +85°C
C = Com mer cial 0°C to +70°C
W 3 32M 72 V - XXX SB X
15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W332M72V-XSBX
Ju;y 2006
Rev. 3
Document Title
32M x 72 SDRAM Multi-Chip Package, 16mm x 22mm 208 PBGA
Revision History
Rev # History Release Date Status
Rev 0 Initial Release May 2004 Advanced
Rev 1 Changes (Pg. 1, 2, 9, 15)
1.1 Change status to Preliminary
1.2 Correct pinout on page 2
1.3 Change storage temperature to +125°C
November 2004 Preliminary
Rev 2 Changes (Pg. 1, 6, 9, 10, 11, 12, 14, 15)
2.1 Change status to Final
2.2 Add 133MHz speed
2.3 Update Capacitance Table data
2.4 Update Thermal Resistance Table data
August 2005 Final
Rev 3 Changes (Pg. 1, 9, 15)
3.1 Update thermal resistance table July 2006 Final
