LT8315
1
8315fa
For more information www.linear.com/LT8315
TYPICAL APPLICATION
FEATURES DESCRIPTION
560VIN Micropower No-Opto
Isolated Flyback Converter
with 630V/300mA Switch
The LT
®
8315 is a high voltage flyback converter with inte-
grated 630V/300mA switch. No opto-isolator is needed for
regulation. The device samples the output voltage from the
isolated flyback waveform appearing across a third wind-
ing on the transformer. Quasi-resonant boundary mode
operation improves load regulation, reduces transformer
size and maintains high efficiency.
At start-up, the LT8315 charges its INTVCC capacitor via a
current source attached to the DRAIN pin. During normal
operation, the current source turns off and the device
draws its power from a third winding on the transformer.
The LT8315 operates from a wide range of input supply
voltages and can deliver up to 15W of power. It is available
in a thermally enhanced 20-pin TSSOP package with four
pins removed for high voltage spacing.
20VIN to 450VIN Isolated 12VOUT Supply
APPLICATIONS
n Wide Input Voltage Range: 18V to 560V
n 630V/300mA Integrated Power Switch
n No Opto-Isolator Required for Regulation
n Quasi-Resonant Boundary Mode Operation
n Constant-Current and Constant-Voltage Regulation
n Low Ripple Light Load Burst Mode
®
Operation
n Low Quiescent Current: 70μA
n Programmable Current Limit and Soft-Start
n TSSOP Package with High Voltage Spacing
n Isolated Telecom, Automotive, Industrial, Medical
Power Supplies
n Isolated Off Line Housekeeping Power Supplies
n Electric Vehicles and Battery Stacks
All registered trademarks and trademarks are the property of their respective owners.
Efficiency
10µF
22nF
47pF
10µF
0.44µF
200µF
4mH
640µH
160µH
20k
93.1k
5.11k
61.9k
100k
330mΩ
121k
470pF
600Ω
DCM
DRAIN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SOURCE
TC
V
C
BIAS
LT8315
V
IN
20V TO 450V
VOUT–
VOUT+
12V
5:1:2
5mA to 220mA (V
IN
= 50V)
5mA to 320mA (V
IN
= 100V)
5mA to 380mA (V
IN
= 150V)
5mA to 440mA (V
IN
> 250V)
8315 TA01a
V
IN
= 50V
V
IN
= 100V
V
IN
= 150V
V
IN
= 250V
V
IN
= 350V
V
IN
= 450V
LOAD CURRENT (mA)
0
100
200
300
400
500
30
40
50
60
70
80
90
EFFICIENCY (%)
8315 TA01b
LT8315
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
DRAIN .....................................................................630V
BIAS, EN/UVLO .........................................................40V
INTVCC ......................................................................15V
SMODE ............................................................... INTVCC
SOURCE, TC, FB, VC, IREG/SS ....................................4V
DCM ...................................................................±100mA
Operating Junction Temperature (Note 2)
LT8315E, LT8315I .............................. −40°C to 125°C
LT8315H ............................................ −40°C to 150°C
Storage Temperature Range .................. −65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300 °C
(Note 1)
FE PACKAGE
20(16)-LEAD PLASTIC TSSOP
TOP VIEW
20 GND
19 NC
18 SOURCE
17 EN/UVLO
16 SMODE
15 GND
14 IREG/SS
13 VC
12 FB
11 TC
DRAIN 1
DRAIN 2
DRAIN 3
INTVCC 8
BIAS 9
DCM 10
21
GND
θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8315EFE#PBF LT8315EFE#TRPBF LT8315FE 20-Lead Plastic TSSOP –40°C to 125°C
LT8315IFE#PBF LT8315IFE#TRPBF LT8315FE 20-Lead Plastic TSSOP –40°C to 125°C
LT8315HFE#PBF LT8315HFE#TRPBF LT8315FE 20-Lead Plastic TSSOP –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LT8315#orderinfo
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8315E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the −40°C
to 125°C operating junction temperature range are assured by design
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. BIAS = 40V, VEN/UVLO = 40V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
BIAS Chip Bias Voltage Supply Range After Startup l9.5 40 V
IQBIAS Quiescent Current Burst Mode Operation
Active
70
470
150
700
μA
ISHDN DRAIN Shutdown Current VEN/UVLO < 0.3V, BIAS = Floating 8 15 μA
VDRAIN(MIN) Minimum Drain Voltage for Startup BIAS = Floating l18 V
ISTARTUP Startup Current through Depletion FET VDRAIN = 18V, BIAS = Floating l130 300 μA
VUVLO EN/UVLO Threshold
EN/UVLO Hysteresis
VEN/UVLO Falling
VEN/UVLO Rising
1.18
30
1.22
65
1.26
120
V
mV
INTVCC UVLO Rising Threshold Startup Current through Depletion FET 11.1 12 13.1 V
INTVCC UVLO Falling Threshold 7.7 8.2 8.7 V
VREG FB Regulation Voltage l1.19 1.22 1.25 V
GMVoltage Error Amplifier Transconductance VFB = 1.22V ± 20mV l75 100 125 μS
VTC TC Voltage
TC Voltage Temperature Coefficient
TA = 25°C 1.16 1.22
+4.1
1.28 V
mV/°C
ITC TC Sinking/Sourcing Current ±100 μA
IIREG/SS IREG/SS Current Current Out-of-Pin
l
9.9
9.5
10 10.1
10.5
μA
IDCM Flyback Collapse Detection Threshold
Resonant Valley Detection Threshold
IDCM Rising
IDCM Falling
–140
–65
−170
−85
–200
–105
μA
μA
RSW Power MOSFET Resistance 7 10 Ω
ISW(MAX) Maximum Switch Current
l
500
300
800 mA
mA
VSOURCE(MIN) Minimum Current Voltage Threshold 15 20 25 mV
VSOURCE(MAX) Maximum Current Voltage Threshold 90 100 110 mV
VSOURCE(ILIM) Over-Current Voltage Threshold 250ns Blanking Period; Restarts Chip 110 120 130 mV
FSW(MIN) Minimum Switching Frequency Burst Mode
Standby Mode
3
187
3.5
220
4
250
kHz
Hz
FSW(MAX) Maximum Switching Frequency 138 140 142 kHz
characterization and correlation with statistical process controls. The
LT8315I is guaranteed over the full −40°C to 125°C operating junction
temperature range. The LT8315H is guaranteed over the full −40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C.
LT8315
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TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency Boundary Mode Waveforms Discontinuous Mode Waveforms
Burst Mode Waveforms Load Transient Response Startup Waveforms
Load and Line Regulation Output Voltage vs Temperature CV/CC Operation
TA = 25°C, unless otherwise noted.
FRONT PAGE APPLICATION
V
IN
= 50V
V
IN
= 100V
V
IN
= 150V
V
IN
= 250V
V
IN
= 350V
V
IN
= 450V
LOAD CURRENT (mA)
0
100
200
300
400
500
11.6
11.7
11.8
11.9
12.0
12.1
12.2
12.3
12.4
OUTPUT VOLTAGE (V)
8315 G01
FRONT PAGE APPLICATION
V
IN
= 350V
I
OUT
= 100mA
I
OUT
= 200mA
I
OUT
= 440mA
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
11.6
11.7
11.8
11.9
12.0
12.1
12.2
12.3
12.4
OUTPUT VOLTAGE (V)
8315 G02
FRONT PAGE APPLICATION
R
IREG/SS
= 66.5kΩ
V
IN
= 100V
V
IN
= 150V
V
IN
= 250V
V
IN
= 350V
V
IN
= 450V
LOAD CURRENT (mA)
0
75
150
225
300
375
450
0
3
6
9
12
15
OUTPUT VOLTAGE (V)
8315 G03
FRONT PAGE APPLICATION
V
IN
= 50V
V
IN
= 100V
V
IN
= 150V
V
IN
= 250V
V
IN
= 350V
V
IN
= 450V
LOAD CURRENT (mA)
0
100
200
300
400
500
0
20
40
60
80
100
120
FREQUENCY (kHz)
8315 G04
10µs/DIV
FRONT PAGE APPLICATION
VIN = 350V, IOUT = 440mA
V
SOURCE
100mV/DIV
V
DRAIN
200V/DIV
V
OUT
AC COUPLED
50mV/DIV
8315 G05
10µs/DIV
V
SOURCE
100mV/DIV
V
DRAIN
200V/DIV
V
OUT
AC COUPLED
50mV/DIV
8315 G06
FRONT PAGE APPLICATION
VIN = 350V, IOUT = 50mA
100µs/DIV
V
SOURCE
100mV/DIV
V
DRAIN
200V/DIV
V
OUT
AC COUPLED
50mV/DIV
8315 G07
FRONT PAGE APPLICATION
VIN = 350V, IOUT = 3mA
10ms/DIV
V
OUT
AC COUPLED
500mV/DIV
I
OUT
500mA/DIV
8315 G08
FRONT PAGE APPLICATION
VIN = 350V, IOUT = 10mA TO 440mA
50ms/DIV
V
IN
350V/DIV
V
OUT
10V/DIV
V
INTVCC
10V/DIV
V
BIAS
10V/DIV
8315 G09
FRONT PAGE APPLICATION
VIN = 350V, ROUT = 28Ω
LT8315
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TYPICAL PERFORMANCE CHARACTERISTICS
EN/UVLO Threshold FB Regulation Voltage TC Pin Voltage
IREG/SS Pin Current Switching Frequency Limit Switch Current Limit
DRAIN Shutdown Current BIAS Quiescent Current Depletion Startup Current
TA = 25°C, unless otherwise noted.
EN/UVLO Rising
EN/UVLO Falling
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.15
1.20
1.25
1.30
1.35
ENABLE THRESHOLD (V)
8315 G13
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.200
1.205
1.210
1.215
1.220
1.225
1.230
1.235
1.240
FB REGULATION VOLTAGE (V)
8315 G14
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0.80
1.00
1.20
1.40
1.60
1.80
TC VOLTAGE (V)
8315 G15
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
9.5
9.6
9.7
9.8
9.9
10.0
10.1
10.2
10.3
10.4
10.5
IREG/SS CURRENT (μA)
8315 G16
MAXIMUM SWITCHING FREQUENCY
MINIMUM SWITCHING FREQUENCY
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
1
2
3
4
5
125
130
135
140
145
150
FREQUENCY (kHz)
8315 G17
MAXIMUM CURRENT LIMIT
MINIMUM CURRENT LIMIT
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
5
10
15
20
25
85
90
95
100
105
110
SOURCE VOLTAGE (mV)
8315 G18
V
DRAIN
= 100V
V
DRAIN
= 630V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
15
30
45
60
SHUTDOWN CURRENT (μA)
8315 G10
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
40
80
120
160
QUIESCENT CURRENT (μA)
8315 G11
–55°C
25°C
150°C
V
INTVCC
(V)
0
3
6
9
12
15
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
I
INTVCC
(mA)
8315 G12
LT8315
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TYPICAL PERFORMANCE CHARACTERISTICS
Switch RDS(ON)
Minimum Switch-On Time Minimum Switch-Off Time
DCM Pin Threshold
TA = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
50
100
150
200
250
300
350
400
ON TIME (ns)
8315 G19
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
500
550
600
650
700
750
800
850
900
OFF TIME (ns)
8315 G20
RESONANT VALLEY DETECT
FLYBACK COLLAPSE DETECT
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
–220
–200
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
DCM CURRENT (µA)
8315 G21
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
2
4
6
8
10
12
14
16
RESISTANCE (Ω)
8315 G22
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PIN FUNCTIONS
DRAIN (Pins 1,2,3): Drain of the 630V Internal Power
Switch and Startup FET. Design a compact layout with the
transformer and input capacitor, and minimize trace area
to reduce EMI and voltage spikes.
INTVCC (Pin 8): Internal Gate Driver Bias Voltage. During
start-up, current from the DRAIN charges this pin to 12V.
During operation, a linear regulator from BIAS maintains
this voltage at 10V. Bypass locally with a ≥2.2μF ceramic
≥15V capacitor.
BIAS (Pin 9): Unregulated Input Voltage for the IC. This pin
derives power from a third winding on the transformer to
provide power to INTVCC. Bypass locally with a capacitor.
DCM (Pin 10): Discontinuous Conduction Mode Detec-
tor. This pin detects the dV/dt of the switching waveform,
ensuring accurate output voltage sampling and quasi-
resonant boundary-mode switching. Connect a capacitor
with series resistance from this pin to the third winding.
TC (Pin 11): Temperature Compensation Pin. This pin
presents a proportional-to-absolute-temperature (PTAT)
voltage, which is equal to the internal 1.22V reference
voltage at 25°C and rises with temperature by 4.1mV/°C,
to compensate for the output rectifier diode. Connect an
appropriate resistor from this pin to FB.
FB (Pin 12): FeedBack Pin. The voltage appearing on this
pin is sampled and regulated to equal the internal 1.22V
reference voltage. Connect this pin to a resistor divider
from the third winding to regulate the output voltage.
VC (Pin 13): Loop Compensation Pin. An internal GM
transconductance amplifier feeds this pin with an error
current depending on the sampled FB voltage. The result-
ing voltage determines the switching frequency and peak
current limit for power delivery. Connect a series R-C
network to stabilize the regulator.
IREG/SS (Pin 14): Current Regulation/Soft-Start Pin. A
10μA current flows out of this pin. The resulting voltage
sets the output current regulation point, as determined by
an internal current regulation loop. Program the current
with a resistor to GND, or connect a capacitor to imple-
ment soft-start.
SMODE (Pin 16): Standby Mode Pin. Connect this pin to
INTVCC to enable Standby Mode, which reduces the mini-
mum switching frequency to 220Hz for ultralow quiescent
power consumption. Connect to GND to disable.
EN/UVLO (Pin 17): Enable/Undervoltage Lockout Pin. The
chip will operate only if the voltage on this pin is greater
than the internal 1.22V reference voltage. Connect to a
resistor divider as desired, or connect to BIAS or INTVCC
if UVLO functionality is not desired.
SOURCE (Pin 18): Source of 630V Internal Power Switch.
The voltage appearing on this pin is used for peak current-
mode control and current limiting. Connect a current-
sensing resistor to GND to program the current limit.
Design a compact layout with the transformer and input
capacitor to reduce EMI and voltage spikes.
NC (Pin 19): No-Connect. This pin is electrically dis-
connected. Leave floating.
GND (Pins 15, 20, 21): Ground. Solder the exposed pad
(Pin 21) to a ground plane for heat sinking.
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BLOCK DIAGRAM
8315 BD
–
+
+
–10V
LDO
BIAS/REF
CONTROL
TSD
INTVCC
BIAS
EN/UVLO
SMODE
9
8
17
16
DCM
10
FB
12
RDCM
RFB2
CDCM
CINTVCC
CBIAS
DBIAS
BOUNDARY
DETECT
S&H
×1
TC
11 ×1
•
RFB1
LTER
:NTS
RTC
+
–
GM
VOLTAGE
ERROR AMP
+4.1mV/°C
1.22V
VOLTAGE
CONTROLLED
OSCILLATOR
–
+
S
Q
R
DRIVER
MASTER
LATCH
630V
DEPLETION
FET
630V
POWER
FET
CURRENT
COMPARATOR
+
–
CURRENT
ERROR AMP
×10
13 14
10µA
1.25×(1–D)
RIREG
IREG/SSVC
RC
CC
M2
DRAIN
1, 2, 3
M1
RSNS
15, 20, 21
GND
SOURCE 18
•
•
ZSNUB
LSEC
LPRI COUT
NPS :1 DOUT
VOUT+
VOUT–
DSNUB
CIN
VIN
VUVLO
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OPERATION
Boundary Mode Operation
Boundary mode is a variable frequency, current-mode
switching scheme. The internal N-channel MOSFET turns
on and the inductor current increases until it reaches the
limit determined by the voltage on the VC pin and the sense
resistor’s value. After the internal MOSFET turns off, the
voltage on the tertiary winding rises to the output voltage
multiplied by the transformer tertiary-to-secondary turns
ratio. After the current through the output diode falls to
zero, the voltage on the tertiary winding falls. A boundary
mode detection comparator on the DCM pin detects the
negative dV/dt associated with the falling voltage and trig-
gers the sample-and-hold circuit to sample the FB voltage.
When the tertiary voltage reaches its minimum and stops
falling, the boundary mode comparator turns the internal
MOSFET back on for minimal switching energy loss.
Boundary mode operation returns the secondary current
to zero every cycle, so parasitic resistive voltage drops
do not cause load regulation errors. Boundary mode
also allows the use of a smaller transformer compared
to continuous conduction mode and does not exhibit
subharmonic oscillation.
Discontinuous Conduction Mode Operation
As the load gets lighter, the peak switch current decreases.
Maintaining boundary mode requires the switching fre-
quency to increase. An excessive switching frequency
increases switching and gate charge losses. To limit these
losses, the LT8315 features an internal oscillator which
limits the maximum switching frequency to 140kHz. Once
the switching frequency hits this limit, the part starts to
reduce its switching frequency and operates in discontinu-
ous conduction mode.
Low Ripple Burst Mode Operation
Unlike traditional flyback converters, the internal MOSFET
has to turn on and off to generate a flyback pulse in order
to update the sampled output voltage. The duration of a
well-formed flyback pulse must exceed the minimum-off
time for proper sampling. To this end, a minimum switch
turn-off current is necessary to ensure a flyback pulse of
sufficient duration.
The LT8315 is a high-voltage current-mode switching
regulator designed for the isolated flyback topology. The
special problem normally encountered in such circuits is
that information relating to the output voltage on the isolated
secondary side of the transformer must be communicated
to the primary side in order to achieve regulation. This is
often performed by opto-isolator circuits, which waste
output power, require extra components that increase the
cost and physical size of the power supply, and exhibit
trouble due to limited dynamic response, nonlinearity,
unit-to-unit variation, and aging over life.
The LT8315 does not need an opto-isolator because it
derives its information about the isolated output voltage
by examining the flyback pulse waveform appearing on a
tertiary winding on the transformer. The output voltage is
easily programmed with two resistors.
The LT8315 features a boundary mode control method (also
called critical conduction mode), where the part operates
at the boundary between continuous conduction mode and
discontinuous conduction mode. Due to boundary mode
operation, the output voltage can be determined from the
tertiary winding’s voltage when the secondary current is
almost zero. This method improves load regulation without
extra resistors and capacitors.
The Block Diagram shows an overall view of the system.
Many of the blocks are similar to those found in traditional
switching regulators, including current comparator, internal
reference, LDO, logic, timers, and an N-channel MOSFET.
The novel sections include a special sampling error ampli-
fier, a temperature compensation circuit, an output current
regulator
, and a depletion-mode startup FET.
Depletion Startup FET
The LT8315 features an internal depletion mode MOSFET.
At startup, this transistor charges the INTVCC capacitor
so that the LT8315 has power to begin switching. This
removes the need for an external bleeder resistor or other
components.
LT8315
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APPLICATIONS INFORMATION
OPERATION
The LT8315 is designed to be an easy-to-use, yet fully-
featured flyback regulator. With proper technique, it is
simple to build an efficient and robust power solution.
However, don’t let the simplicity beguile you into sloppy
lab practices: the voltage and power levels involved can
be lethal. Milliamperes from a high voltage power sup-
ply can cause heart fibrillation and death. Never touch
conductive nodes while the circuit is active, and keep one
hand behind your back while probing. Conduct lab work
in the presence of an assistant, who can perform first aid
in case of emergency.
Depletion Startup FET
The LT8315 features an internal depletion-mode FET, which
has a negative threshold voltage and is therefore normally
on. At startup, this FET charges the INTVCC capacitor to
12V so that the LT8315 has power to begin switching.
This removes the need for an external bleeder resistor or
other startup components. Once INTVCC is charged, the
depletion-mode FET turns off.
The depletion FET is current-limited to avoid destructive
power levels. To ensure start-up, do not load INTVCC or
BIAS with excessive current while the chip is starting.
ENABLE and Undervoltage Lockout (UVLO)
A resistive divider from VIN to the EN/UVLO pin implements
undervoltage lockout (UVLO). The EN/UVLO pin threshold
is set at 1.22V. Upon startup, the EN/UVLO pin exhibits a
~65mV hysteresis voltage to prevent oscillations.
The EN/UVLO pin can also be driven with logic levels and
set by the output pin of a digital controller. Otherwise,
EN/UVLO can also be tied to BIAS or INTVCC to keep the
chip enabled.
Output Voltage
The output voltage is programmed by the RFB1 and RFB2
resistors depicted in the Block Diagram. The LT8315
operates similarly to traditional current-mode switchers,
except in the use of a unique sample-and-hold error ampli-
fier, which regulates the isolated output voltage from the
sampled flyback pulse.
As the load gets very light, the LT8315 reduces switching
frequency while maintaining the minimum current limit in
order to reduce current delivery while still properly sam-
pling the output voltage. Because flyback pulses must be
generated to regulate the output, a minimum switching
frequency of 3.5kHz is enforced. The minimum switch-
ing frequency determines how often the output voltage
is sampled and introduces a minimum load requirement.
Tying the SMODE pin to INTVCC enables Standby Mode,
which reduces the minimum switching frequency to 220Hz,
reducing the minimum load requirement at the expense
of a longer period between samples.
CV/CC Regulation
Like a traditional voltage regulator, the LT8315 imple-
ments a GM transconductance amplifier that regulates
the output voltage. In addition, the LT8315 includes a
current regulation loop which regulates the estimated
output current to a point set by the voltage on the IREG/
SS pin. Below the current setpoint, the output voltage
is regulated for constant-voltage (CV) regulation. Below
the voltage setpoint, the output current is regulated for
constant-current (CC) regulation.
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APPLICATIONS INFORMATION
Operation is as follows: when the power switch M1 turns
off, the voltage across the tertiary winding rises. The
amplitude of the flyback pulse is given as:
VFLBK = (VOUT + VF + ISEC • ESR) • NTS,
where
VF = Output diode (DOUT) forward-biased voltage
ISEC = Transformer secondary current
ESR = Parasitic resistance of secondary circuit
NTS = Transformer tertiary-to-secondary turns ratio
The voltage divider formed by RFB1 and RFB2 feeds a
scaled version of the flyback pulse to the FB pin, where
it is sampled and fed to the error amplifier. Because the
sample-and-hold circuit samples the voltage when the
secondary current is nearly zero, the (ISEC • ESR) term in
the VFLBK equation can be ignored.
The internal 1.22V reference voltage feeds the non-inverting
input of the error amplifier. The high gain of the overall
loop causes the FB voltage to be nearly equal to the refer-
ence voltage. The resulting flyback voltage VFLBK can be
expressed as:
V
FLBK =1+RFB2
R
FB1
⎛
⎝
⎜⎞
⎠
⎟• 1.22V
Combining with the previous VFLBK equation and solving
for VOUT yields:
VOUT =1+RFB2
R
FB1
⎛
⎝
⎜⎞
⎠
⎟•1.22V
N
TS
−V
F
Due to the fast nature of the flyback pulse, it is recom-
mended to keep RFB1 between 1kΩ and 10kΩ in order to
preserve the resistor divider’s dynamic response.
Selecting the Actual RFB2 Resistor Value
The LT8315 uses a unique sampling scheme to regulate
the isolated output voltage. Due to its sampling nature,
the scheme exhibits repeatable delays and error sources,
which will affect the output voltage and force a re-evaluation
of the resistor values.
With a fixed value for RFB1 (such as 10kΩ) chosen, rear-
rangement of the expression for VOUT yields the starting
value for RFB2:
RFB2 =RFB1 •
V
OUT
+V
F
1.22V • NTS −1
⎛
⎝
⎜⎞
⎠
⎟
where
VOUT = Desired output voltage
VF = Output diode (DOUT) forward voltage ≈ 300mV
NTS = Transformer tertiary-to-secondary turns ratio
Power up the application with the final power components
installed and the starting RFB2 value, and measure the
regulated output voltage, VOUT(MEAS). The final RFB2 value
can be adjusted to:
RFB2(FINAL) ≈RFB2 +RFB1
( )
•
V
OUT
VOUT(MEAS)
−RFB
1
Once the final RFB2 value is selected, the regulation ac-
curacy from board to board for a given application will be
very consistent, typically within ±5% when including device
variation of all the components in the system (assuming
resistor tolerances and transformer windings matching
within ±1%). However, if the transformer or the output
diode is changed, or the layout is dramatically altered,
there may be some change in VOUT.
Example: Consider a 12V output supply with an output
diode whose forward voltage at nearly zero current is
300mV at room temperature. If the tertiary-to-secondary
ratio NTS is 1 and RFB1 is 10kΩ, then RFB2 is calculated
as 90.9kΩ. The application is powered up and the output
is slightly high at 12.2V, so RFB2 is adjusted to 88.7kΩ.
Output Diode Temperature Compensation
Reiterating the equation for VOUT,
V
OUT =1+
R
FB2
R
FB2
•
1.22V
N
TS
V
F
The first term in the VOUT equation is insensitive to tem-
perature, but the output diode forward voltage VF has a
significant negative temperature coefficient (from −1mV/°C
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APPLICATIONS INFORMATION
to −2mV/°C). Such a temperature coefficient produces
approximately 200mV to 400mV output voltage variation
across operating temperature.
At higher output voltages, the resulting variation may be
unimportant as it represents a small fraction of the total
output. However, for lower output voltages, the diode
temperature coefficient accounts for a large output volt-
age error.
To correct this error, the TC pin provides a buffered
proportional-to-absolute-temperature (PTAT) voltage. At
room temperature, this voltage is equal to the internal 1.22V
reference, and it has a +4.1mV/°C temperature coefficient.
The output diode’s temperature coefficient TCF can easily
be found experimentally by applying a uniform tempera-
ture to both the output diode and the LT8315. First, RFB1
and RFB2 are adjusted to give the desired output voltage
at room temperature. The temperature is then raised or
lowered by a known amount to a new temperature, and
the diode temperature coefficient is found as:
TCF=
V
OUT(25°C)
−V
OUT(TNEW)
T
NEW – 25°C
where
VOUT(25°C) = VOUT measured at room temperature
VOUT(TNEW) = VOUT measured at new temperature
TNEW = New temperature in Celsius
Alternatively, TCF can be found more accurately by measur-
ing VOUT at two extremes of temperature and computing:
TCF=–
ΔV
OUT
ΔT
It should be noted that for this measurement, it is critical
that the entire board be heated or cooled uniformly, for
example by an oven. A heat gun or freeze spray will not
suffice, since the heating and cooling will not be uniform,
and dramatic temperature mismatch between the LT8315
and the output diode will cause significant error.
If no method is available to apply uniform heat or cooling,
extrapolating data from the diode’s data sheet or assum-
ing a nominal TCF value (such as −1.5mV/°C) may yield
a satisfactory result.
With the output diode’s temperature coefficient known,
a resistor RTC is then attached from the TC pin to the FB
pin. Its value can be calculated as:
RTC =
−R
FB2
• 4.1mV / °C
TCF•N
TS
Example: If the output diode’s temperature coefficient TCF
is found experimentally to be –1.9mV/°C, then with RFB2
= 88.7kΩ, a RTC value of 191kΩ will yield a temperature-
invariant output voltage.
Sense Resistor Selection
The resistor RSNS between the SOURCE pin and GND
should be selected to provide an adequate switch current
to drive the application without exceeding the current limit
threshold.
At maximum current delivery, current limit occurs when
the SOURCE pin voltage is 100mV. In boundary mode,
the maximum output current will depend on the duty cycle
D and is given by:
IOUT(MAX)
100mV
2 •R
SNS
• 1 D
( )
•NP
S
where
NPS = Transformer primary-to-secondary turns ratio
D≈VOUT +V
F
( )
•NPS
VOUT +V
F
( )
•NPS +V
IN
VIN = Power supply voltage.
It should be noted that the worst-case occurs at minimum
VIN, so DVIN(MIN) should be calculated assuming VIN =
VIN(MIN). Solving for the sense resistor value:
RSNS =
1−D
VIN(MIN)
IOUT(MAX)
• 50mV •NPS • 80%
A factor of 80% is introduced to compensate for system
delays and tolerances, but it may need adjustment for the
final application.
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APPLICATIONS INFORMATION
Example: A 12V output voltage is generated from a VIN =
350V input that can drop as low as VIN(MIN) = 250V. If a
transformer with primary-to-secondary turns ratio NPS =
10 is selected and it is to supply a maximum output cur-
rent IOUT(MAX) = 750mA, then the duty cycle is DVIN(MIN) ≈
33% and the sense resistor is calculated RSNS = 356mΩ.
A 330mΩ resistor is selected.
A more accurate value for RSNS can be obtained by finding
D experimentally with an oscilloscope and electronic load.
Output Power
Compared with a buck or a boost converter, a flyback
converter has a complicated relationship between the input
and output currents. Boost converters have relatively con-
stant maximum input current regardless of input voltage,
while buck converters have relatively constant maximum
output current regardless of input voltage, owing to the
fact that they have continuous input and output currents
respectively. A flyback converter, however, has both
discontinuous input and output currents. The duty cycle
affects both input and output currents, making it hard to
predict maximum output power.
The graphs in Figure 1 through Figure 4 show the typical
maximum output power possible for the output voltages
5V, 12V, 24V and 48V. The maximum output power curve
is the calculated output power if the switch voltage is 510V
during the switch-off time. 120V of margin is left for the
leakage inductance voltage spike. To achieve this power
level at a given input, a winding ratio must be calculated
to stress the switch to 510V, resulting in some odd ratio
values. The curves below the maximum output power
curve are examples of common winding ratio values and
the amount of output power at given input voltages.
Figure 1. Maximum Power, VOUT = 5V Figure 2. Maximum Power, VOUT = 12V
Figure 3. Maximum Power, VOUT = 24V Figure 4. Maximum Power, VOUT = 48V
N
PS
= 20
N
PS
= 10
N
PS
= 5
THEORETICAL
MAXIMUM
N
PS
= 40
V
IN
(V)
0
100
200
300
400
500
0
2
4
6
8
10
12
14
16
MAXIMUM OUTPUT POWER (W)
8315 F01
N
PS
= 10
N
PS
= 5
N
PS
= 2
THEORETICAL
MAXIMUM
N
PS
= 20
V
IN
(V)
0
100
200
300
400
500
0
2
4
6
8
10
12
14
16
MAXIMUM OUTPUT POWER (W)
8315 F02
N
PS
= 5
N
PS
= 2
N
PS
= 1
THEORETICAL
MAXIMUM
N
PS
= 10
V
IN
(V)
0
100
200
300
400
500
0
2
4
6
8
10
12
14
16
MAXIMUM OUTPUT POWER (W)
8315 F03
N
PS
= 2
N
PS
= 1
N
PS
= 0.5
THEORETICAL
MAXIMUM
N
PS
= 5
V
IN
(V)
0
100
200
300
400
500
0
2
4
6
8
10
12
14
16
MAXIMUM OUTPUT POWER (W)
8315 F04
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Figure 5. Transformer Model
APPLICATIONS INFORMATION
The following equation calculates output power:
POUT = 0.5 • η • VIN • D • ISW(MAX)
where
η = Efficiency ≈ 80%
D≈VOUT +V
F
( )
•NPS
VOUT +V
F
( )
•NPS +V
IN
ISW(MAX) = Max. switch current limit = 100mV/RSNS
The calculated power is approximate, and does not take
into account timing variations caused by circuit parasitics.
The actual output power must be evaluated on the bench.
Example: Consider a 12V output converter with a VIN(MIN)
of 250V and a VIN(MAX) of 390V. With a ten-to-one primary-
to-secondary winding ratio NPS = 10 and a sense resistor
RSNS = 330mΩ, the maximum power output is 11W at
VIN(MAX) = 390V but lowers to 10W at VIN(MIN) = 250V.
Selecting a Transformer
Transformer specification and design is possibly the most
critical part of successfully applying the LT8315. In addition
to the usual list of guidelines dealing with high-frequency
isolated power supply transformer design, the following
information should be carefully considered.
Linear Technology has worked with several leading mag-
netic component manufacturers to produce pre-designed
flyback transformers for use with the LT8315. Table 1
shows the details of these transformers.
Table 1. Predesigned Transformers — Typical Specifications
TRANSFORMER PART
NUMBER
LPRI
(mH) NP:NS:NTISOLATION VENDOR TARGET APPLICATIONS
PS16-077 4 24:1:4 Reinforced Sumida 140V–380V to 5V/1.5A
PS16-051 4 10:1:2 Reinforced Sumida 140V–380V to 12V/0.6A
PS15-195 4 3:1:1 Reinforced Sumida 100V–500V to 12V/0.2A
PS16-078 4 5:1:1 Reinforced Sumida 140V–380V to 24V/0.3A
750316022 3.3 24:1:4 Functional Wurth 140V–380V to 5V/1.5A
7508111324 2.75 10:1:1 Reinforced Wurth 140V–380V to 12V/0.6A
7508111518 2.4 2.5:1:0.25 Reinforced Wurth 140V–380V to 48V/0.15A
8315 F05
LPRI
LLEAK(PRI) LLEAK(SEC)
NPS:1
IDEAL
Flyback Transformer Modeling
A flyback transformer can be thought of as an ideal trans-
former with a parallel magnetizing inductance and series
leakage inductances, as shown in Figure 5.
The magnetizing inductance, which is the mutual induc-
tance shared by both primary and secondary windings, is
essential for absorbing energy and delivering it to the load.
It stores energy in magnetic flux lines that pass through
both primary and secondary windings.
If the leakage inductances are small, the magnetizing
inductance can be measured by leaving the secondary
open-circuited and measuring the inductance of the pri-
mary, resulting in an inductance LPRI. The magnetizing
inductance can also be measured from the secondary
by leaving the primary open-circuited and measuring the
secondary inductance LSEC. The relationship between the
primary-referred magnetizing inductance and secondary-
referred magnetizing inductance is given by the primary-
to-secondary turns ratio NPS as:
LPRI = LSEC • NPS2
The transformer also has leakage inductances, which are
parasitic inductances associated with each winding. These
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inductances store energy in magnetic flux lines which “leak”
out of the magnetic core and do not pass through both
windings, and therefore represent self-inductances whose
energy cannot be transferred through the transformer. As
such, they contribute to energy loss and reduced converter
efficiency.
If the leakage inductances are small, the combined leak-
age inductance can be measured by short-circuiting the
secondary and measuring the primary inductance. This
results in a primary-referred inductance,
LLEAK = LLEAK(PRI) + LLEAK(SEC) • NPS2
The leakage inductance and magnetizing inductance are
related by the coupling coefficient k according to the
relation:
k=
L
PRI
L
PRI
+L
LEAK
/ 2
Coupling coefficients of k=99% are common, and are a
function of transformer construction and materials. In-
creased voltage isolation between primary and secondary
is often desired for safety purposes, but generally reduces
the coupling coefficient and increases leakage inductance.
Bifilar windings maximize the coupling coefficient, but are
often undesirable because of their minimal isolation and
increased primary-to-secondary capacitance. In the end,
a reasonable trade-off between isolation and coupling
coefficient must be made.
Magnetizing Inductance Requirement
The appropriate magnetizing inductance depends on the
LT8315’s minimum switch-on time, its minimum switch-
off time, and output power.
The conduction of secondary current reflects the output
voltage onto the tertiary winding during the flyback pulse.
The LT8315 obtains output voltage information from the
reflected output voltage on the FB pin. The sample-and-
hold error amplifier needs a minimum of 800ns to settle
and sample the reflected output voltage. In order to ensure
proper sampling, the secondary winding needs to conduct
current for at least 800ns.
The minimum value for primary-side magnetizing induc-
tance is given by:
LPRI ≥tOFF(MIN) •NPS • VOUT +V
F
( )
ISW(MIN)
where
tOFF(MIN) = Minimum switch-off time = 800ns
ISW(MIN) = Minimum switch current limit = 20mV/RSNS
The LT8315 has a minimum switch-on time that prevents
the chip from turning on the power switch for a period
shorter than 250ns in order to blank the initial switch
turn-on current spike. If the inductor current exceeds the
minimum switch current limit during that time, the mini-
mum load current will increase. Therefore, the following
equation must also be observed:
LPRI ≥
t
ON(MIN)
• V
IN(MAX)
ISW(MIN)
where
tON(MIN) = Minimum Switch-On Time = 250ns
Additionally, the magnetizing inductance must be large
enough to provide sufficient power to the output when the
LT8315 operates at maximum frequency. This creates a
third requirement for magnetizing inductance:
LPRI
2 •(V
OUT
+V
F
) •I
OUT(MAX)
•I
SW(MAX)
2• f
SW(MAX)
where
ISW(MAX) = Maximum switch current = 100mV/RSNS
IOUT(MAX) = Maximum load current
fSW(MAX) = Maximum switching frequency = 140kHz
η = Efficiency ≈ 80%
In general, choose a transformer with its primary mag-
netizing inductance about 20% to 50% larger than the
minimum values calculated above.
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APPLICATIONS INFORMATION
Example: For a 12V/750mA output converter with VIN(MAX)
= 390V, VF = 300mV, NPS = 10, and RSNS = 330mΩ, the
first equation requires LPRI ≥ 1.64mH, the second equation
requires LPRI ≥ 1.61mH, and the third equation requires
LPRI ≥ 1.83mH. A reasonable standard value for primary
inductance is LPRI = 2.2mH.
Saturation Current
The current in the transformer windings should not exceed
its rated saturation current. Beyond its saturation value, the
inductance drops and the current rises to an uncontrolled
value, causing extra power dissipation and possible failure.
Choose a transformer whose primary saturation current is
at least 30% greater than ISW(MAX), which is 100mV/RSNS.
Turns Ratios
Typically, choose the transformer primary-to-secondary
turns ratio NPS to maximize available output power. For low
output voltages, a larger NPS ratio can be used to maximize
the transformer’s current gain. However, remember that
the DRAIN pin sees a voltage that is equal to VIN plus the
output voltage multiplied by NPS. Additionally, leakage
inductance will cause a voltage spike (VLEAKAGE) that
adds to this reflected voltage. This total quantity needs to
remain below the 630V absolute maximum rating of the
DRAIN pin to prevent breakdown of the internal power
switch. Together these conditions place an upper limit on
the turns ratio NPS for a given application. Choose a turns
ratio low enough to ensure:
NPS <
630V −V
IN(MAX)
−V
LEAKAGE
V
OUT
+V
F
For producing high output voltages, a low ratio NPS may
be used. However, the multiplied capacitance presented
to the DRAIN node may cause ringing that exceeds the
250ns tON(MIN), causing light-load instability. Fully evaluate
these applications before use with the LT8315.
During operation, the LT8315 derives its power from
a tertiary winding through its BIAS pin. BIAS must be
maintained between 10V and 40V for proper operation.
This dictates a tertiary-to-secondary turns ratio NTS of:
10V
V
OUT
<NTS <
40V
V
OUT
Example: For VOUT = 12V, NTS must lie between 0.83
and 3.33, or a 5:6 and 10:3 tertiary-to-secondary ratio
respectively.
Because the output voltage is measured through the volt-
age appearing on the third winding, NTS directly affects
the output voltage regulation accuracy. For best results,
make sure the transformer is manufactured with a precise
turns ratio specified within ±1%.
Leakage Inductance and Snubbers
Any leakage inductance on either the primary or secondary
windings causes a voltage spike to appear on the primary
after the power switch turns off. This spike is increasingly
prominent at higher load currents where more energy is
stored in the leakage inductance. This energy cannot be
delivered to the load, and must be dissipated as heat. It
is thus very important to minimize transformer leakage
inductance.
When designing an application, adequate margin should
be kept for the worst-case leakage voltage spikes even
under overload conditions. In most cases, the reflected
output voltage on the primary plus VIN should be kept be-
low 510V, as shown in Figure 6. This leaves 120V margin
for the leakage spike across line and load conditions. A
larger voltage margin will be required for poorly wound
transformers with excessive leakage inductance.
In addition to the voltage spikes, the leakage inductance
also causes the DRAIN pin to ring for a while after the
power switch turns off. To prevent the voltage ringing from
falsely triggering the boundary mode detector, the LT8315
internally blanks the boundary mode detector for 800ns.
Any ringing after 800ns may trigger the power switch
to turn back on again before the secondary current falls
to zero, so the leakage inductance spike and associated
ringing should be limited to less than 800ns.
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APPLICATIONS INFORMATION
Figure 7. Snubber Circuits
A snubber circuit is recommended for most applications.
Figure 7 shows two types of snubber circuits that can
protect the internal power switch: the DZ (diode-Zener)
snubber and the RC (resistor-capacitor) snubber. The DZ
snubber ensures a well-defined and consistent clamping
voltage and has slightly higher power efficiency, while
the RC snubber quickly damps the voltage spike ringing
and provides better load regulation and EMI performance.
Figure 6 shows the flyback waveforms with the DZ and
RC snubbers.
For the DZ snubber, proper care must be taken when
choosing both the diode and the Zener diode. Choose a
fast-recovery diode that has a reverse-voltage rating higher
than the maximum DRAIN pin voltage.
Figure 6. Maximum Voltages for SW Pin Flyback Waveform
The Zener diode breakdown voltage should be chosen to
balance power loss and switch voltage protection. The best
compromise is to choose the largest voltage breakdown.
Use the following equation to make the proper choice:
VZENER(MAX) ≤ 630V – VIN(MAX)
Multiple Zener diodes may be placed in series to attain
the required voltage and power dissipation.
The Zener diode must be rated to absorb the power loss in
the clamp, which is due to energy storage in the leakage
inductance and the primary-to-secondary commutation
time, which decreases with higher clamp voltage. A 500mW
Zener is typically recommended.
8315 F06
VSW
tOFF > 800ns
VLEAKAGE
VSW VSW
TIME
No Snubber with DZ Snubber with RC Snubber
tOFF > 800ns
VLEAKAGE
TIME
tOFF > 800ns
VLEAKAGE
TIME
<630V
<510V
<630V
<510V
<630V
<510V
8315 F06b8315 F06a
DZ Snubber RC Snubber
Lℓ
Z
D
C
R
•
•
Lℓ
•
•
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APPLICATIONS INFORMATION
For the RC snubber, the recommended design approach
is to power up at low voltage to avoid overvoltage stress,
measure the period of the ringing on the DRAIN pin when
the power switch turns off without the snubber (TRING),
and then add capacitance CSNUBBER (starting with 100pF)
until the period of the ringing is 1.5 to 2 times longer
(TRING(SNUBBED)). The change in period will determine
the value of the parasitic capacitance CDRAIN, from which
the parasitic inductance LLEAK can also be determined,
according to the equations:
CDRAIN =
C
SNUBBER
T
RING(SNUBBED)
T
RING
2
1
L
LEAK =T
RING
2
2
•1
C
DRAIN
With the value of the DRAIN node capacitance and leakage
inductance known, a resistor can be added in series with
the snubber capacitor to dissipate power and critically
dampen the ringing. The equation for deriving the optimal
series resistance is:
RSNUBBER =LLEAK
C
DRAIN
Energy absorbed by the RC snubber will be converted to
heat and will not be delivered to the load. In high power
applications, the snubber resistor may need to be sized
for thermal dissipation.
Note that the DRAIN capacitance is often dominated by
transformer interwinding capacitance. Also note that
oscilloscope probes present considerable loading capaci-
tance. Use of low-capacitance, high-voltage 100× probes
is recommended.
Leakage Inductance and Output Diode Stress
The output diode may also see increased reverse voltage
stresses from leakage inductance. While it nominally sees
a reverse voltage of the input voltage divided by NPS plus
the output voltage when the MOSFET power switch turns
on, the capacitance on the output diode and the leakage
inductance form an LC tank which may ring beyond that
expected reverse voltage. A snubber or clamp may be
implemented to reduce the voltage spike if it is desired
to use a lower reverse voltage diode.
Secondary Leakage Inductance
Leakage inductance on the secondary forms an inductive
divider that effectively reduces the size of the tertiary-
referred flyback pulse used for voltage feedback. This will
increase the output voltage by a similar percentage. Note
that, unlike leakage spike behavior, this phenomenon is
load independent. To the extent that the secondary leakage
inductance is a constant percentage of mutual inductance
(over manufacturing variations), this can be accommodated
by adjusting the RFB2/RFB1 resistor ratio.
Winding Resistance
Resistance in either the primary or secondary will reduce
conversion efficiency. Good output voltage regulation
will be maintained despite winding resistance due to the
boundary/discontinuous conduction mode operation of
the LT8315.
Boundary Mode Detection
Boundary mode is a variable frequency switching scheme
that always returns the secondary current to zero with
every cycle.
The DCM pin uses a fast, current-input comparator in
combination with a small capacitor CDCM to detect when
the flyback waveform’s dV/dt is negative, indicating that
the secondary diode has turned off and the flyback pulse
on the tertiary winding is falling. To avoid false tripping
due to leakage inductance ringing, a blanking time of
800ns is applied after the switch turns off. The detector
triggers when CDCM draws 170μA of current out of the
DCM pin. This information is used to set the timing of
the FB sample-and-hold and estimate the output current.
This is not the best time to turn the switch on because
the DRAIN voltage is still nearly VIN + (VOUT • NPS), and
turning the switch on would waste all the energy stored
in the parasitic capacitance on the switching node. When
the secondary current reaches zero, discontinuous ringing
begins and the energy in the parasitic capacitance on the
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APPLICATIONS INFORMATION
switch node resonates with the transformer’s magnetizing
inductance, delivering this energy back to VIN. The mini-
mum voltage of the DRAIN node during this discontinuous
ring is VIN – (VOUT • NPS). This is the optimal moment
to turn the switch back on, and the LT8315 does this by
sensing when current drawn out of DCM falls to 85μA.
This switching technique increases efficiency by up to 5%.
Typical CDCM values range from 10pF to 100pF. A good
starting value is 47pF. If the LT8315 is observed not to run
in boundary mode, then increasing this capacitor will help.
An unnecessarily large CDCM value can cause premature
switch turn-on and increased power loss.
Excessive current delivered to the DCM pin can cause erratic
behavior. To avoid this, a resistor RDCM can be added in
series with CDCM to limit the current. Typical values range
from 5kΩ to 50kΩ.
Operation Under Light Output Loads
The LT8315 detects the output voltage from the flyback
pulse appearing on the tertiary winding, which requires
delivering power to the output. Thus, the LT8315 deliv-
ers a minimum amount of energy even during light load
conditions to ensure accurate output voltage information.
The minimum operating frequency at minimum load is
approximately 3.5kHz. The minimum delivery of energy
creates a minimum load requirement on the output of
approximately 1% of the maximum load power.
A Zener diode sufficiently rated to handle the minimum
load power can be used to provide a minimum load without
decreasing efficiency in normal operation. In selecting a
Zener diode for this purpose, the Zener voltage should
be high enough that the diode does not become the load
path during transient conditions but the voltage must
still be low enough that the MOSFET and output voltage
ratings are not exceeded when the Zener functions as the
minimum load.
Standby Mode Operation
For extremely low no-load power dissipation, the LT8315
features a standby mode which is enabled by tying the
SMODE pin to INTVCC. When the load current has dropped
to zero, the LT8315 reduces its minimum switching fre-
quency by a factor of 16 from 3.5kHz to 220Hz.
This reduces the minimum load current by a factor of 16, at
the cost of slower transient response. Because the output
voltage is sampled only once every 4.6ms, the LT8315 will
be unable to respond to load steps for up to this period.
Output Current Regulation and Soft-Start
Using duty cycle information and the current limit set by
the VC pin, the LT8315 estimates the output current and
regulates it to a setpoint determined by the voltage on the
IREG/SS pin. The output current is regulated according
to the equation:
IOUT =
N
PS
• V
IREG/SS
25 • R
SNS
where
VIREG/SS = Voltage on IREG/SS pin.
A trimmed 10μA current flows out of the IREG/SS pin,
so that a resistor tied from this pin to GND programs the
output current according to the equation:
RIREG/SS =
2.5MΩ•I
OUT
•R
SNS
N
PS
Example: For an application with RSNS = 330mΩ, NPS =
10, and a desired regulated output current IOUT = 0.5A, an
IREG/SS resistor is selected RIREG/SS = 41.2kΩ.
Circuit parasitics, especially transformer capacitance, will
influence the accuracy of output current regulation due
to energy delivery to the parasitics. Although this effect
is usually small, some iteration may be necessary if ac-
curacy better than 5% is required. In this case, RIREG/SS
can be implemented with a rheostat and adjusted until the
desired output current is realized, and then replaced with
a fixed-value resistor for production. When the rheostat
is present, a small bypass capacitor is helpful to attenuate
switching interference pickup by the rheostat. Additionally,
an RC snubber placed across the secondary rectifier can
improve current regulation accuracy.
LT8315
20
8315fa
For more information www.linear.com/LT8315
APPLICATIONS INFORMATION
Soft-start functionality can also be implemented by con-
necting a capacitor from the IREG/SS pin to GND. The
10μA current will act to charge the external soft-start
capacitor. At startup, the regulated output current will rise
monotonically until reaching voltage regulation. The soft-
start capacitor then charges entirely and the output current
regulation loop will not interfere with voltage regulation.
In order to avoid an undervoltage condition which causes
the chip to shut down, the combined capacitance on the
INTVCC and BIAS pins must be sufficient to power the
LT8315 until the output achieves regulation.
If power at VIN is removed, over-temperature protection
is engaged, undervoltage lockout trips, or overcurrent in
the sense resistor is detected, a 20Ω pull-down switch to
GND discharges any capacitance on the IREG/SS pin for
the duration of the fault plus 150μs.
Protection from Shorted Output Conditions
During a shorted output condition, the LT8315 operates at
the minimum operating frequency. In normal operation, the
tertiary winding provides power to the IC, but the tertiary
winding voltage collapses during a shorted condition.
This causes the part’s INTVCC UVLO of 8.2V to shutdown
switching and charge through the depletion startup current
source. The part starts switching again when INTVCC has
reached its turn-on voltage of 12V.
To protect the output diode from excessive power dissipa-
tion during overload conditions, it is advised to program
the regulated output current with a resistor RIREG/SS. For
voltage regulators, the programmed current should be
120% to 150% of the maximum load current to ensure cur-
rent regulation does not interfere with voltage regulation.
Loop Compensation
The LT8315 is compensated using an external resistor-
capacitor network on the VC pin. Typical values are in the
range of RC = 100kΩ and CC = 47nF. If too large an RC
value is used, the part will be more susceptible to high
frequency noise and jitter. If too small of an RC value is used,
the transient performance will suffer. The value choice for
CC is somewhat the inverse of the RC choice: if too small a
CC value is used, the loop may be unstable and if too large
a CC value is used, the transient performance will suffer.
Transient response may be evaluated with a load step box
and adjusted with an adjustable RC compensation network.
Stability should be confirmed over the full range of load
current and input voltage.
Figure 8. 12V High Input Voltage Isolated Flyback Converter
DCM
DRAIN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SOURCE
TC
V
C
BIAS
LT8315
D2
D1
D4
D3
10µF
22nF
47pF
10µF
0.1µF
120µF
4.5mH
500µH
500µH
20k
88.7k
10k
191k
110k
390mΩ
88.7k
0.33µF
200Ω
V
IN
100V TO 500V
VOUT–
VOUT+
12V
10mA TO 200mA
3:1:1
T1
T1: SUMIDA PS15-195
D1, D2: CENTRAL CMMR1U-04
D3: DIODES SMAJ75A
D4: CENTRAL CMMR1U-08
8315 F08
LT8315
21
8315fa
For more information www.linear.com/LT8315
APPLICATIONS INFORMATION
Figure 10. 83% Efficiency 5V/1.5A Isolated Flyback Converter
DCM
DRAIN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SOURCE
TC
V
C
BIAS
LT8315
D2
D1
D4
D3
10µF
47nF
47pF
10µF
0.1µF
1.5mF
8315 F10
4mH
160µH
10µH
20k
158k
10k
22pF
100k
100k
330mΩ
200Ω
69.8k
V
IN
250V TO 350V
VOUT–
VOUT+
5V
20mA TO 1.5A
20:1:4
T1
T1: SUMIDA PS16-077
D1: DIODES SBR8U60P5
D2: DIODES BAV20WS-7-F
D3: DIODES SMAJ200A
D4: CENTRAL CMMR1U-08
Figure 9. Wide Input Range Nonisolated 12V Buck Converter
DCM
DRAIN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SOURCE
TC
V
C
BIAS
LT8315
10µF
330nF
10pF
10µF
4.99k
11k
22.1k
330mΩ
100nF
1mH
D3
44µF
D1
10nF
D2
1.24k
D4
8315 F09
V
IN
19V TO 400V
V
OUT
12V
3mA TO 120mA
D1: CENTRAL CMDSH2-3
D2: CENTRAL CMMR1U-06
D3: C3D1P7060Q
D4: MICRO COMMERCIAL SMBJ5350B-TP
LT8315
22
8315fa
For more information www.linear.com/LT8315
PACKAGE DESCRIPTION
FE20(16) (BB) TSSOP REV Ø 1014
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 8 9 10
111214 13
6.40 – 6.60*
(.252 – .260)
1.78
(.070)
1.78
(.070)
REF
20 19
0.2
18 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
1.78
(.070)
4.83
(.1902)
0.48
(.019)
REF
0.42
(.016)
REF
0.45 ±0.05
0.65 BSC
5.00
±0.10
6.60
±0.10
0.80 ±0.10
0.42
5.68
(.224)
REF
5.68
(.224)
REF
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
Variation: FE20(16)
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1990 Rev Ø)
Exposed Pad Variation BB
0.22
Please refer to http://www.linear.com/product/LT8315#packaging for the most recent package drawings.
LT8315
23
8315fa
For more information www.linear.com/LT8315
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/17 Changed Electrical Characteristics Table Symbols, VSENSE(MIN), VSENSE(MAX), VSENSE(ILIM), to VSOURCE(MIN),
VSOURCE(MAX), VSOURCE(ILIM)
Corrected graph title EN/UVLO Threshold
Corrected TCF equations: Inverted sign of the denominator and added negative sign to ∆VOUT/∆T formula
Corrected Table 1 bottom row transformer part number
Changed Figure 9 VIN range from 20V to 560V, to 19V to 400V and added new D3 diode part number and corrected
D3 diode symbol
Changed Typical Application resistor value of RC network on DCM pin to 20kΩ
3
5
12
14
21
24
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LT8315
24
8315fa
For more information www.linear.com/LT8315
LT 1217 REV A • PRINTED IN USA
www.linear.com/LT8315
ANALOG DEVICES, INC. 2017
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85% Efficient Universal Input Offline Power Supply
DCM
DRAIN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SOURCE
TC
V
C
BIAS
LT8315
D2
D1
D4
D3
10µF
82nF
47pF
10µF
300µF
22pF
4mH
160µH
40µH
20k
95.3k
5.05k
102k
100k
330mΩ
59k
F1
RT1
10µH
10µF
10µF
330µH
D5
Y1
8315 TA02
2.2nF
200
L
V
OUT
10:1:2
12V / 0.55A
N
T1
T1: SUMIDA PS16-051
D1: DIODES DFLS2100
D2: DIODES BAV20WS
D3: DIODES SMAJ200A
D4: CENTRAL CMMR1U-08
D5: CENTRAL CMHZ5243B
90VAC
TO 265VAC
