Rev. 0.1/Jun. 02 15
HYMD232726A(L)8J-J
SERIAL PRESENCE DETECT
Byte# Function Description Function Supported Hexa Value Note
0 Number of Bytes written into serial memory at module manufacturer 128 Bytes 80h
1 Total number of Bytes in SPD device 256 Bytes 08h
2 Fundamental memory type DDR SDRAM 07h
3 Number of row address on this assembly 13 0Dh 1
4 Number of column address on this assembly 10 0Ah 1
5 Number of physical banks on DIMM 1Bank 01h
6 Module data width 72 Bits 48h
7 Module data width (continued) - 00h
8 Module voltage Interface levels(VDDQ) SSTL 2.5V 04h
9 DDR SDRAM cycle time at CAS Latency=2.5(tCK) 6.0ns 60h 2
10 DDR SDRAM access time from clock at CL=2.5 (tAC) +/-0.7ns 70h 2
11 Module configuration type ECC 02h
12 Refresh rate and type 7.8us & Self refresh 82h
13 Primary DDR SDRAM width x8 08h
14 Error checking DDR SDRAM data width x8 08h
15 Minimum clock delay for back-to-back random column
address(tCCD) 1 CLK 01h
16 Burst lengths supported 2,4,8 0Eh
17 Number of banks on each DDR SDRAM 4 Banks 04h
18 CAS latency supported 2, 2.5 0Ch
19 CS latency 001h
20 WE latency 102h
21 DDR SDRAM module attributes Differential Clock Input 20h
22 DDR SDRAM device attributes : General
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
C0h
23 DDR SDRAM cycle time at CL=2.0(tCK) 7.5ns 75h 2
24 DDR SDRAM access time from clock at CL=2.0(tAC) +/-0.7ns 70h 2
25 DDR SDRAM cycle time at CL=1.5(tCK) - 00h 2
26 DDR SDRAM access time from clock at CL=1.5(tAC) - 00h 2
27 Minimum row precharge time(tRP) 18ns 48h
28 Minimum row activate to row active delay(tRRD) 12ns 30h
29 Minimum RAS to CAS delay(tRCD) 18ns 48h
30 Minimum active to precharge time(tRAS) 42ns 2Ah
31 Module row density 256MB 40h
32 Command and address signal input setup time(tIS) 0.75ns 75h
33 Command and address signal input hold time(tIH) 0.75ns 75h
34 Data signal input setup time(tDS) 0.45ns 45h
35 Data signal input hold time(tDH) 0.45ns 45h
36~40 Reserved for VCSDRAM Undefined 00h
41 Minimum active / auto-refresh time ( tRC) 60ns 3Ch
42 Minimum auto-refresh to active/auto-refresh
command period(tRFC) 72ns 48h
43 Maximum cycle time (tCK max) 12ns 30h
44 Maximim DQS-DQ skew time(tDQSQ) 0.45ns 2Dh
45 Maximum read data hold skew factor(tQHS) 0.55ns 55h
46~61 Superset information(may be used in future) Undefined 00h
62 SPD Revision code Initial release 00h
63 Checksum for Bytes 0~62 - 12h
64 Manufacturer JEDEC ID Code Hynix JEDEC ID ADh
65~71 --------- Manufacturer JEDEC ID Code - 00h
Bin Sort : J(DDR333@CL=2.5)