inters;| Data Sheet 75A, 55V, 0.008 Ohm, N-Channel UltraFET Power MOSFETs These N-Channel power MOSFETs are manufactured using the innovative UltraFET process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low- voltage bus switches, and power management in portable and battery-operated products. HUF75344G3, HUF75344P3, HUF75344S3S January 2000 File Number 4402.7 Features * 75A, 55V Simulation Models - Temperature Compensated PSPICE and SABER Models - Thermal Impedance PSPICE and SABER Models Available on the WEB at: www.Intersil.com Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature - TB334, Guidelines for Soldering Surface Mount Components to PC Boards Symbol Formerly developmental type TA75344. D Ordering Information PART NUMBER PACKAGE BRAND G HUF75344G3 TO-247 75344G HUF75344P3 TO-220AB 75344P s HUF75344S3S TO-263AB 75344S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF75344S3ST. Packaging JEDEC STYLE TO-247 JEDEC TO-220AB SOURCE DRAIN SOURCE GATE DRAIN GATE DRAIN (FLANGE) JEDEC TO-263AB DRAIN (FLANGE) GATE SOURCE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. UltraFET is a trademark of Intersil Corporation. PSPICE@ is a registered trademark of MicroSim Corporation. SABER@ is a Copyright of Analogy, Inc 1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 2000.HUF75344G3, HUF75344P3, HUF75344S3S Absolute Maximum Ratings Tc = 25C, Unless Otherwise Specified Drain to Source Voltage (Note 1)...........0. 0.0. cee Voss Drain to Gate Voltage (Rag = 20kQ) (Note 1). 0.0... 00 ee VpGR Gate to Source Voltage . 6... eee Ves Drain Current Continuous (Figure 2)... 0.0.0.0 ete eee ID Pulsed Drain Current... 0.0... tenes IDM Pulsed Avalanche Rating.... 0.0... 20.0.0... ccs Eas Power Dissipation .. 0.0... 0... teens Pp Derate Above 25C 00 eee teens Operating and Storage Temperature. .............. 0.00... eee eee Ty. Teta Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s.........0..0 0.00000 eee TL Package Body for 10s, See Techbrief 334............ 0.0.0.0... eee. Tpkg 55 55 +20 75 Figure 4 Figure 6 285 1.90 -55 to 175 300 260 UNITS CAUTION: Siresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. Ty = 25C to 150C. Electrical Specifications Tc. = 25C, Unless Otherwise Specitied PARAMETER SYMBOL TEST CONDITIONS | win] typ | max | unrts OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip = 250A, Vag = OV (Figure 11) 55 - - Vv Zero Gate Voltage Drain Current Ipss Vps = 50V, Vas = OV - - 1 HA Vps = 45V, Vag = OV, Tce = 150C - - 250 pA Gate to Source Leakage Current lass Vas = t20V - - +100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VeasctH) | Yas = Vos: !p = 250A (Figure 10) 2 - 4 v Drain to Source On Resistance 'DS(ON) | !p = 75A, Vas = 10V (Figure 9) - 0.0065 | 0.008 Q THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Rec (Figure 3) - - 0.52 c/w Thermal Resistance Junction to Ambient ReJA TO-247 - - 30 C/W TO-220, TO-263 - - 62 C/W SWITCHING SPECIFICATIONS (Ves = 10V) Turn-On Time ton Vpp = 30V, Ip = 75A, - - 195 ns Turn-On Delay Time ta(on) Ree oe NGS = 10, - 16 - ns Rise Time tr - 112 - ns Turn-Off Delay Time td(OFF) - 37 - ns Fall Time tf - 28 - ns Turn-Off Time torr - - 100 ns GATE CHARGE SPECIFICATIONS Total Gate Charge QgtoT) |Vas=OV to 20V_ | Vpp = 30V, - 175 210 nG Gate Charge at 10V Qgiio) | Vas = OV to 10V Pet ty - 90 108 nc Threshold Gate Charge QgtH) | Vag = OV to 2V ane ae - 5.9 7.0 nc Gate to Source Gate Charge Qgs - 14 - nG Reverse Transfer Capacitance Qgd - 39 - nG 2 intersilHUF75344G3, HUF75344P3, HUF75344S3S Electrical Specifications TT. = 25C, Unless Otherwise Specified (Continued) PARAMETER | SYMBOL | TEST CONDITIONS | MIN | TYP | MAX | UNITS CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vos = 25V, Vas = OV, - 3200 - pF f = 1MHz Output Capacitance Coss (Figure 12) - 1170 - pF Reverse Transfer Capacitance Crss - 310 - pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vep Isp = 75A - - 1.25 Vv Reverse Recovery Time ter Isp = 75A, digp/dt = 100A/us - - 105 ns Reverse Recovered Charge QrRR Isp = 75A, digp/dt = 100A/us - - 210 nG Typical Performance Curves 1.2 80 ri 3 1.0 \ a = 5 < 60 N 2 08 ~ & WwW 5 N ig E 06 NA 5 40 < N\ 5 a z a z a 2 o4 MNS rs . 20 Nn . Ww _ = 0.2 _ a 0 0 0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 Tc, CASE TEMPERATURE (C) Tc, CASE TEMPERATURE (C) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 0.1 ty NOTES: DUTY FACTOR: D = ty/to SINGLE PULSE PEAK Ty = Ppw X Zouc X Rouc + Te 0.01 105 104 103 102 1071 10 10! Zosc: NORMALIZED THERMAL IMPEDANCE t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 intersilHUF75344G3, HUF75344P3, HUF75344S3S Typical Performance Curves (continued) 2000 FOR TEMPERATURES ABOVE 25C DERATE PEAK gq 1000 CURRENT AS FOLLOWS: & | =lo5 [175-T o 150 oe 3 Veg = 20V ee a Veg = 10V 3 LT TTT 409 |. TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 105 104 10% 102 107! 10 10! t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY 1000 t000 Ty = MAX RATED ffR=0 ; yo = tay = (L)(Ias)/(1.3*RATED BVpgs - Vpp) c=25"c = #R#0 z 2 tav = (L/R)In[(las*R)(1.3*RATED BVpgs - Vpp) +1] ~ ira E 100 c w 3 ae Wu 100 3 3b STARTING Ty = z 2 a <_< o 10 a O, a < STARTING Ty = 150C a OPERATION IN THIS z = AREA MAY BE a LIMITED BY rps(on) at Vpss(MAx) = 55V 1 10 0.01 0.1 1 10 1 10 100200 tay, TIME IN AVALANCHE (ms) Vps: DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 150 150 r 7 PULSE DURATION = 801s DUTY CYCLE = 0.5% MAX = 120 _ 120 | Vop=15 = < 2 5 Ww wi 90 c 90 oc a 2 3 oO oO 2 = 60 = 60 a = x Ves = 5V o yi 6 a 25C 30 =~ 30 A PULSE DURATION = 80us 175C DUTY CYCLE = 0.5% MAX -55C - oO, 0 To = 25C 0 0 1 2 3 4 0 1.5 3 45 6 7.5 Vps; DRAIN TO SOURCE VOLTAGE (V) Vas, GATE TO SOURCE VOLTAGE (V) FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARACTERISTICS 4 intersilHUF75344G3, HUF75344P3, HUF75344S3S Typical Performance Curves (continued) 2.5 PULSE DURATION = 80us DUTY CYCLE = 0.5% MAX Vag = 10V, Ip = 75A 2.0 . BZ 7 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1.0 in a 0.5 -80 -40 0 40 80 120 160 200 Ty, JUNCTION TEMPERATURE (C) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.2 1 Ip = 250A \y fo i 1.0 A 7 J -80 -40 0 40 80 120 160 200 Ty, JUNCTION TEMPERATURE (C) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 1.2 Vas = Vps;: Ip = 250nA / ~ NORMALIZED GATE THRESHOLD VOLTAGE o S a 0.4 -80 -40 0 40 80 120 160 200 Ty, JUNCTION TEMPERATURE (C) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 4500 r r Vas = OV, f= 1MHz Ciss = Ces + Cap Crss = Cap c ISs Coss ~ Cps + Cap 3000 \ mm \ Crss 0 10 20 30 40 50 60 Vps, DRAIN TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE = o ao a oy Nn WAVEFORMS IN DESCENDING ORDER: Ip = 75A Vas, GATE TO SOURCE VOLTAGE (V) o Ip = 55A Ip =35A Ip = 20A o 25 50 75 100 Qg, GATE CHARGE (nC) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 5 intersilHUF75344G3, HUF75344P3, HUF75344S3S Test Circuits and Waveforms Vps L VARY tp TO OBTAIN REQUIRED PEAK las Rg i = von Ves DUT P tp ov las 0.010 AAA * VV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT al by lik DUT IG(REF) Vps Y AAA - VVV Ri + Vas = y {je = Vop DUT { | | Res > Vas FIGURE 18. SWITCHING TIME TEST CIRCUIT intersil Vpp tav FIGURE 15. UNCLAMPED ENERGY WAVEFORMS |____ QgcroT) Ig(REF) | 0 Vas 0 __/ FIGURE 17. GATE CHARGE WAVEFORM torr ta(oFF)|* e| t |< F 90% fo 10% 90% 50% <-_ PULSE WIDTH _ FIGURE 19. RESISTIVE SWITCHING WAVEFORMSHUF75344G3, HUF75344P3, HUF75344S3S PSPICE Electrical Model -SUBCKT HUF75337 213; rev 3 Feb 1999 CA 12 8 4.9e-9 CB 15 14 4.75e-9 CIN 6 82.85e-9 LDRAIN DRAIN 2 DBODY 7 5 DBODYMOD Srsict DBREAK 5 11 DBREAKMOD > 4 DPLCAP 10 5 DPLCAPMOD + ESLC Sler EBREAK 11 7 17 1859.7 50 EDS 14 8 5 81 - ESG 6 10681 RLDRAIN DBREAK 11 + 17 EBREAK \18 EGS 13 86 81 >RDRAIN ESG > EVTHRES EVTHRES 6 21 198 1 + EVTEMP 20 6 18 22 1 +fis\-__|2! rt LGATE EVTEMP 3 IT 8 17 1 LDRAIN 25 1e-9 RLGATE LGATE 1 92.6e-9 LSOURCE 3 7 1.1e-9 GATE RGATE 4 4g\-| 6 | ~ ae 9 20 22 [5 # MWEAK LSOURCE KGATE LSOURCE LGATE 0.0085 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.94e-3 RGATE 9 200.36 RLDRAIN 25 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 3.5e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 SiBMOD S2A 6 15 14 13 S2AMOD $2B 13 15 14 13 S2BMOD VBAT 2219 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*400),3))} SOURCE VVY RSOURCE RLSOURCE RBREAK RVTHRES -.MODEL DBODYMOD D (IS = 2.95e-12 RS =2.6e-3 TRS1 = 1.05e-3 TRS2 = 5.0e-7 CJO = 5.19e-9 TT = 5.9e-8 M = 0.55) -MODEL DBREAKMOD D (RS = 1.65e-1 IKF = 30 TRS1 = 1.15e-4 TRS2 = 2.27e-6) -.MODEL DPLCAPMOD D (CJO = 5.40e-9 IS = 1e-30 N=1 M = 0.88 ) -MODEL MMEDMOD NMOS (VTO = 3.29 KP = 5.5 IS = 1e-30 N = 10 TOX = 1 L= 1u W = 1u RG = 0.36) -.MODEL MSTROMOD NMOS (VTO = 3.83 KP = 123 IS = 1e-30 N = 10 TOX = 1 L= 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.90 KP =0.04 IS = 1e-30 N = 10 TOX = 1L = 1u W= 1u RG =3.6) -MODEL RBREAKMOD RES (TC1 = 1.15e-3 TC2 = 2.0e-7) -MODEL RDRAINMOD RES (TC1 = 1.37e-2 TC2 = 3.85e-5) -.MODEL RSLCMOD RES (TC1 = 1.45e-4 TC2 = 2.11e-6) -MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) -MODEL RVTHRESMOD RES (TC1 = -3.7e-3 TC2 = -1.6e-5) -.MODEL RVTEMPMOD RES (TC1 = -2.4e-3 TC2 = 7e-7) -MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF =0.1 VON = -6.9 VOFF= -3.9) -MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF =0.1 VON = -3.9 VOFF= -6.9) -MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF =0.1 VON = -2.99 VOFF= 2.39) -MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF =0.1 VON =2.39 VOFF= -2.99) -ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 7 intersilHUF75344G3, HUF75344P3, HUF75344S3S SABER Electrical Model REV 3 February 1999 template huf75344 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 2.95e-12, cjo = 5.19e-9, tt = 5.90e-8, m = 0.55) d..model dbreakmod = ( LDRAIN d..model dplcapmod = (cjo = 5.40e-9, is = 1e-30, n = 1, m = 0.88) DPLCAP 5 DRAIN m..model mmedmod = (type=_n, vio = 3.29, kp = 5.5, is = 1-30, tox = 1) To if 7_+ 2 m..model mstrongmod = (type=_n, vto = 3.83, kp = 123, is = 1e-30, tox = 1) 2 RLDRAIN m..model mweakmod = (type=_n, vto = 2.90, kp = 0.04, is = 1e-30, tox = 1) <RSLC1 sw_vcesp..model stamod = (ron = 1e-5, roff = 0.1, von = -6.9, voff = -3.9) 2 951 RDBREAK sw_vcsp..model sibmod = (ron = 1e-5, roff = 0.1, von = -3.9, voff = -6.9) RSLCO2 72 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -2.99, voff = 2.39) ISCL RDBODY sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2.39, voff = -2.99) 50 DBREAK c.cani2 n8 = 4.9e-9 s c.cb n15 14 = 4.75e-9 esa($) = RDRAIN n c.cin n6 n8 = 2.85e-9 + EVTHRES 16 +(49\-__ |?! d.dbody n7 n71 = model=dbodymod LGATE EVTEMP 3 DBODY d.dbreak n72 n11 =model=dbreakmod GATE RGATE ./7s\-] 6 ~ ji d.dpicap n10 n5 = model=dplcapmod 1 9 20 22 s a i QMMeD - RLGATE [" MSTRO i.itn8 ni7=1 CIN LSOURCE 8 SOURCE l.Idrain n2 n5 = 1e-9 3 I.Igate n1 n9 = 2.6e-9 RSOURCE |. lsource n3 n7 = 1.1e-9 RLSOURCE k.kl i(L.lgate) i(l.lsource) = I(I.Igate), I(l.lsource), 0.0085 (L1gate) i(l1source) = I(L1gate), I(L!source) RBREAK m.mmed n16 n6 n8 n8 = model=mmedmod, | = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, | = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, | = 1u, w = 1u CA res.rbreak n17n18 =1, tcl = 1.15e-3, tc2 = 2e-7 res.rdbody n71 n5 = 2.6e-3, tcl = 1.05e-3, tc2 = 5e-7 res.rdbreak n72 n5 = 1.65e-1, tc1 = 1.15e-4, tc2 = 2.27e-6 res.rdrain n50 n16 = 1.94e-3, tc1 = 1.37e-2, tc2 = 3.85e-5 res.rgate n9 n20 = 0.36 res.rldrain n2 n5 = 10 RVTHRES res.rigate n1 n9 = 26 res.rlsource n3 n7 = 11 res.rslc1 n5n51 = 1e-6, tel = 1.45e-4, tc2 = 2.11e-6 res.rsic2 n5 n50 = 1e3 res.rsource n&8 n7 = 3.5e-3, tcl = 0, tc2 =0 res.rvtemp n18 n19 =1, tcl = -2.4e-3, tc2 = 7e-7 res.rvthres n22 n8 = 1, tcl = -3.7e-3, tc2 = -1.6e-5 spe.ebreak n11 n7 n17 n18 = 59.7 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n& = 1 sw_vcesp.s1a n6 n12 n13 n8 = model=s1amod sw_vesp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vesp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51 ))))*((abs(v(n5,n51)*1e6/400))** 3)) } } 8 intersilHUF75344G3, HUF75344P3, HUF75344S3S SPICE Thermal Model th JUNCTION REV 5 February 1999 HUF75344 CTHERM1 th 6 5.0e-3 RTHERM = > 7 CTHERM1 CTHERM2 6 5 1.0e-2 CTHERMS 5 4 1.3e-2 CTHERM4 4 3 1.5e-2 6 CTHERM5 3 2 2.2e-2 CTHERM6 2 tl 8.5e-2 RTHERM1 th 6 6.0-4 RTHERM2 7T CTHERM2 RTHERM2 6 5 3.5e-3 RTHERMS3 5 4 2.5e-2 RTHERM4 4 3 4.8e-2 5 RTHERM5S 3 2 1.6e-1 RTHERM6 2 tl 1.8e-1 RTHERM3Z > == CTHERM3 < SABER Thermal Model SABER thermal model HUF75344 4 template thermal_model th tl thermal_c th, tl { < _ ctherm.ctherm1 th 6 = 5.0e-3 RTHERM4 > T CTHERM4 ctherm.ctherm2 6 5 = 1.0e-2 ctherm.ctherm3 5 4 = 1.3e-2 ctherm.ctherm4 4 3 = 1.5e-2 3 ctherm.ctherm5 3 2 = 2.2e-2 ctherm.ctherm6 2 tl = 5.5e-2 RTHERMS5 = S == sCTHERMS rtherm.rtherm1 th 6 = 6.0e-4 < rtherm.rtherm2 6 5 = 3.5e-3 rtherm.rtherm3 5 4 = 2.5e-2 rtherm.rtherm4 4 3 = 4.8e-2 2 rtherm.rtherm5 3 2 = 1.6e-1 rtherm.rtherm6 2 tl = 1.8e-1 } RTHERMG = $ = CTHERM6 < tl CASE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 9 intersil