VSP5000 SLES057 - DECEMBER 2002 12-BIT 30 MSPS DUAL CHANNEL CCD SIGNAL FRONT END FOR DIGITAL COPIER FEATURES D Dual Channel CCD Signal Processing: - - - - Correlated Double Sampler (CDS) Sample Hold Mode Digital Programmable Amplifier CCD Offset Correction (OB loop) D High Performance A/D: - - - - 12-Bit Resolution INL: 2 LSB DNL: 0.5 LSB No Missing Codes D High-Speed Operation - Sample Rate: 30 MHz (Minimum) D 78-dB Signal-To-Noise Ratio (at 0-dB Gain) D Low Power Consumption: - Low Voltage: 3 V to 3.6 V - Low Power: 290 mW (Typ) at 3.3 V - Standby Mode: 20 mW (Typ) APPLICATIONS D Copiers D Scanners D Facsimiles DESCRIPTION The VSP5000 device is a complete application specific standard product (ASSP) for charge-coupled device (CCD) line sensor applications such as copiers, scanners, and facsimiles. The VSP5000 device provides two independent channels of processing lines and performs analog front-end processing and analog-to-digital (A/D) conversion. Each channel has a correlated double sampler (CDS)/sample hold (SH) circuit, a 14-bit analog-to-digital converter (ADC), a digital programmable gain amplifier (DPGA), and an optical black (OB) correction loop. Data output is 12 bits in length and the 2-channel A/D data is multiplexed and output. The VSP5000 is available in a 64-lead LQFP package and operates from a single 3.3-V supply. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Instruments Incorporated VSP5000 www.ti.com SLES057 - DECEMBER 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PRODUCT PACKAGE PACKAGE OUTLINE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING VSP5000 64 Lead LQFP 64-Lead PM -25C 25C to 85C VSP5000PM ORDERING NUMBER TRANSPORT MEDIA VSP5000PM Tray VSP5000PMR Tape and reel (1) A detailed drawing and a dimension table are located at the end of the data sheet. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNITS Supply voltage, VCC, VDD 4V 0.1 V Supply voltage differences, among VCC terminals 0.1 V Ground voltage differences, AGND, DGND Digital input voltage -0.3 V to VDD + 0.3 V Analog input voltage -0.3 V to VCC + 0.3 V 10 mA Input current (any leads except supplies) Ambient temperature under bias -40C to 125C Storage temperature -55C to 150C Junction temperature 150C Lead temperature (soldering, 5 sec) 260C Package temperature (IR reflow, peak) 250C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS all specifications at TA = 25C, all power supply voltages = 3.3 V, and conversion rate (fADCCK) = 30 MHz (unless otherwise noted) VSP5000 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 12 Bits Signal pass 2 ch Maximum conversion rate 30 MHz DIGITAL INPUTS VT+ VT- Input low-to-high threshold voltage 1.8 Input high-to-low threshold voltage 1.1 IIH IIL Input logic high current Input logic low current V V VI = 3 V VI = 0 V Input limit -0.3 SYSCLK clock duty cycle 20 A 20 A VCC+0.3 50% Input capacitance 5 pF DIGITAL OUTPUTS (even and odd channels) Logic coding Straight binary Multiplex frequency VOH VOL 2 Output logic high voltage Output logic low voltage IOH = -2 mA IOL = 2 mA 60 MHz 2.5 V 0.4 V VSP5000 www.ti.com SLES057 - DECEMBER 2002 ELECTRICAL CHARACTERISTICS (CONTINUED) all specifications at TA = 25C, all power supply voltages = 3.3 V, and conversion rate (fADCCK) = 30 MHz (unless otherwise noted) VSP5000 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT (CCDIN) Input signal level for full-scale output DPGA gain = 0 dB 1400 Allowable feed-through level mV 1 Input capacitance V 15 Input limit -0.3 pF 3.3 V TRANSFER CHARACTERISTICS DNL Differential nonlinearity CDS mode, DPGA gain = 0 dB 0.5 1 LSB SH mode, DPGA gain = 0 dB 0.5 1 LSB 2 4 LSB CDS mode, DPGA gain = 0 dB INL Integral nonlinearity 4 SH mode, DPGA gain = 0 dB LSB No missing codes DPGA gain = 0 dB Assured Step input settling time Full-scale step input 1 pixel Overload recovery time Step input from 2 V to 0 V 2 pixels Data latency Signal to noise ratio(1) Signal-to-noise Clock Cycles 9 (fixed) DPGA gain = 0 dB 78 DPGA gain = 24 dB 54 dB 3% Channel mismatch CORRELATED DOUBLE SAMPLER (CDS) Reference level sample settling time Within 1 LSB, driver impedance = 50 8.3 ns Data level sample settling time Within 1 LSB, driver impedance = 50 8.3 ns Clamp-on resistance 400 Clamp level 1.5 V INPUT CLAMP OPTICAL BLACK CLAMP LOOP CCD offset correction range -300 DAC resolution 300 mV 10 Bits Minimum DAC output current COB pin 0.15 A Maximum DAC output current COB pin 153 A Loop time constant CCOB = 0.1 F CCOB = 0.1 F, at current DAC full scale output 40.7 s 1530 V/s Slew rate Program range O ti l bl Optical black k clamp l llevell 0 OB clamp code = 0101 0000 510 160 LSB REFERENCE Positive reference voltage 1.85 V Negative reference voltage 1.1 V 10 Bits DIGITAL PROGRAMMABLE GAIN AMPLIFIER (DPGA) Gain program resolution Gain Gain code = 11 1111 1111 24 dB 16 Gain code = 10 0000 0000 18 dB 8 Gain code = 00 0100 0000 0 dB 1 Gain code = 00 0000 0000 - Gain error V/V 0 0.5 dB (1) SNR = 20 log (16384 / output rms noise in LSB), input connected to ground through a capacitor. 3 VSP5000 www.ti.com SLES057 - DECEMBER 2002 ELECTRICAL CHARACTERISTICS (CONTINUED) all specifications at TA = 25C, all power supply voltages = 3.3 V, and conversion rate (fADCCK) = 30 MHz (unless otherwise noted) VSP5000 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SERIAL INTERFACE Chip address: 2 bits Register address: 4 bits Data: 10 bits Data length 2 Serial clock frequency byte 10 MHz 3.6 V POWER SUPPLY VCC , VDD Supply voltage 3 VCC = VDD = 3.3 V, fSYSCLK = 30 MHz, Load = 10 pF Power dissi dissipation ation 3.3 290 Stand-by mode mW 20 TEMPERATURE RANGE JA Operating temperature -25 85 C Storage temperature -55 125 C Thermal resistance 64-lead LQFP 83 PIN ASSIGNMENTS DGND VCC AGND OUTENB RESET INPUTCLP CA0 CA1 CDS_SEL AGND AGND VCC COB_EV BYPR_EV BYPP_EV BYPM_EV PM PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 B0 (LSB) B1 B2 B3 B4 B5 CLPOB SYSCLK SHD SHP B6 B7 B8 B9 B10 B11 (MSB) 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 DGND VDD AGND VCC AGND SDI SCLK WRT RDO AGND AGND VCC COB_OD BYPR_OD BYPP_OD BYPM_OD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4 BYP_EV CCDIN_EV AGND VCC REFN_EV CM_EV REFP_EV AGND VCC REFP_OD CM_OD REFN_OD VCC AGND CCDIN_OD BYP_OD C/W VSP5000 www.ti.com SLES057 - DECEMBER 2002 FUNCTIONAL BLOCK DIAGRAM SCLK CA0 CA1 SDI RDO WRT BYPP_EV COB_EV BYPM_EV BYP_EV REFP_EV CM_EV Serial Interface REFN_EV Even Channel Internal Reference RESET Current D-to-A Converter Buf CCD Out Signal Decoder Clamp 14-Bit A-to-D Converter CDS/SH CCDIN_EV Digital PGA Output Register OUTENB CDS/SH SEL CLPOB INPUTCLP Output Control Timing / Control SHP 12-Bit Digital Output SHD SYSCLK CCDIN_OD CDS/SH CCD Out Signal 14-Bit A-to-D Converter Digital PGA Output Register Clamp Buf Current D-to-A Converter Decoder Odd Channel Internal Reference BYPP_OD COB_OD BYPM_OD BYP_OD REFP_OD CM_OD REFN_OD 5 VSP5000 www.ti.com SLES057 - DECEMBER 2002 Terminal Functions TERMINAL NO. NAME TYPE(1) DESCRIPTION 1 B0 (LSB) DO A/D converter output, bit 0 (LSB) 2 B1 DO A/D converter output, bit 1 3 B2 DO A/D converter output, bit 2 4 B3 DO A/D converter output, bit 3 5 B4 DO A/D converter output, bit 4 6 B5 DO A/D converter output, bit 5 7 CLPOB DI Optical black clamp pulse 8 SYSCLK DI System clock input 9 SHD DI CCD data sampling pulse 10 SHP DI CCD reference sampling pulse 11 B6 DO A/D converter output, bit 6 12 B7 DO A/D converter output, bit 7 13 B8 DO A/D converter output, bit 8 14 B9 DO A/D converter output, bit 9 15 B10 DO A/D converter output, bit 10 16 B11 (MSB) DO A/D converter output, bit 11 (MSB) 17 DGND P Digital ground for digital outputs (B0-B11) 18 VDD AGND P Digital power supply for digital outputs (B0-B11) P Analog ground VCC AGND P Analog power supply 21 P Analog ground 22 SDI DI Serial interface data input 23 SCLK DI Serial interface data shift clock (triggered at the rising edge) 24 WRT DI Serial interface data write pulse (triggered at the rising edge) 25 RDO DO Serial interface register read output 26 AGND P Analog ground 27 AGND P Analog ground 28 VCC COB_OD P Analog power supply 29 AO Optical black loop output voltage (odd), connect a 0.1-F capacitor from terminal to ground 30 BYPR_OD AO Input buffer reference bypass (odd) 31 BYPP_OD AO CDS positive reference bypass (odd), leave open or bypass to ground through a 0.1-F capacitor 32 BYPM_OD AO CDS negative reference bypass (odd), leave open or bypass to ground through a 0.1-F capacitor 33 BYP_OD AO CDS common reference bypass (odd), bypass to ground through a 0.1-F capacitor 34 CCDIN_OD AI CCD signal input (odd) 35 AGND P Analog ground 36 P Analog power supply 37 VCC REFN_OD AO A/D converter negative reference bypass (odd), bypass to ground through a 0.1-F capacitor 38 CM_OD AO A/D converter common reference bypass (odd), bypass to ground through a 0.1-F capacitor 39 REFP_OD AO A/D converter positive reference bypass (odd), bypass to ground through a 0.1-F capacitor 40 VCC AGND 19 20 41 P Analog power supply Analog ground (1) Designators in TYPE: P: power supply and ground, DI: digital input, DO: digital output, AI: analog input, AO: analog output 6 P VSP5000 www.ti.com SLES057 - DECEMBER 2002 Terminal Functions (Continued) TERMINAL NO. NAME TYPE(1) DESCRIPTION 42 REFP_EV AO A/D converter positive reference bypass (even), bypass to ground through a 0.1-F capacitor 43 CM_EV AO A/D converter common reference bypass (even), bypass to ground through a 0.1-F capacitor 44 REFN_EV AO A/D converter negative reference bypass (even), bypass to ground through a 0.1-F capacitor 45 VCC AGND P Analog power supply 46 P Analog ground 47 CCDIN_EV AI CCD signal input (even) 48 BYP_EV AO CDS common reference bypass (even), bypass to ground through a 0.1-F capacitor 49 BYPM_EV AO CDS negative reference bypass (even), bypass to ground through a 0.1-F capacitor 50 BYPP_EV AO CDS positive reference bypass (even), bypass to ground through a 0.1-F capacitor 51 BYPR_EV AO Input buffer reference bypass (even), bypass to ground through a 0.1-F capacitor 52 COB_EV AO Optical black loop output voltage (even), connect a 0.1-F capacitor from terminal to ground 53 VCC AGND P Analog power supply 54 P Analog ground 55 AGND P Analog ground 56 CDS_SEL DI CDS/SH mode select: High = CDS mode Low = SH mode 57 CA1 DI Chip address 1 58 CA0 DI Chip address 0 59 INPUTCLP DI Input clamp control (active low) 60 RESET DI Asynchronous register reset (active low) 61 OUTENB DI Outputenable/disable: 62 AGND P Analog ground 63 VCC DGND P Analog power supply 64 High = High impedance Low = Output enable P Digital ground for digital outputs (B0-B11) (2) Designators in TYPE: P: power supply and ground, DI: digital input, DO: digital output, AI: analog input, AO: analog output 7 VSP5000 www.ti.com SLES057 - DECEMBER 2002 TIMING SPECIFICATION VSP5000 CDS Mode Timing Specification (Even and Odd Channels) CCD Output Signal N N+1 N+3 N+2 t(CKP) tw(P) SHP t(PD) td(S) t(DP) t(CKP) tw(D) SHD td(S) t(INHIBIT) t(ADC) t(ADC) t(CKP) SYSCLK td(O) B[11:0] N*10 (EV) th(O) N*10 (OD) SYMBOL N*9 (EV) PARAMETER t(CKP) t(ADC) Clock period tw(P) tw(D) SHP pulse width t(PD) t(DP) td(S) t(INHIBIT) Sampling delay th(O) Output hold time(1) td(O) Output delay at data output delay = 0 ns(1) Output delay at data output delay = 3 ns(2) DL Data latency N*9 (OD) N*8 (EV) N*8 (OD) MIN N*7 (EV) TYP 33 SYSCLK pulse width UNIT ns 16.7 ns 6 8.3 ns SHD pulse width 6 8.3 ns SHP trailing edge to SHD leading edge 8 SHD trailing edge to SHP leading edge 8 Inhibited clock period ns ns 3.5 ns 10 ns 6 (1) Load = 25 pF, data output delay = 0 ns, meaning the delay time setting by configuration register of the serial interface. (2) Load = 25 pF, data output delay = 3 ns, meaning the delay time setting by configuration register of the serial interface. 8 MAX ns 9 9 ns 13 ns Clock Cycles VSP5000 www.ti.com SLES057 - DECEMBER 2002 VSP5000 SH Mode Timing Specification (Even and Odd Channels) CCD Output Signal (Even/ Odd) N N+1 N+2 N+3 t(CKP) tw(D) SHD t(DS) td(S) t(ADC) t(ADC) t(CKP) SYSCLK th(O) B[11:0] N*10 (EV) SYMBOL td(O) N*10 (OD) N*9 (EV) PARAMETER t(CKP) t(ADC) Clock period tw(D) td(S) SHD pulse width t(DS) th(O) SHD trailing edge to SYSCLK leading edge Output hold time(1) td(O) Output delay at data output delay = 0 ns(1) Output delay at data output delay = 3 ns(2) DL N*9 (OD) N*8 (EV) N*8 (OD) MIN N*7 (EV) TYP MAX 33 SYSCLK pulse width UNIT ns 16.7 ns 8.3 ns 3.5 ns 6 Sampling delay -8 6 6 Data latency ns ns 9 13 9 ns ns Clock Cycles (1) Load = 25 pF, data output delay = 0 ns, meaning the delay time setting by configuration register of the serial interface. (2) Load = 25 pF, data output delay = 3 ns, meaning the delay time setting by configuration register of the serial interface. 9 VSP5000 www.ti.com SLES057 - DECEMBER 2002 VSP5000 Serial Interface Timing Specification 1 (Write) tsu(X) th(X) WRT tsu(W) tw(CKL) t(CKP) tw(CKH) SCLK th(D) tsu(D) MSB (CA1) SD LSB (D0) 2 Bytes SYMBOL PARAMETER t(CKP) tw(CKH) Clock period tw(CKL) tsu(D) MIN TYP MAX UNIT 100 ns Clock high pulse width 40 ns Clock low pulse width 40 ns Data setup time 30 ns th(D) tsu(X) Data hold time 30 ns WRT to SCLK setup time 15 ns th(X) tsu(W) SCLK to WRT hold time 15 ns WRT setup time 15 ns 10 VSP5000 www.ti.com SLES057 - DECEMBER 2002 VSP5000 Serial Interface Timing Specification 2 (Read) tsu(X) tsu(X) WRT tsu(XW) tw(CKH) tw(CKL) SCLK 1 2 tw(WR) th(X) 15 tw(CKH) 16 1 2 9 th(D) tsu(D) 10 tw(CKH) t(CKP) MSB (CA1) SD LSB (D0) t(CKP) 2 Bytes tsu(R) MSB (D9) RD LSB (D0) 10 Bits SYMBOL PARAMETER t(CKP) tw(CKH) Clock period tw(CKL) tsu(D) MIN TYP MAX UNIT 100 ns Clock high pulse width 40 ns Clock low pulse width 40 ns Data setup time (write) 30 ns th(D) tsu(X) Data hold time (write) 30 ns WRT to SCLK setup time 15 ns th(X) tsu(XW) SCLK to WRT hold time 15 ns WRT setup time 15 ns tw(WR) tsu(R) Minimum WRT width 10 ns Data setup time (read) 30 ns 11 VSP5000 www.ti.com SLES057 - DECEMBER 2002 PRINCIPLES OF OPERATION INTRODUCTION The VSP5000 device was developed for an analog front-end of CCD line image sensor applications such as copiers, facsimiles, and scanners. The VSP5000 device provides two independent even/odd channels of processing line, each operating at 30 MHz. The output signals from each even/odd channel of the CCD image sensor are sampled by a correlated double sampling (CDS) circuit and then transmitted to a 14-bit high-precision analog-to-digital converter (ADC). The ADC output is amplified to the required gain in the digital programmable gain amplifier (DPGA), then rounded to 12-bit data, and output sequentially as even/odd data, which synchronizes with SYSCLK. The CDS can be used as a sample/hold (SH) circuit by setting terminal 56 (CDS_SEL) low. Each channel has an optical black level clamp circuit (OB loop) and automatically compensates for offsets of the CCD and CDS/SH during the OB pixel period (CLPOB). The OB level output value can be set at the required value by the serial interface. DC bias lost in ac-coupling is reproduced as an input clamp voltage, which is at a necessary level for internal operation. The input clamp voltage charges a capacitor connected to CCDIN during the dummy pixel period (INPUTCLP) by SHP. Gain setting, operation polarity of each clock, and selection of operation mode are accomplished through a serial interface by accessing an internal register. All register bits are reset to their default values by setting terminal 60 (RESET) to low. CORRELATED DOUBLE SAMPLER (CDS) AND SAMPLE HOLD (SH) CIRCUIT The CDS circuit removes low frequency and common-mode noise from the CCD image sensor output as it fluctuates per pixel. Noise longer than one pixel in duration among the input signals is rejected by the subtraction operation at the CDS circuit. Figure 1 shows a simplified CDS block graphic. VSP5000 SHP C1 = 10 pF + CCDIN OPA CCD Output - CIN C2 = 10 pF INPUTCLP SHD SHP VCLAMP Figure 1. Simplified Block Diagram of CDS and Input Clamp The CDS can be configured as a sample hold (SH) circuit by setting terminal 56 (CDS_SEL) low. Figure 2 shows a simplified SH circuit block graphic. In the SH mode, the input clamp voltage (VCLAMP) is charged by the INPUTCLP signal and the sampling signal (SHD) to the CIN capacitor. INPUTCLP is activated at the dummy pixel (or OB pixel) of the CCD. By these operations, the dummy pixel (or OB pixel) level voltage is fixed to VCLAMP at the CCDIN terminal. 12 VSP5000 www.ti.com SLES057 - DECEMBER 2002 At the sampling for the OB pixel and effective pixel, VCLAMP voltage is charged to capacitor C1. The voltage lower than VCLAMP, according to the signal voltage from the CCD, is charged to capacitor C2. As the voltage difference in C1 and C2 is acquired at the hold period, the signals from the CCD are acquired as the voltage based on VCLAMP. In the CDS mode, signal voltage takes as voltage difference between sampled voltage by SHP (reference level) and SHD (data level), the signal level is not affected, even when VCLAMP changes or fluctuates in some degree due to leakage, etc. However, when operated as SH, VCLAMP fluctuation causes an offset error, because the signal is acquired based on VCLAMP. In order to prevent VCLAMP leakage, a buffer is inserted to input in the SH mode. VSP5000 VCLAMP SHD C1 = 10 pF + OPA - CCDIN C2 = 10 pF CCD Output CIN SHD INPUTCLP SHD VCLAMP Figure 2. Simplified Sample Hold (SH) Circuit INPUT CLAMP (DUMMY PIXEL CLAMP) Output from the CCD image sensor is ac-coupled with the VSP5000 device through a capacitor. The input clamp reproduces the dc bias lost by ac-coupling and supplies optimum dc bias for proper operation of the CDS/SH circuit. Simplified block diagrams of the input clamp circuit are shown in Figure 1 and Figure 2. The input signal level is clamped to the internal reference voltage by activating both SHP (when at CDS mode or SHD when at SH mode) and INPUTCLP during the CCD dummy pixel output period. HIGH PERFORMANCE ANALOG-TO-DIGITAL CONVERTER (ADC) The analog-to-digital converter of the VSP5000 device is composed of pipeline architecture. The ADC converter has complete differential circuit configuration, error correction circuit, and 14-bit resolution is assured. Circuits which generate the necessary reference voltage at the ADC are built inside the device and are shown as REFP (high-potential reference), REFN (low-potential reference), and CM (common-mode voltage) terminals outside the device. In order to assure ADC accuracy, these reference voltage terminals need to be sufficiently decoupled by capacitors. DIGITAL PROGRAMMABLE GAIN AMPLIFIER (DPGA) The digital programmable gain amplifier (DPGA) circuit controls the gain value in the range of 0 fold to 16 fold (24 dB) by inputting the digital code through the serial interface. See the serial interface section for details. Gain changes linearly in proportion to the setting code. 13 VSP5000 www.ti.com SLES057 - DECEMBER 2002 GAIN vs INPUT GAIN CODE 18 16 14 Gain - V/V 12 10 8 6 4 2 0 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 Input Gain Code ( Decimal, 0 to 1023) Figure 3. Setting Code vs Gain OPTICAL BLACK (OB) LEVEL LOOP AND OB CLAMP LEVEL The VSP5000 device has a built-in self calibration circuit (OB loop), which compensates the OB level by using the optical black (OB) pixels that are output from the CCD image sensor. Figure 4 shows a block diagram of the OB loop and OB clamp circuit. The CCD offset is compensated by converging the calibration circuit, while activating CLPOB during a period when the OB pixels are output from the CCD. In the CDS mode, the CCD offset is compensated as a difference between the reference level and data level of an OB pixel. In the SH mode, VCLAMP is compensated by INPUTCLP as a difference between the fixed dummy pixel and the OB pixel. These compensated signal levels are recognized as actual OB levels and the outputs are clamped to the OB levels set by the serial interface. These OB levels are the black base for the effective pixel period thereafter. Since the DPGA is a gain stage outside the OB loop, the OB levels are not affected even when the gain is changed. The converging time of the OB loop is determined based on the capacitor value connected to the COB terminal and the output from the current output DAC of the loop. The time constant can be obtained from the following equation: T+ 16384 C I MIN where, C is the capacitor value connected to COB, IMIN is the minimum current (0.15 A) of the current DAC, and 0.15 A is equivalent to 1 LSB of the DAC output. When C = 0.1 F, T is 40.7 s. Slew rate (SR) can be obtained from following equation: I SR + MAX C where, C is the capacitor value connected to COB, IMAX is the maximum current (153 A) of the current DAC, and 153 A is equivalent to 1023 LSB of the DAC output. 14 VSP5000 www.ti.com SLES057 - DECEMBER 2002 OB Clamp Level CCDIN ADC CDS/SH DPGA Data Out BYPP Current DAC Decoder CLPOB COB Figure 4. OB Loop and OB Level Clamp The OB clamp level (digital output value) can be set through the serial interface by inputting a digital code to the OB clamp level register. Table 1 shows the digital code and the corresponding OB clamp level. Table 1. Input Code and OB Clamp Level To Be Set INPUT CODE OB CLAMP LEVEL (12-BIT) 0000 0000 0 LSB 0000 0001 2 LSB L L 0100 1111 158 LSB 0101 0000 (default) 160 LSB 0101 0001 162 LSB L L 1011 1111 508 LSB 1111 1111 510 LSB SETTLING OF OB LOOP AND INPUT CLAMP As the input clamp voltage of the capacitor connected to CCDIN and the voltage of the OB loop COB capacitor are completely discharged at start-up and after a long standby state, these two capacitors need to be charged to the proper operational voltage. The charging time for the input clamp voltage is logical AND of SHP (SHD when in SH mode) and INPUTCLP. Actual charging time per line is only the width of the numbers of the SHP in the dummy pixel period. Equally, COB is only charged during the OB pixel period. Therefore, some time is necessary to bring the VSP5000 device to normal operation status at start-up. Though start-up time depends on the number of dummy and pixels per line, 500 ms to 1 s must be kept to be on the safe side. 15 VSP5000 www.ti.com SLES057 - DECEMBER 2002 STANDBY MODE Normal operation mode and standby mode can be switched by the serial interface. In standby mode, power consumption can be reduced as operation is suspended, except for the interface circuit and reference voltage supply. During standby mode, further power reduction may be obtained by suspending SYSCLK. When restoring SYSCLK, which was suspended during standby mode, more than two clocks of SYSCLK must be acquired before inputting the first command. OUTPUT DATA DELAY At the timing when the output data changes, large transient noise occurs due to many logic lines changing at one time. When this transient noise timing overlaps the analog signal sampling timing, it may affect the A/D converting value. To avoid this, changing the timing of the VSP5000 output data can be delayed in approximately 3-ns steps by the serial control. Delayed value, in this case, means the time addition for the default time between SYSCLK and the data output of the timing specification. TEST MODE AND TEST PATTERN The VSP5000 device can be set to the test mode by setting the configuration register. During the test mode, the test pattern generated inside the device is output with or without input. There are two test patterns. One is a pattern which outputs code that is OB level +128 LSB per specific number of pixels (stripe pattern) and the other is a pattern which increments code from 1 to 4095 in specified LSB per pixel (gradation pattern). These can be selected by the serial interface setting the configuration register. CHIP ADDRESS The VSP5000 device has two chip address terminals, CA0 and CA1. The setting of these terminals gives a particular address for the device and the data-writing device can be selected by the address in the serial interface data. By using this function, the serial interface can be used as a common line for up to four devices. REGISTER READING Each register data can be read from the RDO terminal by setting the A3 bit of the serial interface data to 1 and setting the reading register address to A[2:0]. After writing data which specifies the register, pulldown WRT and pullup SCLK and the output reading register value will be output sequentially on RDO. See the serial interface section for details. While reading the register, the writing function is disabled. SERIAL INTERFACE The serial interface of the VSP5000 device is composed of three signals: SDI, SCLK, and WRT. SDI data is sequentially stored in the shift register at the SCLK rising edge and shift register data is stored to parallel latch at the WRT rising edge. Serial data is 2-bytes fixed length and is composed of a 2-bit chip address, a 4-bit register address, and 10-bit data. The chip address can only write to a register in a device that matches its value to the address set by CA0 and CA1. By using this 2-bit chip address, the serial interface can be shared by other devices. Both address and data store from MSB data first and LSB data last. When data with more than 2 bytes is applied, the final 2 bytes immediately before the WRT rising edge are effective and data stored first is lost. Table 2 shows the register configuration and serial data format. Each register value is defined at the time of power on. Resetting to the default value by the RESET signal or setting to the desired value by the serial interface is necessary. 16 VSP5000 www.ti.com SLES057 - DECEMBER 2002 Table 2. Serial Interface Data Format MSB LSB CA1 CA0 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Configuration X X 0 0 0 0 0 0 C7 C6 0 C4 0 C2 C1 C0 Standby mode X X 0 0 0 1 0 0 0 0 0 0 0 0 0 S0 DPGA gain even X X 0 0 1 0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 DPGA gain odd X X 0 0 1 1 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 OB clamp level even X X 0 1 0 0 0 0 O7 O6 O5 O4 O3 O2 O1 O0 OB clamp level odd X X 0 1 0 1 0 0 O7 O6 O5 O4 O3 O2 O1 O0 Test mode X X 0 1 1 0 0 0 0 0 T5 T4 0 T2 0 T0 Reserved X X 0 1 1 1 0 0 0 0 0 0 0 0 0 0 Read out X X 1 R2 R1 R0 X X X X X X X X X X REGISTERS REGISTER DEFINITION Configuration Register (address = 00h) C[2:0]: Clock polarity select (default = 000) C0: INPUTCLP polarity 0 = active low, 1 = active high C1: CLPOB polarity 0 = active low, 1 = active high C2: SHP/SHD polarity 0 = active low, 1 = active high C4: Data output order (default = 0) 0 = Even/Odd, 1 = Odd/Even C[7:6]: Data output delay (default = 00) C7 = 0, C6 = 0 Delay time = 0 ns (typ) C7 = 0, C6 = 1 Delay time = 3 ns (typ) C7 = 1, C6 = 0 Delay time = 6 ns (typ) C7 = 1, C6 = 1 Delay time = 9 ns (typ) Standby Mode (address = 01h) S0: Standby/normal operation select (default = 0) 0 = Normal operation mode, 1 = standby mode Even Channel gain Register (address = 02h) G[9:0]: Gain value = GAIN[9:0] /64 (default = 00 0100 0000) Odd Channel Gain Register (address = 03h) G[9:0]: Gain value = GAIN[9:0] /64 (default = 00 0100 0000) Even Channel OB Clamp Register (address = 04h) O[7:0]: OB clamp level = 2LSB x O[7:0] (default = 0101 0000) Odd Channel OB Clamp Register (address = 05h) O[7:0]: OB clamp level = 2LSB x O[7:0] (default = 0101 0000) Test Mode Register (address = 06h) T0: Test mode enable/disable (default = 0) 0 = Disable, 1 = Enable T2: Test pattern select (default = 0) 0 = Gradation Pattern, 1 = Stripe Pattern T[5:4]: Test pattern data interval (default = 00) T5 = 0, T4 = 0 Stripe pattern = 8 pixels, gradation pattern = 2 pixels T5 = 0, T4 = 1 Stripe pattern = 16 pixels, gradation pattern = 4 pixels T5 = 1, T4 = 0 Stripe pattern = 32 pixels, gradation pattern = 8 pixels T5 = 1, T4 = 1 Stripe pattern = 64 pixels, gradation pattern = 16 pixels 17 VSP5000 www.ti.com SLES057 - DECEMBER 2002 Register Read Out R[2:0]: sets reading register address (A[2:0]) POWER SUPPLY, GROUNDING, AND DEVICE DECOUPLING RECOMMENDATIONS The VSP5000 device incorporates high-precision, high-speed, ADC and analog circuitry, which are vulnerable to any extraneous noise from the voltage rails or elsewhere. For this reason, although the VSP5000 device has analog and digital supply terminals, it must be treated as an analog component and all supply terminals except for VDD must be powered by the analog supply only. This ensures the most consistent results, since digital power lines often carry high levels of wide-band noise that would otherwise be coupled into the device and degrade the achievable performance. Proper grounding, short lead length, and the use of ground planes are also important for high-frequency designs. Multilayer PC boards are recommended for the best performance, since they offer distinct advantages, for example, minimized ground impedance and separation of signal layers by ground layers. It is highly recommended that the analog and digital ground terminals of the VSP5000 device be joined together at the IC and be connected only to the analog ground of the system. The driver stage of the digital outputs (B[11:0]) is supplied through a dedicated supply VDD (terminal 18). VDD must be separated from the other supply terminals completely or at least with a ferrite bead. Because of the high operational speed, the ADC also generates high-frequency current transients and noises that are fed back into the supply and reference lines. This requires the supply and reference terminals to be sufficiently bypassed. In most cases, 0.1-F ceramic chip capacitors are adequate to decouple the reference terminals. Supply terminals should be decoupled to the ground plane with a parallel combination of tantalum (1 F to 22 F) and ceramic (0.1 F) capacitors. The effectiveness of the decoupling largely depends on the proximity to the individual terminal. VDD must be decoupled to the proximity of DGND (terminal 17 and terminal 64). 18 VSP5000 www.ti.com SLES057 - DECEMBER 2002 MECHANICAL DATA PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 Gage Plane 0,25 0,05 MIN 0-7 1,45 1,35 0,75 0,45 Seating Plane 1,60 MAX 0,08 4040152/ C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. 19 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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