Features FAST ACCESS TIME : 35/45/55 ns max STANDBY CURRENT : 20 mA * OPERATING CURRENT : 150 mA ASYNCHRONOUS INPUTS TTL COMPATIBLE INPUTS AND OUTPUT * SINGLE 5 VOLT SUPPLY * 300 MILS WIDTH PACKAGE CAPABLE OF WITHSTANDING GREATER THAN 2000V ELECTROSTATIC DISCHARGE WIDE TEMPERATURE RANGE : - 55C TO + 125C -Description The HM 65764 is a high speed CMOS static RAM organised as 8192 x 8 bits. It is manufactured using MHSs high performance, CMOS technology. Access times as fast as 35 ns are available with maximum power consumption of only 825 mW. The HM 65764 features fully static operation requiring no external clocks or timing strobes, additionally the automatic power-down feature reduces the power consumption by 73 % when deselected. Easy memory expansion is provided by an active low chip select (CS1) and three state drivers, an active high chip select (CS2), an active low output enable. All inputs and outputs of the HM 65764 are TTL compatible and operate from a single 5V supply thus simplifying system design. The HM 65764 is packaged in a plastic/ceramic 300 mils 28 pins DIL, SO 28 pins DIL, or a 32 pins Leadless Chip Carrier allowing high board-level packing densities. The HM 65764 is 100 % processed following the test methods of MIL STD 883C. Block Diagram SENSE AMPS COLUMN DECODER AO AS At2 2-84 HIGH SPEED CMOS SRAM foo ep pan ee T-46-23-12 HM 65764 8K x 8 OCTOBER 1987 Pinouts (top view) DIL (28 PINS) LCG (32 PINS) Logic Symbol Vec i Lid ttt r 00 r Ot P- OZ P= HOS f 04 r 705 r VOR r 07 | Gnd PIN NAMES A0-A12 : Address inputs OE : Output enable 0 : Input/Output Gnd : Ground S1-CS2 : Chip select W_: Write enable Vec : Power TRUTH TABLE CS82 Din Dout MODE = rFrcrtxr x OE X xox rc xitrerxr xsi N Zz Deselect (power down) Valid Read 4 Write Zz Deselect z Deselect L = Low, H = High, X = HorLHM 65764 fan pny an T-46-23-12 * ABSOLUTE MAXIMUM RATINGS _ .. * OPERATING RANGE - * . Operating Voltage Operating Temperature Supply voltage to GND potential -- 0.5 V* to + 7.0V DC input or output voltage : - 3,0V to 7.0V Military (- 2) VCC + 10% - 55C to + 125C DC output voltage in high Z state : - 0,5V to 7,0V : Storage temperature: - 65 Cto + 150C - Commercial (- 5) VCC + 10% OC to + 70C Output current into outputs (low) : 20 mA Electro Static Discharge Voltage = 20000 (per MIL STD 883, Method 3015.2) ELECTRICAL CHARACTERISTICS DC PARAMETERS 65764K-5 Symbol . Parameter 65764M-5 65764M-2 | 65764N-5 |65764N-2 | Unit | Value ICCSB?1 (1) | Stand by supply current 40 40 40 40 mA | max ICCSB2 (2) | Stand by supply current 20 20 20 20 mA | max ICCOP (3) | Average operating supply current 150- 150 150 150 mA | max BMX (4) Input leakage current + 10 + 10 + 10 + 10 pA | max 1OZ (4) Output leakage current + 10 + 10 + 10 + 10 pA | max VIL (5) Input low voltage - 0.8 0.8 0.8 0.8 Vv | max VIH (6) Input high voltage 2.2 2.2 2.2 2.2 Vv min VOL (6) Output low voltage 0.4 0.4 0.4 0.4 v max VOH (6) Output high voltage 2.4 2.4 2.4 2.4 Vv min 1 OS (7) Output short circuit current 350 - 350 - 350 -3 mA | max C IN (8) Input capacitance 5 5 5 5 | pF | max C OUT (8) | Output capacitance 7 7 7 7 pF |} max Note 1: CS > VIH Note 2: CS > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Note 3: VCC max, lout = 0 mA Note 4: GND < VI < VCC, GND < VO < VCC Output disabled Note 5: ViL min = - 3.0V, VIH max = VCC Note 6: VCC = min, {OH = 4 mA, IOL = 8.0 mA Note 7: VCC = max, Vout = GND, duration of the short circuit should not exceed 30 seconds. Not more than 1 output should be shorted at one time Note 8 ; This parameter is sampled and not 100 % tested. TA = 25C, F = 1 MHz, VCC = 5.0V Ss \ 2-85HM 65764 7246-23-12 AC PARAMETERS : Conditions : treat pulse levels GND to gov Guiputfoadhng IOLIOH (eee fig, 1aand 1b) + 30 pF Read cycle Parameter Description 65764-K5 |65764M-5 |65764M-2 | 65764N-5 | 65764N-2/ Unit | Value TAVAV Read cycle time 35 45 45 55 55 ns | min TAVQV Address to data valid 35 45 45 55 55 ns | max TAVQX Data hold from address change 3 5 5 5 5 ns min TELIQV | CS7 low to data valid 35 45 45 55 55 ns | max TEL2QV | CS2 high to data valid 35 45 45 55 55 ns | max TELi1QX | CS low to tow Z (9) 10 10 10 10 ns | min TEH2QX = | CS2 low to low Z 5 10 10 10 10 ns | max TEHIQZ_ |CSi high to high Z (8, 9) 15 20 20 20 20 ns TEL2QZ |CS2 low to high Z 15 20 20 20 20 ns TELIC CSi low to power up 0 0 0 0 0 ns TEHICCL |CS1 high to power down 20 25 25 25 25 ns | max TGLQV OE low to data valid 15 20 20 25 25 ns | max TGLQX OE low to low Z 0 0 0 7) 0 ns | min TGHOZ GE high to high Z 20 25 25 30 30 ns | max Write cycle (10) Parameter Description 65764K-5 |65764M-5 | 65764M-2 | 65764N-5 | 65764N-2 | Unit | Value TAVAV Write cycle time 30 40 40 50 50 ns | min TELIWH |CS8i low to write end 30 40 40 45 45 ns | min TEH2WH j|CS2 high to write end 30 40 40 45 45 ns | min TAVWH Address set up to write end 30 40 40 45 45 ns | min TWHAX Address hold from write end . 0 0 0 ns | min TAVWL Address set up to write start 0 0 0 0 ns min TWLWH _ |W pulse width 20 25 25 30 30 ns | min TDVWH Data set up to write end 15 20 20 25 25 ns | min TWHDX Data hold from write end 0 0 0 0 0 ns | min TWLQZ W high to low Z (10) 15 20 20 20 20 ns | max TWHQX _ |W low to high Z (9, 10) Oo 0 0 0 0 ns |} min Note 9: TEHQZ, TWLQZ are tested with C1 = 5 pF as in figure 1b. Transition is measured + 500 mV from steady Note 10: At yan temperature and voltage condition, TEHQZ is less than TELQX for all devices. These parameters are sampled and not 100 % sampled. Note 11: we Gata input set up and hold timing should be referenced to the rising edge of the signal that terminates 2.86 IIAee eee HM 65764 R1 4810 Ri 4810 5V O A 5v O____~W 3.0V OUTPUT TI ouTPUT ) > sor $2 I... $f ano Linctuine 266 0 [incuvowa 288 a eJIGAND = S-JIGAND at = SCOPE = = SCOPE = Figure la Figure 1b Switching Waveforms READ CYCLE No. 1 (Notes 11, 12) f TAVAV we Vee wy (eee ee | AG-23-12 ALL INPUT PULSES ADDRESS TAVQV 4 b# tavox + oouT PREVIOUS DATA VALID READ CYCLE No. 2 (Notes 11, 13) DATA VALID HIGH IMPEDANCE TEHICCL e TGLOX HIGH IMPEDANCE pout DATA VALIO LOZ TELIC Vee SUPPLY 50% CURRENT \ 2-87 sox =<HM 65764 T-46-23-12 Write Cycle No. 1 (W Controlled) (Note 7) ADDRESS TELIWH TEH2WH = DIN DATA-IN VALID TWLOZ | TWHOX | HIGH IMPEDANCE DoUT DATA UNDEFINED Write Cycle No. 2 (CS Controlled) (Note 7) TAVAV < | f TAVWL Tetwi f * cs2 7 TAVWH TWiLWH W kk HITT LLL Lh Lh po TDVWH TWHDX DIN DATA-IN VALID TWLOZ | \ HIGH IMPEDANCE DOUT OATA UNDEFINED f Note : If CS goes high simultaneously with W high, the output remains in a high impedance state. Note 12 : W is high for read cycle. _ Note 13 : Device is continuously setected, CS = VIL. Note 14 : Address valid prior to or coincident with CS transition low. 2-88HM 65764 Ordering information foo A FG ~23-12 HMT-65764 () -5 HM4-65764 ( ) -5 HM4-65764 () -2 HM4-65764 ( ) -8 jL_ SO PLASTIC DIL LOC 28 pin LCC 28 pin LCC 28 pin PERFORMANCE : DEVICE TYPE PACKAGE TEMPERATURE RANGE HM1-65764 ( ) -5 CERAMIC DIL 0C to + 70C HM1-65764 () -2 CERAMIC DIL - 55C to + 125C HM1-65764 ( ) -8 CERAMIC DIL 55C to + 125C HM3-65764 ( ) -5 PLASTIC DIL 0C to + 70C 0C to + 70C 0C to + 70C - 55C to + 125C 55C to + 125C TEMPERATURE RANGE (- 2, 5, 8) K_: 35 ns (commercial only) M : 45 ns N ; 55 ns DEVICE TITLE 1: CERAMIC 3 : PLASTIC 4 :Lcc T : 80 2-89 PACKAGE (1, 3, 4, T)