DS077-1 (v1.0) No vember 15, 2001 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
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Introduction
The Spartan™-IIE 1.8V Field-Programmable Gate Array
family gives users high performance, abundant logic
resources, and a rich feature set, all at an e x ceptionally low
price. The f ive-member family offers de ns ities ranging f rom
50,000 to 300,0 00 system gates, as shown in Table 1. Sy s-
tem perform anc e is supported beyond 200 MHz.
Spar tan-IIE devices deliver more gates, I/Os, an d features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined architecture based on
the prov en Virt e x™-E platf orm. Features include bl ock RAM
(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable
I/O standards, and four DLLs (Delay-Locked Loops). Fast,
predictabl e interconnect means that successive design iter-
ations continue to meet timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA av oids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no ha rdware replaceme nt
necessary (impossible with ASICs).
Features
• Second generation ASIC replacement technology
- Dens ities as high as 6,912 logic cells with u p to
300,000 system gates
- Streamlined features based on Virt ex-E
architecture
- Unlimited in-system re programmability
- Ver y low cost
• S y stem level feat ures
- SelectRAM+™ hierarchical memory:
·16 bits/LUT distributed RAM
·Configurable 4K-bit true dual-por t block RAM
·Fast interfaces to external RAM
- F ully 3.3V PCI com plia nt to 64 bits a t 66 MHz and
CardBus compliant
- Low-power segmented routing architecture
- Full readback ability fo r verification/observabilit y
- Dedicated carr y logi c for high -spe ed arithm et ic
- E fficient multiplier support
- Cascade chain for wide-input functions
- Ab undant registers/latches with enable , set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution nets
- I EEE 1149. 1 comp ati ble boundar y scan logic
•Versatile I/O and packaging
- Low cost packages available in all densities
- Family footprint compatibility in common packages
- 19 high-perf ormance interf ace standards, including
LVDS and LVPECL
- Up to 120 differential I/O pairs that can be i nput,
output, or bidirectional
- Z ero hold time simplifies system timing
•Fully s upported by powerful Xilinx ISE deve lopment
system
- F ully autom atic mapping, placement, and routing
- I ntegrated with design entry and verification tools
0Spartan-IIE 1.8V FPGA Family:
Introduction and Ordering
Information
DS077-1 (v1.0) November 15, 2001 00Preliminary Product Speci fication
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Table 1: Spar tan-IIE FPGA Family Members
Device Logic
Cells
Typical
System Gate Rang e
(Logic and RAM)
CLB
Array
(R x C) Total
CLBs
Maximum
Available
User I/O
Maximum
Differentia l
I/O Pai rs Distributed
RAM Bits Block
RAM Bits
XC2S50E 1,728 23,000 - 50,000 16 x 24 384 182 84 24,576 32K
XC2S100E 2,700 37,000 - 100,000 20 x 30 600 202 86 38,400 40K
XC2S150E 3,888 52,000 - 150,000 24 x 36 864 263 114 55,296 48K
XC2S200E 5,292 71,000 - 200,000 28 x 42 1,176 289 120 75,264 56K
XC2S300E 6,912 93,000 - 300,000 32 x 48 1,536 329 120 98,304 64K
Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information
2www.xilinx.com DS077-1 (v1 .0) November 15, 2 001
1-800-255-7778 Preliminary Product Specification
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General Overview
The Spartan-IIE family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corn er of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and t he IOB col um ns. These funct iona l elemen ts are
interconnected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spartan-IIE FPGAs are customized by loading configura-
tion data into interna l static me mor y cells. Unlimited repro-
gramming cycles are possible with this approach. Stored
values i n these cells determine logic functions and intercon-
nections implem ent ed in the F PGA . Configu ration data can
be read from an external serial PROM (master serial mode),
or written into the FPGA in slave serial, slave parallel, or
Boundary Scan modes. The Xilinx XC17S00A PROM f amily
is recommended for serial configuration of Spartan-IIE
FPGAs. The XC18V00 reprogrammable PROM family is
recommended for parallel or serial configuration.
Spar t an-I IE FPGAs are typica lly used in high-volume appli-
cations where the versat ility of a f ast programmable solution
adds benefits. Spartan-IIE FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
Spartan-IIE FPGAs achieve high-performance, low-cost
operation through advanced architecture and semiconduc-
tor technology. Spartan-IIE devices provide system clock
rates beyond 200 MHz. Spartan-IIE FPGAs offer the most
cost-effective solution while maintaining leading edge per-
formance. In addition to the conventional benefits of
high-volume programmable logic solutions, Spartan-IIE
FPGAs also offer on-chip synchronous single-port and
dual-port RAM (block and distr ibuted for m ), DLL c lock driv-
ers, programmable set and reset on al l flip-flops, fast carry
logic, and many other features .
Spartan-IIE Fa mil y Compar ed to Spartan- II
Family
•Higher density and more I/O
•Higher perfor m anc e
•Unique pino uts in cost-effective packages
•Differential signaling
- LVDS, Bus LVDS, LVPECL
•VCCINT = 1.8V
- Lower power
- 5V to lerance with 100Ω external resistor
- 3V tolerance directly
•PCI, LVTTL, and LVCMOS2 input buffe rs powered by
VCCO instead of VCCINT
•Unique larger bitstream
Figure 1: Basi c Spar tan -IIE Family FPGA Block Diagram
DLL
DL
L
DLL
DLL
B
L
OC
K RAM
B
L
OC
K RAM
B
L
OC
K RAM
B
L
OC
K RAM
I
/O
L
OG
I
C
DS077
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Sparta n - IIE 1.8 V FP GA Fa m ily: Int roduct i on a nd Orderin g In forma tion
DS077-1 (v1.0) No vember 15, 2001 www.xilinx.com 3
Preliminary Product Specification 1-800-255-7778
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Spartan-IIE Product Availability
Table 2 shows the package and spee d grades ava ilable for
Spartan-IIE family devices. Table 3 shows the maximum user I/Os available on the device and the number of user
I/Os available for each de vice/package combination.
Table 2: Spar ta n-IIE Pack age and Speed Gr ade Availability
Device
Pins 144 208 256 456
Type Plastic TQFP Plastic PQFP Fine Pitch BGA Fine Pitch BGA
Code TQ144 PQ208 FT256 FG456
XC2S50E -6 C, I C, I C, I -
-7 (C) (C) (C) -
XC2S100E-6 C, IC, IC, IC, I
-7 (C) (C) (C) (C)
X C 2 S1 5 0E -6 - (C, I) (C, I) (C, I)
-7 - (C) (C) (C)
XC2S 200 E -6 - C, I C, I C, I
-7 - (C) (C) (C)
XC2S 300 E -6 - C, I C, I C, I
-7 - (C) (C) (C)
Notes:
1. C = Commerc ial, TJ = 0 ° to +85°C; I = Indus trial, TJ = –40°C to +10 0 °C
2. P arentheses indicate product not yet released. Contact sales for avail ability.
Table 3: Spar tan-IIE Us er I/O Chart
Device Maximum
User I/O
Available User I/O According to Packag e Type
TQ144 PQ208 FT256 FG456
XC2S50E 182 102 146 182 -
XC2S100E 202 102 146 182 202
XC2S150E 263 - 146 182 263
XC2S200E 289 - 146 182 289
XC2S300E 329 - 146 182 329
Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information
4www.xilinx.com DS077-1 (v1 .0) November 15, 2 001
1-800-255-7778 Preliminary Product Specification
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Ordering Information
Revision History
The Spartan-IIE Family Data Sheet
DS077-1, Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information (Modu le 1)
DS077-2, Spart an- I IE 1 .8V FP GA Fa mily: Funct i on a l Des crip tio n (Mod ule 2)
DS077-3, Spart an- I IE 1 .8V FP GA Fa mily: DC and Switching Characteristics (Modu le 3)
DS077-4, Spart an- I IE 1 .8V FP GA Fa mily: Pinout Tables (Module 4)
Version No. Date Description
1.0 11 /15/01 Initial X ilinx rele as e .
XC2S50E -6 PQ 208 C
Example: Temperature Range
Numbe r of Pins
Package Type
De vi ce Type
Speed Grade
Device O rdering Options
Device Speed Grade Package Type / Number of Pins Temperature Range (TJ)
XC2S50E -6 Standard Performance TQ144 144-pin Plastic Thin QFP C = Commercial 0°C to +85 °C
XC2S100E - 7 Higher Performance PQ208 208-pin Plastic QFP I = Indust ria l –40°C to +100°C
XC2S150E FT256 256-ball Fine Pitch BGA
XC2S200E FG456 456-bal l Fi ne Pit ch BGA
XC2S300E
