0 XCR3032XL 32 Macrocell Automotive IQ CPLD R DS119 (v1.2) October 18, 2004 0 Advance Product Specification 14 Features * * * * * * * * * The CoolRunner XCR3032XL-Q is supported by WebPACKTM and WebFITTERTM from Xilinx and industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, ViewLogic, and Synplicity), using text (ABEL, VHDL, Verilog) and schematic capture design entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Guaranteed to meet full electrical specifications over TA = -40C to +125C Technology: 0.35 m EEPROM process Full Boundary Scan Test (IEEE 1149.1) for flexible in-system device and system testing Fast programming times in production saves time and money - Increases system reliability through reduced device handling High-speed pin-to-pin delays of 10 ns (100 MHz) Slew rate control per output to reduce EMI 100% routable which enables all device resources to be utilized Refer to XPLA3 Family data sheet (DS012) for architecture description Refer to XCR3032XL data sheet (DS023) for pin descriptions The XCR3032XL-Q features also include industry-standard, IEEE 1149.1, JTAG interface through which boundary-scan testing and In-System Programming (ISP) and reprogramming of the device can occur. This device is electrically reprogrammable using industry standard device programmers. Table 1: CoolRunner XCR3032XL-Q XCR3032XL-Q Description The CoolRunnerTM XCR3032XL-Q CPLD Automotive IQ product is targeted for low power systems that include portable, handheld, automotive, and power sensitive applications. This device includes Fast Zero PowerTM (FZP) design technology that combines low power and high speed. With this design technique, the XCR3032XL-Q delivers low standby current without the need for "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. CoolRunner devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. Macrocells 32 Usable Gates 750 Registers 32 FSYSTEM (MHz) 95 User I/O (44-pin VQFP) 36 Typical ICC (mA) 20 15 10 5 The CoolRunner XCR3032XL-Q employs a full PLA structure for logic allocation within a functon block. The PLA provides maximum flexibility and logic density, with superior pin locking capability, while maintaining deterministic timing. 0 0 20 40 60 80 100 120 140 160 180 200 Frequency (MHz) DS023_01_080101 Figure 1: ICC vs. Frequency at VCC = 3.3V, 25C Table 2: ICC vs. Frequency (VCC = 3.3V, 25C) Frequency (MHz) 0 1 5 10 20 50 100 200 Typical ICC (mA) 0.02 0.13 0.54 1.06 2.09 5.2 10.26 20.3 (c) 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS119 (v1.2) October 18, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 1 R XCR3032XL 32 Macrocell Automotive IQ CPLD Absolute Maximum Ratings(1) Symbol Parameter Min. Max. Unit VCC Supply voltage(2) relative to GND -0.5 4.0 V VI Input voltage(3) relative to GND -0.5 5.5(4) V IOUT Output current, per pin -100 100 mA TJ Maximum junction temperature -40 150 C TSTR Storage temperature -65 150 C Notes: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. The chip supply voltage must rise monotonically. 3. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to 7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 4. External I/O voltage may not exceed VCC by 4.0V. Recommended Operating Conditions Symbol Parameter Min. Max. Unit TA Ambient temperature -40 +125 C VCC Supply voltage 3.0 3.6 V VIL Low-level input voltage 0 0.8 V VIH High-level input voltage 2.0 5.5 V VO Output voltage 0 VCC V TR Input rise time - 20 ns TF Input fall time - 20 ns Quality and Reliability Characteristics Symbol 2 Parameter TDR Data retention NPE Program/erase cycles (Endurance) @ TA = 70C www.xilinx.com 1-800-255-7778 Min Max Units 20 - Years 10,000 - Cycles DS119 (v1.2) October 18, 2004 Advance Product Specification R XCR3032XL 32 Macrocell Automotive IQ CPLD DC Electrical Characteristics Over Recommended Operating Conditions Symbol VOH (1) Parameter Test Conditions Min. IOH = -500 A Output High voltage IIL Unit - V 2.4 - V - 0.4 V 10 A 90%VCC VCC = 3.0V, IOH = -8 mA VOL Max. Output Low voltage IOL = 8 mA (3) Input leakage current VIN = GND or VCC -10 (3) (2) I/O High-Z leakage current VIN = GND or VCC -10 10 A ICCSB Standby current VCC = 3.6V - 1.0 mA ICC Dynamic current(4) f = 1 MHz - 2.0 mA f = 50 MHz - 10 mA f = 1 MHz - 8 pF f = 1 MHz - 12 pF f = 1 MHz - 10 pF IIH CIN CCLK CI/O Input pin capacitance(5) Clock input I/O pin capacitance(5) capacitance(5) Notes: 1. See Figure 2 for output drive characteristics of the XPLA3 family. 2. This parameter guaranteed by design and characterization, not by testing. 3. Typical leakage current is less than 1 A. 4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 5. Typical values, not tested. 100 90 IOL (3.3V) 80 70 mA 60 50 IOH (3.3V) 40 30 IOH (2.7V) 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Volts DS012_10_040402 Figure 2: Typical I/V Curve for the XPLA3 Family, 3.3V, 25C DS119 (v1.2) October 18, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 3 R XCR3032XL 32 Macrocell Automotive IQ CPLD AC Electrical Characteristics Over Recommended Operating Conditions(1) -10 Min. Max. Unit TPD1 Symbol Propagation delay time (single p-term) - 9.1 ns TPD2 Propagation delay time (OR array) - 10.0 ns TCO Clock to output (global synchronous pin clock) - 6.5 ns Setup time (fast input register) 3.0 - ns Setup time (single p-term) 5.4 - ns Setup time (OR array) 6.3 - ns 0 - ns TSUF TSU1 (2) TSU2 TH (2) TWLH Parameter Hold time (2) Global Clock pulse width (High or Low) 4.0 - ns TPLH(2) P-term clock pulse width 6.0 - ns TR(2) Input rise time - 20 ns Input fall time - 20 ns TL (2) fSYSTEM (2) - 95 MHz time(3) - 60 s TINIT ISP initialization time - 60 s TPOE(2) TPOD(2) TPCO(2) TPAO(2) P-term OE to output enabled - 11.2 ns TCONFIG (2) Maximum system frequency Configuration P-term OE to output disabled(4) - 11.2 ns P-term clock to output - 10.7 ns P-term set/reset to output valid - 11.2 ns Notes: 1. Specifications measured with one output switching. 2. These parameters guaranteed by design and/or characterization, not testing. 3. Typical current draw during configuration is 3 mA at 3.6V. 4. Output CL = 5 pF. 4 www.xilinx.com 1-800-255-7778 DS119 (v1.2) October 18, 2004 Advance Product Specification R XCR3032XL 32 Macrocell Automotive IQ CPLD Internal Timing Parameters(1) -10 Symbol Parameter Min. Max. Unit Buffer Delays TIN Input buffer delay - 2.2 ns TFIN Fast Input buffer delay - 3.1 ns TGCK Global Clock buffer delay - 1.3 ns TOUT Output buffer delay - 3.6 ns TEN Output buffer enable/disable delay - 5.7 ns - 2.0 ns Internal Register, Product Term, and Combinatorial Delays TLDI Latch transparent delay TSUI Register setup time 1.2 - ns THI Register hold time 0.7 - ns TECSU Register clock enable setup time 3.0 - ns TECHO Register clock enable hold time 5.5 - ns TCOI Register clock to output delay - 1.6 ns TAOI Register async. S/R to output delay - 2.1 ns TRAI Register async. recovery - 6.0 ns TPTCK Product term clock delay - 3.3 ns TLOGI1 Internal logic delay (single p-term) - 3.3 ns TLOGI2 Internal logic delay (PLA OR term) - 4.2 ns - 2.9 ns Feedback Delays TF ZIA delay Time Adders TLOGI3 Fold-back NAND delay - 3.0 ns TUDA Universal delay - 2.5 ns TSLEW Slew rate limited delay - 6.0 ns Notes: 1. These parameters guaranteed by design and characterization, not testing. DS119 (v1.2) October 18, 2004 Advance Product Specification www.xilinx.com 1-800-255-7778 5 R XCR3032XL 32 Macrocell Automotive IQ CPLD Switching Characteristics VCC S1 Component R1 R2 C1 R1 Values 390 390 35 pF VIN VOUT R2 Measurement TPOE (High) TPOE (Low) TP C1 S1 Open Closed Closed S2 Closed Open Closed Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH - 300 mV. S2 DS023_03_102401 Figure 3: Typical AC Load Circuit +3.0V 90% 10% 0V TR 1.5 ns TL 1.5 ns Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. DS023_06_042800 Figure 4: Typical Voltage Waveform 6 www.xilinx.com 1-800-255-7778 DS119 (v1.2) October 18, 2004 Advance Product Specification R XCR3032XL 32 Macrocell Automotive IQ CPLD Device Part Marking R XCRxxxxXL Device Type This line not related to device part number VQ44 10Q Package Speed Operating Range Sample package with part marking. Ordering Combination Information Device Ordering and Part Marking Number XCR3032XL-10VQ44Q Speed (pin-to-pin delay) Pkg. Symbol No. of Pins 10 ns VQ44 44 Package Type Very Thin Quad Flat Pack (VQFP) Operating Range(1) Q Notes: 1. Q = Automotive: TA = -40 to +125C Revision History The following table shows the revision history for this document. Date Version 10/28/02 1.0 Initial Xilinx release. 02/14/03 1.1 Deleted architecture and pinout sections. 10/18/04 1.2 Added "Not to be used in new designs" watermark; moved to "Mature Products" DS119 (v1.2) October 18, 2004 Advance Product Specification Revision www.xilinx.com 1-800-255-7778 7