IDT7188S IDT7188L CMOS STATIC RAM 64K (16K x 4-BIT) Integrated Device Technology, Inc. FEATURES: * High-speed (equal access and cycle times) -- Military: 25/35/45/55/70/85ns (max.) * Low power consumption * Battery backup operation -- 2V data retention (L version only) * Available in high-density industry standard 22-pin, 300 mil ceramic DIP * Produced with advanced CMOS technology * Inputs/outputs TTL-compatible * Military product compliant to MIL-STD-883, Class B DESCRIPTION: The IDT7188 is a 65,536-bit high-speed static RAM organized as 16K x 4. It is fabricated using IDT's highperformance, high-reliability technology -- CMOS. This stateof-the-art technology, combined with innovative circuit design techniques, provides a cost effective approach for memory intensive applications. Access times as fast as 25ns are available. The IDT7188 offers a reduced power standby mode, ISB1, which is activated when CS goes HIGH. This capability significantly decreases power while enhancing system reliability. The low-power version (L) version also offers a battery backup data retention capability where the circuit typically consumes only 30W operating from a 2V battery. All inputs and outputs are TTL-compatible and operate from a single 5V supply. The IDT7188 is packaged in 22-pin, 300 mil ceramic DIP providing excellent board-level packing densities. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM A0 VCC GND 65,536-BIT MEMORY ARRAY DECODER A13 I/O0 I/O1 I/O2 COLUMN I/O INPUT DATA CONTROL I/O3 CS WE 2989 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. AUGUST 1996 6.3 DSC-2989/7 1 IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATIONS Symbol A0 A1 A2 A3 A4 A5 A6 A7 A8 CS GND 1 22 2 21 20 3 4 V CC A 13 A 12 A 11 A 10 A9 I/O 3 I/O 2 I/O 1 I/O 0 WE 19 18 5 6 17 D22-1 7 16 8 15 9 14 10 13 11 12 Rating Com'l. Mil. Unit VTERM Terminal Voltage -0.5 to +7.0 with Respect to GND -0.5 to +7.0 V TA Operating Temperature 0 to +70 -55 to +125 C TBIAS Temperature Under Bias -55 to +125 -65 to +135 C TSTG Storage Temperature -55 to +125 -65 to +150 C PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA NOTE: 2989 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2989 drw 02 DIP TOP VIEW CAPACITANCE (TA = +25C, f = 1.0MHz, VCC = 0v)) Parameter(1) Symbol Description A0-A13 Address Inputs CS Chip Select WE Write Enable I/O0-3 Data Input/Output VCC Power GND Ground Input Capacitance CI/O I/O Capacitance Max. Unit VIN = 0V 6 pF VOUT = 0V 6 pF NOTE: 2989 tbl 04 1. This parameter is determined by device characterization, but is not production tested. PIN DESCRIPTIONS Name CIN Conditions RECOMMENDED DC OPERATING CONDITIONS Symbol 2989 tbl 01 Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage -- 6.0 V -- 0.8 V VIL Input Low Voltage 2.2 -0.5 (1) NOTE: 2989 tbl 05 1. VIL (min.) = -3.0V for pulse width less than 20ns,once per cycle. TRUTH TABLE(1) Mode RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE CS WE I/O Standby H X High Z Standby Read L H DOUT Active Military Write L L DIN Active Commercial NOTE: 1. H = VIH, L = VIL, X = don't care. Power Grade 2989 tbl 02 6.3 Temperature GND VCC -55C to +125C 0V 5V 10% 0C to +70C 0V 5V 10% 2989 tbl 06 2 IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS VCC = 5.0V 10% IDT7188S Symbol Parameter Test Condition IDT7188L Min. Max. Min. Max. Unit |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC MIL. COM'L. -- -- 10 5 -- -- 5 2 A |ILO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to VCC MIL. COM'L. -- -- 10 5 -- -- 5 2 A VOL Output Low Voltage IOL = 10mA, VCC = Min. 0.5 -- 0.5 V VOH Output High Voltage IOL = 8mA, VCC = Min. -- 0.4 -- 0.4 IOH = -4mA, VCC = Min. 2.4 -- 2.4 -- V 2989 tbl 07 DC ELECTRICAL CHARACTERISTICS(1) (VCC = 5V 10%, VLC = 0.2V, VHC = VCC - 0.2V) 7188S25 7188L25 7188S35 7188L35 7188S45 7188L45 7188S55/70 7188L55/70 7188S85 7188L85 Com'l. Com'l. Symbol Parameter Power Com'l. Mil. ICC1 Operating Power Supply Current CS = VIL, Outputs Open VCC = Max., f = 0(2) S -- 105 -- 105 -- 105 -- 105 L -- 80 -- 80 -- 80 -- Dynamic Operating Current CS = VIL, Outputs Open VCC = Max., f = fMAX(2) S -- 155 -- 140 -- 140 L -- 120 -- 115 -- Standby Power Supply Current (TTL Level) CS VIH, VCC = Max., Outputs Open, f = fMAX(2) S -- 60 -- 50 L -- 40 -- Full Standby Power Supply Current (CMOS Level) CS VHC, VCC=Max., VIN VHC or VIN VLC, f = 0(2) S -- 20 L -- 1.5 ICC2 ISB ISB1 Mil. Unit -- 105 mA 80 -- 80 -- 140 -- 140 110 -- 110 -- 105 -- 50 -- 50 -- 50 40 -- 35 -- 35 -- 35 -- 20 -- 20 -- 20 -- 20 -- 1.5 -- 1.5 -- 1.5 -- 1.5 Com'l. Mil. Com'l. Mil. Mil. NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change. 6.3 mA mA mA 2989 tbl 08 3 IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only) VHC = VCC - 0.2V Typ. (1) VCC @ Symbol Parameter Test Condition VDR VCC for Data Retention ICCDR Data Retention Current tCDR(3) Chip Deselect to Data Retention Time tR(3) Operation Recovery Time (3) |ILI| Max. VCC @ Min. 2.0v 3.0V 2.0V 3.0V Unit 2.0 -- -- -- -- V -- -- 10 10 15 15 600 150 900 225 A 0 -- -- -- -- ns tRC(2) -- -- -- -- ns -- -- -- 2 2 A -- MIL. COM'L. VHC VIN VHC or VLC CS Input Leakage Current NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization but is not production tested. 2989 tbl 09 LOW VCC DATA RETENTION WAVEFORM DATA RETENTION MODE VCC 4.5V 4.5V VDR 2V t CDR V IH CS tR V IH VDR 2989 drw 03 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2989 tbl 10 5V 5V 480 480 DATA OUT DATA OUT 255 255 30pF* 5pF* 2989 drw 05 2989 drw 04 Figure 1. AC Test Load Figure 2. AC Test Load (for tHZ, tLZ, tWZ, tOHZ and tOW) *Includes scope and jig capacitances 6.3 4 IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges) 7188S25 7188L25 Symbol Parameter 7188S35/45 7188L35/45 7188S55/70 7188L55/70 7188S85 7188L85 Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 25 -- 35/45 -- 55/70 -- 85 -- ns tAA Address Access Time -- 25 -- 35/45 -- 55/70 -- 85 ns tACS Chip Select Access Time -- 25 -- 35/45 -- 55/70 -- 85 ns tOH Output Hold from Address Change 5 -- 5 -- 5 -- 5 -- ns Output Selection to Output in Low-Z 5 -- 5 -- 5 -- 5 -- ns tLZ (1) tHZ(1) Chip Deselect to Output in High-Z -- 10 -- 14 -- 20/25 -- 30 ns tPU (1) Chip Select to Power Up Time 0 -- 0 -- 0 -- 0 -- ns tPD (1) Chip Deselect to Power Down Time -- 25 -- 35/45 -- 55/70 -- 85 ns NOTES: 1. This parameter is guaranteed by device characterization but is not production tested. 2989 tbl 11 TIMING WAVEFORM OF READ CYCLE NO. 1(1, 2) tRC (5) ADDRESS tAA tOH PREVIOUS DATA VALID DATAOUT DATA VALID 2989 drw 06 TIMING WAVEFORM OF READ CYCLE NO. 2(1, 3) tRC (5) CS tACS tHZ (4) tLZ (4) DATAOUT DATA VALID tPU HIGH IMPEDANCE tPD ICC VCC SUPPLY CURRENT ISB 2989 drw 07 NOTES: 1. WE is HIGH for Read cycle. 2. CS is LOW for Read cycle. 3. Address valid prior to or coincident with CS transition LOW. 4. Transition is measured 200mV from steady state voltage. 5. All Read cycle timings are referenced from the last valid address to the first transitioning address. 6.3 5 IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges) 7188S25 7188L25 Symbol Parameter 7188S35/45 7188L35/45 7188S55/70 7188L55/70 7188S85 7188L85 Min. Max. Min. Max. Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time 20 -- 30/40 -- 50/60 -- 75 -- ns tCW Chip Select to End-of-Write 20 -- 25/35 -- 50/60 -- 75 -- ns tAW Address Valid to End-of-Write 20 -- 25/35 -- 50/60 -- 75 -- ns tAS Address Set-up Time 0 -- -- 0 -- 0 -- ns tWP Write Pulse Width 20 -- 25/35 -- 50/60 -- 75 -- ns tWR Write Recovery Time 0 -- -- 0 -- 0 -- ns tDW Data Valid to End-of-Write 13 -- 15/20 -- 25/30 -- 35 -- ns tDH Data Hold Time 0 -- 0 -- 0 -- 0 -- ns Write Enable to Output in High-Z -- 7 -- 10/15 -- 25/30 -- 40 ns Output Active from End-of-Write 5 -- 5 -- 5 -- 5 -- tWZ (1) tOW(1) 0 0 NOTES: 1. This parameter is guaranteed by device characterization. ns 2989 tbl 12 TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2 ,3) tWC ADDRESS tAW CS1 , CS2 tWP tAS (7) tWR WE tWZ (6) DATAOUT tOW (6) (4) (4) tDW tDH DATA VALID DATAIN 2989 drw 08 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals should not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 6. Transition is measured 200mV from steady state. 6.3 6 IDT7188S/L CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1,2,3,5) tWC ADDRESS tAW CS tAS t WR tCW WE tDW tDH DATA VALID DATAIN 2989 drw 09 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals should not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 6. Transition is measured 200mV from steady state. ORDERING INFORMATION IDT7188 Device Type X XX X X Power Speed Package Process/ Temperature Range B Military (-55C to +125C) Compliant to MIL-STD-883, Class B D 300 mil Ceramic DIP (D22-1) 25 35 45 55 70 85 Speed in nanoseconds S L Standard Power Low Power 2989 drw 10 6.3 7 This datasheet has been downloaded from: www.DatasheetCatalog.com Datasheets for electronic components.