MOTOROLA INC., 1994
MOTOROLA
TECHNICAL DATA
SEMICONDUCTOR
The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP). On a single semi-
conductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, pro-
gram and data mem ories, a number of peripherals, a nd system support ci r cuitry. Unique feature s
of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL). This com-
bination of features makes the DSP56156 a cost-effective, high-performance solution for many DSP
applications, especially speech coding, digital communications, and cellular base stations.
The central pr ocessing unit of the DSP56156 is the DSP56100 core processor. Like all DSP56100-
based DSPs, the DSP56156 consists of three execution units operating in parallel, allowing up to
six operations to b e performed during each instruction cycle. This parallelism greatly increases the
effective processing speed of the DSP56156. The MPU-style programming model and instruction
set allow straightfo rward ge neration of ef fici ent, compa ct code. The ba sic ar c hitect ur es and devel -
opment tools of Motorola's 16-bit, 24-bit, and 32-bit DSPs ar e so similar that understanding how to
design and program one greatly reduces the time needed to learn the others.
On-Chi p Emulation (OnCETM port) circuitry pr ovides convenient and inexpensi ve debug facil-
ities normally available only through expensive external hardware. Development costs are re-
duced and in-field testing is greatly simplified using the OnCETM port. Figure 1 illustrates the
DSP56156 in detail.
Figure 1 DSP56156 Block Diagram
Specifications and information herein are subject to change without notice.
OnCE is a trademark of Motorola, Inc.
Data
16
Control
9
Address
16
Data ALU
16 x 16 + 40 —> 40-bit MAC
Two 40-bit Accumulators
PLL Clock
Gen.
GDB
PDB
XDB
Internal
Data
Bus
Switch
External
Data
Bus
Switch
Bus
Control
PAB
XAB1
XAB2
Address
Generation
Unit
External
Address
Bus
Switch
IRQ 2
16-bit Bus
16-bit
56100 DSP
Core
Program
Address
Generator
Program
Decode
Controller
Interrupt
Control
Program Control Unit
Sigma-
Delta
Codec
4
3
OnCE™ Port
16-bit
Timer/
Event
Counter
Sync.
Serial
(SSI)
or I/ O
Host
Interface
(HI)
or I/O
5 15 2
(boot)
Sync.
Serial
(SSI)
or I/O
5
7
Data
Memory
2048 × 16 RAM
Program
Memory *
2048 × 16 RAM
64 × 16 ROM
* 12 k x 16 ROM replaces the program RAM on the DSP56156ROM
Advance Information
16-bit Digital Signal Processor
DSP56156
Order this document
by DSP56156/D
REV 1
DSP56156ROM
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2 DSP56156 Data Sheet MOTOROLA
Introduction
DSP56156 Features
Digital Signal Processing Core
• Efficient, object code compatible, 16-bit 56100-Family DSP engine
— Up to 30 Million Instructions Per Second (MIPS) – 33 ns instruction cycle at 60 MHz
— Up to 180 M il li on Opera tion s P er Sec ond ( MOPS) at 60 M Hz
— Highly para lle l i nstruct ion s et wit h unique DSP a ddress ing modes
— Two 40-bi t accumulators including exte nsion b yte
— Parallel 16 × 16- bit multi ply- ac cumul ate in 1 in st ruct i on cyc le (2 clock cyc le s)
— Double pre cis ion 3 2 × 32-bit multiply wit h 72- bi t res u lt i n 6 instruction c yc les
— Least Mean Square (LMS) adap tive loop fil ter i n 2 instructions
— 40-bit Addition/Subt ract ion i n 1 i nstruction cycle
— Fractional and integ er ari thmeti c with support for mult iprec is ion ari thmet ic
— Hardware support f or b lock-f l oati ng poi nt FFT
— Hardware-nested DO loops includi ng inf init e loops
— Zero-overhead fast interrupts (2 instructi on cycl es)
— Three 16-bit internal data buses and t hree 16-bit internal address buse s f or
maximum i nfor ma tion t r ansf er on- ch ip
Memory
• On-chip Harvard architecture permitting simultaneous accesses to program
and memories
• 2048 × 16-bit on-chip program RAM and 64 × 16-bit bootstrap ROM
(or 12 k × 16-bit on-chip program ROM on the DSP56156ROM)
• 2048 × 16-bit on-chip data RAM
• External memory expansion with 16-bit address and data buses
• Bootstrap loading from external data bus, Host Interface, or
Synchronous Serial Interface
Peripheral and Support Circuits
• Byte-wide Host Interface (HI) with Direct Memory Access support
• Two Synchronous Serial Interfaces (SSI) to communicate with codecs and
synchronous serial devices
— Built in µ-law an d A- law c ompres sion/expansion
— Up to 32 software-s elec ta ble ti me s lots in network mode
• 16-bit Timer/Event Counter also generates and measures digital waveforms
• On-chip sigma-delta voice band Codec:
— Samplin g c lo ck ra tes between 100 kHz and 3 MHz
— Four software-programmable decimation/interpola tion ratios
— Internal voltage reference ( 2/5 of positive power supp ly)
— No external components required
DSP56156 Features
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MOTOROLA DSP56156 Data Sheet 3
Introduction
• On-chip peripheral registers memory mapped in data memory space
• Double buffered peripherals
• Up to 27 general purpose I/O pins
• Two external interrupt request pins
• On-Chip Emulation (OnCE™) port for unobtrusive, processor speed-independent
debugging
• Software-programmable, Phase-Locked Loop-based (PLL) frequency synthesizer for the
core clock
Miscellaneous Features
• Power-saving Wait and Stop modes
• Fully static, HCMOS design for operating frequencies from 40 or 60 MHz down to DC
• 112-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; 20 × 20 × 3 mm
• 112-pin Plastic Thin Quad Flat Pack (TQFP) surface-mount package; 20 × 20 × 1.5 mm
• 5 V power supply
Product Documentation
This data sheet plus the two manuals listed in Table 1 are required for a complete DSP56156
description and are necessary to properly design with the part. Documentation is available
from a local Motorola distributor, a semiconductor sales office, or through a Motorola Litera-
ture Distribution Center.
Table 1 DS P56156 Documentation
Topic Description Order Number
DSP56100 Family Manual Detailed description of the 56000-
family architecture and the 16-bit core
processor and instruction set
DSP56100FAMUM/AD
DSP56156 User’s Manual Detailed description of memory,
peripherals, and interfaces DSP56156UM/AD
DSP56156 Data Sheet Pin and package descriptions, and
electrical and timing specifications DSP56156/D
DSP56156 Features
Documentation
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4 DSP56156 Data Sheet MOTOROLA
Introduction
Related Documentation
Table 2 lists additional documentation relevant to the DSP56156.
Data Sheet Conten ts
This data sheet contains:
• signal definitions and pin locations
• electrical specifications and timings
• package descriptions
• design considerations
• ordering information
Table 2 Related Motorola Documentation
Topic Description Order Number
DSP Family Brochure Overview of all DSP product families BR1105/D
Development Tools Product Brief. Includes ordering
information DSPTOOLSP/D
Fractional and Integer Arithmetic Application Report. Includes code APR3/D
Fast Fourier Transforms (FFTs) Application Report. Comprehensive
FFT algorithms and code for
DSP56001, DSP56156, and
DSP96002
APR4/D
G.722 Audio Processing Application Report. Theory and code
using SB-ADPCM APR404/D
Dr. BuB Bulletin Board Flyer. Motorola’s electronic bulletin
board where free DSP software is
available
BR297/D
Third Party Compendium Brochures from companies selling
hardware and software that supports
Motorola DSPs
DSP3RDPTYPAK/D
University Support Program Flyer. Motorola’s program that sup-
ports universities in DSP research
and education
BR382/D
Documentation
Data Sheet Contents
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MOTOROLA DSP56156 Data Sheet 5
Introduction
Pin Groupings
The DSP56156 is avai lab le in a 112- pin Cerami c Quad Flat P ack ( CQFP) an d a 112- pin Pla stic
Thin Quad Flat Pack (TQFP). The input and output signals are organized into the functional
groups indicated in Table 3. Figure 2 illustrates the chip’s pin functions.
NOTE: OVERBARS are used throughout this document to indicate a signal which is at Ground voltage (typi-
cally a TTL logic low — VIL or VOL) when the function is logically true. These signals are, likewis e, at
VCC voltage (typically a TTL logic high — VIH or VOH) when the f unc tion is l ogically false.
Table 3 Functional Pin Groupings
Functional Group Number of Pins
Address 16
Data Bus 16
Bus Control 9
Host Interface (HI) 15
Synchronous Serial Interfaces (SSI) 10
Timer Interface 2
Interrupt and Mode Control 4
Phase-Locked Loop (PLL) and Clock 3
On-Chip Emulation (OnCETM Port) 4
On-Chip Codec 7
Power (VCC)10
Ground (GND) 16
Total 112
Pin Groupings
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6 DSP56156 Data Sheet MOTOROLA
Introduction
Figure 2 D SP56156 Pin Functions
* These pins have an alternate function of general purpose input/output.
H0-H7*
HA0-HA2*
HR/W*
HEN*
HREQ*
HACK*
Interrupt/
Mode
Control
DSP56156
Host
Interface (HI)
On-Chip
Emulator
(OnCE)
Port
STD0*
SRD0*
SCK0*
SC00-SC10*
STD1*
SRD1*
SCK1*
SC01-SC11*
MIC
AUX
SPKM
BIAS
VREF
VDIV VCC
GND
SPKP
MODA/IRQA
MODB/IRQB
MODC
RESET
EXTAL
CLKO
SXFC
A0-A15
D0-D15
BS
PS/DS
WR
RD
R/W
TA
BR
BG
BB
DSI/OS0
DSCK/OS1
DSO
DR
Clock
and
Phase-locked
Loop
(PLL)
External
Bus
On-Chip
Codec
Two
Synchronous
Serial
Interfaces
(SSI)
112 pins
Timer/Event
Counter TIN*
TOUT*
Pin Functions
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Pin Description s
MOTOROLA DSP56156 Data Sheet 7
Pin Descriptions
Address and Data Bus
A0-A15 (Address Bus) — three-state, active
high outputs. A0-A15 change in t0 and
specify the address for external pro-
gram and data memory accesses. If
there is no external bus activity, A0-A15
remain at their previous values. A0-A15
are three-stated during hardware reset.
D0-D15 (Data Bus) — three-state, active
high, bidirectional input/outputs.
Read data is sampled on the trailing
edge of t2, while write data output is
enabled by the leading edge of t2 and
three-stated at the leading edge of t0. If
there is no external bus activity, D0-D15
are three-stated . D0-D15 are also thre e-
stated during hardware reset.
Bus Control
PS/DS (Program/Data Memory Select) —
three-state, active low output. This out-
put is asserted only when external data
memory is referenced. PS/DS timing is
the same for the A0-A15 address lines.
PS/DS is high for program memory ac-
cess and is low f or data memory access. If
the external bus is not used during an in-
struction cycle (t0, t1, t2, t3), PS/DS goes
high in t0. PS/DS is in the high imped-
ance state du ring hardware re set.
R/W (Read/Write) — three-state, active
low output. Timing is th e same as the
address lines, providing an “early
write” signal. R/W (which changes in
t0) is high for a read access and is low
for a write access. If the external bus is
not used during an instruction cycle
(t0, t1, t2, t3), R/W goes high in t0. R/W
is thre e-stated during hardw a re reset.
WR (Write Enable) — three-state, active
low output. This output is asserted dur-
ing external memo ry write cycles. When
WR is asserted in t1, the data bus pins
D0-D15 become outputs and the DSP
puts data on the bus during the leading
edge of t2 . When WR is deasserted in t3,
the external d ata has bee n latched inside
the external device. When WR is assert-
ed, it qualifies the A0-A15 and PS/DS
pins. WR can be connected directly to
the WE pin of a static RAM. WR is three-
stated during hardware reset or when
the DSP is not bus master.
RD (Read Enable) — three-state, active
low output. This output is asserted
during external memory read cycles.
When RD is asserted in late t0/early t1,
the data bus pins D0-D15 become in-
puts and an external device is enabled
onto the data bus. When RD is deas-
serted in t3, the external data is latched
inside the DSP. When RD is asserted, it
qualifies the A0-A15 and PS/DS pins .
RD can be connected directly to the
OE pin o f a s tatic RAM o r RO M. RD is
three-stated during hardware reset or
when the DSP is not bus master.
BS (Bus Strobe) — three-state, active
low output. Asserted at the start of a
bus cycle (during t0) and deasserted at
the end of the bus cycle (during t2).
This pin provides an “early bus start”
signal which can be used as address
latch and as an “early bus end” signal
which can be used by an external bus
controller. BS is three-stated during
hardware reset.
Address and Data Bus
Bus Contro l
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8 DSP56156 Data Sheet MOTOROLA
Pin Descriptions
TA (Transfer Acknowledge) — active
low input. If there is no external bus ac-
tivity, the TA input is ignored by the
DSP. When there is external bus cycle
activity, TA can be used to insert wait
states in the external bus cycle. TA is
sampled on the leading edge of the
clock. Any numb er of wait stat es f rom 1
to infinity may be inserted by using TA.
If TA is sampled high on the leading
edge of the clock beginning the bus c y-
cle, the bus cycle will end 2T after the
TA has been sampled low on a l eading
edge of the clock; if the Bus Control Reg-
ister (BCR) value does not program
more wait states. The number of wait
states is determined b y the TA in put or
by the Bus Control Register (BCR),
whichever is longer. TA is still sampled
during the leading edge of the clock
when wait states are controlled by the
BCR value. In that case, TA will have to
be sampled low during the leading edge
of the last period of the bus cycle pro-
grammed by the BCR (2T before the end
of the bus cycle programmed by the
BCR) in order not to add any wait states.
TA should always be deasserted during
t3 to be sampled high by the leading
edge of T0. If TA is sampled low (assert-
ed) at the leading edge of the t0 begin-
ning the bus cycle, and if no wait states
are specified in the BCR register, zero
wait st ates wi ll be in serted in the exter-
nal bus cycle, regardless the status of
TA during the leading edge of T2.
BR (Bus Request) — active low output
when in master mode, active low in-
put when in slave mode. After power-
on reset, this pin is an input (slave
mode). In this mode, the bus request
BR allows another device such as a pro-
cessor or DMA controller to become
the master of the DSP external data
bus D0-D15 and external address bus
A0-A15. The DSP asserts BG a few T
states after the BR input is asserted.
The DSP bus controller releases control
of the external data bus D0-D15, ad-
dress bus A0-A15 and bus control pins
PS/DS, RD, WR, and R/W at the earli-
est time po ssible cons istent with prop -
er synchronization. Th ese pins are then
placed in the high impedance state and
Bus Control
T0 T1 T2 T3 T0 T1 T2 Tw T2 T3 T0 T1 T2 T3 T0 T1 T2 Tw T2 Tw T2 T3
T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1 T2 Tw T2 Tw T2 T3 T0 T1 T2
CLKO
TA
BS
CLKO
TA
BS
Figure 3 TA Controlled Accesses
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Pin Description s
MOTOROLA DSP56156 Data Sheet 9
the BB pin is deasserted. The DSP con-
tinues executing instructions only if in-
ternal program and data memory
resources are accessed. If the DSP re-
quests the external bus while BR input
pin is asserted, the DSP bus controller
inserts wait states until the external bus
becomes available (BR and BB deas-
serted). Note that interrupts are not
serviced when a DSP instruction is
waiting for the bus controller. Note
also that BR is prevented from inter-
rupting the execution of a read/ modi-
fy/write instruction.
If the master bit in the OMR regis ter is
set, this pin becomes an output (Master
Mode). In this mode, the DSP is not the
external bus master and has to assert
BR to request the bus mastership. The
DSP bus controller will insert wait
states until BG input is asserted and
will then begin normal bus accesses af-
ter the rising of the clock which sam-
pled BB high. The BR output signal will
remain asserted until the DSP no long-
er needs the bus. In this mode, the Re-
quest Hold bit (RH) o f th e Bus Control
Register (BCR) allows BR to be asserted
under software control.
During external accesses caused by an
instruction executed out of external pro-
gram memory, BR remains asserted low
for consecutive external X memory ac-
cesses and continues toggling for con-
secutive external P memory accesses
unless the Request Hold bit (RH) is set
inside the Bus Control Register (BCR).
In the master mode, BR can also be
used for non arbitration purpose: if BG
is always asserted, BR is asserted in t0
of every externa l bus access. It can th en
be used as a chip select to turn a exter-
nal memory device off and on between
internal and external bus accesses. BR
timing is in that case similar to A0-A15,
R/W and PS/DS; it is asserted and
deasserted during t0.
BG (Bus Grant) — active low input when
in master mode, active low output
when in slave mode. Output after
power on reset if the slave is selected,
this pin is asserted to acknowledge an
external bus request. It indicates that
the DSP will release control of the ex-
ternal address bus A0-A15, data bus
D0-D15 and bus control pins when BB
is deasserted. The BG output is assert-
ed in response to a BR input. When the
BG output is asserted and BB is deas-
serted, the external address bus A0-A15,
data bus D0-D15 and bus control pins
are in the high i mpedance state. BG as-
sertion may occur in the middle of an
instruction which requires more than
one external bus cycle for execution.
Note that BG assertion will not occur
during indivisible read-modify-write
instructions (BFSET, BFCLR, BFCHG).
When BR is deasserted, the BG output
is deasserted and the DSP regains con-
trol of the external address bus, data
bus, and bus control pins when the BB
pin is sam pled high.
This pin becomes an input if the master
bit in the OMR register is set (Master
Mode). It is asserted by an external pro-
cessor when the DSP may become the
bus master. The DSP can start normal
extern al memory access afte r the BB pin
has been deasserted by the previous
bus ma ster . When BG is deasserted, the
DSP will release the bus as soon as the
curre nt trans fer is com ple ted. The stat e
of BG may be tested by testing the BS bit
in the Bus Control Register. BG is ig-
nored during hardware reset.
Bus Control
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10 DSP56156 Data Sheet MOTOROLA
Pin Descriptions
BB (Bus Busy) — active low input when
not bus master, active low output
when bus master. This pin is asserted
by the DSP when it becomes the bus
master and it performs an external ac-
cess. It is deass erted when the DSP re-
leases bus mastership. BB becomes an
input when the DSP is no longer the
bus master.
Interrupt and Mode Control
MODA/IRQA (Mode Select A/External In-
terrupt Request A) — input. This in-
put has two functions:
•to select the initial chip operating
mode and,
•to allow an external device to request
a DSP interru pt after internal syn-
chronization.
MODA is read and internally latched
in the DSP when the processor exits the
reset state. MODA and MODB select
the initial chip operating mode. Several
clock cycles after leaving the reset state,
the MODA pin changes to the external
interrupt request IRQA. The chip oper-
ating mode can be changed by soft-
ware after reset.
The IRQA input is a synchronized ex-
ternal interrupt request which indi-
cates that an external device is
requesting service. It may be pro-
grammed to be l evel sensitiv e or neg a-
tive edge triggered. If level sensitive
triggering is selected, an external pull
up resistor is required for wired-OR
operation. If the processor is in the stop
standby state and IRQA is asserted, the
processor will exit th e stop state.
MODB/IRQB (Mode Select B/External In-
terrupt Request B) — input. This in-
put has two func tions:
•to select the initial chip operatin g
mode and,
•to allow an external device to request
a DSP interrupt after internal syn-
chronization.
MODB is read and internally latched in
the DSP when the processor exits the
reset state. MODA and MODB select
the initial chip operating mode . Several
clock cycles after leaving the reset state,
the MODB pin changes to the external
interrupt request IRQB . A fter reset, th e
chip operating mode can be changed
by software.
The IRQB input is an external interrupt
request which indicates that an exter-
nal device is requesting service. It may
be programmed to be level sensitive or
negative edge triggered. If level sensi-
tive triggering is selected, an external
pull up resistor is required for wired-
OR operation.
MODC (Mode Select C) — input. This input
selects the initial bus operating mode.
When tied high, the external bus is pro-
grammed in the master mode (BR out-
put and BG input) and when tied low
the bus is programmed in the slave
mode (BR input and BG output).
MODC is read and internally latched in
the DSP when the processor exits the
reset state. After RESET, the bus operat-
ing mode can be changed by software by
writing the MC bit of the OMR register .
RESET (Reset) — input. This input is a direct
hardware reset of the processor. When
RESET is assert ed, the DSP is initialized
and placed in the reset state. A Schmitt
Interrupt an d Mode Control
Bus Control
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Pin Description s
MOTOROLA DSP56156 Data Sheet 11
trigg er inpu t is u sed for nois e immuni ty.
When the reset pin is deasserted, the ini-
tial chip operating mode is latched from
the MODA and MODB pins, and the ini-
tial bus operating mode is latched from
the MODC pin. The int ernal reset si gnal
should be deasserte d synch ronized with
the internal clocks.
Host Interface
H0- H7 (Ho st Dat a Bu s) — bidirectional. This
bidirectional data bus is used to transfer
data between the host processor and the
DSP. This bus is an input unless enabled
by a host processor read. H0-H7 may be
programmed as Port B general purpose
parallel I/O pins called PB0-PB7 when
the Host Interface (HI) is not being used.
HA0-HA2 (Host Address 0-2) — input*. These
inputs provide the address selection
for each HI register and are stable
when H EN is asserted. H A0-HA2 may
be programmed as Port B general pur-
pose parallel I/O pins called PB8-PB10
when the HI is not being used.
HR/W (Host Read/Write) — input*. This in-
put selects the direction of data transfer
for each host processor access. If HR/W
is high and H EN is asserted, H0-H7 are
outputs and DSP data is transferred to
the host processor. If HR/W is low an d
HEN is asserted, H0-H7 are inputs and
host data is transferred to the DSP.
When HEN is asserted, HR/W is stable.
HR/W may be programmed as a gen-
eral purpose I/O pin called PB11
when the HI is not being used.
HEN (Host Enable) — input*. This input en-
ables a data transfer on the host data
bus. When HEN is asserted and HR/W
is high , H0-H7 becomes an output and
DSP data may be latched by the host
processor. When HEN is asserted and
HR/W is low, H0-H7 is an input and
host data is latched inside the DSP
when HEN is deasserted. Normally a
chip select signal derived from host ad-
dress decoding and an enable clock is
connected to the Host Enable. HEN
may be programmed as a general pur-
pose I/O pin called PB12 when the HI
is not being used.
HREQ (Host Request) — output*. This open-
drain output signal is used by the HI to
request service from the host proces-
sor. HREQ may be conn ected to an in-
terrupt request pin of a host processor,
a transfer request of a DMA controller,
or a co ntrol input of external circuitry.
HREQ is asserted when an enabled re-
quest occurs in the HI. HREQ is deas-
serted when the enabled request is
cleared or masked, DMA HACK i s as-
serted, or the DSP is reset. HREQ may
be programmed as a general purpose
I/O pin (not open-drain) called PB13
when the HI is not being used.
HACK (Host Acknowledge) — input*. This
input has two functions:
•to provide a host acknowledge signal
for DMA transfers and,
•to control handshaking and to pro-
vide a host interrupt acknowledge
compatible with MC68000 family
processors.
If programmed as a host acknowledge
signal, HACK may be used as a data
strobe for HI DMA data transfers. If pro-
gramme d as an MC68000 ho st interrupt
Host Interface
* These pins can be bidirectional when programmed as general purpose I/O.
Interrupt and Mode Control
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12 DSP56156 Data Sheet MOTOROLA
Pin Descriptions
acknowledge, HACK enables the HI
Interrupt Vector Register (IVR) onto
the host data bus H0-H7 if the Host Re-
quest HREQ output is asserted. In this
case, all other HI control pins are ig-
nored and the HI state is not affected.
HACK may be programmed as a gen-
eral purpose I/O pin called PB14 whe n
the HI is not being used.
16-bit Timer
TIN (Timer Input) — input*. This input re-
ceives external pulses to be counted by
the on-chip 16-bit timer when external
clocking is selected. The pulses are in-
ternally synchronized to the DSP core
internal clock. TIN may be pro-
grammed as a general purpose I/O pin
called PC10 when the external event
function is not being used.
TOUT (Timer Output) — output*. This out-
put generates pulses or toggles on a
timer overflow event or a compare
event. TOUT may be programmed as a
general purpose I/O pin called PC11
when disabled by the timer out enable
bits (TO2-TO0).
Synchronous Serial
Interfaces (SSI)
STD0-1 (SSI0-1 Transmit Data) — output*.
These output pins transmit serial data
from the SSI0-1 Transm it Shift R egister.
STD0 and STD1 may be programmed
as a general purpose I/O pin called
PC0 and PC5, respectively, when the
STD function is not being used.
SRD0-1 (SSI0-1 Receive Data) — input*.
These input pins receive serial data and
transfer the data to the SSI0-1 Receive
Shift Register. SRD0 and SRD1 may be
programmed as a general purpose I/O
pin called PC1 and PC6, respectively,
when the SRD function is not being
used.
SCK0-1 (SSI0-1 Serial Clock) — bidirection-
al. These bidirectional pins provide t he
serial bit rate clock for the SSI0-1 inter-
face. SCK0 and SCK1 may be pro-
grammed as a general purpose I/O pin
called PC2 and PC7, respectively,
when the SSI0-1 interfaces are not be-
ing used.
SC10-11 (SSI0-1 Serial Control 1) — bidirec-
tional. These bidirectional pins are
used by the SSI0-1 serial interface as
frame sync I/O or flag I/O. SC10 and
SC11 may be pro grammed a s a general
purpose I/O pin called PC3 and PC8,
respectively, when the SSI0-1 are not
using these pins.
SC00-01 (SSI0-1 Serial Control 0) — bidirec-
tional. These bidirectional pins are
used by the SSI0-1 serial interface as
frame sync I/O or flag I/O. SC00 and
SC01 may be pro grammed a s a general
purpose I/O pin called PC4 and PC9,
respectively, when the SSI0-1 are not
using these pins.
16-bit T imer
SSI
* These pi ns can be bidirectional when programmed as general purpose I/O.
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Pin Description s
MOTOROLA DSP56156 Data Sheet 13
On-Chip Emulation
(OnCETM Port)
DSI/OS0 (Debug Serial Input/Chip Status 0) —
bidirectional. The DSI/OS 0 pin, when
an input, is the pin through which seri-
al data or commands are provided to
the OnCE port controller. The data re-
ceived on the DSI pin will be recog-
nized only when the DSP has entered
the debug mode of operation. Data
must have valid TTL logic levels before
the serial clock falling edge. Data is al-
ways shifted into the OnCE serial port
most significant bit (MSB) first. When the
DSP is not in the de bug mo de, the D SI/
OS0 pin provides information about the
chip status if it is an output and used in
conjunction wit h t he OS1 pin.
DSCK/OS1 (Debug Serial Clock/Chip Status 1)
— bidirectional. The DSCK/OS1 pin,
when an input, is the pin through
which the serial clock is supplied to the
OnCE port. The serial clock provides
pulses required to shift data into and
out of the OnCE serial port. Data is
clocked into the OnCE port on the fall-
ing edge and is clocked out of the
OnCE serial port on the rising edge. If
the DSCK/OS1 pin is an output and
used in conjunction with the OS0 pin, it
provides information about the chip
status when the DSP is not in the debug
mode.
DSO (Debug Serial) — output. The debug
serial output provides the data con-
tained in one of th e OnCE por t cont rol-
ler registers as specified by the last
command received from the command
controller. When idle, this pin is high.
When the requested data is available, the
DSO line will be asserted (negative true
logic) for four T cycles (one instruction
cycle) to indi cate that the serial shi ft reg-
ister is ready to receive clocks in order to
deliver the data. When the chip enters
the debug mode due to an external de-
bug request (DR), an internal software
debug request (DEBUG), a hardware
breakpoint occurrence or a trace/step
occurrence, this line will be asserted for
three T cycles to indicate that the chip
has entered the debug mode and is wait-
ing for commands. Data is always shift-
ed out the OnCE serial port with the
most signific ant bit first.
DR (Debug Request) — input. The debug
request input provides a means of en-
tering the debug mode of operation.
This pin, when asserted, will cause the
DSP to finish the curr ent instructi on be-
ing executed, enter the debug mode,
and wait for commands to be entered
from the debug serial input line.
On-Chip Codec
AUX (Auxiliary) — input. This pin is select-
ed as the analog input to the A/D con-
verter when the INS bit is set in the
codec control register COCR. This pin
should be left floating when the codec
is no t us e d.
BIAS (Bias current) — input. This input is
used to determine the bias current for
the analog circuitry. Connecting a re-
sistor between BIAS and GNDA will
program the current bias generator.
This pin should be left floating when
the codec is not used.
MIC (Microphone) — input. This pin is se-
lected as the analog input to the A/D
converter when the INS bit is cleared in
OnCE
On-Chip Codec
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14 DSP56156 Data Sheet MOTOROLA
Pin Descriptions
the codec control register COCR. This
pin shou ld be left fl oating w hen the co-
dec is not used.
SPKP (Speaker Plus) — output. This pin is
the positive analog output from the on-
chip D/A converter. This pin should be
left floating when the codec is not used.
SPKM (Speaker Minus) — output. This pin is
the negative analog output from the
on-chip D/A converter. This pin
should be left floating when the codec
is no t us e d.
VREF (Voltage Reference) — output. This
pin is the op-amp buffer output in the
reference voltage generator. It has a
value of ( 2/5)VCCA. This pin sh oul d al-
ways be connected to the GNDA
through two capa citors, even w he n the
codec is not used.
VDIV (Voltage Division) — output. This
output pin is also the outpu t to the on-
chip op-amp buffer in the reference
voltage generator. It is connected to a
resistor divider netw ork located within
the codec block which provides a volt-
age equal to (2/5)VCCA. Th is pi n sh ould
be connected to the GND via a capacitor
when the codec is used and should be
left floating when the codec is not used.
Power, Ground, and Clock
VCC (Power) — Power pins
GND (Ground) — Ground pins
VCCS (Synthes izer Power) — This pin sup-
plies a quiet power source to the Phas e-
Locked Loop (PLL) to provide greater
frequency stab ility.
GNDS (Synthesizer Ground) — This pin sup-
plies a quiet ground source to the PLL
to provide gre ater freque ncy stabili ty.
VCCA (Analog Power) — This pin is the posi-
tive analog supply input. It should be con-
nected to VCC when the codec is not used.
GNDA (Analog Ground) — This pin is the an-
alog ground return. It should be con-
nected to digital GND when the codec
is not used.
EXTAL (External Clock) — input. This input
should be driven by an external clock or
by an external oscillator. After being
squared, the input frequency can be
used as the DSP core internal clock. In
that case, it is divided by two to produce
a four phase in structio n cycl e cloc k, the
minimum instruct ion time being two in-
put clo ck periods . This i nput frequen cy
is also used, after division, as input
clock for the on-chip codec and the on-
chip PLL.
CLKO (Clock Output) — output. This pin
outputs a buffered clock signal. By pro-
gramming two bits (CS1-CS0) inside
the PLL Control Register (PLCR), the
user can select between outputting a
squared version of the signal applied to
EXTAL, a squared version of the signal
applied to EXTAL divided by 2, and a
delayed version of the DSP core master
clock. The clock frequency on this pin
can be disabled by setting the Clockout
Disable bit (CD; bit 7) of the Operating
Mode Register (OMR). When disabled,
the pin can be left floating.
SXFC (External Filter Capacitor) — This pin
adds an external capacitor to the PLL
filter circuit. A low leakage capacitor
should be connected between and lo-
cated very close to SXFC and VCCS.
Power, Ground, and Clock
On-Chip Codec
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Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 15
Electrical Characteristics and Timing
CAUTION:
Exceeding maximum electrical ratings will permanently damage or
disable the chip, or impair the chip’s long term reliability.
The DSP56156 is fabricated in high density HCMOS with TTL compatible inputs and CMOS
compatible out puts .
NOTE: This device contains protective circ uitry to guard against damage due to high static voltage or elec trical
fields. However, normal precautions are advised to avoid application of any voltages higher than maximum
rated vo ltages to t his high-i mpedanc e circuit . Reliab ility of opera tion is enhance d if unuse d inputs a re tied
to an appropriate logic voltage level (e.g., either GND or VCC).
Table 4 Maximum Electrical Ratings (GND = 0 Vdc)
Rating Symbol Value Unit
Supply Voltage VCC -0.3 to +7.0 V
All Input Voltages VIN GND - 0.5 to VCC + 0.5 V
Current Dra in per Pin ex cludi ng VCC and GN D I 1 0 m A
Storage Temperat ure Tstg -55 to +150 °C
Table 5 Operating Conditions
Supply Voltage
VCC
Junction Temperature
TJ (°C)
Min Max Min Max
4.5 5.5 -40 115
Table 6 Thermal Characteristics of CQFP and TQFP Packages
Thermal Resistance
Characteristics Symbol Value Rating
CQFP TQFP
Junction to Ambient ΘJA 40 49 °C/W
Junction to Case (estimated) ΘJC 78°C/W
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Electrical Ch aracteristics and Timing
16 DSP56156 Data Sheet MOTOROLA
Analog I/O Characteristics
(VCCA = 5.0 V dc ± 10%, TJ = -40° to +125°C)
The analog I/O characteristics of this device are listed in Table 7.
For additional information regarding the use of analog signals, see “Design Considerations”
at the end of this document.
Table 7 Analog I/O Charac teristics
Characteristic Min Typ Max Unit
Input Impedance on MIC and AUX (See Note 1) 46 78 1400 kΩ
Input Capacitance on MIC and AUX ——10pF
Peak Input Voltage on the MIC/AUX Input for Full Scale
Linearity (0.14 dBm0): 6 dB - MGS1 - 0 = 00
(See Note 2) 0 dB - MGS1 - 0 = 01
6 dB - MGS1 - 0 = 10
17 dB - MGS1 - 0 = 11
—
—
—
—
—
—
—
—
1.414
0.707
354
100
Vp
Vp
mVp
mVp
Internal Input Gain Variation;
G = -6 dB, 0 dB, 6 dB or 17 dB
(±0.83 dB variation due to 10% variation on VCC):
G - 0.83 G G + 0.83 dB
VREF Output Voltage 1.8 2 2.2 V
VREF Output Current — — ±1 mA
DC Offset Between SPKP and SPKM — — 100 mV
Allowable Differential Load Capacitance on
SPKP and SPKM (with 1 kΩ in series) 0 — 0.05 µF
Allowable Single-ended Load Capacitance on
SPKP or SPKM (with 0.5 kΩ in seri es) 0
(See Note 3) — 100
0.1 µF
Maximum Single-ended Signal Output Level — — 1 Vp
Maximum Differential Signal Output Level — — 2 Vp
Single-ended Load Resistance 500 — — Ω
Differential Load Resistance 1 — — kΩ
Resist ance BIAS — 10
(See
Note 4)
—kΩ
Internal Output Volume Control Variation
VC = -20, -15, -10, -5, 0, 6, 12, 18, 24, 30, 35 dB
(± 0.83 dB variation due to 10% variation on VCC)
VC - 0.83 VC VC + 0.83 dB
NOTES: 1. Minimum value reached for a Codec clock of 3 MHz, typical for 2 MHz and maximum for 100 kHz
2. 0 dBm0 corres ponds to 3.14 dB below the inpu t saturat ion lev el
3. AC coupling is necessary in single-ended mode when the load resistor is not tied to VREF
4. ± 10%
Analog I/O Characteristics
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Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 17
A/D and D/A Performance
(VCCA = 5.0 V dc ± 10%, TJ = -40° to +125°C)
The A/D and D/A performance of the codec section are given in Table 8 with an
example presented in Figure 4.
NOTES: 1. 0 dB gain on th e A/D and D/A; Codec clock at 1.5 38 MHz with 12 8 decimatio n/interpolatio n ratio and
tested at 1502 Hz
2. 0 dBm0 corresponds to -3.14 dB below the input saturation level
Figure 4 Example: S/N and S/N+T Performance for the A/D Section
Table 8 A/D and D/A Performance of Codec
Characteristic Level Min Typ
(See Note 1) Max Unit
Analog to D i git al Section Signal to Noise
plus Distortion Ratio (S/N+T) 0 dBm0
(See Note 2) 55 65 —dB
-50 dBm0 15 2 0 — dB
Digital to Analog Section Sign al to Noise
plus Distortion Ratio (S/N+T) 0 dB 55 65 — dB
-50 dB 15 20 — dB
S in dB
0
10
20
30
40
50
60
70
80 S/N
S/N+T
Signal in dB
÷13
CODEC
÷(12+1)*4
2 MHz
1 MHz
PLL 52 MHz
COCR=$E400
PLL
Codec
÷(12+1)x4
÷ 13
÷ 6.5
13 MHz
A/D and D/A Performance
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Electrical Ch aracteristics and Timing
18 DSP56156 Data Sheet MOTOROLA
Other On-Chip Codec Characteristics
(VCCA = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
The analog I/O characteristics of this device are shown in Table 9.
Table 9 Analog I/O Characteristics of On-Chip Codec
Characteristic Min Typ Max Unit
Codec Master Clock 0.1 2.048 3 MHz
Codec Sampling Rate 78 16000 37000 Hz
A/D Section Group Delay ——0.2msec
D/A Section Group Delay — — 0.2 msec
Other On-Chip Codec Characteristics
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DC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 19
DC Electrical Characteristics
(GND = 0 V dc)
(VCC = 5.0 V dc ± 10%, T J = -40° to +125°C, CL = 50 pF + 1 TTL Load)
The DC electrical c haracteristics of th is devi ce are shown in Table 10.
NOTES: 1. When EX TAL is AC coupled, VIHC - VILC Š 1 V must be true.
2. Input capacitance is periodically sampled and not 100% tested in production.
Table 10 DC Electrical Characteristics
Characteristic Symbol Min Typ Max Unit
Input High Voltage
except EXTAL, RESET, MODA, MODB, MODC VIH 2.0 — VCC V
Input Low Voltage
except EXTAL, MODA, MODB, MODC VIL -0.5 — 0.8 V
Input High Voltage
EXTAL DC coupled
EXTAL AC coupled (See Note 1)
VIHC 70% of VCC
1—
—VCC
VCC
V
Input Low Voltage
EXTAL DC coupled
EXTAL AC coupled (See Note 1)
VILC -0.5
-0.5 —
—20% of VCC
VCC-1
V
Input High Voltage RESET V
IHR 2.5 — VCC V
Input High Voltage MODA, MODB, MODC VIHM 3.5 — VCC V
Input Low Voltage MODA, MODB, MODC VILM -0.5 — 2.0 V
Input Leakage Current EXTAL
RESET, MODA, MODB, MODC, TA, DR, BR
IIN -100
-1
—100
1µA
µA
Three-State (Off-State) Input Current
(@2.4 V/0.5 V) TSI -10 — 10 µA
Output High Voltage (IOH = -10 µA) VOHC VCC -0.1 — — V
Output High Voltage (IOH = -0.4 mA) VOH 2.4 — — V
Output Low Voltage (IOL = 10 µA) VOLC ——0.1V
Output Low Voltage (IOL = 3.2 mA
R/W IOL = 1.6 mA; Open Drain
HREQ IOL = 6.7 mA, TXD IOL = 6.7 mA)
VOL ——0.4V
Input Capacitance (See Note 2) CIN —10—pF
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AC Electrical Characteristics and Timi ng
20 DSP56156 Data Sheet MOTOROLA
AC Electrical Characteristics
(GND = 0 V dc)
The timing waveforms in the AC Elec trical Char acteristic s ar e tested with a V IL m aximum of
0.5 V and a VIH minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, MODB and
MODC. These fi ve pins ar e tes ted using th e input levels set forth in the DC Elect rical Charac -
teristics. AC timing specifica tions which ar e r eferen ced to a device input signa l are measur ed
in production with respect to the 50% point of the respective input signal’s transition. The
DSP56156 output levels are measured with the production test machine VOL and VOH refe r-
ence levels set at 0.8 V and 2.0 V respectively.
Clock Operation Timing
The system clock to the DSP56156 must be externally supplied to EXTAL as illustrated in
Figure 6.
NOTES: 1. Rise a nd fall tim e may be rel axed to 12 n s maximum i f the EXTAL i nput frequen cy is less th an or equal
to 20 MHz. If the EXTAL input frequency is between 20 MHz and 40 MHz, rise and fall time should
meet the sp ecified valu es in the 40 MHz column (4 ns maximum).
2. The duty c ycle may be relaxed to 43-57 % if the EXTAL input frequency is les s than or equal to 20 MHz.
If the EXTAL input frequency is between 20 MHz and 40 MHz, the duty cycle should be such that TH
and TL meet the speci fied values in the 40 MHz column (12 ns mi nim um ).
3. T = ICYC / 4 is used in the electrical characteristics. The exact length of each T is affected by the duty
cycle of the external clock input.
4. Duty cycles and EXTAL widths are mea sured at the EXTAL input signal midpoint when AC coupled and
at VCC/2 when not AC coupled.
Table 11 Clock Operation Timing
Num Characteristics Sym 40 MHz 50 MHz 60 MHz Unit
Min Max Min Max Min Max
1 Frequency of Operation (EXTAL) f 0 40 0 50 0 60 MHz
2 Instruction Cycle Time = 2TCICYC 50 ×40×33×ns
3 Wait State Time = TC = 2T — 25 × 20 × 16.6 × ns
4 EXTAL Cycle Period TC25 × 20 × 16.6 × ns
5 EXTAL Rise Time (See Note 1) — 4 — 3 — 3 ns
6 EXTAL Fall Time (See Note 1) — 4 — 3 — 3 ns
7 EXTAL Width High
48-52% duty cycle
(See Notes 2, 3, 4 )
TH12 × 9.6 × 8 × ns
8 EXTAL Width Low
48%-52% du ty cycle
(See Notes 2, 3, 4 )
TL12 × 9.6 × 8 × ns
Clock Operation Timing
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 21
Figure 5 External Clock Timing
Other Clock and PLL Operation Timing
Clock and PL L timings a re listed i n Table 12 and the cloc king configurati ons ar e i llustrated i n
Figure 6.
Figure 6 Clocking Configur ations
EXTAL
VIHC
Midpoint
7 8
42
5
6
THTL90%
10% VILC
Table 12 Clock and PLL Timing
Characteristics Min Max Unit
PLL Output frequency 10 Max Fosc
(See Note 1) MHz
EXTAL Input Clock Amplitude (See Note 2) 1 VCC Vpp
NOTES: 1. Maximum DSP operating frequency. See Table 11.
2. An AC coupling capacitor is required on EXTAL if the levels are out of the normal CMOS level
range (VILC>20% of VCC or VIHC<70% of VCC).
EXTAL
PLL
PLLE=1
PLLE=0
Fosc
ED3-ED0
CLKO ÷ 2 internal phase PH0 at Fosc
CS1-CS0
1000 pF
GSM
SXFC VCCS
XFC
0.01 µF
GNDS
0.1 µF
100 KΩ÷ 1 to ÷ 16
÷ 6.5
CODEC
VCO
LF
PFD
YD3-YD0
÷ 1 to ÷ 16
10 nF
÷ 4
Clock Operation Timing
PLL
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AC Electrical Characteristics and Timi ng
22 DSP56156 Data Sheet MOTOROLA
Reset, Stop, Wait, Mode Select, and Interrupt Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
ws = Number of wait st ates progra mmed into external b us acces s using BCR (WS = 0 - 3 1)
Table 13 Reset, Stop, Wait, Mode Select, and Inter rupt Timing
Num Characteristics 40 MHz 50 MHz 60 MHz Unit
Min Max Min Max Min Max
10 RESET Assertion to Address, Data and
Control Signals High Impedance —25—23—21ns
11 Minimum Stabil izati on Dur ation
(See Note 1) OMR bit 6=0
OMR bit 6=1 600KT
60T —
—600KT
60T —
—600KT
60T —
—ns
ns
12 Asynchronous RESET Deassertion to
First External Address Output
(See Note 7)
16T 18T+20 16T 18T+17 16T 18T+15 ns
13 Synchronous Reset Setup Time from
RESET Deassertion to Rising Edge of
CLKO
7 cyc-4 6 cyc-3 5 cyc-2 ns
14 Synchronous Reset Delay Time from
CLKO High to the First External Access
(See Note 7)
16T+3 16T+20 16T+ 3 16T+18 16T+3 16T+16 ns
15 Mode Select Setup Time 22 — 20 — 18 — ns
16 Mode Select Hold Time 0—0—0—ns
17 Edge-triggered Interrupt Request Width 13 — 11 — 9 — ns
18 Delay from IRQA, IRQB Assertion to
External Data Memory Access Out Valid
- Caused by First Interrupt
Instruction Fetch
- Caused by First Interrupt
Instruction Execution
11T+4
19T+4
—
—
11T+4
19T+4
—
—
11T+3
19T+3
—
—
ns
ns
19 Delay from IRQA, IRQB Assertion to
General Purpose Out put Vali d Cause d
by the Execution of the First Interrupt
Instruction
22T+5 —22T+4 — 22T+3 — ns
20 Delay from External Data Memory
Address Output Valid Caused by First
Interrupt Instruction Execution to Inter-
rupt Request Deassertion for Level Sen-
sitive Fast Interrupts (See Note 2)
—5T-26
+
cyc × ws
—5T-24
+
cyc × ws
—5T-22
+
cyc × ws
ns
Reset, Stop, Wait, Mode Select, and Interrupt Timing
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 23
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing (continued)
Num Characteristics 40 MHz 50 MHz 60 MHz Unit
Min Max Min Max Min Max
21 Delay from General-Purpose
Output Valid Caused by the
Execution of the First Inter-
rupt Instruction to IRQA,
IRQB Deassertion for Level
Sensitive Fast Interru pts — If
2nd Interrupt Instruction is:
Single Cycle
(See Note 2) Two Cycles
—
—
cyc - 29
3 cyc - 2 9
—
—
cyc - 27
3 cyc - 27
—
—
cyc - 26
3 cyc - 26
ns
ns
22 Synchronous setup time from
IRQA, IRQB assertion to
Synchronous falling edge of
CLKO (See Notes 5 and 6)
14 cyc-3 13 cyc-2 12 cyc-1 ns
23 Falling Edge o f CLKO to First
Interrupt Vector Address Out
Valid after Synchronous
recovery from Wait State
(See Notes 3 and 5)
27T+3 27T+20 27T+3 27T+18 27T+3 27T+16 ns
24 IRQA Wid t h Assertio n to
Recover from Stop State
(See Note 4)
15 — 13 — 12 — ns
25 Delay from IRQA Assertion to
Fetch of first instruction (exit-
ing Stop)
(See Notes 1 and 3)
OMR bit 6=0
OMR bit 6=1 524303T+4
47T+4 —
—524303T+3
47T+3 —
—524303T+3
47T+3 —
—ns
ns
28 Duration for Level Sensitive
IRQA Assertio n to Cau se the
Fetch of First IRQA Interrupt
Instruction (exiting Stop)
(See Notes 1 and 3)
OMR bit 6=0
OMR bit 6=1 524303T
47T —
—524303T
47T —
—524303T
47T —
—ns
ns
29 Delay from Level Sensitive
IRQA Assertion to First Inter-
rupt Vector Address Out
Valid (exiting Stop)
(See Notes 1 and 3)
OMR bit 6=0
OMR bit 6=1 524303T +4
47T+4 —
—524303T+3
47T+3 —
—524303T+3
47T+3 —
—ns
ns
Reset, Stop, Wait, Mode Select, and Interrupt Timing
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AC Electrical Characteristics and Timi ng
24 DSP56156 Data Sheet MOTOROLA
NOTES: 1. Circuit stabilization delay is required during reset when using an external clock in two cases:
• after pow er-on reset
• when recovering from Stop mode
2. When using fast interrupts, IRQA or IRQB is defined as level-sensitive, then timings 20 and 21
apply to prevent multiple interrupt service. To avoid these timing restrictions, the negative edge-trig-
gered mode is recommended when using fast interrupts.
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
4. The minimum is specified for the duration of an edge triggered IRQA interrupt required to recover
from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted.
5. Timing #22 is for all IRQx interrupts while timing #23 is only when exiting the Wait state.
6. Timing #22 triggers off T1 in the normal state and off phi1 when exiting the Wait state.
7. The instruction fetch is visible on the pins only in Mode 2 and Mode 3.
Figure 7 Asynchronous Reset Timing
Figure 8 Synchronous Reset Timing
RESET
D0-D15
A0-A15
PS/DS
R/W
BS
10 11 12
First Fetch
VIHR
CLKO
RESET
A0-A15
PS/DS
BS
R/W
14
13
Reset, Stop, Wait, Mode Select, and Interrupt Timing
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 25
Figure 9 Operating Mode Select Tim ing
Figure 10 External Interrupt Timing (Negative Edge-Triggered)
Figure 11 External Level-Sensi tive Fast Interrupt Timing
RESET
MODA
MODB
MODC
VIHR
IRQA
IRQB
VIHM
VILM
VIH
VIL
16
15
IRQA
IRQB 17
First Interrupt Instruction Execution
A0-A15
PS/DS
BS
R/W
IRQA
IRQB
2018
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
IRQA
IRQB 19 21
b) General Purpose I/O
Reset, Stop , Wait, Mode Select, and Interrupt Timing
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AC Electrical Characteristics and Timi ng
26 DSP56156 Data Sheet MOTOROLA
Figure 12 Synchronous Interrupt from Wait State Timing
Figure 13 Recovery from Stop State Using Asynchronous Interrupt Ti ming
Figure 14 Recovery from Stop State Using IRQA Interrupt Service
22
23
T0, T2
phi0 T1, T3
phi1
CLKO
IRQA
IRQB
A0-A15
PD/DS
BS
R/W Instructio n Fetch
First Interrupt
IRQA
A0-A15
PD/DS
BS
R/W
24
25
Not IRQA Interrupt Vector
First Instruction Fetch
IRQA
A0-A15
PD/DS
BS
R/W First IRQA Interrupt
Instruction Fetc h
28
29
Reset, Stop, Wait, Mode Select, and Interrupt Timing
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 27
Table 14 Wait and Stop Timings
Num Characteristics 40 MHz 50 MHz 60 MHz Unit
Min Max Min Max Min Max
30 DR Ass erted to CLK high (Setup
Time f or Synchronou s Recove ry
from Wait State) 10 cyc - 4 9 cyc - 3 8 cyc - 2 ns
31 CLK high to DSO (ACK) Valid
(Enter Debug Mode) after Syn-
chrono us R eco ve ry fr om Wait
State 18 cyc — 18 c yc — 18 cyc — ns
32 DR to DSO (ACK) Valid
(Enter Debug Mode)
- After Asynchronous Recovery
from Stop State
- After Asynchronous Recovery
from Wait State
29 cyc
18 cyc
—
—
29 cyc
18 cyc
—
—
29 cyc
18 cyc
—
—
ns
ns
33 DR Assertion Width
- to Recover from Wait/Stop
without entering debug mode
- to Recover from Wait/Stop
short wake-up and enter
debug mode
- to Recover from Stop
long wake-up and enter
debug mode
12
29 cyc
262157
cyc
10 cyc
—
—
11
29 cyc
262157
cyc
10 cyc
—
—
10
29 cyc
262157
cyc
10 cyc
—
—
ns
ns
ns
Figure 15 Recovery from Wait State Using DR Pin — Synchronous Timing
DR
(input)
DSO
(output)
33
32
33
Reset, Stop , Wait, Mode Select, and Interrupt Timi ng
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AC Electrical Characteristics and Timi ng
28 DSP56156 Data Sheet MOTOROLA
Figure 16 Recovery from Wait/Stop State Using DR Pin — Asynchronous Timing
Capacitance Derating
The DSP56156 External Bus T iming Specifications ar e designed and tested at the maximum c a-
pacitive loa d of 5 0 pF, including stray capacitance. Typically, the drive capability of the Exter-
nal Bus pins (A0-A15, D0 -D15, PS/DS, RD, BS, WR , R/W) derates linearly at 1 ns per 12 pF of
additional capacitance fr om 50 pF to 250 pF of loading. Port B and C pins derate linearly at 1 ns
per 5 pF of additional capacitance from 50 pF to 250 pF of loading.
When an internal memory access follows an external memory access, the PS/DS, R/W, RD
and WR strobes remain deasserted and A0-A15 do not change from their previous state.
CLKO
(output)
DR
(input)
DSO
(output)
31
T1, T3
30
33
T0, T2
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Capacitance Derati ng
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 29
External Bus Synchronous Timing
(VCC = 5.0 V dc ± 10%, TJ = - 40° to +125°C, CL = 50 pF + 1 TTL Load)
Table 15 lists external bus synchronou s timing. Figure 17 and illustrate the bus timings
with no wait states and two wait states, respectively.
Table 15 External Bus Synchronous Timing
Num Characteristic 40 MHz 50 MHz 60 MHz Unit
Min Max Min Max Min Max
34 EXTAL CLK In High to CLKO High 2.4 9 2.4 9 2.4 9 ns
35 CLKO High to
a. A0-A15 Valid
b. PS/DS, R/W Valid, BS, RD Asserted
4.7
4.7
12
14
4.7
4.7
12
14
4.7
4.7
12
(See Note)
4
ns
ns
36 BS Width Deasserted 18.3 — 13.4 — 9.8 — ns
37 CLKO High to WR Asserted Low T+3.1 T+12.4 T+3.1 T+12.4 T+3.1 T+12.4 ns
38 WR and RD Deasserted High to BS
Asserted Low (2 Successive Bus Cycles) 14.3 15.8 11.8 13.3 10.2 11.8 ns
39 <intentionally blank>
40 CLKO High to BS Deasserted 2.6 10.3 2.6 10.3 2.6 10.3 ns
41 TA Valid to CLKO High (Setup) 4.5 — 4.5 — 4.5 — ns
42 CLKO High to TA Invalid (Hold) 0 — 0 — 0 — ns
43 CLKO High to D0-D15 Out Valid 1.7 7.1 1.7 7.1 1.7 7.1 ns
44 CLKO High to D0-D15 Out Invalid 2.0 — 2.0 — 2.0 — ns
45 D0-D15 In Valid to CLKO Low (Setup) 6 — 6 — 6 — ns
46 CLKO Low to D0-D15 In Invalid (Hold) 0 — 0 — 0 — ns
47 CLKO Low to WR, RD Deasserted — 10 — 10 — 10 ns
48 WR, R D Hold Time from CLKO Low 2.2 — 2.2 — 2.2 — ns
49 CLKO High to D0-D15 Three-state 0 6 0 6 0 6 ns
50 CLKO High to D0-D15 Out Active 1.2 4.2 1.2 4.2 1.2 4.2 ns
51 CLKO High to A0-A15, PS/DS, R/W Invalid 2.8 — 2.8 — 2.8 — ns
NOTE: 10 ns CL = 25 pF
External Bus Synchronous Timing
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AC Electrical Characteristics and Timi ng
30 DSP56156 Data Sheet MOTOROLA
NOTE: During Read-Modify-Write instructions and internal instructions, the address lines do not change state.
Figure 17 External Bus Synchronous Timing — No Wait States
EXTAL
(Input)
T0 T1 T2 T3 T0 T1 T2
Data In
37
35
35
41
43
Data Out
34
36
40
42
47
48
51
50
46
49
45
47
48
CLKO
(Output)
A0-A15
PS/DS
R/W
(See Note)
BS
(Output)
WR
(Output)
RD
(Output)
TA
(Input)
D0-D15
(Output)
D0-D15
(Input)
41
35
44
External Bus Synchronous Timing
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 31
Figure 18 External Bus Synchronous Timing – Two Wait States
EXTAL
(Input)
T0 T1 T2 Tw T2 Tw T2 T3 T0
Data In
37
35
41
43
44
Data Out
34
36
40
42
47
48
51
50
46
49
45
35
47
48
42
41
CLKO
(Output)
A0-A15,
PS/DS, R/W
(Outputs)
BS
(Output)
WR
(Output)
RD
(Output)
TA
(Input)
D0-D15
(Output)
D0-D15
(Input)
35
External Bus Synchronous Timing
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AC Electrical Characteristics and Timi ng
32 DSP56156 Data Sheet MOTOROLA
External Bus Asynchronous Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
WS = Number of Wait States, Determined by BCR Register (WS = 0 to 31)
WT = WS × cyc = 2T × WS
External Bus Asynchronou s Timing
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 33
Figure 19 External Bus Asynchr onous Timing
Data In
64
59
Data Out
62 67
68 54 66 69
58 57
63
65
61
55
A0-A15,
PS/DS, R/W
(See Note)
53
60
56
BS
WR
D0-D15
RD
52
NOTE: During Read-Modify-Write instructions and internal instructions, the address lines do not change state.
External Bus Asynchronous Timing
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AC Electrical Characteristics and Timi ng
34 DSP56156 Data Sheet MOTOROLA
Bus Arbitration Timing — Slave Mode
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
cyc = Cloc k cycle = 1/2 in struction cycle = 2 T cycles
WS = Number of Wait States for external X or P memory, Determined by BCR
Register (WS = 0 to 31)
WT = WS
× cyc=2T × WS
WX = Number of Wait States for external X memory, Determined by BCR
Register (WS = 0 to 31)
WP = Number of Wait States for external P memory, Determined by BCR
Register (WS = 0 to 31)
NOTES: 1. With no external access from the DSP56156
2. During external read or write access
3. During external read-modify-write access
4. During Stop mode — external bus is released and BG is always low
5. During Wait mode
6. With external accesses pending by the DSP56156
7. Slave mode, when bus is still busy after bus request has been deasserted
Table 17 Sl ave Mode
Num Characteristics 40/50/60 MHz Unit
Min Max
70 BR Input to CLKO low setup time 0 1 ns
71 Delay from BR Input Assertion to (See Note 1)
BG Output Assertion (See Note 2)
(See Note 3)
(See Note 4)
(See Note 5)
5T+1.9
3T+1.9
5T+1.9
NA
T+1.9
9T+4.2
6T+WT+4.2
26T+4T x WX
+2T x WP+4.2
NA
3T+4.2
ns
72 CLKO high to BG Output Assertion 1.9 5.2 ns
73 BG Output Deassertion Duration (See Note 1)
(See Note 5)
(See Note 6)
5T-0.5
2T-0.5
3T-0.5
—
—
—
ns
74 CLKO High to Control Bus High Impedance 2.7 6.5 ns
75 CLKO High to BB Output Deassertion 3.2 7.8 ns
76 CLKO High to BB Input 3.3 8.1 ns
77 BR Input Deassertion to (See Note 1)
BG Output Deasse rtion (See Note 5)
(See Note 7)
4T+2.5
3T+3.2
3T+3.2
9T+6.4
8T+7.8
8T+8.0
ns
78 CLKO Low to BG Deassertion (See Note 1)
CLKO High to BG Deassertion (See Note 5)
CLKO High to BG Deassertion (See Note 7)
2.5
3.2
3.2
6.4
7.8
8.0
ns
79 CLKO High to BB Output Active 1.3 3.6 ns
80 CLKO High to BB Output Assertion 2.3 5 ns
81 CLKO High to Address and Control Bus Active 1 3 ns
82 CLKO High to Address and Control Bus Valid 2 4.4 ns
Bus Arbitration Timing — Slave Mode
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MOTOROLA DSP56156 Data Sheet 35
Figure 20 Bus Arbitration Timing — Slave Mode — Bus Release
72
74
70
71
74
76
75
73
CLKO
(Output)
BR
(Input)
BG
(Output)
BB
(I/O)
A0-A15
PS/DS
R/W
D0-D15
Bus Arbitration Timing — Slave Mode
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AC Electrical Characteristics and Timi ng
36 DSP56156 Data Sheet MOTOROLA
Figure 21 Bus Arbitration Timing — Slave Mode — Bus Acquisition
70
78
80
79
77
81
82
CLKO
(Output)
BR
(Input)
BG
(Output)
BB
(I/O)
A0-A15
PS/DS
R/W
Bus Arbitration Timing — Slave Mode
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 37
Bus Arbitration Timing — Master Mode
(VCC = 5.0 V dc ± 10%, TJ = - 40° to +125°C, CL = 50 pF + 1 TTL Load)
Figure 22 Bus Arbitration Timing — Master Mode — Bus Acquisition
Table 18 Master Mode
Num Characteristic 40 MHz 50 MHz 60 MHz Unit
Min Max Min Max Min Max
85 CLKO High to BR Output Assertion
CLKO High to BR Output Deassertion 4.7 12 4.7 12 4.7 12 ns
86 BG Input Asserted/ Deasserted to CLKO
Low (Setup) 9.2 —6.5—4.5— ns
87 CLKO Low to BG Input Invalid (Hold) 0—0—0—ns
88 BB Input Deasserted to CLKO Low (Setup) 9.2 — 6.5 — 4.5 — ns
89 CLKO Low to BB Input Deasserted (Hold) 0 — 0 — 0 — ns
90 CLKO High to BB Output Asserted 4.7 12 4.7 12 4.7 12 ns
86
85
89
88
87
90
81
82
Three-state
CLKO
(Output)
BR
(Output)
BG
(Input)
BB
(I/O)
A0-A15
PS/DS
R/W
Bus Arbitration Timing — Master Mode
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AC Electrical Characteristics and Timi ng
38 DSP56156 Data Sheet MOTOROLA
Figure 23 Bus Arbitration Timing — Master Mode — Bus Release
85
86
87
74
76
75
CLKO
(Output)
BR
(Output)
BG
(Input)
BB
(I/O)
A0-A15
PS/DS
R/W
Bus Arbitration Timing — Master Mode
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 39
Host Port Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
T = ICYC / 4
cyc = Clock cycle = 1/2 instruction cycle= 2 T cycle
tHSDL = Host Synchronization Delay Time (See Note 1)
tsuh = Host Processor Data Setup Time
Active low lines should be “pulled up” in a manner consiste nt with the AC and DC specifica-
tions.
Table 19 Host Port Timing
Num Characteristic 40 MHz 50 MHz 60 MHz Unit
Min Max Min Max Min Max
100 tHSDL Host Synchronous Delay
(See Note 1) T3TT3TT3Tns
101 HEN/HACK Assertion Width
• CVR, ICR, ISR Read
• Read
• Write
(See Notes 2, 4)
2T+36
32+tsuh
32 —
—
2T+33
29+tsuh
29 —
—
2T+30
26+tsuh
26 —
—
ns
102 HEN/HACK De assertion Width
(See Note 2) 31 — 29 — 27 — ns
103 Minimum Cycle Time Between Two
HEN Assertion for Consecutive
CVR, ICR, ISR Reads
4T+36 — 4T+33 — 4T+30 — ns
104 Host Data Inp ut Setup Time befo re
HEN/HACK Deassertion 5—4—3—ns
105 Host Data Input Hold Time after
HEN/HACK Deassertion 7—6—5—ns
106 HEN/HACK Assertion to Output
Data Active from High Impedance 0—0—0—ns
107 HEN/HACK Assertion to Output
Data Valid —32—29—26ns
108 HEN/HACK Deassertion to Output
Data High Impedance — 20 — 18.5 — 17 ns
109 Output Data Hold Time after
HEN/HACK Deassertion 5—5—4—ns
Host Port Timing
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AC Electrical Characteristics and Timi ng
40 DSP56156 Data Sheet MOTOROLA
NOTES: 1. “Host Synch roniza tion D elay (tH SDL)” is th e time perio d requi red for th e DSP56 156 to sam ple any
external asynchronous input signal, determine whether it is high or low, and synchronize it to the
internal clock.
2. See Host Port Considerations.
3. HREQ is pulled up by 1 kΩ.
4. Only if two consecutive reads from one of these registers are executed.
Table 19 Hos t Port Timing (continued)
Num Characteristic 40 MHz 50 MHz 60 MHz Unit
Min Max Min Max Min Max
110 HR/W Low Setup Time before HEN Assertion 6 — 5 — 4 — ns
111 HR/W Low Hold Time after HEN Deassertion 6 — 5 — 4 — n s
112 HR/W High Setup Time to HEN Assertion 6 — 5 — 4 — ns
113 HR/W High Hold Time after HEN/HACK
Deassertion 5—4—3—ns
114 HA0-HA2 Setup Time before HEN Assertion 9 — 7.5 — 6 — ns
115 HA0-HA2 Hold Time after HEN Deassertion 8—7—6—ns
116 DMA HACK Assertion to HREQ Deassertion
(See Note 3) 52T
+37 52T
+36 42T
+35 ns
117 DMA HACK Deassertion to HREQ
Assertion (See Note 3) for DMA RXL Read
for DMA TXL Write
for All Other Cases
tHSDL
+3T+5
tHSDL
+2T+5
5
—
—
—
tHSDL
3T+5
tHSDL
+2T+5
5
—
—
—
tHSDL
+3T+4
tHSDL
+2T+4
4
—
—
—
ns
ns
ns
118 Delay from HEN Deassertion to HREQ
Assertion for RXL Read (See Note 3) tHSDL
+3T+5 —t
HSDL
+3T+5 —t
HSDL
+3T+4 —ns
119 Delay from HEN Deassertion to HREQ
Assertion for TXL Write (See Note 3) tHSDL
+2T+5 —t
HSDL
+2T+5 —t
HSDL
+2T+4 —ns
120 Delay from HEN Assertion to HREQ
Deassertion for RXL Read, TXL Write
(See Note 3)
52T
+37 52T
+36 52T
+35 ns
Host Port Timing
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MOTOROLA DSP56156 Data Sheet 41
Figure 24 Host Synchronization Delay
Figure 25 Host Interrupt Vector Register (IVR) Read
External
Internal
100100
HREQ
(Output)
HACK
(Input)
HR/W
(Input)
H0-H7
(Output)
102
103
112 113
108107
106 109
Data Valid
101
Host Port Timing
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42 DSP56156 Data Sheet MOTOROLA
Figure 26 Host Read Cycle (Non-DMA Mode)
Figure 27 Host Write Cycle (Non-DMA Mode)
HREQ
(Output)
HEN
(Input)
HA0-HA2
(Input)
HR/W
(Input)
H0-H7
(Output)
118
120
103
101 102
114 115
112 113
107 108
109
RXL
Read
RXH
Read
Address
Valid Address
Valid
Data
Valid
Data
Valid
106
119
120
101 102
114 115
TXL
Write
TXH
Write
Address
Valid Address
Valid
Data
Valid Data
Valid
HREQ
(Output)
HEN
(Input)
HA0-HA2
(Input)
HR/W
(Input)
H0-H7
(Input)
110 111
104 105
103
Host Port Timing
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 43
Figure 28 Host Read Cycle (DMA Mode)
Figure 29 Host Write Cycle (DMA Mode)
Data
Valid
Data
Valid
RXL
Read
RXH
Read
HREQ
(Output)
HACK
(Input)
H0-H7
(Output)
101 102
116 117
107
106
108
109
HREQ
(Output)
HACK
(Input)
H0-H7
(Input)
101 102
116 117
104
105
Data
Valid
Data
Valid
TXL
Write
TXH
Write
Host Port Timing
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AC Electrical Characteristics and Timi ng
44 DSP56156 Data Sheet MOTOROLA
Synchronous Serial Interfaces (SSI) Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to + 125°C, CL = 50 pF + 1 TTL Load)
T= I
CYC / 4
SCK = Serial Clock Pin
FST (T ransmit Frame Sync) = SCx0 Pin
FSR (Receive Frame Sync) = SCx1 Pin
i ck = Internal Clock
x ck = External Clock
i ck a = Internal Clock, Asynchronous Mode (Asynchronous
implies that FSR and FST are two different frame syncs)
i ck s = Internal Clock, Synchronous Mode (Synchronous implies
that only one frame sync FS is used)
bl = bit length
wl = word length
NOTE: All the timings for the SSI are given for a non-inverted serial clock polarity (SCKP=0 in CRB) and a non-
inverted fram e sync (FSI=0 in CRB). If the po larity of the clock and/or the frame sync have been inverte d,
all the timing s remain valid by invertin g the clock signal SC K and/or the frame sy nc FSR/FST in the tables
and in the figures.
Table 20 Synchronous Serial Interfaces Timing
Num Characteristic 40/50/60 MHz Case Unit
Min Max
130 Clock Cycle (See Note) 100 ——ns
131 Clock High Period 45 — — ns
132 Clock Low Period 45 — — ns
133 Output Clock Rise/Fall Time — 7 — ns
134 SCK Rising Edge to FSR Out
(bl) High —
—32
18 x ck
i ck a ns
135 SCK Rising Edge to FSR Out
(bl) Low —
—32
15 x ck
i ck a ns
136 SCK Rising Edge to FSR Out
(wl) High —
—32
15 x ck
i ck a ns
137 SCK Rising Edge to FSR Out
(wl) Low —
—32
15 x ck
i ck a ns
138 Data In Setup Time before SCK
Falling Edge 30
40 —
—x ck
i ck ns
139 Data In Hold Time after SCK
Falling Edge 25
12 —
—x ck
i ck ns
SSI Timing
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 45
SSI Timing
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46 DSP56156 Data Sheet MOTOROLA
Table 20 Synchronous Serial Interfaces Timing (continued)
Num Characteristic 40/50/60MHz Case Unit
Min Max
140 FSR Input (bl) High before SCK
Falling Edge 7
15 —
—x ck
i ck a ns
141 FSR Input (wl) High before SCK
Falling Edge 7
15 —
—x ck
i ck a ns
142 FSR Input Hold Time after SCK
Falling Edge 15
7—
—x ck
i ck a ns
143 Flags Input Setup before SCK
Falling Edge 7
15 —
—x ck
i ck ns
144 Flags Input Hold Time after SCK
Falling Edge 15
7—
—x ck
i ck ns
145 SCK Rising Edge to FST Out
(bl) High —
—33
15 x ck
i ck ns
146 SCK Rising Edge to FST Out
(bl) Low —
—30
15 x ck
i ck ns
147 SCK Rising Edge to FST Out
(wl) High —
—30
15 x ck
i ck ns
148 SCK Rising Edge to FST Out
(wl) Low —
—33
15 x ck
i ck ns
149 SCK Rising Edge to Data Out
Enable from High Impedance —
—30
12 x ck
i ck ns
150 SCK Rising Edge to Data Out Valid —
—30
12 x ck
i ck ns
151 SCK Rising Edge to Data Out High
Impedance —
—30
20 x ck
i ck ns
152 FST Input (bl) Setup Time before SCK
Falling Edge 6
16 —
—x ck
i ck ns
153 FST Input (wl) to Data Out Enable from
High Impedance —36—ns
154 FST Input (wl) Setup Time before SCK
Falling Edge 8
17 —
—x ck
i ck ns
155 FST Input Hold Time after SCK
Falling Edge 15
4—
—x ck
i ck ns
156 Flag Output Valid after SCK
Rising Edge —
—32
15 x ck
i ck ns
SSI Timing
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 47
Figure 30 SSI Receiver T iming
SCK
(Input/Output)
FSR (Bit)
Out
FSR ( Word)
Out
Data In
FSR (Bit)
In
FSR ( Word)
In
Flags In
First Bit Last Bit
131 132
133
130
134 135
136 137
138 139
140 142
142141
143 144
SSI Timing
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AC Electrical Characteristics and Timi ng
48 DSP56156 Data Sheet MOTOROLA
Figure 31 SSI Tr ansmitter Timing
NOTE: In the Network mode, output flag transiti ons can occur at the start of each time slot within the frame.
In the Normal mode, the output flag state is asserted for the entire frame period.
150
151
155
152
153
155
156
First Bit Last Bit
(See Note)
132
130
133 131
145 146
147 148
149
150
SCK
(Input/Output)
FST (Bit)
Out
FST (Word)
Out
Data Out
FST (Bit)
In
FST (Word)
In
Flags Out
154
Timer Timing
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 49
Timer Timi ng
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
Figure 32 Timer Timing
Table 21 Timer Timing
Num Characteristic 40/50/60 MHz Unit
Min Max
170 TIN Valid to CLKO Low (Setup time) 6 —ns
171 CLKO Low to TIN Invalid (Hold time) 0 — ns
172 CLKO High to TOUT Asserted 3.5 14 ns
173 CLKO High to TOUT Deasserted 5.1 20.7 ns
174 TIN Period 8T — ns
175 TIN High/Low Period 4T — ns
170
172
171 173
CLKO
(Output)
TIN
(Input)
TOUT
(Output)
OnCE Port Timing
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AC Electrical Characteristics and Timi ng
50 DSP56156 Data Sheet MOTOROLA
OnCETM Port Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
NOTES: 1. 45%-55% duty cycle
2. Td = DSCK High (Timing #183)
Table 22 OnCE Port Timing
Num Characteristic 40/50/60 MHz Unit
Min Max
180 DSCK High to DSO Valid —37ns
181 DSI Valid to DSCK Low (Setup) 5.2 — ns
182 DSCK Low to DSI Invalid (Hold) 0 — ns
183 DSCK High (See Note 1) 2Tc — ns
184 DSCK Low (See Note 1) 2Tc — ns
185 DSCK Cycle Time (See Note 1) 4Tc — ns
186 CLKO High to OS0-OS1 Valid 14.5 ns
187 CLKO High to OS0-OS1 Invalid — — ns
188 Last DSCK High to OS0-OS1 (See Note 2)
Last DSCK High to ACK Active (data) (See Note 2)
Last DSCK High to ACK Active (command) (See Note 2)
10T+Td+14.5
10T+Td+13.5
21T+Td+13.5
—
—ns
189 D S O ( A C K ) Asserted to OS0-OS1 Three-state — 0 ns
190 D S O ( A C K ) Asserted to First DSCK High 3Tc — ns
191 D S O ( A C K ) Width Asserted:
• when entering debug mode
• when acknowledging command/data transfer 3T-2
2Tc+0.5 3T-5
2Tc+3 ns
ns
192 Last DSCK High of Read Register to First
DSCK High of Next Command 6Tc — ns
193 DSCK High to DSO Invalid (See Note 2) Td+11.2 — ns
194 DR asserted to DSO (ACK) Asserted 11T+19.5 — ns
OnCE Port Timing
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AC Electrical Characteristics and Timing
MOTOROLA DSP56156 Data Sheet 51
Figure 33 OnCE Port Serial Clock Timing
Figure 34 OnCE Port Acknowledge T iming
Figure 35 OnCE Port Data I/ O To Status Timing
DSCK
(Input)
185
183
184
194
ACK
DR
(Input)
DSO
(Output)
188
(ACK)
(OS0)
(OS1)(Last)
DSCK
(Input)
DSO
(Output)
DSI
(Input)
193
180
181 182
(See Note)
NOTE: Three-stat e, external pull-down resistor
OnCE Port Timing
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Pin-out and Package
52 DSP56156 Data Sheet MOTOROLA
Pin-out and Package Information
Figure 39 T op View of the DSP56156 1 12-pin Plastic (FC) and Ceramic (FE) Quad Flat Packages
GND4
D2
D3
VCC3
D4
D5
GND5
D6
D7
D8
D9
GND6
D10
D11
VCC4
D12
D13
GND7
D14
D15
TA
DR
VCCA
SPKP
SPKM
GNDA
VDIV
VREF
Orientation Mark
1
29
57
85
D1
D0
A15
A14
GND3
A13
A12
A11
GNDQ1
VCC2
A10
GND2
A9
A8
A7
A6
VCCQ1
GND1
A5
A4
VCC1
A3
A2
GND0
A1
A0
MODC
MODB/IRQB
NOTE: An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
MIC
AUX
BIAS
BG
VCCQ0
BR
BB
VCC5
WR
GND8
RD
PS/DS
BS
R/W
DSO
DSCK/OS1
DSI/OS0
CLKO
GNDQ0
GNDS
SXFC
VCCS
EXTAL
SC01/PC9
GND9
SC11/PC8
SCK1/PC7
H7/PB7
(Top View)
MODA/IRQA
RESET
STD0/PC0
SRD0/PC1
SCK0/PC2
SC10/PC3
SC00/PC4
TIN/PC10
VCC7
TOUT/PC11
HA0/PB8
GND10
HA1/PB9
HA2/PB10
HR/W/PB11
HEN/PB12
HACK/PB14
HREQ/PB13
H0/PB0
H1/PB1
STD1/PC5
SRD1/PC6
H4/PB4
H3/PB3
H2/PB2
VCC6
H5/PB5
H6/PB6
Top View
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Pin-out and Package
MOTOROLA DSP56156 Data Sheet 53
Figure 40 Bottom V iew of the DSP56156 112-pin Plast ic (FC) and Ceramic (FE) Quad Flat Pack ages
NOTE: An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
MODA/IRQA
RESET
STD0/PC0
SRD0/PC1
SCK0/PC2
SC10/PC3
SC00/PC4
TIN/PC10
VCC7
TOUT/PC11
HA0/PB8
GND10
HA1/PB9
HA2/PB10
HR/W/PB11
HEN/PB12
HACK/PB14
HREQ/PB13
H0/PB0
H1/PB1
STD1/PC5
SRD1/PC6
H4/PB4
H3/PB3
H2/PB2
VCC6
H5/PB5
H6/PB6
GND4
D2
D3
VCC3
D4
D5
GND5
D6
D7
D8
D9
GND6
D10
D11
VCC4
D12
D13
GND7
D14
D15
TA
DR
VCCA
SPKP
SPKM
GNDA
VDIV
VREF
Orientation Mark
1
29
57
85H7/PB7
SCK1/PC7
SC11/PC8
GND9
SC01/PC9
EXTAL
VCCS
SXFC
GNDS
GNDQ0
CLKO
DSI/OS0
DSCK/OS1
DSO
R/W
BS
PS/DS
RD
GND8
WR
VCC5
BB
BR
VCCQ0
BG
BIAS
AUX
MIC
MODB/IRQB
MODC
A0
A1
GND0
A2
A3
VCC1
A4
A5
GND1
VCCQ1
A6
A7
A8
A9
GND2
A10
VCC2
GNDQ1
A11
A12
A13
GND3
A14
A15
D0
D1
(on Top side)
(Bottom View)
Bottom View
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Pin-out and Package
54 DSP56156 Data Sheet MOTOROLA
Table 23 DSP56156 General Purpose I/O Pin Identification
112-pin
Package
Pin #
DSP56156
Primary Pin
Function
DSP56156
General
Purpose I/O
ID
66 H0 PB0
65 H1 PB1
60 H2 PB2
61 H3 PB3
62 H4 PB4
58 H5 PB5
57 H6 PB6
56 H7 PB7
74 HA0 PB8
72 HA1 PB9
71 HA2 PB10
70 HR/W PB11
69 HEN PB12
67 HREQ PB13
68 HACK PB14
82 STD0 PC0
81 SRD0 PC1
80 SCK0 PC2
79 SC10 PC3
78 SC00 PC4
64 STD1 PC5
63 SRD1 PC6
55 SCK1 PC7
54 SC11 PC8
52 SC01 PC9
77 TIN PC10
75 TOUT PC11
General Purpose I/O
NOTES: 1. In Tables 23, 24, and 25, OVERBAR indicates the signal is asserted when the voltage = ground (active low).
2. For more information on power and ground, see Table 26 under Design Considerations.
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Pin-out and Package
MOTOROLA DSP56156 Data Sheet 55
Pin Number
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Pin-out and Package
56 DSP56156 Data Sheet MOTOROLA
Table 24 DSP56156 Pin I dentif ication by Pin Number
112-pin
Package
Pin # Signal Name 112-pin
Package
Pin # Signal Name 112-pin
Package
Pin # Signal Name
1GND4 39RD 76 VCC7
2D2 40PS/DS 77 TIN/PC10
3D3 41BS 78 SC00/PC4
4V
CC3 42 R/W 79 SC10/PC3
5 D4 43 DSO 80 SCK0/PC2
6 D5 44 DSCK/OS1 81 SRD0/PC1
7 GND5 45 DSI/OS0 82 STD0/PC0
8D6 46CLKO 83RESET
9D7 47GNDQ0 84MODA/IRQA
10 D8 48 GNDS 85 MODB/IRQB
11 D9 49 SXFC 86 MODC
12 GND6 50 VCCS 87 A0
13 D10 51 EXTAL 88 A1
14 D11 52 SC01/PC9 89 GND0
15 VCC4 53 GND9 90 A2
16 D12 54 SC11/PC8 91 A3
17 D13 55 SCK1/PC7 92 VCC1
18 GND7 56 H7/PB7 93 A4
19 D14 57 H6/PB6 94 A5
20 D15 58 H5/PB5 95 GND1
21 TA 59 VCC6 96 VCCQ1
22 DR 60 H2/PB2 97 A6
23 VCCA 61 H3/PB3 98 A7
24 SPKP 62 H4/PB4 99 A8
25 SPKM 63 SRD1/PC6 100 A9
26 GNDA 64 STD1/PC5 101 GND2
27 VDIV 65 H1/PB1 102 A10
28 VREF 66 H0/PB0 103 VCC2
29 MIC 67 HREQ/PB13 104 GNDQ1
30 AUX 68 HACK/PB14 105 A11
31 BIAS 69 HEN/PB12 106 A12
32 BG 70 HR/W/PB11 107 A13
33 VCCQ0 71 HA2/PB10 108 GND3
34 BR 72 HA1/PB9 109 A14
35 BB 73 GND10 110 A15
36 VCC5 74 HA0/PB8 111 D0
37 WR 75 TOUT/PC11 112 D1
38 GND8
Signal Name
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Pin-out and Package
MOTOROLA DSP56156 Data Sheet 57
Signal Name
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Pin-out and Package
58 DSP56156 Data Sheet MOTOROLA
Table 25 DSP56156 Pin Identification by Signal Name
112-pin
Package
Pin # Signal Name 112-pin
Package
Pin # Signal Name 112-pin
Package
Pin # Signal Name
87A0 6D5 47GNDQ0
88 A1 8 D6 104 GNDQ1
90A2 9D7 48GNDS
91 A3 10 D8 66 H0
93 A4 11 D9 65 H1
94 A5 13 D10 60 H2
97 A6 14 D11 61 H3
98 A7 16 D12 62 H4
99 A8 17 D13 58 H5
100 A9 19 D14 57 H6
102 A10 20 D15 56 H7
105 A11 22 DR 74 HA0
106 A12 44 DSCK 72 HA1
107 A13 45 DSI 71 HA2
109 A14 43 DSO 68 HACK
110 A15 51 EXTAL 69 HEN
30 AUX 89 GND0 70 HR/W
35 BB 95 GND1 67 HREQ
32 BG 101 GND2 84 IRQA
31 BIAS 108 GND3 85 IRQB
34 BR 1 GND4 29 MIC
41 BS 7 GND5 84 MODA
46 CLKO 12 GND6 85 MODB
111 D0 18 GND7 86 MODC
112D1 38GND8 45OS0
2D2 53GND9 44OS1
3D3 73GND10 66PB0
5D4 26GNDA 65PB1
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Pin-out and Package
MOTOROLA DSP56156 Data Sheet 59
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Pin-out and Package
60 DSP56156 Data Sheet MOTOROLA
Table 25 DSP56156 Pin Identification by Signal Name (continued)
112-pin
Package
Pin # Signal Name 112 -pin
Package
Pin # Signal Name 112 -pin
Package
Pin # Signal Name
60 PB2 55 PC7 64 STD1
61 PB3 54 PC8 49 SXFC
62 PB4 52 PC9 21 TA
58PB5 77PC10 77TIN
57PB6 75PC11 75TOUT
56 PB7 40 PS/DS 92 VCC1
74 PB8 42 R/W 103 VCC2
72 PB9 39 RD 4V
CC3
71 PB10 83 RESET 15 VCC4
70 PB11 78 SC00 36 VCC5
69 PB12 52 SC01 59 VCC6
67 PB13 79 SC10 76 VCC7
68 PB14 54 SC11 23 VCCA
82PC0 80SCK0 33V
CCQ0
81PC1 55SCK1 96V
CCQ1
80PC2 25SPKM 50V
CCS
79PC3 24SPKP 27VDIV
78 PC4 81 SRD0 28 VREF
64 PC5 63 SRD1 37 WR
63 PC6 82 STD0
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MOTOROLA DSP56156 Data Sheet 61
112 CQFP
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Pin-out and Package
62 DSP56156 Data Sheet MOTOROLA
-L-
VIEW Y
PIN 1
Identifier 112
1
28
29 56
57
84
85
CE
WG 108 Place
VIEW P
0.15 (0.006)
0.20 (0.008) TL-M SNSM
0.20 (0.008) TL-MSNS
M
0.20 (0.008) TL-M N
0.20 (0.008) TL-M N
A
S
-M-
BV
-N-
-H- DATUM
PLANE
-T- SEATING
PLANE
J1
J1
P
VIEW Y
3 Place
-L-, -M-, -N-
A1
θ1
θ2
R R1
R R2
K
-H-
DATUM
PLANE
VIEW P
C1
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
E
F
G
J
K
P
S
V
W
A1
B1
C1
R1
R2
θ2
18.880
18.880
2.740
0.220
2.340
0.220
0.130
0.650
22.950
22.950
0.300
0.200
0.120
0°
20.400
20.400
3.450
0.380
3.060
0.330
0.230
0.950
23.450
23.450
0.600
0.132
0.743
0.743
0.108
0.009
0.092
0.009
0.005
0.026
0.904
0.904
0.012
0.008
0.0047
0.803
0.803
0.135
0.015
0.120
0.013
0.009
0.037
0.923
0.923
0.024
0.0052
0.650 BSC 0.02 56 B SC
0.325 BSC 0.01 28 B SC
1.800 REF 0.070 REF
0.200 REF 0.008 REF
0.200 REF 0.008 REF
NOTES: 1.Dimensioning and tolerancing per ANSI Y14.5M, 1982.
2.Controlling dimension: millimeter.
3.Datum plane -H- is coincident with the bottom of the lead
where the lead exits the ceramic body.
4.Datums -L-, -M- and -N- to be determined at datum plane -H-.
5.Dimensions S and V to be determined at seating plane -T-.
6.Dimensions A and B define maximum ceramic body dimensions
including glass protrusion and mismatch.
θ10°8°
8°0°
0°8°
8°
M
0.127 (0.005) TL-M N
BASE
METAL
PLATING
SECTION J1-J1
112 Plac e
VIEW R O T ATED 9 0°
F
D
JB1
Figure 41 DSP56156 112-pin Ceramic Quad Flat Pack (CQFP) Mechanical Information
S S
M
M
S
S
S
S
NOTE: BSC = Between Statistical Center
(i.e., typical)
TOP
VIEW
Case 915-01
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MOTOROLA DSP56156 Data Sheet 63
112 TQFP
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Pin-out and Package
64 DSP56156 Data Sheet MOTOROLA
0.100 (0.004)
CC2 VIEW AB
SEATING
PLANE
-T-
-L-, -M-, -N-
VIEW Y
J1
J1
F
J
D
BASE
METAL
AA
SECTION J1-J1
(VIEW ROTATED 90° COUNTER CLOCKWISE)
VIEW AB
θ1
R2
R1
0.13 (0.005) T L-M MCM
M
VIEW Y
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A20.000 BSC 0.790 BSC
A1 10.000 BSC 0.395 BSC
B20.000 BSC 0.790 BSC
B1 10.000 BSC 0.395 BSC
C1.400 1.600 0.055 0.063
C1 0.050 0.150 0.002 0.006
C2 1.350 1.450 0.053 0.057
D0.270 0.370 0.011 0.014
E0.450 0.750 0.018 0.030
F0.270 0.330 0.011 0.013
G0.650 BSC 0.0256 BSC
J0.115 0.175 0.006 0.007
K0.500 BSC 0.020 BSC
P0.325 BSC 0.013 BSC
R1 0.100 0.200 0.004 0.008
R2 0.100 0.200 0.004 0.008
S22.000 BSC 0.866 BSC
S1 11.000 BSC 0.433 BSC
V22.000 BSC 0.866 BSC
V1 11.000 BSC 0.433 BSC
Y0.250 REF 0.010 REF
Z1.000 REF 0.039 REF
AA 0.115 0.135 0.004 0.005
θ
θ1
θ2
θ3
PIN 1
Identifier 112 85
84
56
28 57
1
29
-L- -M-
-N-
V1
S1
0°
3°
11°
11°
0°
3°
11°
11°
8°
7°
13°
13°
8°
7°
13°
13°
0.200 (0.008) T L-M N
0.200 (0.008) H L-M N
4x 4x 28 TIPS
θ3
θ2
S
A
V
B
B1
A1
θ
C1
0.25 (0.010)
4x P
108x G
GAGE PLANE
0.050 (0.002) S
-H-
Y
K
E
Z
NOTES: 1.Dimensioning and tolerancing per ANSI Y14.5M, 1982.
2.Controlling dimension: Millimeter.
3.Datum plane -H- is located at bottom of lead and is coincident with the lead
where the lead exits the plastic body at the bottom of the parting line.
4.Datums -L-, -M- and -N- to be determined at datum plane -H-.
5.Dimensions S and V to be determined at seating plane -T-.
6.Dimensions A and B do not include mold protrusion. Allowable protrusion is
0.25 (0.010) per side. Dimensions A and B do include mold mismatch and are
determined at datum plane -H-.
7.Dimension D does not include dambar protrusion. Allowable dambar
protrusion shall not cause the D dimension to exceed 0.43 (0.017).
Figure 42 DSP56156 112-pin Pl astic Thin Quad Flat Pack (TQFP) Mechanical Information
NOTE: BSC = Between Statistical Center
(i.e., typical)
TOP
VIEW
Case 987-01
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Design Considerati ons
60 DSP56156 Data Sheet MOTOROLA
Design Considerations
ΘJC is device-related and cannot be influ-
enced by the user. However, ΘCA is user-de-
pendent and can be minimized by such
thermal management tech ni ques as heat
sinks, ambient air cooling, and thermal con-
vection. Thus, good thermal management on
the par t of the user can significantly reduce
ΘCA so that ΘJA approximately equals ΘJC.
Substitution of ΘJC for ΘJA in equation (1) will
result in a lower semiconductor junction
temperature. Values for thermal resistance
presented in this document, unless estimat-
ed, were derived using the procedure de-
scribed in Motorola Reliability Report 7843,
“Thermal Resistance Measurement Method
for MC68XX Microcomponent Devices”, and
ar e provided for design purposes only. Ther-
mal measurements are complex and depen-
dent on procedure and setup. User-derived
values for thermal resistance may diff er.
Power, Ground, and
Noise
Each DSP 561 56 V CC pin should be provided
with a low-impedance path to +5 volts. Each
DSP56156 GND pin should likewise be pro-
vided with a low-impedance path to ground.
The power supply pi ns drive dis tinct groups
of logic on chip as shown in Table 26.
The VCC power supply should be by-
passed to GND ground using at least six
0.01 – 0.1 µF bypass capacitor s located ei-
ther underneath the chip’s socket or as close
as possible to the four sides of the package.
The capacitor leads and the associated
printed circuit traces connecting to chip VCC
and GND should be kept to less than 0.5” per
Heat Dissipation
The average chip j unction temperatur e, TJ, in
°C, can be obtained from:
TJ = TA + (PD × ΘJA)(1)
Where:
TA= ambient temperature, °C
ΘJA = package thermal resistance,
junction-to-ambient, °C/W
PD=P
INT + PI/O
PINT =I
CC × VCC watts — chip internal
power
PI/O = power dissipation on input and
output pins — user determined
For most applications PI/O < PINT an d PI/O can
be neglected. An appropriate relationship be-
tween PD an d TJ (if PI/O is neglected) is:
PD = K/( TJ + 273) (2)
Solving equations (1) and (2) for K gives:
K = PD × (TA + 273) + PD × ΘJA (3)
Where K is a constant pertaining to the partic-
ular package. K can be determined from
equation (2) by measuring PD (at equilibri-
um) for a known TA. Using this value of K, the
values of PD and TJ can be obtained by solv-
ing equations (1) and (2) iteratively for any
value of TA. The total thermal resistance of a
package (ΘJA) can be separated into two com-
ponents, ΘJC and ΘCA, representing the barrier
to heat fl ow f r om the semiconductor junction
to the p ack age ( c ase) s urfac e (ΘJC) and from
the ca se t o the outside ambient (ΘCA). These
terms are rela ted b y t he equati on:
ΘJA = ΘJC + ΘCA (4)
Heat Dissipation
Power, Ground, and Noise
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Design Considerations
MOTOROLA DSP56156 Data Sheet 61
capacitor lead. The use of at least a four lay-
er board is recommended, employing two
inner layers a s VCC and GND planes. All
output pins on this DSP have fast rise and
fall times. Printed Circuit Board (PCB)
trace length shou ld be minimized in o rde r
to minimize undershoot and reflections
caused by these fast output switching
times. This recommendation particularly
applies to the address and data buses as
well as the PS/DS, BS, RD, WR, R/W, inter-
rupt, and HEN pins. Maximum PCB trace
lengths on the order of 6" are recommended.
Capacitance calculations should consider all
device loads as well as parasitic capaci tan c-
es due to PCB traces. Attention to proper
PCB layout and bypassing becomes espe-
cially critical in systems wi th h igher capac-
itive loads because these loads create
higher transient currents in the VCC and
GND circuits.
Clock signals should not be run across
many signals and should be kept away
from analog power and ground traces as
well as any analog signals. See Figure 44 for
more details.
Power, Ground, and Noise
Table 26 Power and Ground Connections
Circuitry
Power Ground
Signal
Name Pin # Signal
Name Pin #
Addr ess Bus Buffers VCC1
VCC2 92
103 GND0
GND1
GND2
GND3
89
95
101
108
Data Bus Buffers VCC3
VCC4 4
15 GND4
GND5
GND6
GND7
1
7
12
18
Bus Control Buffers VCC5 36 GND8 38
Codec VCCA 23 GNDA 26
Digital Peripherals VCC6
VCC7 59
76 GND9
GND10 53
73
Internal logic VCCQ0
VCCQ1 33
96 GNDQ0
GNDQ1 47
104
Phase-Locked Loop (PLL) VCCS 50 GNDS 48
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Design Considerati ons
62 DSP56156 Data Sheet MOTOROLA
Power Consumption
(VCC = 5.0 V dc ± 10%, TJ = - 4 0° to + 125°C, C L = 50 pF + 1 TTL Load)
The DC electrical characteristics of this device are shown in Table 27. Power consumption is
application dependant. The data in Table 27 is collected by running the following code using
internal memory afte r having programmed all pins of port B and C as input and after having
three-stated the data bus (MC = 0 in OMR) and pulled high:
move #0,r0
move #0,r3
move #$100,r2
move #$00ff,m0
loop clr a
move x:(r0)+,a ;initial value to accumulator
move a1,a0
rep #30
mac x0,y0,a x:(r3)+,x0 ;mac on typical data
move a,p:(r2) ;store the mac result
move #0,r3
jmp loop
To minimize the power dissipation, all unused digital input pins should be tied inactive to
gr ound or power; a nd all unused I/O pins should be tied inacti ve th rough a 10K¾ resistor to
ground or power. When the codec is not used, GNDA should be connected to GND; and VCCA
should be connected to VCC. Also, all codec pins should be left floating, except VREF which
should still be decoupled.
Table 27 DC Electrical Characteristics
Conditions Symbol
Typical
Unit
40
MHz 50
MHz 60
MHz
Digital current with Codec and PLL disabled ICC 91 112 133 mA
Digital current Wait Mode with Codec
and PLL disabled ICC 12 14 17 mA
Digital current Wait Mode with Codec Enabled
and PLL disabled ICC 92 113 134 mA
Stop mode with PLL and CLKO disabled ICC — 250 — µA
Digital current drawn by the PLL when active ICC —1—mA
Digital current drawn by CLKO when active ICC —3.6—mA
An alog current with Codec enabled ICCA —12—mA
Analog current with Codec disabled ICCA —70—µA
Powe r Co nsumption
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Design Considerations
MOTOROLA DSP56156 Data Sheet 63
Host Port
Considerations
Careful synchronization is required when
reading multi-bit registers that are written by
another async hronous system. This is a com-
mon problem when two asynchronous sys-
tems are connected. The situation exists in
the host interface. The considerations for
proper operation are discussed below.
Host Programming
Considerations
1. Unsynchronized Reading of
Receive Byte Registers
When reading receive byte registers,
RXH or RXL, the host program should
use interrupts or poll the RXDF flag
which indicates that data is available.
This assures that the data in the receive
byte registers will be stable.
2. Overwriting Transmit Byte Registers
The host program should not write to the
transmit byte registers, TXH or TXL, un-
less the TXDE bit is set indicating that the
transmit byte registers are empty. This
guarantees that the transmit byte regis-
ters will transfer valid data to the HRX
register.
3. Synchronization of Status Bits from
DSP to Host
HC, HREQ, DMA, HF3, HF2, TRDY,
TXDE, and RXDF status bits are set or
cleared from inside the DSP and read by
the host processor (r ef er to DSP56156 Us-
er’s Manu al, I/O Interface section, Host/
DMA Interface Programming Model for
descriptions of these status bits). The
host can read these status bits very quick-
ly without re gard to the clock rate used
by the DSP, but the possibili ty exists that
the state of the bit could be changing dur-
ing the read operation. This is generally
not a system problem, since the bit will
be read correctly in the next pass of any
host polling routine.
However, if the host asserts HEN for
more than timing number 101 (T101),
with a minimum cycle time of timing
number 103 (T103), then these status bits
are guaranteed to be stable. Care must
be exercised when reading status bits
HF3 and HF2 as an encoded pair. If the
DSP changes HF3 and HF2 from 00 to 1 1,
there is a small probab ility that the host
could r ead the bits during the transiti on
and receive 01 or 10 instead of 11 . If the
combination of HF3 and HF2 has signif-
icance, the host could read the wrong
combination. Therefore, read the bits
twice and check for consensus.
4. Overwriting the Host Vector
The host program should change the
Host Vector register only when the Host
Command bit (HC) is clear. This change
will guarantee that the DSP interrupt
control logic will receive a stable vector.
5. Cancelling a Pending Host Command
Exception
The host processor may elect to clear the
HC bit to cancel the host command ex-
ception request at any time before it is
recognized by the DSP. Because the host
does not know exactly when the excep-
tion will be r ecognized (due to e xception
pr ocessing synchroniz ation and pipeline
delays), the DSP may execute the host
command exception after the HC bit is
cleared. For these reasons, the HV bits
must not be changed at the same time
that the HC bit is cleared.
Host Port Considerations
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Design Considerati ons
64 DSP56156 Data Sheet MOTOROLA
DSP Programming
Considerations
1. Sy nchronization of Status Bit s
from Host to DSP
DMA, HF1, HF0, and HCP, H TDE,
and HRDF status bits are set or
clear ed by the host process or side of
the interface. These bits are individ-
ually synchr onized to the DSP clock.
(Refer to the DSP56156 User’s Manual,
I/O Interface se c ti o n, Host/DMA In-
terface Programming Model for de-
scriptions of these status bits.)
2. Read ing HF0 an d HF1 as an
Encoded Pair
Care must be exercised when reading
status bits HF0 and HF1 as an encod-
ed pair , i.e., the four combinations 00,
01, 10, and 11 each have signif ican ce.
A very small probability exists th at
the DSP will read the status bits syn-
chronized during transition. There-
fore, HF0 and HF1 should be read
twice and checked for consensus.
Bus Operation
Figure 43 depicts the operation of the external memory interface with multiple wait states.
Figure 43 Read and Write Bus Operation (3 Wait States)
T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1
T
Data out
CLKO
BS
A0-A15
PS/DS
R/W
WR
RD
D0-D15 Data in
DSP Programming Considerations
Bus Operation
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Design Considerations
MOTOROLA DSP56156 Data Sheet 65
Analog I/ O Considerations
Figur e 44 describes the r ecommended a nalog I/O and power supply conf igurations. The two
analog inputs are electrically identical. When one is not used, it can be left floating. When
used, an AC coupling capacitor is required. The value of the capacitor along with the input
impedance of the pin determine the cut off frequency of a high pass filter. The input imped-
ance of the MIC and AUX varies as a function of the sigma-delta (²ý) modulator master clock.
78 kΩ is a typical value at 2 MHz. An AC capacitor of 1µF defines a high pass filter pole of 2
Hz. A smaller capacitor value will move this pole higher in frequency.
Figure 44 R ecommended Analog I/O Configuration
Σ∆
modulator
2.0 V ±10%
(≤ ±1mA)
MIC
VREF
AUX
Bias
Š10 µF
-6 dB
6 dB
MGS1-0 bits
3 POLE
2 ZERO
Low P ass
Filter (LPF)
VC3-VC0
(to microphone)
SPKP
(2/5 VCC)
+
digital VCC
INS bit
17 dB
VDIV
ð50 nF
1 µF600 Ω
0.001 µF
1 µF
600 Ω
RBias
15 µF0.1 µF
+5 dB
54 KΩ
36 KΩ
Š1 KΩ
10 KΩ
5.6 KΩ
VREF
0.001 µF
VCCA GNDA
+
15 µF0.1 µF
MUX
GNDA
GNDA
+5 V
+
220 µF
Analog Decoupling
near DSP
Single trace
External External Supply
GND
digital GND Single trace
GNDA
VCCA
0.01 µF
SPKM
5.6 KΩ
VREF
GND
Analog I/O Considerations
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Design Considerati ons
66 DSP56156 Data Sheet MOTOROLA
Figure 45 shows three possible single-ended output configurations. Configuration (a) is highly
recommended. For configur ati o ns (b) and (c), an AC coupling c apac itor is required since the
load resistor is tied to GNDA.
Figure 46 shows a recommended layout for power and ground planes.
Figure 46 Ground and Power planes
Š 500 Ω
SPKP
SPKM
Š 500 Ω
47 K¾
47 K¾
47 K¾
VREF
47 K¾
SPKP
SPKM
SPKP
SPKM
Š 500 Ω
0 < C ð 100 nF
NC
(a) (b) (c)
-
+
VCCA
GNDA
0 < C ð 100 nF
0 < C ð 100 nF
Figure 45 Single-ended Output Configurations
128
84 57
56 29
112 85
Analog Ground and
Power pl anes
Digital Ground and
Power planes
Analog I/O Consi deratio ns
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Design Considerations
MOTOROLA DSP56156 Data Sheet 67
A four level board is recommended. The top layer (directly under the parts) and the bottom
layer should be interconnect layers. The two center layers should be power and ground.
Ground and power planes should be completely separated. The digital and analog power/
ground planes should not overlap. All codec pins should be over the analog planes. The ana-
log planes should not encompass any digital pins. All codec signal traces should be over the
analog planes.
Figur e 47 shows that 0.1 µF bypass caps should be located as close to the pins being bypassed
as possible. The ground side of these caps should be connected as close as possible to the VCCA
pin. The ground side of the bypass cap should be connected to the VCCA pin by short traces.
Figure 47 Suggested Top Layer Bypassing
The pins with 0.1 µF bypass caps ar e VREF and GND A. The la r gest si ze pr actica l bypa ss
caps should al so be added for each of these pins as well as for the VDIV pin; 10 µF bypass
caps should be considered a minimum value for the larger caps (65 µF on VDIV may be
used). These ca ps should be nea r the packag e but do not have to be rig ht next to the pins.
The DAC outputs (SPKP and SPKM) should be run right next to each other as shown on Figure 48.
28
29
GNDA
SPKP
SPKM
VCCA
BIAS
AUX
MIC
0.1 µF0.1 µF
Š10 µF
25 µF
VDIV
VREF
65 µF
10 kΩ
Analog I/O Considerations
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Design Considerati ons
68 DSP56156 Data Sheet MOTOROLA
Figure 48 Suggested Bottom Layer Routing
The output should be used differentially if at all possible. Analog signal traces should be
shielded by running traces connected to analog ground next to them. Unused board area on
both inter connect levels should be copper fi lled and connect ed to analog gr ound. The copper
fill is only shown on this page for clarity and simplicity. The ADC input anti-aliasing should
be done with respect to VREF.
Figure 49 presents four options for good power supply connections.
28
29
GNDA
SPKP
SPKM
VCCA
0.25 µF
47 kΩ
47 kΩ
Copper Fill of unused board space
should be connected to the analog ground plane.
BIAS
AUX
MIC
VDIV
VREF
47 kΩ
1nF
47 kΩ
5.6 kΩ
MIC IN
SPK OUT
Analog I/O Considerations
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Design Considerations
MOTOROLA DSP56156 Data Sheet 69
Figure 49 Four Possible Power Supply Connections
28
29
GNDA
SPKP
SPKM
VCCA
AUX
MIC
VREF
VDIV
Ideal Choice — Two separate powe r su ppl ies.
Ground planes connected with a single trace as
close as possible to the VCCA pin on the codec.
GNDA
SPKP
SPKM
VCCA
Second Choice — One p ower su pp ly.
Two regulators, one for the digital supply, one for
the analog supply . Ground planes connected with
a 10 ¾ resistor as close as possible to the VCCA
pin on the codec.
10Ω
Voltage
Regulator
BIAS
28
29
AUX
MIC
VREF
VDIV
BIAS
Voltage
Regulator
Third Choice — One power supply.
One regulator for the analog supply. Digital sup-
plies driven directly by voltage source. Ground
planes connected with a 10 ¾ resistor as close as
possible to the VCCA pin on the codec.
10Ω
Fourth Choice — One power supply . Ground
planes connected at source. Ground planes
connected with a 10 ¾ resistor as close as pos-
sible to the VCCA pin on the codec.
28
29
GNDA
SPKP
SPKM
VCCA
AUX
MIC
VREF
VDIV
BIAS
10Ω
28
29
GNDA
SPKP
SPKM
VCCA
AUX
MIC
VREF
VDIV
BIAS
Voltage
Regulator
Analog I/O Considerations
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Ordering Information
70 DSP56156 Data Sheet MOTOROLA
Ordering Information
Table 28 lists information for ordering parts.
Table 28 DSP56156 Ordering Infor m ation
Supply
Voltage Package Type Pin Count Frequency
(MHz) Order Number
5 V Ceramic Quad Flat
Pack (CQFP) 112 40 DSP56156FE40
60 DSP56156FE60
5 V Plastic Thin Quad
Flat Pack (TQFP) 112 40 DSP56156FV40
60 DSP56156FV60
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MOTOROLA
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any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights
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alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and M are registered trademarks of Motorola, Inc. Motorola, Inc.
is an Equal Opportunity/Affirmative Action Employer.
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