TPS7A47xx
RF LDO
Amplifier
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TPS7A470x 36-V, 1-A, 4-µV
RMS
, RF LDO Voltage Regulator
1 Features 3 Description
The TPS7A47 is a family of positive voltage (+36 V),
1 Input Voltage Range: +3 V to +36 V ultralow-noise (4 µVRMS) low-dropout linear regulators
Output Voltage Noise: (LDO) capable of sourcing a 1-A load.
4 µVRMS (10 Hz, 100 kHz) The TPS7A4700 output voltages are user-
Power-Supply Ripple Rejection: programmable (up to 20.5 V) using a printed circuit
82 dB (100 Hz) board (PCB) layout without the need of external
resistors or feed-forward capacitors, thus reducing
55 dB (10 Hz, 10 MHz) overall component count.
Two Output Voltage Modes: The TPS7A4701 output voltage can be configured
ANY-OUT™ Version (User-Programmable with a user-programmable PCB layout (up to 20.5 V),
Output via PCB Layout): or adjustable (up to 34 V) with external feedback
No External Feedback Resistors or Feed- resistors.
Forward Capacitors Required The TPS7A47 is designed with bipolar technology
Output Voltage Range: +1.4 V to +20.5 V primarily for high-accuracy, high-precision
Adjustable Version (TPS7A4701 only): instrumentation applications where clean voltage rails
Output Voltage Range: +1.4 V to +34 V are critical to maximize system performance. This
feature makes the device ideal for powering
Output Current: 1 A operational amplifiers, analog-to-digital converters
Dropout Voltage: 307 mV at 1 A (ADCs), digital-to-analog converters (DACs), and
CMOS Logic Level-Compatible Enable Pin other high-performance analog circuitry in critical
applications such as medical, radio frequency (RF),
Built-In Fixed Current Limit and and test-and-measurement.
Thermal Shutdown
Available in High-Performance Thermal Package: In addition, the TPS7A47 is ideal for post dc-dc
converter regulation. By filtering out the output
5-mm × 5-mm QFN voltage ripple inherent to dc-dc switching
Operating Temperature Range: conversions, maximum system performance is
–40°C to 125°C ensured in sensitive instrumentation, test-and-
measurement, audio, and RF applications.
2 Applications For applications where positive and negative low-
Voltage-Controlled Oscillators (VCO) noise rails are required, consider TI's TPS7A33 family
Frequency Synthesizers of negative high-voltage, ultralow-noise linear
regulators.
Test and Measurement
Instrumentation, Medical, and Audio Device Information(1)
RX, TX, and PA Circuitry PART NUMBER PACKAGE BODY SIZE (NOM)
Supply Rails for Operational Amplifiers, TPS7A470x VQFN (20) 5 mm × 5 mm
DACs, ADCs, and Other High-Precision Analog (1) For all available packages, see the orderable addendum at
Circuitry the end of the datasheet.
Post DC-DC Converter Regulation and
Ripple Filtering
Base Stations and Telecom Infrastructure
+12-V and +24-V Industrial Buses
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A4700
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TPS7A4701
SBVS204F JUNE 2012REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
1 Features.................................................................. 18 Application and Implementation ........................ 16
8.1 Application Information............................................ 16
2 Applications ........................................................... 18.2 Typical Application ................................................. 16
3 Description............................................................. 19 Power Supply Recommendations...................... 20
4 Revision History..................................................... 29.1 Power Dissipation (PD)........................................... 20
5 Pin Configuration and Functions......................... 410 Layout................................................................... 21
6 Specifications......................................................... 510.1 Layout Guidelines ................................................. 21
6.1 Absolute Maximum Ratings ...................................... 510.2 Layout Example .................................................... 21
6.2 Handling Ratings....................................................... 610.3 Thermal Protection................................................ 22
6.3 Recommended Operating Conditions....................... 610.4 Estimating Junction Temperature ......................... 22
6.4 Thermal Information.................................................. 611 Device and Documentation Support................. 23
6.5 Electrical Characteristics........................................... 711.1 Documentation Support ........................................ 23
6.6 Typical Characteristics.............................................. 811.2 Related Links ........................................................ 23
7 Detailed Description............................................ 12 11.3 Trademarks........................................................... 23
7.1 Overview................................................................. 12 11.4 Electrostatic Discharge Caution............................ 23
7.2 Functional Block Diagram....................................... 12 11.5 Glossary................................................................ 23
7.3 Feature Description................................................. 12 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 13 Information ........................................................... 23
7.5 Programming........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (January 2014) to Revision F Page
Added Handling Rating table, Feature Description section, Device Functional Modes,Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
Reworded ninth bullet in Features list.................................................................................................................................... 1
Changed polarity of op amp shown on right side of the functional block diagram .............................................................. 12
Reworded second paragraph in Soft-Start And Inrush Current section .............................................................................. 13
Revised Capacitor Recommendations section..................................................................................................................... 16
Changed paragraph 2 of Dropout Voltage (VDO)section for clarity ..................................................................................... 17
Revised paragraph 1 of Startup section .............................................................................................................................. 17
Rewrote paragraph 1 of Power-Supply Rejection Ratio (PSRR) section to eliminate confusion ........................................ 18
Changed paragraph 1 of Power Supply Recommendations section ................................................................................... 20
Changed paragraph 1 and paragraph 4 of Power Dissipation (PD)section......................................................................... 20
Revised paragraph 2 of Layout Guidelines section ............................................................................................................. 21
Changed second paragraph of Thermal Protection section ................................................................................................ 22
Changes from Revision D (December 2013) to Revision E Page
Changed Output Voltage Noise value from 4.17 µV to 4 µV in three instances on front page.............................................. 1
Changed 2nd and 3rd paragraphs of Description section...................................................................................................... 1
Added "Thermal Pad" to pin configuration drawing................................................................................................................ 4
Changed EN pin description................................................................................................................................................... 4
Changed SENSE/FB pin to be for TPS7A4701 only.............................................................................................................. 5
Added new row to Pin Descriptions table for SENSE pin (for TPS7A4700 only)................................................................... 5
Added new row to Pin Descriptions table for thermal pad ..................................................................................................... 5
Added VREF parameter............................................................................................................................................................ 7
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SBVS204F JUNE 2012REVISED SEPTEMBER 2014
Added TPS7A4701 device to test conditions for VNR parameter............................................................................................ 7
Added Feedback Pin Current parameter to Electrical Characteristics .................................................................................. 7
Deleted Dropout Voltage vs Output Current graph ................................................................................................................ 8
Added EN pin to Functional Block Diagram......................................................................................................................... 12
Added sentence to ANY-OUT Programmable Output Voltage section to clarify ANY-OUT is for both devices.................. 13
Changed last two paragraphs of Adjustable Operation section ........................................................................................... 14
Added "TPS7A4701 Only" to Adjustable Operation section title.......................................................................................... 14
Deleted equation in Figure 23 .............................................................................................................................................. 14
Changed Equation 3............................................................................................................................................................. 14
Changes from Revision C (July 2013) to Revision D Page
Changed data sheeet status from production mix to production data.................................................................................... 1
Changed TPS7A4701 ESD rating from > 1 kV to 2.5 kV....................................................................................................... 1
Changed noise reduction pin voltage parameter to show both devices................................................................................. 7
Added text clarifying VREF typical value to last paragraph on page...................................................................................... 14
Changes from Revision B (April 2013) to Revision C Page
Deleted TPS7A4702 preview device from data sheet............................................................................................................ 1
Changes from Revision A (July 2012) to Revision B Page
Changed TPS7A47 to TPS7A4700........................................................................................................................................ 1
Added TPS7A4701 and TPS7A4702 preview devices to data sheet..................................................................................... 1
Changed front-page figure...................................................................................................................................................... 1
Added FB to SENSE pin to Functional Block Diagram........................................................................................................ 12
Added new paragraph after Table 1..................................................................................................................................... 14
Added new Table 2............................................................................................................................................................... 14
Added Adjustable Operation section.................................................................................................................................... 14
Changes from Original (June 2012) to Revision A Page
Moved to full production data (changes throughout document)............................................................................................. 1
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OUT
NC
NC
NC
IN
1
2
3
4
5
620
719
818
917
10 16
15
14
13
12
11
OUT IN
NR
EN
0P1V
0P2V
3P2V
GND
1P6V
0P8V
0P4V
NC
SENSE/FB
6P4V2
6P4V1
(Thermal Pad)
TPS7A4700
,
TPS7A4701
SBVS204F JUNE 2012REVISED SEPTEMBER 2014
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5 Pin Configuration and Functions
RGW Package
5-mm × 5-mm VQFN-20
(Top View)
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
When connected to GND, this pin adds 0.1 V to the nominal output voltage of the regulator.
0P1V 12 I Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 0.2 V to the nominal output voltage of the regulator.
0P2V 11 I Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 0.4 V to the nominal output voltage of the regulator.
0P4V 10 I Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 0.8 V to the nominal output voltage of the regulator.
0P8V 9 I Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 1.6 V to the nominal output voltage of the regulator.
1P6V 8 I Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 3.2 V to the nominal output voltage of the regulator.
3P2V 6 I Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator.
6P4V1 5 I Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator.
6P4V2 4 I Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
Enable pin. The device is enabled when the voltage on this pin exceeds the maximum
EN 13 I enable voltage, VEN(HI). If enable is not required, tie EN to IN.
GND 7 Ground
Input supply. A capacitor greater than or equal to 1 µF must be tied from this pin to ground to
assure stability.
IN 15, 16 I A 10-µF capacitor is recommended to be connected from IN to GND (as close to the device
as possible) to reduce circuit sensitivity to printed circuit board (PCB) layout, especially when
long input traces or high source impedances are encountered.
NC 2, 17-19 This pin can be left open or tied to any voltage between GND and IN.
Noise reduction pin. When a capacitor is connected from this pin to GND, RMS noise can be
reduced to very low levels. A capacitor greater than or equal to 10 nF must be tied from this
NR 14 pin to ground to assure stability. A 1-µF capacitor is recommended to be connected from NR
to GND (as close to the device as possible) to maximize ac performance and minimize noise.
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Pin Functions (continued)
PIN I/O DESCRIPTION
NAME NO.
Regulator output. A capacitor greater than or equal to 10 µF must be tied from this pin to
ground to assure stability. A 47-µF ceramic output capacitor is highly recommended to be
OUT 1, 20 O connected from OUT to GND (as close to the device as possible) to maximize ac
performance.
Control-loop error amplifier input (TPS7A4701 only).
This is the SENSE pin if the device output voltage is programmed using ANY-OUT (no
external feedback resistors). This pin must be connected to OUT. Connect this pin to the
SENSE/FB 3 I point of load to maximize accuracy.
This is the FB pin if the device output voltage is set using external resistors. See the
Adjustable Operation section for more details.
Control-loop error amplifier input (TPS7A4700 only).
SENSE 3 I This is the SENSE pin of the device and must be connected to OUT. Connect this pin to the
point of load to maximize accuracy.
Connect the thermal pad to a large-area ground plane. The thermal pad is internally
Thermal Pad connected to GND.
6 Specifications
6.1 Absolute Maximum Ratings
Over junction temperature range, unless otherwise noted.(1)
MIN MAX UNIT
IN pin to GND pin –0.4 +36 V
EN pin to GND pin –0.4 +36 V
EN pin to IN pin –36 +0.4 V
OUT pin to GND pin –0.4 +36 V
NR pin to GND pin –0.4 +36 V
SENSE/FB pin to GND pin –0.4 +36 V
0P1V pin to GND pin –0.4 +36 V
Voltage(2) 0P2V pin to GND pin –0.4 +36 V
0P4V pin to GND pin –0.4 +36 V
0P8V pin to GND pin –0.4 +36 V
1P6V pin to GND pin –0.4 +36 V
3P2V pin to GND pin –0.4 +36 V
6P4V1 pin to GND pin –0.4 +36 V
6P4V2 pin to GND pin –0.4 +36 V
Current Peak output Internally limited
Temperature Operating virtual junction, TJ–40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability..
(2) All voltages are with respect to network ground terminal.
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6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per –1000 1000
ANSI/ESDA/JEDEC JS-001, all pins(1)
TPS7A4700 V
Charged device model (CDM), per JEDEC –500 500
specification JESD22-C101, all pins(2)
Electrostatic
V(ESD) discharge Human body model (HBM), per –2500 2500
ANSI/ESDA/JEDEC JS-001, all pins(1)
TPS7A4701 V
Charged device model (CDM), per JEDEC –500 500
specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over junction temperature range (unless otherwise noted) MIN NOM MAX UNIT
VI3.0 35.0 V
VO1.4 34.0 V
VEN 0 VIN V
IO0 1.0 A
6.4 Thermal Information TPS7A47xx
THERMAL METRIC(1) RGW UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 32.5
RθJC(top) Junction-to-case (top) thermal resistance 27
RθJB Junction-to-board thermal resistance 11.9 °C/W
ψJT Junction-to-top characterization parameter 0.3
ψJB Junction-to-board characterization parameter 11.9
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At –40°C TJ125°C; VI= VO(nom) + 1.0 V or VI= 3.0 V (whichever is greater); VEN = VI; IO= 0 mA; CIN =10 µF; COUT = 10
µF; CNR = 10 nF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN, unless
otherwise noted.PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIInput voltage range 3 35 V
VIrising 2.67 V
VUVLO Under-voltage lockout threshold VIfalling 2.5 V
V(REF) Reference voltage V(REF) = V(FB), TPS7A4701 only 1.4 V
VUVLO(HYS) Under-voltage lockout hysteresis 177 mV
TPS7A4700, TPS7A4701 using ANY-OUT VOUT V
option
VNR Noise reduction pin voltage TPS7A4701 in adjustable mode only 1.4 V
TPS7A4700,
TPS7A4701 1.4 20.5 V
using ANY-
VIVO(nom) + 1.0 V or 3 V OUT option
Output voltage range (whichever is greater), TPS7A4701
COUT = 20 µF using
VO1.4 34 V
adjustable
option
Nominal accuracy TJ= 25°C, COUT = 20 µF –1.0 1.0 %VO
VO(nom) + 1.0 V VI35 V,
Overall accuracy –2.5 2.5 %VO
0 mA IO1 A, COUT = 20 µF
ΔVO(ΔVI) Line regulation VO(nom) + 1.0 V VI35 V 0.092 %VO
ΔVO(ΔIO) Load regulation 0 mA IO1 A 0.3 %VO
VI= 95% VO(nom), IO= 0.5 A 216 mV
V(DO) Dropout voltage VI= 95% VO(nom), IO= 1 A 307 450 mV
I(CL) Current limit VO= 90% VO(nom) 1 1.26 A
IO= 0 mA 0.58 1.0 mA
I(GND) Ground pin current IO= 1 A 6.1 mA
VEN = VI0.78 2 µA
I(EN) Enable pin current VI= VEN = 35 V 0.81 2 µA
VEN = 0.4 V 2.55 8 µA
I(SHDN) Shutdown supply current VEN = 0.4 V, VI= 35 V 3.04 60 µA
V+EN(HI) Enable high-level voltage 2.0 VIV
V+EN(LO) Enable low-level voltage 0.0 0.4 V
I(FB) Feedback pin current 350 nA
VI= 16 V, VO(nom) = 15 V, COUT = 50 µF,
PSRR Power-supply rejection ratio 78 dB
IO= 500 mA, CNR = 1 µF, f = 1 kHz
VI= 3 V, VO(nom) = 1.4 V, COUT = 50 µF, 4.17 µVRMS
CNR = 1 µF, BW = 10 Hz to 100 kHz
VnOutput noise voltage VIN = 6 V, VO(nom) = 5 V, COUT = 50 µF, 4.67 µVRMS
CNR = 1 µF, BW = 10 Hz to 100 kHz
Shutdown, temperature increasing 170 °C
Tsd Thermal shutdown temperature Reset, temperature decreasing 150 °C
TJOperating junction temperature –40 125 °C
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0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
VEN (V)
G005
0
200
400
600
800
1000
0 5 10 15 20 25 30 35 40
Input Voltage (V)
IQ (µA)
−40°C
0°C
+25°C
+105°C
+125°C
IOUT = 0 µA
G006
−4
−3
−2
−1
0
1
2
3
4
0 100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
VOUT(NOM) (%)
−40°C
0°C
+25°C
+85°C
+125°C
G002
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
VIN (V)
UVLO Threshold Off
UVLO Threshold On
G004
0.01
0.1
1
10
100
10 100 1k 10k 100k 1M
Frequency (Hz)
Noise (µV Hz)
VOUT = 1.4 V, VNOISE = 4.17 µVRMS
VOUT = 5 V, VNOISE = 4.67 µVRMS
VOUT = 10 V, VNOISE = 7.25 µVRMS
VOUT = 15 V, VNOISE = 12.28 µVRMS
IOUT = 500 mA
COUT = 50 µF
CNR = 1 µF
BWRMSNOISE (10 Hz, 100 kHz)
G020
−4
−3
−2
−1
0
1
2
3
4
0 5 10 15 20 25 30 35 40
Input Voltage (V)
VOUT(NOM) (%)
−40°C
0°C
+25°C
+85°C
+125°C
G001
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6.6 Typical Characteristics
At –40°C TJ125°C; VI= VO(nom) + 1.0 V or VI= 3.0 V (whichever is greater); VEN = VI; IO= 0 mA; CIN =10 µF; COUT = 10
µF; CNR = 1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN, unless
otherwise noted.
Figure 1. Noise vs Output Voltage Figure 2. Line Regulation
Figure 3. Load Regulation Figure 4. UVLO Threshold vs Temperature
Figure 5. Enable Voltage Threshold vs Temperature Figure 6. Quiescent Current vs Input Voltage
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0
10
20
30
40
50
60
70
80
90
100
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
PSRR (dB)
CNR = 0.01 µF
CNR = 0.1 µF
CNR = 1 µF
CNR = 2.2 µF
IOUT = 1 A
COUT = 50 µF
VIN = 3 V
VOUT = 1.4 V
G011
0
10
20
30
40
50
60
70
80
90
100
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
PSRR (dB)
CNR = 0.01 µF
CNR = 0.1 µF
CNR = 1 µF
CNR = 2.2 µF
IOUT = 0.5 A
COUT = 50 µF
VIN = 3 V
VOUT = 1.4 V
G012
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35 40
Input Voltage (V)
ISHDN (µA)
−40°C
0°C
+25°C
+105°C
+125°C
G009
0
0.5
1
1.5
2
2.5
3
0 4 8 12 16 20
Input Voltage (V)
ICL (A)
−40°C
0°C
+25°C
+85°C
+125°C
VOUT = 90% VOUT(NOM)
G010
0.1
1
10
1 10 100 1000
Output Current (mA)
IGND (mA)
−40°C
0°C
+25°C
+85°C
+125°C
G007
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 5 10 15 20 25 30 35 40
Input Voltage (V)
IEN (µA)
−40°C
0°C
+25°C
+85°C
+125°C
G008
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Typical Characteristics (continued)
At –40°C TJ125°C; VI= VO(nom) + 1.0 V or VI= 3.0 V (whichever is greater); VEN = VI; IO= 0 mA; CIN =10 µF; COUT = 10
µF; CNR = 1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN, unless
otherwise noted.
Figure 7. Ground Current vs Output Current Figure 8. Enable Current vs Input Voltage
Figure 9. Shutdown Current vs Input Voltage Figure 10. Current Limit vs Input Voltage
Figure 11. Power-Supply Rejection Ratio vs CNR Figure 12. Power-Supply Rejection Ratio vs CNR
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0
10
20
30
40
50
60
70
80
90
100
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
PSRR (dB)
VOUT = 1.4 V
VOUT = 3.3 V
VOUT = 5V
VOUT = 10V
VOUT = 15 V
CNR = 1 µF
COUT = 50 µF
IOUT = 500 mA
G017
0
10
20
30
40
50
60
70
80
90
100
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
PSRR (dB)
VOUT = 1.4V
VOUT = 3.3V
VOUT = 5V
VOUT = 10V
VOUT = 15V
CNR = 1µF
COUT = 50µF
IOUT = 1000mA
G018
0
10
20
30
40
50
60
70
80
90
100
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
PSRR (dB)
VDO = 200 mV
VDO = 300 mV VDO = 500 mV
VDO = 1 V
VOUT = 3.3 V, IOUT = 500 mA
CNR = 1 µF, COUT = 50 µF
G015
0
10
20
30
40
50
60
70
80
90
100
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
PSRR (dB)
VDO = 200 mV
VDO = 300 mV VDO = 500 mV
VDO = 1 V
VOUT = 3.3 V
CNR = 1 µF
COUT = 50 µF
IOUT = 1 A
G016
0
10
20
30
40
50
60
70
80
90
100
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
PSRR (dB)
IOUT = 0 mA
IOUT = 50 mA
IOUT = 500 mA
IOUT = 1000 mA
CNR = 1 µF
COUT = 50 µF
VIN = 3 V
VOUT = 1.4 V
G013
0
10
20
30
40
50
60
70
80
90
100
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
PSRR (dB)
VDO = 200 mV
VDO = 300 mV
VDO = 500 mV
VDO = 1 V
VOUT = 3.3 V
CNR = 1 µF
COUT = 50 µF
IOUT = 50 mA
G014
TPS7A4700
,
TPS7A4701
SBVS204F JUNE 2012REVISED SEPTEMBER 2014
www.ti.com
Typical Characteristics (continued)
At –40°C TJ125°C; VI= VO(nom) + 1.0 V or VI= 3.0 V (whichever is greater); VEN = VI; IO= 0 mA; CIN =10 µF; COUT = 10
µF; CNR = 1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN, unless
otherwise noted.
Figure 13. Power-Supply Rejection Ratio vs IOFigure 14. Power-Supply Rejection Ratio vs Dropout
Figure 15. Power-Supply Rejection Ratio vs Dropout Figure 16. Power-Supply Rejection Ratio vs Dropout
Figure 17. Power-Supply Rejection Ratio vs Output Voltage Figure 18. Power-Supply Rejection Ratio vs Output Voltage
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0.01
0.1
1
10
100
10 100 1k 10k 100k 1M
Frequency (Hz)
Noise (µV Hz)
IOUT = 50 mA, VNOISE = 5 µVRMS
IOUT = 20 mA, VNOISE = 5.9 µVRMS
VOUT = 4.7 V
COUT = 10 µF
CNR = 1 µF
BWRMSNOISE [10 Hz, 100 kHz]
G019
Time (50 ms/div) G062
V
(2 V/div)
OUT
V
(2 V/div)
EN
I
(200 mA/div)
OUT Startup Time = 65 ms
V = 6 V, V = 5 V
I = 500 mA
C = 10 F
C = 50 F
IN OUT
OUT
IN
OUT
m
m
Time (5 ms/div) G061
V
(10 V/div)
IN
V
(10 mV/div)
OUT
V = 5 V to 15 V
V = 3.3 V
I = 845 mA
IN
OUT
OUT
TPS7A4700
,
TPS7A4701
www.ti.com
SBVS204F JUNE 2012REVISED SEPTEMBER 2014
Typical Characteristics (continued)
At –40°C TJ125°C; VI= VO(nom) + 1.0 V or VI= 3.0 V (whichever is greater); VEN = VI; IO= 0 mA; CIN =10 µF; COUT = 10
µF; CNR = 1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins OPEN, unless
otherwise noted.
Figure 19. Load Transient Figure 20. Line Transient
Figure 21. Startup Figure 22. Noise vs Output Current
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200 kW
400 kW
800 kW
1.6 MW
3.2 MW
0P8V
0P4V
0P2V
0P1V
1P6V
100 kW
3P2V
50 kW
6P4V
50 kW
6P4V
Band
Gap
265.5 kW
100 kW
1.572 MW
IN
IN
CIN
Fast
Charge
Current
Limit
OUT
OUT
COUT
NR
CNR
UVLO
Thermal
Shutdown
SENSE/FB
Enable EN
TPS7A4700
,
TPS7A4701
SBVS204F JUNE 2012REVISED SEPTEMBER 2014
www.ti.com
7 Detailed Description
7.1 Overview
The TPS7A4700 and TPS7A4701 (TPS7A470x) are positive voltage (+36 V), ultralow-noise (4 µVRMS) LDOs
capable of sourcing a 1-A load. The TPS7A470x is designed with bipolar technology primarily for high-accuracy,
high-precision instrumentation applications where clean voltage rails are critical to maximize system
performance. This feature makes the device ideal for powering operational amplifiers, analog-to-digital converters
(ADCs), digital-to-analog converters (DACs), and other high-performance analog circuitry.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Internal Current Limit (ICL)
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The
LDO is not designed to operate at a steady-state current limit. During a current-limit event, the LDO sources
constant current. Therefore, the output voltage falls while load impedance decreases. Note also that when a
current limit occurs while the resulting output voltage is low, excessive power is dissipated across the LDO,
which results in a thermal shutdown of the output.
7.3.2 Enable (EN) And Under-Voltage Lockout (UVLO)
The TPS7A470x only turns on when both EN and UVLO are above the respective voltage thresholds. The UVLO
circuit monitors input voltage (VI) to prevent device turn-on before VIrises above the lockout voltage. The UVLO
circuit also causes a shutdown when VIfalls below lockout. The EN signal allows independent logic-level turn-on
and shutdown of the LDO when the input voltage is present. EN can be connected directly to VIif independent
turn-on is not needed.
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V = V + ( ANY-OUT Pins to Ground)
OUT REF S
I =
OUT(t)
COUT OUT
´dV (t)
dt
VOUT(t)
RLOAD
+
TPS7A4700
,
TPS7A4701
www.ti.com
SBVS204F JUNE 2012REVISED SEPTEMBER 2014
Feature Description (continued)
7.3.3 Soft-Start And Inrush Current
Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO have
achieved threshold voltage. The noise reduction capacitor serves a dual purpose of both governing output noise
reduction and programming the soft-start ramp during turn-on.
Inrush current is defined as the current through the LDO from IN to OUT during the time of the turn-on ramp up.
Inrush current then consists primarily of the sum of load and charge current to the output capacitor. Inrush
current can be estimated by Equation 1:
where:
VOUT(t) is the instantaneous output voltage of the turn-on ramp,
dVOUT(t)/dt is the slope of the VOramp, and
RLOAD is the resistive load impedance (1)
7.4 Device Functional Modes
The TPS7A470x has the following functional modes:
1. Enabled: When EN goes above V+EN(HI), the device is enabled.
2. Disabled: When EN goes below V+EN(LO), the device is disabled. During this time, OUT is high impedance,
and the current into IN does not exceed I(SHDN).
7.5 Programming
7.5.1 ANY-OUT Programmable Output Voltage
Both devices can be used in ANY-OUT mode. For ANY-OUT operation, the TPS7A4700 and TPS7A4701 do not
use external resistors to set the output voltage, but use device pins 4, 5, 6, 8, 9, 10, 11, and 12 to program the
regulated output voltage. Each pin is either connected to ground (active) or is left open (floating). The ANY-OUT
programming is set by Equation 2 as the sum of the internal reference voltage (V(REF) = 1.4 V) plus the
accumulated sum of the respective voltages assigned to each active pin; that is, 100 mV (pin 12), 200 mV (pin
11), 400 mV (pin 10), 800 mV (pin 9), 1.6 V (pin 8), 3.2 V (pin 6), 6.4 V (pin 5), or 6.4 V (pin 4). Table 1
summarizes these voltage values associated with each active pin setting for reference. By leaving all program
pins open, or floating, the output is thereby programmed to the minimum possible output voltage equal to V(REF).
(2)
Table 1. ANY-OUT Programmable Output Voltage
ANY-OUT PROGRAM PINS (Active Low) ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 4 (6P4V2) 6.4 V
Pin 5 (6P4V1) 6.4 V
Pin 6 (3P2) 3.2 V
Pin 8 (1P6) 1.6 V
Pin 9 (0P8) 800 mV
Pin 10 (0P4) 400 mV
Pin 11 (0P2) 200 mV
Pin 12 (0P1) 100 mV
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OUT REF
1
REF
FB
2
V V
R = V
I
R
-
+
TPS7A4701
OUT
FB
GND
C
10 F
IN
m
C
1 F
NR/SS
m
R1
R2
C
47 F
OUT
m
IN
EN
NR
VIN VOUT
TPS7A4700
,
TPS7A4701
SBVS204F JUNE 2012REVISED SEPTEMBER 2014
www.ti.com
Table 2 shows a list of the most common output voltages and the corresponding pin settings. The voltage setting
pins have a binary weight; therefore, the output voltage can be programmed to any value from 1.4 V to 20.5 V in
100-mV steps.
Table 2. Common Output Voltages and Corresponding Pin Settings
PIN NAMES AND VOLTAGE PER PIN
0P1V 0P2V 0P4V 0P8V 1P6V 3P2V 6P4V1 6P4V2
VO(V) 100 mV 200 mV 400 mV 800 mV 1.6 V 3.2 V 6.4 V 6.4 V
1.4 Open Open Open Open Open Open Open Open
1.5 GND Open Open Open Open Open Open Open
1.8 Open Open GND Open Open Open Open Open
2.5 GND GND Open GND Open Open Open Open
3 Open Open Open Open GND Open Open Open
3.3 GND GND Open Open GND Open Open Open
4.5 GND GND GND GND GND Open Open Open
5 Open Open GND Open Open GND Open Open
10 Open GND GND Open GND Open GND Open
12 Open GND Open GND Open GND GND Open
15 Open Open Open GND Open Open GND GND
18 Open GND GND Open Open GND GND GND
20.5 GND GND GND GND GND GND GND GND
7.5.2 Adjustable Operation (TPS7A4701 Only)
The TPS7A4701 has an output voltage range of 1.4 V to 34 V. For adjustable operation, set the nominal output
voltage of the device using two external resistors, as shown in Figure 23.
Figure 23. Adjustable Operation for Maximum AC Performance
R1and R2can be calculated for any output voltage within the operational range. The current through feedback
resistor R2must be at least 5 µA to ensure stability. Additionally, the current into the FB pin (I(FB), typically 350
nA) creates an additional output voltage offset that depends on the resistance of R1. For high-accuracy
applications, select R2such that the current through R2is at least 35 µA to minimize any effects of I(FB) variation
on the output voltage; 10 kΩis recommended. R1can be calculated using Equation 3.
where
VREF = 1.4 V
IFB = 350 nA (3)
Use 0.1% tolerance resistors to minimize the effects of resistor inaccuracy on the output voltage.
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,
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SBVS204F JUNE 2012REVISED SEPTEMBER 2014
Table 3 shows the resistor combinations to achieve some standard rail voltages with commercially-available 1%
tolerance resistors. The resulting output voltages yield a nominal error of < 0.5%.
Table 3. Suggested Resistors for Common Voltage Rails
VOUT R1, Calculated R1, Closest 1% Value R2
1.4 V 0 Ω0Ω
1.8 V 2.782 kΩ2.8 kΩ9.76 kΩ
3.3 V 13.213 kΩ13.3 kΩ9.76 kΩ
5 V 25.650 kΩ25.5 kΩ10 kΩ
12 V 77.032 kΩ76.8 kΩ10.2 kΩ
15 V 101.733 kΩ102 kΩ10.5 kΩ
18 V 118.276 kΩ118 kΩ10 kΩ
24 V 164.238 kΩ165 kΩ10.2 kΩ
To achieve higher nominal accuracy, two resistors can be used in the place of R1. Select the two resistor values
such that the sum results in a value as close as possible to the calculated R1value.
There are several alternative ways to set the output voltage. The program pins can be pulled low using external
general-purpose input/output pins (GPIOs), or can be hardwired by the given layout of the printed circuit board
(PCB) to set the ANY-OUT voltage. The TPS7A4701 evaluation module (EVM), available for purchase from the
TI eStore, allows the output voltage to be programmed using jumpers.
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