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Dear Customer,
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Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
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1. General description
The 74AHC132-Q100; 74AHCT132-Q100 is a high-speed Si-gate CMOS de vice and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A.
The 74AHC132-Q100; 74AHCT13 2-Q100 contains four 2-input NAND gates which accept
standard input signals. They can transform slowly changing input signals into sharply
defined, jitter free output signals. The gate switches at different points for positive-going
and negative-going signals. The difference between the positive voltage VT+ and the
negative VT is defined as the hysteresis voltage VH.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
Inputs accept voltages higher tha n V CC
Input levels:
For 74AHC132-Q100: CMOS level
For 74AHCT132-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Multiple package options
74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
Rev. 1 — 8 November 2013 Product data sheet
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 2 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC132D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads;
body width 3.9 mm SOT108-1
74AHCT132D-Q100
74AHC132PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74AHCT132PW-Q100
74AHC132BQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enh anced
very thin quad flat package; no leads;
14 terminals; body 2.5 30.85 mm
SOT762-1
74AHCT132BQ-Q100
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna407
1A
1Y
1
3
1B
2
2A
2Y
4
6
2B
5
3A
3Y
9
8
3B
10
4A
4Y
12
11
4B
13
23
&
1
56
&
4
10 8
&
9
mna408
13 11
&
12
Fig 3. Logic diagram (one S chm itt trigger)
mna409
A
Y
B
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 3 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level.
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14
$+&4
$+&74
$
9&&
%
%
<
$
$
<
%
%
<
$
*1' <
DDD





DDD
$+&4
$+&74
7UDQVSDUHQWWRSYLHZ
< $
% %
*1'

$ <
< $
% %
*1'
<
$
9
&&





WHUPLQDO
LQGH[DUHD
Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A, 4A 1, 4, 9, 12 data input nA
1B, 2B, 3B, 4B 2, 5, 10, 13 data input nB
1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output nY
GND 7 ground (0 V)
VCC 14 supply voltage
Table 3. Function table[1]
Input Output
nA nB nY
LLH
LHH
HLH
HHL
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 4 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: above 70 C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 package: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 package: above 60 C the value of Ptot derates linearly at 4.5 m W/K.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
VIinput voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V [1] 20 - mA
IOK output clamping curre nt VO <0.5 V or VO > VCC + 0.5 V [1] 20 +20 mA
IOoutput current VO =0.5 V to (VCC + 0.5 V) 25 +25 mA
ICC supply current - +75 mA
IGND ground current 75 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 Cto+125C[2] - 500 mW
Table 5. Operating conditio ns
Symbol Parameter Conditions Min Typ Max Unit
74AHC132-Q100
VCC supply voltage 2.0 5.0 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V
VCC = 4.5 V to 5.5 V - - 20 ns/V
74AHCT132-Q100
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC = 4.5 V to 5.5 V - - 20 ns/V
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 5 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 Cto+85C40 Cto+125CUnit
Min Typ Max Min Max Min Max
74AHC132-Q100
VOH HIGH-level
output voltage VI= VT+ or VT
IO=50 A; VCC = 2.0 V 1.9 2.0 - 1.9 2.2 1.9 - V
IO=50 A; VCC = 3.0 V 2.9 3.0 - 2.9 3.15 2.9 - V
IO=50 A; VCC = 4.5 V 4.4 4.5 - 4.4 3.85 4.4 - V
IO=4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V
IO=8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage VI= VT+ or VT
IO=50A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO=50A; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO=50A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO=4.0mA; V
CC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO=8.0mA; V
CC = 4.5 V - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI= 5.5 V or GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 2.0 - 20 - 40 A
CIinput
capacitance VI=V
CC or GND - 3 10 - 10 - 10 pF
COoutput
capacitance -4-----pF
74AHCT132-Q100
VOH HIGH-level
output voltage VI= VT+ or VT; VCC =4.5V
IO=50 A 4.4 4.5 - 4.4 - 4.4 - V
IO=8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage VI= VT+ or VT; VCC =4.5V
IO=50A - 0 0.1 - 0.1 - 0.1 V
IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI= 5.5 V or GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 2.0 - 20 - 40 A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V; other pins
at VCC or GND; IO=0A;
VCC = 4.5 V to 5.5 V
- - 1.35 - 1.5 - 1.5 mA
CIinput
capacitance VI=V
CC or GND - 3 10 - 10 - 10 pF
COoutput
capacitance -4-----pF
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 6 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
10. Dynamic characteristics
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC =5.0V).
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of the outputs.
Table 7. Dynam ic characteristics
Vo ltages are referenced to GND (ground = 0 V); for test circuit, see Figure 7.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
74AHC132-Q100
tpd propagation
delay nA, nB to nY; see Figure 6 [2]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 4.4 11.9 1.0 14.0 1.0 15.0 ns
CL= 50 pF - 6.2 15.4 1.0 17.5 1.0 19.5 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 3.3 7.7 1.0 9.0 1.0 10.0 ns
CL= 50 pF - 4.7 9.7 1.0 11.0 1.0 12.5 ns
CPD power
dissipation
capacitance
fi= 1 MHz; VI=GNDtoV
CC [3] -11- - - - -pF
74AHCT132-Q100
tpd propagation
delay nA, nB to nY; see Figure 6 [2]
VCC = 4.5 V to 5.5 V
CL= 15 pF - 3.5 7.0 1.0 8.0 1.0 9.0 ns
CL= 50 pF - 5.0 8.0 1.0 9.0 1.0 10.0 ns
CPD power
dissipation
capacitance
fi= 1 MHz; VI=GNDtoV
CC [3] -14- - - - -pF
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 7 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Input to output propagation delays
001aaa662
tPHL tPLH
VM
VM
nA, nB input
nY output
GND
VI
VOH
VOL
Table 8. Measurement points
Type Input Output
VMVM
74AHC132-Q100 0.5 VCC 0.5 VCC
74AHCT132-Q100 1.5 V 0.5 VCC
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 8 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 7. Test circuit for measuring switching times
Table 9. Test data
Type Input Load Test
VItr, tfCL
74AHC132-Q100 VCC 3.0 ns 50 pF, 15 pF tPLH, tPHL
74AHCT132-Q100 3.0 V 3.0 ns 50 pF, 15 pF tPLH, tPHL
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 9 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
12. Transfer characteristics
13. Transfer characteristics waveforms
Table 10. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 Cto+85C40 Cto+125CUnit
Min Typ Max Min Max Min Max
74AHC132-Q100
VT+ positive-going threshold
voltage VCC = 3.0 V - - 2.2 - 2.2 - 2.2 V
VCC = 4.5 V - - 3.15 - 3.15 - 3.15 V
VCC = 5.5 V - - 3.85 - 3.85 - 3.85 V
VTnegative-going threshold
voltage VCC = 3.0 V 0.9 - - 0.9 - 0.9 - V
VCC = 4.5 V 1.35 - - 1.35 - 1.35 - V
VCC = 5.5 V 1.65 - - 1.65 - 1.65 - V
VHhysteresis voltage VCC = 3.0 V 0.3 - 1.2 0.3 1.2 0.25 1.2 V
VCC = 4.5 V 0.4 - 1.4 0.4 1.4 0.35 1.4 V
VCC = 5.5 V 0.5 - 1.6 0.5 1.6 0.45 1.6 V
74AHCT132-Q100
VT+ positive-going threshold
voltage VCC = 4.5 V - - 1.9 - 1.9 - 1.9 V
VCC = 5.5 V - - 2.1 - 2.1 - 2.1 V
VTnegative-going threshold
voltage VCC = 4.5 V 0.5 - - 0.5 - 0.5 - V
VCC = 5.5 V 0.6 - - 0.6 - 0.6 - V
VHhysteresis voltage VCC = 4.5 V 0.3 - 1.4 0.3 1.4 0.3 1.4 V
VCC = 5.5 V 0.3 - 1.5 0.3 1.5 0.3 1.5 V
Fig 8. Transfer characteristics Fig 9. De finition of VT+,V
Tand VH
mna207
VO
VI
VHVT+
VT−
mna208
V
O
V
I
V
H
V
T+
V
T−
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 10 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
a. VCC = 3.0 V b. VCC = 4.5 V
c. VCC = 5.5 V
Fig 10. Typica l 74A HC132-Q100 transfer characteristics
001 3
1.5
0.5
1
mna411
2V
I
(V)
I
CC
(mA)
05
VI (V)
ICC
(mA)
5
0
1
mna412
2
3
4
1234
02 6
6
0
2
4
mna413
4V
I
(V)
I
CC
(mA)
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 11 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
14. Application information
a. VCC = 4.5 V. b. VCC = 5.5 V.
Fig 11. Typical 74AHCT132-Q100 transfer characteristics
05
VI (V)
ICC
(mA)
6
0
mna414
2
4
1234
02 6
8
0
2
4
6
mna415
4VI (V)
ICC
(mA)
For 74AHC132-Q100:
For 74AHCT132-Q100:
Fig 12. Rel axation osc ill ator
001aac440
VCC VCC
A
B
Y
R
C
f1
T
---1
0.55 RC
------------------------
=
f1
T
---1
0.60 RC
------------------------
=
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 12 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
15. Package outline
Fig 13. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 13 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
Fig 14. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 14 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
Fig 15. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 15 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
16. Abbreviations
17. Revision history
Table 11. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MIL Military
MM Machine Model
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AHC_AHCT132_Q100 v.1 20131108 Product data sheet - -
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 16 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
18. Legal information
18.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — T his NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, t he product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74AHC_AHCT132_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 8 November 2013 17 of 18
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 November 2013
Document identifier: 74 AHC_AHCT132_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
20. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Transfer characteristics . . . . . . . . . . . . . . . . . . 9
13 Transfer characteristics waveforms. . . . . . . . . 9
14 Application information. . . . . . . . . . . . . . . . . . 11
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
19 Contact information. . . . . . . . . . . . . . . . . . . . . 17
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18