100304
Low Power Quint AND/NAND Gate
General Description
The 100304 is monolithic quint AND/NAND gate. The Func-
tion output is the wire-NOR of all five AND gate outputs. All
inputs have 50 kΩpull-down resistors.
Features
nLow Power Operation
n2000V ESD protection
nPin/function compatible with 100104
nVoltage compensated operating range =−4.2V to −5.7V
nAvailable to industrial grade temperature range
nAvailable to Standard Microcircuit Drawing
(SMD) 5962-9153701
Logic Symbol
Logic EquationF=(D
1a
•D
2a
)+(D
1b
•D
2b
)+D
1c
•D
2c
)+(D
1d
•D
2d
)+(D
1e
•D
2e
).
Pin Names Description
D
na
–D
ne
Data Inputs
F Function Output
O
a
–O
e
Data Outputs
O
a
–O
e
Complementary Data Outputs
DS100304-1
August 1998
100304 Low Power Quint AND/NAND Gate
© 1998 National Semiconductor Corporation DS100304 www.national.com
Connection Diagrams
24-Pin DIP
DS100304-2
24-Pin Quad Cerpak
DS100304-3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above which the useful life may be impaired
Storage Temperature (T
STG
) −65˚C to +150˚C
Maximum Junction Temperature (T
J
)
Ceramic +175˚C
V
EE
Pin Potential to Ground Pin −7.0V to +0.5V
Input Voltage (DC) V
EE
to +0.5V
Output Current (DC Output HIGH) −50 mA
ESD (Note 2) ≥2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Military −55˚C to +125˚C
Supply Voltage (V
EE
) −5.7V to −4.2V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
=−4.2V to −5.7V, V
CC
=V
CCA
=GND, T
C
=−55˚C to +125˚C
Symbol Parameter Min Max Units T
C
Conditions Notes
V
OH
Output HIGH Voltage −1025 −870 mV 0˚C to
+125˚C
−1085 −870 mV −55˚C V
IN
=V
IH
(Max) Loading with (Notes 3, 4, 5)
V
OL
Output LOW Voltage −1830 −1620 mV 0˚C to or V
IL
(Min) 50Ω0 to −2.0V
+125˚C
−1830 −1555 mV −55˚C
V
OHC
Output HIGH Voltage −1035 mV 0˚C to
+125˚C
−1085 mV −55˚C V
IN
=V
IH
(Min) Loading with (Notes 3, 4, 5)
V
OLC
Output LOW Voltage −1610 mV 0˚C to or V
IL
(Max) 50Ωto −2.0V
+125˚C
−1555 mV −55˚C
V
IH
Input HIGH Voltage −1165 −870 mV −55˚C Guaranteed HIGH Signal (Notes 3, 4, 5, 6)
+125˚C for All Inputs
V
IL
Input LOW Voltage −1830 −1475 mV −55˚C to Guaranteed LOW Signal (Notes 3, 4, 5, 6)
+125˚C for All Inputs
I
IL
Input LOW Current 0.50 µA −55˚C to V
EE
=−4.2V (Notes 3, 4, 5)
+125˚C V
IN
=V
IL
(Min)
Input High Current
D
2a
–D
2e
250 µA 0˚C to
D
1a
–D
1e
350 +125˚C V
EE
=−5.7V (Notes 3, 4, 5)
I
IH
V
IN
=V
IH
(Max)
D
2a
–D
2e
350 µA −55˚C
D
1a
–D
1e
500
I
EE
Power Supply Current −75 −25 mA −55˚C to Inputs Open (Notes 3, 4, 5)
+125˚C
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 4: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C, Subgroups, 1, 2 3, 7, and 8.
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.
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AC Electrical Characteristics
V
EE
=−4.2V to −5.7V, V
CC
=V
CCA
=GND
Symbol Parameter T
C
=−55˚C T
C
=+25˚C T
C
=+125˚C Units Conditions Notes
Min Max Min Max Min Max
t
PLH
Propagation Delay 0.30 1.90 0.40 1.80 0.30 2.30 ns
t
PHL
D
na
–D
ne
to O, O (Notes 7, 8, 9)
t
PLH
Propagation Delay 0.80 2.90 0.90 2.80 0.90 3.40 ns
Figures 1, 2
t
PHL
Data to F
t
TLH
Transition Time 0.20 1.80 0.30 1.60 0.20 2.00 ns (Note 10)
t
THL
20%to 80%,80
%to 20%
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures.
Note 8: Screen tested 100%on each device at +25˚C temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each mfg. lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data).
Test Circuitry
DS100304-5
Notes:
VCC,V
CCA =+2V, VEE =−2.5V
L1 and L2 =equal length 50Ωimpedance lines
RT=50Ωterminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ωto GND
CL=Fixture and stray capacitance ≤3pF
FIGURE 1. AC Test Circuit
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Switching Waveforms
DS100304-6
FIGURE 2. Propagation Delay and Transition Times
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Pin Ceramic Dual-In-Line Package (D)
NS Package Number J24E
24-Pin Quad Cerpak (F)
NS Package Number W24B
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VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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100304 Low Power Quint AND/NAND Gate
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
