TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Features Ultra-Low Supply Current: 200 nA per channel Fast Response Time: 13 s Propagation Delay, with 100 mV Overdrive Internal Hysteresis for Clean Switching Offset Voltage: 2.0 mV Maximum Offset Voltage Temperature Drift: 0.3 V/C Input Bias Current: 6 pA Typical Input Common-Mode Range Extends 200 mV Push-Pull Output with 25 mA Drive Capability Output Latch (TP2011N Only) No Phase Reversal for Overdriven Inputs Low Supply Voltage: 1.6V to 5.5V Applications Battery Monitoring / Management Alarm and Monitoring Circuits Peak and Zero-crossing Detectors Threshold Detectors/Discriminators Sensing at Ground or Supply Line Logic Level Shifting or Translation Window Comparators Oscillators and RC Timers Mobile Communications and Notebooks Ultra-Low-Power Systems Descriptions The TP201x family of push-pull output comparators features the world-class lowest nano-power (250nA maximum) and fast 13s response time capability, allowing operation from 1.6V to 5.5V. Input common-mode range beyond supply rails makes the TP201x an ideal choice for power-sensitive, low-voltage (2-cell) applications. The TP201x push-pull output supports rail-to-rail output swing and interfaces with TTL /CMOS logic, and are capable of driving heavy DC or capacitive loads. The internal input hysteresis eliminates output switching due to internal input noise voltage, reducing current draw. The output limits supply current surges and dynamic power consumption while switching. Beyond the rails input and rail-to-rail output characteristics allow the full power-supply voltage to be used for signal range. Micro-sized packages provide options for portable and space-restricted applications. The single (TP2011) is available in SC70-5, and the dual (TP2012) is available in SOT23-8. The related TP2015/6/8 family of comparators from 3PEAK has an open-drain output. Used with a pull-up resistor, these devices can be used as level-shifters for any desired voltage up to 10V and in wired-OR logic. 3PEAK and the 3PEAK logo are registered trademarks of 3PEAK Incorporated. All other trademarks are the property of their respective owners. Related Products DEVICE DESCRIPTION TP2015 /TP2016/TP2018 Ultra-low 200nA, 13s, 1.6V, 2mV VOS-MAX, Internal Hysteresis, RRI, Open-Drain Output Comparators TP1931 /TP1932/TP1934 950ns, 3A, 1.8V, 2.5mV VOS-MAX, Internal Hysteresis, RRI, Push-Pull Output Comparators TP1935 /TP1936/TP1938 950ns, 3A, 1.8V, 2.5mV VOS-MAX, Internal Hysteresis, RRI, Open-Drain Comparators Fast 68ns, Low Power, Internal Hysteresis, Typical Application of TP201x Comparators TP1941/TP1941N 3mV Maximum VOS, - 0.2V to VDD + 0.2V RRI, /TP1942/TP1944 Push-Pull (CMOS/TTL) Output Comparators Fast 68ns, Low Power, Internal Hysteresis, TP1945/TP1945N 3mV Maximum VOS, - 0.2V to VDD + 0.2V RRI, /TP1946/TP1948 Open-Drain Output Comparators www.3peakic.com.cn REV1.2 1 TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Pin Configuration (Top View) Order Information Model Name Order Number Package Transport Media, Quantity Marking Information TP2011-TR 5-Pin SOT23 Tape and Reel, 3000 C1TYW (1) TP2011-CR 5-Pin SC70 Tape and Reel, 3000 C1CYW (1) TP2011-SR 8-Pin SOIC Tape and Reel, 4000 2011S TP2011U-TR 5-Pin SOT23 Tape and Reel, 3000 C1AYW (1) TP2011U-CR 5-Pin SC70 Tape and Reel, 3000 C1BYW (1) TP2011U2 TP2011U2-TR 5-Pin SOT23 Tape and Reel, 3000 C1EYW (1) TP2011N TP2011N-TR 6-Pin SOT23 Tape and Reel, 3000 C1NYW (1) TP2012-TR 8-Pin SOT23 Tape and Reel, 3000 C12YW (1) TP2012-SR 8-Pin SOIC Tape and Reel, 4000 2012S TP2012-VR 8-Pin MSOP Tape and Reel, 3000 2012V TP2014-SR 14-Pin SOIC Tape and Reel, 2500 TP2014S TP2014-TR 14-Pin TSSOP Tape and Reel, 3000 TP2014T TP2011 TP2011U TP2012 TP2014 Note (1): `YW' is date coding scheme. 'Y' stands for calendar year, and 'W' stands for single workweek coding scheme. Pin Functions N/C: No Connection. -IN: Inverting Input of the Comparator. Voltage range of this pin can go from V- - 0.3V to V+ + 0.3V. +IN: Non-Inverting Input of Comparator. This pin has the same voltage range as -IN. V+ (VDD): Positive Power Supply. Typically the voltage is from 1.6V to 5.5V. Split supplies are possible as long as the voltage between V+ and V- is between 1.6V and 5.5V. A bypass capacitor of 0.1F as close to the part as possible should be used between power supply pins or between supply pins and ground. 2 REV1.2 V- (VSS): Negative Power Supply. It is normally tied to ground. It can also be tied to a voltage other than ground as long as the voltage between V+ and V- is from 1.6V to 5.5V. If it is not connected to ground, bypass it with a capacitor of 0.1F as close to the part as possible. OUT: Comparator Output. The voltage range extends to within millivolts of each supply rail. LATCH: Active Low Latch enable. Latch enable threshold is 1/2V+ above negative supply rail. www.3peakic.com.cn TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Absolute Maximum Ratings Note 1 Supply Voltage: V+ - V-....................................6.0V Input Voltage............................. 0.3 Maximum Junction Temperature................... 150C Storage Temperature Range.......... -65C to 150C Output Current: OUT.................................... 25mA Lead Temperature (Soldering, 10 sec) ......... 260C Output Short-Circuit Duration - 0.3 to Note 3............ V+ + Operating Temperature Range.......-40C to 85C Note 2..........................10mA Input Current: +IN, -IN, V- Indefinite Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 500mV beyond the power supply, the input current should be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply voltage and how many amplifiers are shorted. Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces connected to the leads. ESD, Electrostatic Discharge Protection Symbol Parameter Condition Minimum Level Unit HBM Human Body Model ESD ANSI/ESDA/JEDEC JS-001 2 kV CDM Charged Device Model ESD ANSI/ESDA/JEDEC JS-002 1 kV Thermal Information Package RJA RJC(Top) Unit 8-Pin SOP 112.4 64.1 C/W 14-Pin SOP 96.7 46.7 C/W 14-Pin TSSOP 108.1 42.7 C/W www.3peakic.com.cn REV1.2 3 TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Electrical Characteristics The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 27C. VDD = +1.6V to +5.5V, VIN+ = VDD, VIN- = 1.2V, CL =15pF. SYMBOL PARAMETER CONDITIONS MIN VDD Supply Voltage VOS Input Offset Voltage Note 1 VCM = 1.2V -3.0 0.5 +3.0 mV VOS Input Offset Voltage Note 1 VCM = 0V -3.0 0.5 +3.0 mV VOS VOS TC VHYST IB IOS RIN Input Offset Voltage Note 1 Input Offset Voltage Drift Note 1 Input Hysteresis Voltage Note 1 Input Bias Current Input Offset Current Input Resistance VCM = Vdd VCM = 1.2V VCM = 1.2V VCM = 1.2V VCM = 1.2V -4.0 +4.0 mV V/C mV pA pA G CIN Input Capacitance CMRR VCM PSRR VOH VOL ISC IQ tR Common Mode Rejection Ratio Common-mode Input Voltage Range Power Supply Rejection Ratio High-Level Output Voltage Low-Level Output Voltage Output Short-Circuit Current Quiescent Current per Comparator Rising Time 0.5 0.3 4 6 4 > 100 2 4 82 tF Falling Time tPD+ Propagation Delay (Low-to-High) Overdrive=100mV, VIN- =1.2V 13 19 s tPD- Propagation Delay (High-to-Low) Overdrive=100mV, VIN- =1.2V 14 18 s tPD-SKEW Propagation Delay Skew Note 2 Overdrive=100mV, VIN- =1.2V 1 5 s IOUT=-1mA IOUT=1mA Sink or source current MAX UNITS 5.5 V 1.6 2 Differential Common Mode VCM = VSS to VDD TYP 50 V- 60 VDD-0.3 7 pF V+ 90 VSS+0.3 160 25 200 5 250 5 dB V dB V V mA nA ns ns Note 1: The input offset voltage is the average of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points. Note 2: Propagation Delay Skew is defined as: tPDSKEW = tPD+ - tPD-. 4 REV1.2 www.3peakic.com.cn TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Input Offset Voltage vs. Temperature Input Hysteresis Voltage vs. Temperature 5 10 Input Hysteresis Voltage (mV) Input Offset Voltage (mV) Typical Performance Characteristics 2.5 5V 0 1.8V -2.5 -5 -50 VCM=1.2V -25 0 25 50 75 100 8 6 5V 4 2 0 -50 -25 0 TEMPERATURE ( ) 50 75 100 Propagation Delay vs. Temperature 1000 25 800 600 Propagation Delay (s) Quiescent Current (nA) 25 TEMPERATURE ( ) Quiescent Current vs. Temperature 5V 400 200 1.8V VCM=1.2V 0 -50 -25 0 25 50 75 tpd-@VDD =5V t @V =5V pd+ DD 20 15 10 tpd-@VDD =1.8V 5 tpd+@VDD =1.8V VCM=1.2V 0 100 -50 TEMPERATURE ( ) 0 50 100 TEMPERATURE ( ) Propagation Delay Skew vs. Temperature Propagation Delay vs. Overdrive Voltage 100 8 Propagation Delay (s) Propagation Delay Skew (s) 1.8V V CM=1.2V 4 5V 0 -4 1.8V V CM=1.2V -8 -50 60 40 tpd20 tpd+ 0 0 50 TEMPERATURE ( ) www.3peakic.com.cn REV1.2 VDD =5V VCM=2.5V 80 100 10 100 1V Common Mode Voltage (mV) 5 TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Typical Performance Characteristics Propagation Delay Skew vs. Overdrive Voltage Propagation Delay vs. Overdrive Voltage 100 V DD =5V V CM=2.5V 15 10 Propagation Delay (s) Propagation Delay Skew (s) 20 5 0 -5 -10 -15 -20 VDD =1.8V VCM=0.9V 80 60 40 tpd- 20 tpd+ 0 10 100 1V 10 Common Mode Voltage (mV) Propagation Delay Skew vs. Overdrive Voltage 5 10 Input Offset Voltage (mV) V DD =1.8V V CM=0.9V 15 5 0 -5 -10 -15 2.5 0 -2.5 VDD =5V -5 -20 10 100 0 1V 1 Input Offset Voltage vs. Common Mode Voltage 2.5 0 -2.5 VDD =1.8V 0 0.5 1 1.5 Common Mode Voltage (V) REV1.2 3 4 5 Input Hysteresis Voltage vs. Common Mode Voltage Inpur Hysteresis Voltage (mV) Input Offset Voltage (mV) 5 -5 2 Common Mode Voltage (V) Common Mode Voltage (mV) 6 1V Input Offset Voltage vs. Common Mode Voltage 20 Propagation Delay Skew (s) 100 Common Mode Voltage (mV) 2 10 8 6 4 2 VDD =5V 0 0 1 2 3 4 5 Common Mode Voltage (V) www.3peakic.com.cn TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Typical Performance Characteristics Quiescent Current vs. Common Mode Voltage 10 1000 Quiescent Current (nA) Input Hysteresis Voltage (mV) Input Hysteresis Voltage vs. Common Mode Voltage 8 6 4 2 0 800 600 400 200 VDD =1.8V 0 VDD =5V 0 0.5 1 1.5 0 2 1 Quiescent Current vs. Common Mode Voltage Propagation Delay (s) Quiescent Current (nA) 600 400 200 VDD =1.8V 0 5 tpd+ 15 tpd- 10 5 VDD =5V 0 0.5 1 1.5 2 0 1 Common Mode Voltage (V) 2 3 4 5 Common Mode Voltage (V) Propagation Delay vs. Common Mode Voltage Propagation Delay Skew vs. Common Mode Voltage 5 Propagation Delay Skew (s) 20 Propagation Delay (s) 4 20 800 15 tpd+ 10 tpd- 5 0 3 Propagation Delay V.S. Common Mode Voltage 1000 0 2 Common Mode Voltage (V) Common Mode Voltage (V) VDD =1.8V 0 0.5 1 1.5 Common Mode Voltage (V) www.3peakic.com.cn REV1.2 2 2.5 0 -2.5 VDD =5V -5 0 1 2 3 4 5 Common Mode Voltage (V) 7 TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Typical Performance Characteristics Propagation Delay Skew vs. Common Mode Voltage Input Offset Voltage Distribution 60% Percentage of Occurences Propagation Delay Skew (s) 5 2.5 0 -2.5 -5 VDD =1.8V 0 1462 Samples VDD =5V VCM=1.2V 50% 40% 30% 20% 10% 0% 0.5 1 1.5 -6 -5 -4 -3 -2 -1 0 2 40% 60% 1462 Samples VDD =5V VCM=1.2V 40% 30% 20% 10% 0% 0 1 2 3 4 5 6 7 8 30% 20% 15% 10% 5% 160 20% 10% 0% 14 16 18 20 22 Propagation Low to High Delay (s) 8 REV1.2 180 200 220 240 260 24 High to Low Propagation Delay Distribution Percentage of Occurences Percentage of Occurences 30% 12 6 Quiscent Current (nA) 1462 Samples VDD =5V VCM=1.2V 100mV overdrive 40% 5 0% 9 10 11 12 Low to High Propagation Delay Distribution 50% 4 25% 140 60% 3 1462 Samples VDD =5V VCM=1.2V 35% Input Hysteresis Voltage (mV) 70% 2 Quiescent Current Distribution Percentage of Occurences Percentage of Occurences Input Hysteresis Voltage Distribution 50% 1 Input Offset Voltage (mV) Common Mode Voltage (V) 45% 40% 1462 Samples VDD =5V VCM=1.2V 100mV overdrive 35% 30% 25% 20% 15% 10% 5% 0% 10 12 14 16 18 20 22 Propagation High to Low Delay (s) www.3peakic.com.cn TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Typical Performance Characteristics Output Voltage Headroom vs. Output Load Current 5 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% VDD=5V 1462 Samples V DD =5V V CM=1.2V 100mV overdrive Output Voltage (V) Percentage of Occurences Propagation Delay Skew Distribution 4 Sourcing Current 3 2 Sinking Current 1 0 -2 0 2 4 6 8 10 0 5 Propagation Delay Skew (s) 10 15 Output Load Current (mA) Output Voltage Headroom vs. Output Load Current Output Voltage Headroom vs. Supply Voltage 2 400 Output Voltage (mV) Output Voltage (V) VDD =1.8V 1.5 Sourcing Current 1 0.5 Sinking Current 300 VOH 200 100 I OUT=1mA 0 0.0 VOL 0 0.5 1.0 1.5 2.0 Output Load Current (mA) 1 2 3 4 5 Supply Voltage (V) Output Short Current vs. Supply Voltage Short Current (mA) 30 25 20 I sinking 15 10 Isourcing 5 0 1 2 3 4 5 Supply Voltage (V) www.3peakic.com.cn REV1.2 9 TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Operation The TP201x family single-supply comparators feature internal hysteresis, high speed, and low power. Input signal range extends beyond the negative and positive power supplies. The output can even extend all the way to the negative supply. The input stage is active over different ranges of common mode input voltage. Rail-to-rail input voltage range and low-voltage single-supply operation make these devices ideal for portable equipment. Applications Information Inputs The TP201x comparator family uses CMOS transistors at the input which prevent phase inversion when the input pins exceed the supply voltages. Figure 1 shows an input voltage exceeding both supplies with no resulting phase inversion. 6 Vout Voltage (mV) Input Voltage 4 +In 2 -In 1K Core 1K 0 VDD=5V Output Voltage -2 Time (100s/div) Figure 1. Comparator Response to Input Voltage Chip Figure 2. Equivalent Input Structure The electrostatic discharge (ESD) protection input structure of two back-to-back diodes and 1k series resistors are used to limit the differential input voltage applied to the precision input of the comparator by clamping input voltages that exceed supply voltages, as shown in Figure 2. Large differential voltages exceeding the supply voltage should be avoided to prevent damage to the input stage. Internal Hysteresis Most high-speed comparators oscillate in the linear region because of noise or undesired parasitic feedback. This tends to occur when the voltage on one input is at or equal to the voltage on the other input. To counter the parasitic effects and noise, the TP201x implements internal hysteresis. The hysteresis in a comparator creates two trip points: one for the rising input voltage and one for the falling input voltage. The difference between the trip points is the hysteresis. When the comparator's input voltages are equal, the hysteresis effectively causes one comparator input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. Figure 3 illustrates the case where IN- is fixed and IN+ is varied. If the inputs were reversed, the figure would look the same, except the output would be inverted. 10 REV1.2 www.3peakic.com.cn TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Vi Vtr Hysteresis Band Vin- Vtf Vhyst=Vtr-Vtf Vtr+Vtf -V inVos= 2 Time VDD Vi Vtr Vhyst=Vtr-Vtf Vtr+Vtf -V inVos= 2 Hysteresis Band Vin- Vtf Time VDD 0 0 Non-Inverting Comparator Output Inverting Comparator Output Figure 3. Comparator's hysteresis and offset External Hysteresis Greater flexibility in selecting hysteresis is achieved by using external resistors. Hysteresis reduces output chattering when one input is slowly moving past the other. It also helps in systems where it is best not to cycle between high and low states too frequently (e.g., air conditioner thermostatic control). Output chatter also increases the dynamic supply current. Non-Inverting Comparator with Hysteresis A non-inverting comparator with hysteresis requires a two-resistor network, as shown in Figure 4 and a voltage reference (Vr) at the inverting input. Figure 4. Non-Inverting Configuration with Hysteresis When Vi is low, the output is also low. For the output to switch from low to high, Vi must rise up to Vtr. When Vi is high, the output is also high. In order for the comparator to switch back to a low state, Vi must equal Vtf before the non-inverting input V+ is again equal to Vr. Vr R2 R1 R 2 Vtr Vr (VDD Vtf ) Vtr Vtf R1 R 2 R2 R1 R 2 R2 R1 R1 R 2 Vr Vr Vhyst Vtr Vtf www.3peakic.com.cn REV1.2 Vtf R1 R2 VDD R1 R2 VDD 11 TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Inverting Comparator with Hysteresis The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator supply voltage (VDD), as shown in Figure 5. Figure 5. Inverting Configuration with Hysteresis When Vi is greater than V+, the output voltage is low. In this case, the three network resistors can be presented as paralleled resistor R2 || R3 in series with R1. When Vi at the inverting input is less than V+, the output voltage is high. The three network resistors can be represented as R1 ||R3 in series with R2. Vtr Vtf R2 R1 || R 3 R 2 R 2 || R 3 R 2 || R 3 R1 VDD VDD Vhyst Vtr Vtf R1 || R 2 R1 || R 2 R 3 VDD Low Input Bias Current The TP201x family is a CMOS comparator family and features very low input bias current in pA range. The low input bias current allows the comparators to be used in applications with high resistance sources. Care must be taken to minimize PCB Surface Leakage. See below section on "PCB Surface Leakage" for more details. PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5pA of current to flow, which is greater than the TP201x's input bias current at +27C (6pA, typical). It is recommended to use multi-layer PCB layout and route the comparator's -IN and +IN signal under the PCB surface. The effective way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 6 for Inverting configuration application. 1. For Non-Inverting Configuration: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the same reference as the comparator. 12 REV1.2 www.3peakic.com.cn TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators 2. For Inverting Configuration: a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the comparator (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. Figure 6. Example Guard Ring Layout for Inverting Comparator Ground Sensing and Rail to Rail Output The TP201x family implements a rail-to-rail topology that is capable of swinging to within 10mV of either rail. Since the inputs can go 300mV beyond either rail, the comparator can easily perform `true ground' sensing. The maximum output current is a function of total supply voltage. As the supply voltage of the comparator increases, the output current capability also increases. Attention must be paid to keep the junction temperature of the IC below 150C when the output is in continuous short-circuit condition. The output of the amplifier has reverse-biased ESD diodes connected to each supply. The output should not be forced more than 0.5V beyond either supply, otherwise current will flow through these diodes. ESD The TP201x family has reverse-biased ESD protection diodes on all inputs and output. Input and output pins can not be biased more than 300mV beyond either supply rail. Power Supply Layout and Bypass The TP201x family's power supply pin should have a local bypass capacitor (i.e., 0.01F to 0.1F) within 2mm for good high frequency performance. It can also use a bulk capacitor (i.e., 1F or larger) within 100mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. Good ground layout improves performance by decreasing the amount of stray capacitance and noise at the comparator's inputs and outputs. To decrease stray capacitance, minimize PCB lengths and resistor leads, and place external components as close to the comparator' pins as possible. Proper Board Layout The TP201x family is a series of fast-switching, high-speed comparator and requires high-speed layout considerations. For best results, the following layout guidelines should be followed: 1. Use a printed circuit board (PCB) with a good, unbroken low-inductance ground plane. 2. Place a decoupling capacitor (0.1F ceramic, surface-mount capacitor) as close as possible to supply. 3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback around the comparator. Keep inputs away from the output. 4. Solder the device directly to the PCB rather than using a socket. 5. For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less) placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some degradation to propagation delay when the impedance is low. The topside ground plane should be placed between the output and inputs. 6. The ground pin ground trace should run under the device up to the bypass capacitor, thus shielding the inputs from the outputs. www.3peakic.com.cn REV1.2 13 TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators Typical Applications IR Receiver The TP2011 is an ideal candidate to be used as an infrared receiver shown in Figure 7. The infrared photo diode creates a current relative to the amount of infrared light present. The current creates a voltage across RD. When this voltage level cross the voltage applied by the voltage divider to the inverting input, the output transitions. Optional Ro provides additional hysteresis for noise immunity. VDD Ro R1 TP2011 Vo R2 RD Figure 7. IR Receiver Relaxation Oscillator A relaxation oscillator using TP2011 is shown in Figure 8. Resistors R1 and R2 set the bias point at the comparator's inverting input. The period of oscillator is set by the time constant of R4 and C1. The maximum frequency is limited by the large signal propagation delay of the comparator. TP2011's low propagation delay guarantees the high frequency oscillation. If the inverted input (VC1) is lower than the non-inverting input (VA), the output is high which charges C1 through R4 until VC1 is equal to VA. The value of VA at this point is VA1 VDD R 2 R 1 || R 3 R 2 At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is VA2 VDD R 2 || R 3 R 1 R 2 || R 3 If R1=R2=R3, then VA1=2VDD /3, and VA2= VDD/3 The capacitor C1 now discharges through R4, and the voltage VC decreases till it is equal to VA2, at which point the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it takes to discharge C1 from 2VDD/3 to VDD/3. Hence the frequency is: Freq 14 REV1.2 1 2 ln2 R 4 C1 www.3peakic.com.cn TP2011/TP2012/TP2014 Ultra-Low Power 200nA, 1.6V, RRIO, Push-Pull Output Comparators VDD R3 VO R1 T2011 VA VC1 R2 C1 t Vo 2/3VDD R4 VC1 1/3VDD R1=R2=R3 t Figure 8. Relaxation Oscillator Windowed Comparator Figure 9. shows one approach to designing a windowed comparator using a single TP2012 chip. Choose different thresholds by changing the values of R1, R2, and R3. OutA provides an active-low undervoltage indication, and OutB gives an active-low overvoltage indication. ANDing the two outputs provides an active-high, power-good signal. When input voltage Vi reaches the overvoltage threshold VOH, the OutB gets low. Once Vi falls to the undervoltage threshold VUH, the OutA gets low. When VUH