ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The ICS8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.The clock enable isinternally synchronized to eliminate runt pulses on theoutputs during asynchronous assertion/deassertion of the clock enable pin. * 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs Guaranteed output and part-to-part skew characteristics make the ICS8737-11 ideal for clock distribution applications demanding well defined performance and repeatability. * Maximum output frequency: 650MHz * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input * Output skew: 60ps (maximum) * Part-to-part skew: 200ps (maximum) * Bank skew: Bank A - 20ps (maximum), Bank B - 35ps (maximum) * Additive phase jitter, RMS: 0.04ps (typical) * Propagation delay: 1.7ns (maximum) * 3.3V operating supply * 0C to 70C ambient operating temperature * Lead-Free package RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT QA0 nQA0 D CLK_EN QA1 nQA1 Q CLK nCLK PCLK nPCLK CLK_SEL MR 8737AG-11 VEE CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc MR VCC LE 0 /1 1 /2 QB0 nQB0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 QA0 nQA0 VCC QA1 nQA1 QB0 nQB0 VCC QB1 nQB1 ICS8737-11 QB1 nQB1 20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View www.idt.com 1 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1 VEE Power 2 CLK_EN Power 3 CLK_SEL Input 4 CLK Input 5 6 7 8 nCLK PCLK nPCLK nc Input Input Input Unused Description Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pullup No connect. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs QXx to go low and the inver ted outputs 9 MR Input Pulldown nQXx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Power Positive supply pins. 10, 13, 18 VCC 11, 12 nQB1, QB1 Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. 14, 15 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 16, 17 nQA1, QA1 Output 19, 20 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k 8737AG-11 Test Conditions www.idt.com 2 Minimum Typical Maximum Units REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs MR CLK_EN CLK_SEL Selected Source QA0, QA1 nQA0, nQA1 QB0, QB1 nQB0, nQB1 1 X X X LOW HIGH LOW HIGH 0 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH 0 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH 0 1 0 CLK, nCLK Enabled Enabled Enabled Enabled 0 1 1 PCLK, nPCLK Enabled Enabled Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown if Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQA0, nQA1, nQB0, nQB1 QA0, QA1, QB0, QB1 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK or PCLK nCLK or nPCLK QAx nQAx QBx nQBx 0 0 LOW HIGH LOW HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting 1 1 HIGH LOW HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 8737AG-11 www.idt.com 3 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 50 mA Maximum Units TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical VIH CLK_EN, CLK_SEL, MR 2 3.765 V VIL CLK_EN, CLK_SEL, MR -0.3 0.8 V IIH Input High Current 5 A IIL Input Low Current CLK_EN CLK_SEL, MR VIN = VCC = 3.465V VIN = VCC = 3.465V 150 A CLK_EN VIN = 0V, VCC = 3.465V -150 A CLK_SEL,MR VIN = 0V, VCC = 3.465V -5 A TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units nCLK VIN = VCC = 3.465V Test Conditions Minimum Typical 5 A CLK VIN = VCC = 3.465V 150 A nCLK VIN = 0V, VCC = 3.465V -150 A CLK VIN = 0V, VCC = 3.465V -5 A Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. VPP 8737AG-11 www.idt.com 4 1.3 V VCC - 0.85 V REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C Symbol Parameter IIH Test Conditions Minimum Typical VIN = VCC = 3.465V Input High Current VIN = VCC = 3.465V IIL Input Low Current VPP Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 VOH Output High Voltage; NOTE 3 VOL Output Low Voltage; NOTE 3 Maximum Units 150 A 5 A VIN = 0V, VCC = 3.465V -5 A VIN = 0V, VCC = 3.465V -150 A 0.3 1 V VEE + 1.5 VCC V VCC - 1.4 VCC - 0.9 V VCC - 2.0 VCC - 1.7 V 1.0 V VSWING Peak-to-Peak Output Voltage Swing 0.65 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units 650 MHz 1.3 1.7 ns 1.2 1.6 ns 60 ps 20 ps 35 ps 200 ps fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(b) Bank Skew; NOTE 4 t sk(pp) tR Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 5 Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps 52 % tjit CLK, nCLK 650MHz PCLK, nPCLK Bank A Bank B 0.04 odc Output Duty Cycle 48 50 All parameters measured at 500MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Driving only one input clock. 8737AG-11 www.idt.com 5 ps REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 Input/Output Additive Phase Jitter at 155.52MHz -10 -20 = 0.04ps typical -30 -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 8737AG-11 vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.idt.com 6 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V V CC VCC Qx SCOPE nCLK, nPCLK V LVPECL VEE -1.3V 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 nQx nQx Qx Qx PART 2 nQy nQy Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK, nPCLK CLK, PCLK nQAx, nQBx QAx, QBx CMR CLK, PCLK nQx VEE V Cross Points PP 80% 80% VSW I N G Clock Outputs 20% 20% tR tF tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY nQAx, nQBx QAx, QBx Pulse Width t odc = PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8737AG-11 www.idt.com 7 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K CLK_IN + V_REF C1 0.1uF - R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50 125 FOUT FIN Zo = 50 Zo = 50 FOUT 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o FIN 50 Zo = 50 VCC - 2V RTT 84 FIGURE 3A. LVPECL OUTPUT TERMINATION 8737AG-11 125 84 FIGURE 3B. LVPECL OUTPUT TERMINATION www.idt.com 8 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 LVPECL HiPerClockS Input R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. CLK/nCLK INPUT DRIVEN BY LVHSTL DRIVER FIGURE 4B. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V Zo = 50 Ohm R3 125 3.3V R4 125 Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 4C. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 4D. CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 4E. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE 8737AG-11 www.idt.com 9 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR LVPECL CLOCK INPUT INTERFACE are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here 2.5V 3.3V 3.3V 3.3V CML Zo = 50 Ohm R1 50 3.3V 2.5V R2 50 SSTL Zo = 60 Ohm R3 120 R4 120 PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 5A. PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER FIGURE 5B. PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 3.3V 3.3V 3.3V 3.3V HiPerClockS PCLK/nPCLK R2 120 3.3V R3 125 Zo = 50 Ohm 3.3V R4 125 Zo = 50 Ohm C1 LVDS R3 1K R4 1K PCLK PCLK R5 100 Zo = 50 Ohm nPCLK LVPECL R1 84 C2 nPCLK Zo = 50 Ohm HiPerClockS Input R1 1K R2 84 FIGURE 5C. PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER HiPerClockS PCL K/n PC LK R2 1K FIGURE 5D. PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 5E. PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 8737AG-11 www.idt.com 10 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8737-11. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8737-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 50mA = 173.25mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120mW = 293.25mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.293W * 66.6C/W = 89.5C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 20-PIN TSSOP, FORCED CONVECTION by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5C/W 73.2C/W 98.0C/W 66.6C/W 88.0C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8737AG-11 www.idt.com 11 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CC * For logic high, VOUT = V OH_MAX (V CC_MAX * -V OH_MAX OL_MAX CC_MAX CC_MAX - 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CC_MAX - 1.7V ) = 1.7V -V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX - (V CC_MAX - 2V))/R ] * (V -V ) = [(2V - (V -V -V ) = [(2V - (V -V CC_MAX L OH_MAX CC_MAX OH_MAX ))/R ] * (V [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V OL_MAX - (V CC_MAX - 2V))/R ] * (V L CC_MAX OL_MAX CC_MAX [(2V - 1.7V)/50] * 1.7V = 10.2mW OL_MAX CC_MAX L ))/R ] * (V L CC_MAX -V OH_MAX -V OL_MAX )= )= Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8737AG-11 www.idt.com 12 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5C/W 73.2C/W 98.0C/W 66.6C/W 88.0C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8737-11 is: 510 8737AG-11 www.idt.com 13 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 8737AG-11 www.idt.com 14 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8737AG-11 ICS8737AG-11 20 lead TSSOP tube 0C to 70C 8737AG-11T ICS8737AG-11 20 lead TSSOP 2500 tape & reel 0C to 70C 8737AG-11LF ICS8737AG11L 20 lead "Lead-Free" TSSOP tube 0C to 70C 8737AG-11LFT ICS8737AG11L 20 lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 8737AG-11 www.idt.com 15 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR REVISION HISTORY SHEET Rev Table Page Description of Change Date A 3 Updated Figure 1, CLK_EN Timing Diagram. 10/17/01 A 3 Revised Figure 1, CLK_EN Timing Diagram. 10/31/01 A 8 2 6 Added Termination for LVPECL Outputs section. Pin Description Table - revised MR description. 3.3V Output Load Test Circuit Diagram, revised VEE equation from "-1.3V 0.135V" to " -1.3V 0.165V". Revised Output Rise/Fall Time Diagram. Pin Description Table - revised MR description. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings, updated Output rating. AC Characteristics Table - added Additive Phase Jitter. Added Additive Phase Jitter Section. Updated LVPECL Output Termination drawings. Added Differential Clock Input Interface section. Added LVPECL Clock Input Interface section. Updated format throughout the data sheet. Added Lead-Free bullet to Features section. Added Lead-Free marking to Ordering Information table. Features Section - deleted bullet, "Industrial temperature information available upon request." Ordering Information Table - added Lead-Free note. LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to VCC - 0.9V; and VSWING max. from 0.9V to 1.0V. Power Considerations - corrected power dissipation to reflect VOH max in Table 4D. Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. 1 A T1 T2 T5 B B T9 7 2 2 4 5 6 8 9 10 1 15 1 B T9 T4D C C 8737AG-11 T9 15 5 11 - 12 15 17 www.idt.com 16 6/3/02 8/19/02 2/3/04 2/10/05 3/18/05 4/13/07 8/9/10 REV. C AUGUST 9, 2010 ICS8737-11 /2 LOW SKEW, /1// DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR We've Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales Tech Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 netcom@idt.com (c) 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8737AG-11 www.idt.com 17 REV. C AUGUST 9, 2010