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ICS8737-11
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8737-11 is a low skew, high performance
Differential-to-3.3V LVPECL Clock Generator/Divider. The
ICS8737-11 has two selectable clock inputs. The CLK, nCLK
pair can accept most standard differential input levels. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels.The clock enable isinternally synchronized to
eliminate runt pulses on theoutputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8737-11 ideal for clock distribution applications
demanding well defined performance and repeatability.
FEATURES
•2 divide by 1 differential 3.3V LVPECL outputs;
2 divide by 2 differential 3.3V LVPECL outputs
•Selectable differential CLK, nCLK or LVPECL clock inputs
•CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•Maximum output frequency: 650MHz
•Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
•Output skew: 60ps (maximum)
•Part-to-part skew: 200ps (maximum)
•Bank skew: Bank A - 20ps (maximum),
Bank B - 35ps (maximum)
•Additive phase jitter, RMS: 0.04ps (typical)
•Propagation delay: 1.7ns (maximum)
•3.3V operating supply
•0°C to 70°C ambient operating temperature
•Lead-Free package RoHS compliant
BLOCK DIAGRAM PIN ASSIGNMENT
ICS8737-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
VEE
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
MR
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
QA0
nQA0
VCC
QA1
nQA1
QB0
nQB0
VCC
QB1
nQB1
QA0
nQA0
QA1
nQA1
÷1
÷2
D
Q
LE
CLK_EN
CLK
nCLK
PCLK
nPCLK
MR
QB0
nQB0
QB1
nQB1
CLK_SEL
0
1
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
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C
NI
ecnaticapaCtupnI 4Fp
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PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
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1V
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2NE_KLCrewoPpulluP
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.
hgihdecroferastuptuoQn,woldecroferastuptuoQ,WOLnehW
.slevelecafretniLTTVL/SOMCVL
3LES_KLCtupnInwodlluP .stu
pniKLCPn,KLCPstceles,HGIHnehW.tupnitceleSkcolC
.slevelecafretniLTTVL/SOMCVL.stupniKLCn,KLCstceles,WOLn
ehW
4KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
5KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
6KLCPtu
pnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN
7KLCPntupnIpulluP.tupnikcolcLCEPVLlaitnereffidgnitrevn
I
8cndesunU.tcennocoN
9RMtupnInwodlluP
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stuptuodetrevnie
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n
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81,31,01V
CC
rewoP.snipylppusevitisoP
21,111BQ,1BQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
51,410BQ,0BQntuptuO.
slevelecafretniLCEPVL.riaptuptuolaitnereffiD
71,611AQ,1AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnere
ffiD
02,910AQ,0AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
:ETON pulluP dna nwodlluP .seulavlacipyt
rof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
RMNE_KLCLES_KLCecruoSdetceleS1AQ,0AQ1AQn,0AQn1BQ,0BQ1BQn,0BQn
1X X X WOLHGIHWOLHGIH
00 0 KLCn,KLCWOL;delbasiDHGIH;d
elbasiDWOL;delbasiDHGIH;delbasiD
00 1 KLCPn,KLCPWOL;delbasiDHGIH;delbasiDWOL;delbasiDHGIH;delbasiD
01 0 KLCn,KLCdelbanEde
lbanEdelbanEdelbanE
01 1 KLCPn,KLCPdelbanEdelbanEdelbanEdelbanE
egdekcolctupnignillafdnagnisiragniwollofdelbanerod
elbasiderastuptuokcolceht,sehctiwsNE_KLCretfA
.1erugiFfinwohssa
debircsedsastupniKLCPn,KLCPdnaKLCn,KLCe
htfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
.B3elbaTni
stupnIstuptuO edoMtuptuOottupnIytiraloP
KLCProKLCKLCPnroKLCnxAQxAQnxBQxBQn
00WOLHGIHWOLHGIHlaitnereffiDotlaitnereffiDg
nitrevnInoN
11HGIHWOLHGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHWOLHGIHlaitnereffiDotdednEelg
niSgnitrevnInoN
11ETON;desaiBHGIHWOLHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
1ETON;desaiB0HGIHWOLHGIHWOLlaitneref
fiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHWOLHGIHlaitnereffiDotdednEelgniSgnitrevnI
."sleveLdednEelgniStpec
cAottupnIlaitnereffiDehtgniriW",noitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON
Enabled
Disabled
FIGURE 1. CLK_EN TIMING DIAGRAM
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQA0, nQA1,
nQB0, nQB1
QA0, QA1,
QB0, QB1
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
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I
EE
tnerruCylppuSrewoP 05Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
RM,LES_KLC,NE_KLC2567.3V
V
LI
RM,LES_KLC,NE_KLC 3.0-8.0V
I
HI
tnerruChgiHtupnI NE_KLCV
NI
V=
CC
V564.3=5Aµ
RM,LES_KLCV
NI
V=
CC
V564.3=051Aµ
I
LI
tnerruCwoLtupnI NE_KLCV
NI
V,V0=
CC
V564.3=051-Aµ
RM,LES_KLCV
NI
V,V0=
CC
V564.3=5-Aµ
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCnV
NI
V=
CC
V564.3=5Aµ
KLCV
NI
V=
CC
V564.3=051Aµ
I
LI
tnerruCwoLtupnI KLCnV
NI
V,V0=
CC
V564.3=051-Aµ
KLCV
NI
V,V0=
CC
V564.3=5-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
;egatloVtupnIedoMnommoC
2,1ETON V
EE
5.0+V
CC
58.0-V
snoitacilppadedneelgnisroF:1ETON ,VsiKLCn,KLCrofegatlovtupnimumixameht
CC
.V3.0+
siegatlovedomnommoC:2ETONVsadenifed
HI
.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA 73.2°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
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t)o(ks4,2ETON;wekStuptuO 06sp
t)b(ks4ETON;wekSk
naB AknaB02sp
BknaB53sp
t)pp(ks4,3ETON;wekStraP-ot-traP 002sp
ttij otrefer;SMR,rettiJesahPevitiddAreffuB
5ETON,noi
tceSrettiJesahPevitiddA 40.0sp
t
R
emiTesiRtuptuOzHM05@%08ot%02003007sp
t
F
emiTllaFtuptuOzHM05@%08ot%02003007sp
cdoelcyCytuDtuptuO 840525%
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lA
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.tniopgnisso
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.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
s
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derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
.stniopssorclaitnereffidehtta
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
.kcolctupnienoylnognivirD:5ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI V
NI
V=
CC
V564.3=051Aµ
V
NI
V=
CC
V564.3=5Aµ
I
LI
tnerruCwoLtupnI V
NI
V,V0=
CC
V564.3=5-Aµ
V
NI
V,V0=
CC
V564.3=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 3.01V
V
RMC
2,1ETON;egatloVtupnIedoMnommoCV
EE
5.1+V
CC
V
V
HO
3ETON;egatloVhgiHtuptuOV
CC
4.1-V
CC
9.0-V
V
LO
3ETON;egatloVwoLtuptuOV
CC
0.2-V
CC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP 56.00.1V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.
VsiKLCPn,KLCProfegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
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CC
.V2-
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ADDITIVE PHASE JITTER
Input/Output Additive
Phase Jitter at 155.52MHz
= 0.04ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100 1k 10k 100k 1M 10M 100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
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PARAMETER MEASUREMENT INFORMATION
PART-TO-PART SKEW
PROPAGATION DELAY OUTPUT RISE/FALL TIME
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
SCOPE
Qx
nQx
LVPECL
2V
-1.3V ± 0.165V
V
CMR
Cross Points
V
PP
VCC
VEE
CLK,
PCLK
nCLK,
nPCLK
tsk(o)
nQx
Qx
nQy
Qy
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
Pulse Width
tPERIOD
tPW
tPERIOD
odc =
QAx,
QBx
nQAx,
nQBx
t
PD
CLK,
PCLK
nCLK,
nPCLK
QAx,
QBx
nQAx,
nQBx
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
VCC
VEE
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
R2
1K
VCC
CLK_IN +
-
R1
1K
C1
0.1uF
V_REF
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Zo = 50Ω
Zo = 50Ω
FOUT FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
FIGURE 4C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4E show
interface examples for the CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
FIGURE 4A. CLK/nCLK INPUT DRIVEN BY
LVHSTL DRIVER
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for LVHSTL
drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 4E. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
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LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 5A to 5E show interface
examples for the PCLK/nPCLK input driven by the most
common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use
their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver
termination requirements.
FIGURE 5A. PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 5B. PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 5C. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 5D. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
FIGURE 5E. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PCLK/nPCLK
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8737-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8737-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 50mA = 173.25mW
•Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120mW = 293.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.293W * 66.6°C/W = 89.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6. THERMAL RESISTANCE θθ
θθ
θJA FOR 20-PIN TSSOP, FORCED CONVECTION
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3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 6.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CC
- 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX - VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCC_MAX
– 1.7V
(VCC_MAX - VOL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX
))/R
L
] * (VCC_MAX
- VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX
))/R
L
] * (VCC_MAX
- VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
VOUT
VCC
RL
50
VCC - 2V
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RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8737-11 is: 510
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N02
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
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1E03.405.4
eCISAB56.0
L5
4.057.0
α°0°8
aaa--01.0
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TABLE 9. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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We’ve Got Your Timing Solution.
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© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
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