16-bit FCT Ground Bounce Cypress 16-bit FCT Logic Has Low Ground and VCC Bounce Introduction This application note explains what ground bounce is, what causes it, how it is specified, and what systems level problems it may cause. Data taken on Cypress 8-bit and 16-bit FCT products in various packages is presented. VCC What is Ground Bounce? It's Noise. Ground bounce is the temporary increase in the voltage reference potential, usually ground, of an Integrated Circuit (IC). Ground bounce is also called "simultaneous switching noise" and "delta i noise". It has been around for years, but has caused increased concerns since the introduction of the FACT logic family by Fairchild in 1987 (now FACT from National). Fairchild put very fast CMOS logic with rail-to-rail outputs into industry standard (7400) pinouts and customers began having trouble making their boards work. Lp + i As illustrated in Figure 1, the voltage, VL, developed across the ground lead inductance (Lg) is opposite to the rate of change of the current (di/dt) through it. This causes two problems. (1) the input threshold voltage is increased by this amount, and (2), the output voltage, Vout, of an output that is LOW and not switching is also temporarily increased by this amount. Ground and VCC bounce are specified and measured on a per package basis. Cypress supports the test methodology described in military standard 883, DESC Form 193A. Test Circuit The test circuit of Figure 2 is used for all measurements. The load is a 50 pF capacitor in parallel with a 500 resistor to ground. The resistor is implemented as a 450 resistor and a 50 resistor in series, so that the 50 resistor matches the input impedance of the oscilloscope used to monitor the output of the DUT (Device Under Test). Cypress Semiconductor Corporation * R Lg B - Q = CVout Vout i= dV dQ = C out dt dt VL = -L g di dt The threshold increase may cause storage elements to "change ones to zeros," or the outputs of gates to glitch low. The noise problem on the outputs cannot be eliminated, but it can be controlled. How are Ground Bounce and VCC Bounce Specified and Measured? Vout C + VL - What Causes Ground Bounce? Ground bounce is caused by several outputs simultaneously switching from HIGH to LOW. The voltage developed across the parasitic inductance of the (single) ground return connection (pin) of the IC causes a transient voltage increase in the ground reference of the IC with respect to the system ground. A = -LgC d 2Vout dt 2 Figure 1. Simplified Model Ground and VCC bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of induced noise, on that output, caused by other simultaneously switching outputs. The measurements are made at the output pin (node A, Figure 1), using a ground reference that is physically close to the DUT (node B, Figure 1). Ground Bounce Test Procedure The device is conditioned such that N-1 of N outputs are at the VOH state and one output is at the VOL state. The inputs are then switched, with signals having a skew of less than 250 ps, such that the N-1 outputs at VOH transition from VOH to VOL, and the output at VOL does not change. The values of VOLP and VOLV are measured with respect to ground (See Figure 3.) Both are caused by the inductance of the ground lead. 3901 North First Street * San Jose * CA 95134 * 408-943-2600 September 1996 16-bit FCT Ground Bounce Output 1 50pF DUT Voltage 2.4 V OH 500 N IH = V OH - V IH = 0.4V Output 2 50pF 500 Output N 50pF V IH 2 VT 1.5 V IL 0.8 500 N IL = V IL - V OL = 0.4V V OL 0.4 Figure 2. Load Circuit 0 Figure 4. TTL Compatible Voltage Levels V OH V OH TTL Levels and Noise Margins Other Outputs V OLP V OL Quiet Output V OL V OLV Figure 4 illustrates the TTL levels and noise margins. In theory, the voltage threshold for TTL compatible products, VT, can lie anywhere between VIL and VIH. In real world products, it is located very precisely at 1.5V. If the width of the VOLP pulse is several nanoseconds wide at the 1.5V amplitude point, it may either trigger a flip-flop or latch (if connected to the clock input), or cause a glitch on the output of a gate or buffer (if connected to its input). V OHP V OH V OHV In a similar manner, if the width of the VOHV pulse is several nanoseconds wide at the 1.5V points, after it subtracts from the VOH level, it may cause identical problems. However, this scenario is fairly unlikely (for Cypress FCT), because the VOH voltage level is not the minimum 2.4 Volts, but is VCC minus an n-channel (NMOS) transistor threshold (typically 0.8V, worst case 1V), or approximately four volts. Under heavy DC loads (e.g., 10 mA or more) the VOH may be further reduced by 100mV due to the transistor body effect. Figure 3. Ground and VCC Bounce VCC Bounce Test Procedure The device is conditioned such that N-1 of N outputs are at the VOL state and one output is at the VOH state. The inputs are then switched, with signals having a skew of less than 250 ps, such that the N-1 outputs at VOL transition from VOL to VOH, and the output at VOH does not change. The values of VOHP and VOHV are measured with respect to VOH. Both are caused by the inductance of the VCC lead. Test Results for High Drive Buffers Test results for high drive (64/-32 mA) 244 type devices are summarized in Table 1. Only VOLP and VOHV are tabulated, as they decrease the dynamic noise margins. The improved performance (i.e., lower noise) of the 16-bit products in the 48-lead package is due to the lower lead inductance and eight ground and four VCC leads. Noise Margins There will always be noise generated in digital systems when signals switch. It is the responsibility of the system designer to accurately predict the noise under worst case conditions and to design the system such that the noise will not cause the system to malfunction. Today the process is called signal integrity analysis. A little thought will convince the reader that VOLP reduces the dynamic LOW level noise immunity, and that VOHV reduces the dynamic HIGH level noise immunity. VOLV does not cause secondary effects until it forward biases the input clamping diodes to ground (-0.8V). VOHP does not cause problems until it either reaches a diode drop above VCC (if there are clamping diodes from output pins to VCC; which are not in Cypress FCT), or reaches a voltage high enough to cause an avalanche breakdown (20V, which is highly unlikely). Multiple grounds also significantly reduce the transient threshold increase phenomenon, as well as ground and VCC bounce. All Cypress FCT products use edge rate control to reduce noise. Table 1. Ground and VCC Bounce, in Volts Ta = 25 Celsius, VCC = 5V. Parameter 2 48-lead (16-bit) 20 lead (8-bit) TSSOP SSOP SOIC QSOP VOLP 0.57 0.538 0.9 0.7 VOHV -0.33 -0.575 -0.5 -0.3 16-bit FCT Ground Bounce Interpretation of Table 1 Data The first point to note is that none of the VOHV values are large enough to cause the output voltage to drop to the 1.5V level, even if VOH is 2.4V. A second observation is the improved performance of the 48-lead packages (vs 20-lead packages), primarily due to the additional power and ground leads. There is a 330-mV (37%) reduction in VOLP noise when comparing the 20-lead SOIC with the 48-lead TSSOP. The sum of (the absolute values of) VOLP and VOHV is a measure of the "quietness" of the package. The TSSOP is 500mV (36%) quieter than the SOIC. And Then There is Hysteresis... Hysteresis reduces the effects of ground bounce and VCC bounce by increasing the threshold during a LOW to HIGH transition of the input signal and decreasing the threshold during a HIGH to LOW transition of the input signal. This is illustrated graphically in Figure 5. The wide dashed line illustrates the transfer function of a logic inversion without hysteresis. The solid lines and rectangle show the same function with hysteresis. All FCT inputs have 100 mV of hysteresis, or 50 mV in each direction. This translates into 50 mV of additional noise immunity in each direction. Real World Noise Budget For example, the amplitude of the VOLP pulse for the 48-lead TSSOP is 0.57V. This appears to be 0.57V - 0.4V=0.17V greater than the low-level noise immunity. However, in reality, the threshold voltage is 1.5V + 0.05V = 1.55V. So 1.55V - 0.57V = 0.98V of noise immunity remains. The amplitude of the VOHV pulse for the 48-lead TSSOP is -0.33V. If VOH is 2.4V, the voltage level becomes 2.4V - 0.44V = 2.07V, which is 70 mV above the minimum TTL specification. However, in reality, the threshold voltage is 1.5V - 0.05V = 1.45V, and the VOH level is 4V. So 4V - 0.33V = 3.67V - 1.45 V= 2.22V of noise immunity remains. Test Results for 16-bit Latches and Buffers in SSOP Test results for high drive and balanced drive 373 type latches in the SSOP are summarized in Table 2. The ground bounce of the balanced drive device is seen to be 0.681V-0.513V=0.168V less than that of the high drive device. This is a 25% noise reduction. Adding VOLP and VOHV (absolute value) shows that the balanced drive device is 180 mV quieter. This is a 15% noise reduction. Table 2. Ground and VCC Bounce, in Volts, 16-bit, 373 FCT, in SSOP. Ta = 25 Celsius, VCC = 5V. Parameter CY16373 (high drive) CY162373 (balanced) VOLP 0.681 0.513 VOLV -0.694 -0.556 VOHP 0.413 0.344 VOHV -0.500 -0.488 Balanced drive devices are recommended in all applications except for driving heavily capacitively loaded backplanes where incident wave switching is required. Test results for high drive and balanced drive 244 type buffers in the SSOP are summarized in Table 3. Table 3. Ground and VCC Bounce, in Volts, 16-bit, 244 FCT, in SSOP. Ta = 25 Celsius, VCC = 5V. Parameter CY16244 (high drive) CY162244 (balanced) VOLP 0.538 0.463 VOLV -0.781 -0.506 VOHP 0.406 0.388 VOHV -0.575 -0.463 V OH The ground bounce of the balanced drive device is 75 mV less than that of the high drive device. This is a 14% noise reduction. Vout Adding VOLP and VOHV (absolute value) shows that the balanced drive device is 190 mV quieter. This is a 17% noise reduction. V T = 1.5V V OL Vh = 50mV V T - Vh V T V T + Vh Vin in Volts Summary The combination of hysteresis, balanced drive, internal edge control, low power CMOS, and the 48-lead TSSOP significantly reduce system noise and increase package density without decreasing speed or wasting power. FCT logic devices from Cypress at competitive prices give your products the edge. Figure 5. FCT Hysteresis (c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.