16-bit FCT Ground Bounce
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 1996
Cypress 16-bit FCT Logic Has Low Ground and VCC Bounce
Introduction
This application note explains what ground bounce is, what
causes it, how it is specified, and what systems level prob-
lems it may cause. Data taken on Cypress 8-bit and 16-bit
FCT product s in various packages is presented.
What is Ground Bounce? It’ s Noise.
Ground bounce is the temporary increase in the v oltage ref-
erenc e p oten tial, usually ground, of an Integrated Circuit (IC ).
Ground boun ce is also c a lled “simultaneous switching noise”
and “delta i noise”. It has been around for years, but has
caused increased concerns since the introduction of the
FACT logic famil y by Fair chi ld in 1987 (now FACT from Na-
tional). Fairchild put very fast CMOS logic with rail-to-rail
outputs into indust ry st andard (7400) pinouts and customers
began having tro uble making their boards work.
What Causes Ground Bounce?
Ground bounce is caused by several outputs simultaneously
switching from HIGH to LOW. The voltage developed across
the paras itic inductance of the (s ingle) ground return connec-
tion (pin) of the IC causes a t ransient volta ge increase in the
groun d reference of the IC wi th respec t to the sys tem ground.
As illustr ated in
Figure 1
, the voltage, VL, developed across
the ground lead inductance (Lg) is opposite to the rate of
change of the curren t (di/dt) through it. This causes two prob-
lems. (1) the input threshold voltage is increased by this
amount, and (2), the output voltage, Vout, of an output that is
LOW and not sw itching is also temporar ily i ncr eased by thi s
amount.
The threshold increase may cause storage elements to
“change ones to zer os,” or the out puts of gate s to glitch low.
The noise problem on the outp uts cannot be eliminated, but
it can be controlled.
How are Ground Bounce and VCC Bounce
Specified and Measured?
Ground and VCC bounce are specified and measured on a
per package basis. Cypress supports the test methodology
described in military standard 883, DESC Form 193A.
Test Circuit
The test circuit of
Figure 2
is used for all measurements. Th e
load is a 50 pF capacitor in parallel with a 500Ω resistor to
ground. The resistor is implemented a s a 450Ω r e sist or a nd
a 50Ω resistor in series, so that the 50Ω resistor matc hes the
input impedance of the oscilloscope used to m onitor the out-
put of the DUT (Device Under Test).
Ground and VCC bounce tests are performed on a
non-switching (quiescent) output and are used to measure
the magnitude of induced noise, on that output, caused by
other simultaneously switching outputs. The measurements
are made at the output pin (node A,
Figure 1
), using a ground
reference that is physically close to the DUT (node B,
Figure
1
).
Ground Bounce Test Procedure
The device is conditioned such that N-1 of N outputs are at
the VOH state an d one output is at the VOL state. The inputs
are then switched, with signals having a skew of less than 250
ps, such that t he N–1 outputs at VOH t ransitio n from VOH to
VOL, and the output at VOL does n ot change. The values of
VOLP and VOLV are measured with respect to ground (See
Figure 3
.) Both are caused by the induct ance of the gr ou nd
lead.
Figure 1. Simplified Model
i
VCC
+
–Lg
CR
+
–
VL
Vout
A
Lp
Q
=
CV
out
i
=
dQ
dt
=
CdV
out
dt
V
L
=
–L
g
di
dt
=
–L
g
Cd
2
V
out
dt
2
V
out
B
16-bit FCT Ground Bounce
2
VCC Bounce Test Pro cedure
The device is c onditioned such that N−1 of N outputs are at
the VOL state and one output is at the VOH state. T he input s
are then switched, with signals having a skew of less than 250
ps, such that the N−1 outputs at VOL transition from VOL to
VOH, and the output at VOH does n ot change. The values of
VOHP and VOHV are measured wit h respect to VOH. Both are
caused by the inductance of t he VCC lead.
Noise Margins
There will always b e noise generated in digital s ystems when
signals switch. It i s the responsibility of the system designer
to accurately predict the noise under worst case conditions
and to d esign the sy st em such that t he noise will not cause
the system to malfunct ion. Today the process is called signal
integrity analysis. A little tho ught will convinc e the reader that
VOLP reduces the dynamic LOW level noise immunity, and
that VOHV reduces the dynamic HIGH level noise immunity.
VOLV does not cause secon dary effects until it forward biases
the input clamping diodes to ground (−0 .8V). VOHP doe s not
cause problems until it either reaches a diode drop above
VCC (if there are clamping diodes from output pins to VCC;
which are not in Cypress FCT), or reaches a voltage high
enough to cause an avalanche breakdown (20V, which is
highly unlikely).
TTL Levels and Noise Margins
Figure 4
illustrates the TTL levels and noise margi ns.
In theory, the voltage threshold for TTL compatible products,
VT, can lie anywhere between V IL and VIH. In real world prod-
ucts, it is located v ery precisely at 1.5V. If the widt h of the
VOLP pulse is several nanoseconds wide at the 1.5V ampli-
tude point, it may either trigger a flip-flop or la tch ( if con nected
to the cloc k input), or cause a glitch on the output of a gate or
buffer (if connected t o it s input).
In a similar manner, if the widt h of the VOHV pulse is s everal
nanoseconds wide at the 1.5V points, after it su bt racts fr om
the VOH level, it may caus e id en tical problems. However, this
scen ario is fairly unlikely (for Cypress FCT), because the VOH
voltage level is not the minimum 2.4 Volts, but is VCC minus
an n-channel (NMOS) transistor threshold (typically 0.8V,
wors t case 1V), or approximately four volts. Under heavy DC
loads (e.g., 10 mA or more) the VOH may be furth er r e duce d
by 100mV due to the transistor body effect.
Test Res ults for High Drive Buff ers
Test results for high drive (64/–32 mA) 244 type devices are
summariz ed i n
Tab le 1
. Only V OLP and VOHV are t abulate d,
as they decrease the dynamic noise margins. The improved
performance (i.e., lower noise) of the 16-bit products in the
48-lead package is due to the lower lead inductance and eight
ground and four VCC leads.
Multiple grounds also significantly reduce the transient
threshold increase phenomenon, as well as ground and VCC
bounce. All Cypress FCT products use edge rate contr ol to
reduce noise.
Figure 2. Load Cir cui t
Figure 3. Ground and VCC Bounce
DUT
Output 1
Output 2
Output N
50pF
50pF
50pF
500Ω
500Ω
500Ω
Other Outputs
Quiet Output VOHP
VOHV
VOLP
VOLV
VOL VOH
VOL
VOH
VOH Figure 4. TTL Compatible Voltage Levels
Table 1. Ground and VCC Bounce, in Volts
Ta = 25 Celsius, VCC = 5V.
Parameter 48-lead (16-bit) 20 lead (8-bit)
TSSOP SSOP SOIC QSOP
VOLP 0.57 0.538 0.9 0.7
VOHV –0.33 –0.575 –0.5 –0.3
VT
VOH
VIH
VIL
VOL
2.4
2
1.5
0.8
0.4
0
Voltage
NIH =V
OH −VIH
NIL =V
IL −VOL
=0.4V
=0.4V
16-bit FCT Ground Bounce
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor does it convey or im ply an y li cense under patent or other rights . Cypress Semicondu ctor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Interpretation of
Table 1
Data
The fi rst point to note is that non e of the VOHV values are large
enough to cause the output voltage to drop to the 1.5V level,
even if VOH is 2.4V.
A second observation is the improved performance of the
48-lead pac kages (vs 20-lead packages), primarily du e to the
additional power and ground leads. There is a 330-mV (37%)
reduct ion in VOLP noise when compari ng the 20-l e ad SOIC
with the 48-lead TSSOP.
The sum of (the abs olute values of) VOLP a nd VOHV i s a mea-
sure o f the “quietness” of the p ackag e . The TSSOP is 500mV
(36%) quieter than the SOIC.
And Then There is H ys teresis...
Hysteresis reduces the effects of ground bounce and VCC
bounce by increasing the threshold during a LOW to HIGH
transition of the input signal and decreasing the threshold dur-
ing a HIGH to LOW transition of the input signal. This is illus-
trated graphica lly in
Figure 5
. The wide dashe d line illustrates
the transfer function of a logic inversion without hysteresis.
The solid lines and rectangle show the same function with
hysteresis. All FCT inputs have 100 mV of hysteresis, or 50
mV in each direction. This translates into 50 mV of additional
noise immunity in each directi on.
Real World Noise Budget
For example, the amplitude of the VOLP pulse for the 48-lead
TSSOP is 0.57V. This appears to be 0.57V – 0.4V=0.17V
greater than the low-level noise immunity. Howev er , in reality ,
the threshold voltage is 1.5V + 0.05V = 1.55V. So
1.55V – 0.57V = 0.98V of noise immunity remains.
The amplitude of the VOHV pulse for the 48-lead TSSOP is
–0.33V. If VOH is 2.4V, the voltage level becomes 2.4V –
0.44V = 2.07V, which is 70 mV above the m inimum TTL spec-
ification. However, in reality, the threshold voltage is 1.5V –
0.05V = 1.45V, and the VOH level is 4V. So 4V – 0.33V =
3.67V – 1.45 V= 2.22V of noise immunity remains.
Test Results for 16-bit L atches and Buffers in
SSOP
Test results for high drive and balanced d riv e 37 3 type l atc hes
in the SSOP are summarized in
Table 2
.
The ground bounce of the balanced drive device is seen to
be 0.681V–0.513V=0.168V less than that of the high drive
device. This is a 25% noise reduction.
Adding VOLP and VOHV (absolute value) s hows that the bal-
anced drive device is 180 mV quieter. This is a 15% noise
reduction.
Balanced drive devices are recommended in all applications
except for driving heavily capacitively loaded backplanes
where i n cid ent wave switching is required.
Test results for h igh drive an d balanced drive 244 ty pe buffers
in the SSOP are summarized in
Table 3
.
The ground bounce of the balanced drive device is 75 mV
less than that of the high drive device. This is a 14% noise
reduction.
Adding VOLP and VOHV (absolute value) s hows that the bal-
anced drive device is 190 mV quieter. This is a 17% noise
reduction.
Summary
The combination of hysteresis, bal anced drive, internal edge
control, low power CMOS, and the 48-lead TSSOP signifi-
cantly reduce system noise and increase package density
withou t dec reas ing speed o r wasting power. FCT logic dev ic-
es from Cypress at competitive prices give your products the
edge.
Figure 5. FCT Hysteresis
VOH
VOL
VT
VT+V
h
–V
h
V
h=50mV
V
T
V
T= 1.5V
Vin in Volts
Vout
T able 2. Ground and VCC Bounce, in V olts, 16-bit, 373 FCT,
in SSOP.
Ta = 25 Celsius, VCC = 5V.
Parameter CY16373
(high drive) CY162373
(balanced)
VOLP 0.681 0.513
VOLV –0.694 –0.556
VOHP 0.413 0.344
VOHV –0.500 –0.488
T able 3. Ground and VCC Bounce, in V olts, 16-bit, 244 FCT,
in SSOP.
Ta = 25 Celsius, V CC = 5 V.
Parameter CY16244
(high drive) CY162244
(balanced)
VOLP 0.538 0.463
VOLV –0.781 –0.506
VOHP 0.406 0.388
VOHV –0.575 –0.463
