CYUSB202X
SD2™ USB and Mass Storage Peripheral Controller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-87710 Rev. *A Revised September 5, 2013
Features
■Latest-generation storage support
❐SD2.0/SDXC – UHS1 SDR50 / DDR50 Master
❐eMMC 4.4 Master
❐SDIO 3.0 Master
■USB integration
❐Certified USB 2.0 peripheral: Hi-Speed (HS), and Full-Speed
(FS) only)
❐Thirty-two physical endpoints
❐Integrated transceiver
❐Accessory charger adaptor (ACA) support
■Ultra low-power in core power-down mode
❐Less than 60 µA with VBATT on and 20 µA with VBATT off
■I2C master controller at 1 MHz
■Selectable input clock frequencies
❐19.2, 26, 38.4, and 52 MHz
❐19.2-MHz crystal input support
■Independent power domains for core and I/O
■10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package
Applications
■USB thumb drives
■Card readers
■Laptop with SD slots
■SD slot in TV/STB
■WIFI Dongles
■USB SDIO Bridge
Logic Block Diagram
USB
EPs
GPIOs HS/FS
Peripheral
D+
D-
USB INTERFACE
SDIO/SD/MMC Controller
S0-PORT S1-PORT
I2C
I2C_SCL
I2C_SDA
FSLC[0]
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
XTALIN
XTALOUT
S0_SD0
S0_SD1
S0_SD2
S0_SD3
S0_SD4
S0_SD5
S0_SD6
S0_SD7
S0_CMD
S0_CLK
S0_WP
S0S1_INS
MMC0_RST_OUT
S1_SD0
S1_SD1
S1_SD2
S1_SD3
S1_SD4
S1_SD5
S1_SD6
S1_SD7
S1_CMD
S1_CLK
MMC1_RST_OUT
S1_WP
ARM926EJ-S
JTAG
Embedded
SRAm
(512 kB/
256 KB)
TDI
TDO
TRST#
TMS
TCK
UART
SPI
I2S
CYUSB202X
Document Number: 001-87710 Rev. *A Page 2 of 27
Contents
Functional Overview ........................................................ 3
USB Interface (U-Port) ................................................3
Mass-Storage Support (S-Port) ................................... 3
I2C Interface ................................................................ 3
UART Interface ............................................................3
I2S Interface ................................................................ 3
SPI Interface ................................................................4
Boot Options ................................................................ 4
Reset ...........................................................................4
Clocking .......................................................................4
32-kHz Watchdog Timer Clock Input ........................... 4
Power ..........................................................................5
Configuration Fuse ......................................................8
Digital I/Os ...................................................................8
EMI .............................................................................. 8
System Level ESD ...................................................... 8
Pinout for BGA ..................................................................8
Pin Description for BGA ..................................................9
AC Timing Parameters ................................................... 12
Storage Port Timing .................................................. 12
I2C Interface Timing .................................................. 15
Absolute Maximum Ratings .......................................... 20
Operating Conditions ..................................................... 20
DC Specifications ........................................................... 20
Reset Sequence .............................................................. 22
Package Diagram ............................................................ 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Acronyms ........................................................................ 25
Document Conventions ................................................. 25
Units of Measure ....................................................... 25
Document History Page ................................................. 26
Sales, Solutions, and Legal Information ...................... 27
Worldwide Sales and Design Support ....................... 27
Products .................................................................... 27
PSoC® Solutions ...................................................... 27
Cypress Developer Community ................................. 27
Technical Support ..................................................... 27
CYUSB202X
Document Number: 001-87710 Rev. *A Page 3 of 27
Functional Overview
SD2™ is a USB 2.0 High Speed mass-storage controller
providing the latest SD/MMC support. SD2 complies with the SD
Specification, Version 3.0, and the MMC Specification, Version
4.41.
SD2 offers the following access paths among USB and mass
storage ports:
■A USB-port (U-Port) supporting USB 2.0 peripheral
■Two mass-storage ports (S0-Port and S1-Port) supporting
mass-storage devices. Following are the possible configura-
tions for the two mass-storage ports:
❐SD and MMC
❐SD and SD
❐MMC and MMC
❐SD and SDIO
❐MMC and SDIO
❐SDIO and SDIO
Combinations of these accesses can happen independently or
in an interleaved manner.
The SD2 complies with the USB 2.0 specification.
USB Interface (U-Port)
SD2 offers the following features:
■Supports USB peripheral functionality compliant with the USB
2.0 Specification
■Supports up to 16 IN and 16 OUT endpoints.
■Supports the USB 2.0 Streams feature. It also supports USB
Attached SCSI (UAS) device class to optimize mass-storage
access performance.
■As a USB peripheral, SD2 supports UAS and Mass Storage
Class (MSC) peripheral classes.
■When the USB port is not in use, the PHY and transceiver may
be disabled for power savings.
Figure 1. USB Interface Signals
Mass-Storage Support (S-Port)
The SD2 storage interface port supports the following
specifications:
■SD Specification, Version 3.0
■Multimedia Card-System Specification, MMCA Technical
Committee, Version 4.4
■SDIO Host controller compliant with SDIO Specification
Version 3.00
I2C Interface
SD2 has an I2C interface compatible with the I2C Bus
Specification Revision 3. Because SD2’s I2C interface is capable
of operating only as I2C master, it may be used to communicate
with other I2C slave devices. For example, SD2 may boot from
an EEPROM connected to the I2C interface, as a selectable boot
option.
SD2’s I2C master controller also supports multi-master mode
functionality.
The power supply for the I2C interface is VIO5, which is a
separate power domain from the other serial peripherals. This is
to allow the I2C interface the flexibility to operate at a different
voltage than the other serial interfaces.
The I2C controller supports bus frequencies of 100 kHz,
400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum
operating frequency supported is 100 kHz. When VIO5 is 1.8 V,
2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz
and 1 MHz. The I2C controller supports the clock stretching
feature to enable slower devices to exercise flow control.
Both SCL and SDA signals of the I2C interface require external
pull-up resistors. These resistors must be connected to VIO5.
UART Interface
The UART interface of SD2 supports full-duplex communication.
It includes the signals noted in Table 1.
The UART is capable of generating a range of baud rates, from
300 bps to 4608 Kbps, selectable by the firmware. If flow control
is enabled, then SD2’s UART only transmits data when the CTS
input is asserted. In addition to this, SD2’s UART asserts the
RTS output signal, when it is ready to receive data.
I2S Interface
SD2 has an I2S port to support external audio codec devices.
SD2 functions as I2S Master as transmitter only. The I2S
interface consists of four signals: clock line (I2S_CLK), serial
data line (I2S_SD), word select line (I2S_WS), and master
system clock (I2S_MCLK). SD2 can generate the system clock
as an output on I2S_MCLK or accept an external system clock
input on I2S_MCLK.
SD3
VBATT
VBUS
USB Interface
D-
D+
Table 1. UART Interface Signals
Signal Description
TX Output signal
RX Input signal
CTS Flow control
RTS Flow control
CYUSB202X
Document Number: 001-87710 Rev. *A Page 4 of 27
The sampling frequencies supported by the I2S interface are
32 kHz, 44.1 kHz, and 48 kHz.
SPI Interface
SD2 supports an SPI Master interface on the Serial Peripherals
port. The maximum operation frequency is 33 MHz.
The SPI controller supports four modes of SPI communication
(see SPI Timing Specification on page 18 for details on the
modes) with the Start-Stop clock. This controller is a
single-master controller with a single automated SSN control. It
supports transaction sizes ranging from 4 bits to 32 bits.
Boot Options
SD2 can load boot images from various sources, selected by the
configuration of the PMODE pins. The boot options for the SD2
are as follows:
■Boot from USB
■Boot from I2C
■Boot from eMMC on S0-Port
■Boot from SPI
Reset
A reset is initiated by asserting the Reset# pin on SD2. The
specific reset sequence and timing requirements are detailed in
Figure 3 on page 15 and Table 13 on page 22. All I/Os are
tristated during a hard reset.
Clocking
SD2 allows either a crystal to be connected between the XTALIN
and XTALOUT pins or an external clock to be connected at the
CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins
can be left unconnected if not used.
Crystal frequency supported is 19.2 MHz, while the external
clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.
SD2 has an on-chip oscillator circuit that uses an external
19.2 MHz (±100 ppm) crystal (when the crystal option is used).
An appropriate load capacitance is required with a crystal. Refer
to the specification of the crystal used to determine the appro-
priate load capacitance. The FSLC[2:0] pins must be configured
appropriately to select the crystal option/clock frequency option.
The configuration options are shown in Table 3.
Clock inputs to SD2 must meet the phase noise and jitter require-
ments specified in Table 4.
The input clock frequency is independent of the clock/data rate
of SD2 core or any of the device interfaces. The internal PLL
applies the appropriate clock multiply option depending on the
input frequency.
32-kHz Watchdog Timer Clock Input
SD2 includes a watchdog timer that can be used to interrupt the
core, automatically wake up SD2 in Standby mode, and reset the
core. The watchdog timer runs off a 32-kHz clock, which may
optionally be supplied from an external source on a dedicated
pin of SD2.
The watchdog timer can be disabled by firmware.
Requirements for the optional 32-kHZ clock input are listed in
Tab le 4 .
Table 2. Booting Options for SD2
PMODE[2:0][1] Boot From
FF0 S0-Port: eMMC
On failure, USB boot enabled
FF1 USB Boot
FFF I2C
On Failure, USB Boot is enabled
0FF I2C only
0F1 SPI
On Failure, USB Boot is enabled
Note
1. F indicates Floating.
Table 3. Crystal/Clock Frequency Selection
FSLC[2] FSLC[1] FSLC[0] Crystal/Clock
Frequency
0 0 0 19.2-MHz crystal
1 0 0 19.2-MHz input CLK
1 0 1 26-MHz input CLK
1 1 0 38.4-MHz input CLK
1 1 1 52-MHz input CLK
Table 4. Input Clock Specifications for SD2
Parameter Description Specification Units
Min Max
Phase noise 100-Hz offset – –75 dB
1-kHz offset – –104 dB
10-kHz offset – –120 dB
100-kHz offset – –128 dB
1-MHz offset – –130 dB
Maximum frequency
deviation
–150ppm
Duty cycle 30 70 %
Overshoot – 3 %
Undershoot – –3 %
Rise time/fall time – 3 ns
Table 5. 32-kHz Clock Input Requirements
Parameter Min Max Units
Duty cycle 40 60 %
Frequency deviation – ±200 ppm
Rise Time/fall Time – 200 ns
CYUSB202X
Document Number: 001-87710 Rev. *A Page 5 of 27
Power
SD2 has the following main groups of power supply domains:
■IO_VDDQ: This refers to a group of independent supply
domains for digital I/Os. The voltage level on these supplies
are 1.8 V to 3.3 V. SD2 provides six independent supply
domains for digital I/Os listed as follows:
❐VIO2: S0-Port (for SD/MMC) I/O Power Supply Domain
❐VIO3: S1-Port (for SD/MMC) I/O Power Supply Domain
❐VIO1: S2-Port (GPIO) Power Supply Domain
❐VIO4: S1-Port GPIO[53:57]/O Power Supply Domain (these
pins support MMC’s high nibble data line - D[7:4] on S1-Port)
❐VIO5: I2C Power Supply Domain (supports 1.2 V to 3.3 V)
❐CVDDQ: Clock Power Supply Domain
■VDD: This is the supply voltage for the logic core. The nominal
supply voltage level is 1.2 V. This supplies the core logic
circuits. The same supply must also be used for the following:
❐AVDD: This is the 1.2-V supply for the PLL, crystal oscillator
and other core analog circuits
■VBATT/VBUS: This is the 3.2-V to 6-V battery power supply
for the USB I/O and analog circuits. This supply powers the
USB transceiver through SD2’s internal voltage regulator.
VBATT is internally regulated to 3.3 V.
Power Modes
SD2 supports the following power modes:
■Normal mode: This is the full-functional operating mode. In this
mode the internal CPU clock and the internal PLLs are enabled.
Normal operating power consumption does not exceed the sum
of ICC_CORE max and ICC_USB max (see Table 8 on page 12
for current consumption specifications).
The I/O power supplies (VIO2, VIO3, VIO4, and VIO5) may be
turned off when the corresponding interface is not in use.
S2VDDQ cannot be turned off at any time if the S2-Port is used
in the application.
■SD2 supports four low-power modes (see Table 6 on page 5):
❐Suspend mode with USB 2.0 PHY enabled (L1 mode)
❐Suspend mode with USB 2.0 PHY disabled (L2 mode)
❐Standby mode (L3 mode)
❐Core power-down mode (L4 mode)
Table 6. Entry and Exit Methods for Low-Power Modes
Low Power Mode Characteristics Methods of Entry Methods of Exit
Suspend mode with
USB 2.0 PHY
Enabled (L1 mode)
■The power consumption in this
mode does not exceed ISB1
■USB 2.0 PHY is enabled and is in
U3 mode (one of the suspend
modes defined by the USB 3.0
specification). This one block
alone operates with its internal
clock while all other clocks are
shut down
■All I/Os maintain their previous
state
■Power supply for the wakeup
source and core power must be
retained. All other power domains
can be turned on/off individually
■The states of the configuration
registers, buffer memory and all
internal RAM are maintained
■All transactions must be
completed before SD2 enters
Suspend mode (state of
outstanding transactions are not
preserved)
■The firmware resumes operation
from where it was suspended
(except when woken up by
RESET# assertion) because the
program counter does not reset
■Firmware executing on the core can
put SD2 into suspend mode. For
example, on USB suspend
condition, firmware may decide to
put SD2 into suspend mode
■D+ transitioning to low or high
■D– transitioning to low or high
■Resume condition on SSRX +/-
■Detection of VBUS
■Assertion of GPIO[17]
■Assertion of RESET#
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Document Number: 001-87710 Rev. *A Page 6 of 27
Suspend mode with
USB 2.0 PHY
disabled (L2 mode)
■The power consumption in this
mode does not exceed ISB2
■USB 2.0 PHY is disabled and the
USB interface is in suspend mode
■The clocks are shut off. The PLLs
are disabled
■All I/Os maintain their previous
state
■USB interface maintains the
previous state
■Power supply for the wakeup
source and core power must be
retained. All other power domains
can be turned on/off individually
■The states of the configuration
registers, buffer memory, and all
internal RAM are maintained
■All transactions must be
completed before SD2 enters
Suspend mode (state of
outstanding transactions are not
preserved)
■The firmware resumes operation
from where it was suspended
(except when woken up by
RESET# assertion) because the
program counter does not reset
■Firmware executing on the core can
put SD2 into suspend mode. For
example, on USB suspend
condition, firmware may decide to
put SD2 into suspend mode
■D+ transitioning to low or high
■D– transitioning to low or high
■Resume condition on SSRX +/-
■Detection of VBUS
■Assertion of GPIO[17]
■Assertion of RESET#
Table 6. Entry and Exit Methods for Low-Power Modes (continued)
Low Power Mode Characteristics Methods of Entry Methods of Exit
CYUSB202X
Document Number: 001-87710 Rev. *A Page 7 of 27
Standby Mode (L3
mode)
■The power consumption in this
mode does not exceed ISB3
■All configuration register settings
and program/data RAM contents
are preserved. However, data in
the buffers or other parts of the
data path, if any, is not
guaranteed. Therefore, the
external processor should take
care that needed data is read
before putting SD2 into this
Standby Mode
■The program counter is reset
after waking up from Standby
■GPIO pins maintain their
configuration
■Crystal oscillator is turned off
■Internal PLL is turned off
■USB transceiver is turned off
■Core is powered down. Upon
wakeup, the core re-starts and
runs the program stored in the
program/data RAM
■Power supply for the wakeup
source and core power must be
retained. All other power domains
can be turned on/off individually
■Firmware executing on the core or
external processor configures the
appropriate register
■Detection of VBUS
■Assertion of GPIO[17]
■Assertion of RESET#
Core Power Down
Mode (L4 mode)
■The power consumption in this
mode does not exceed ISB4
■Core power is turned off
■All buffer memory, configuration
registers and the program RAM
do not maintain state. It is
necessary to reload the firmware
on exiting from this mode
■In this mode, all other power
domains can be turned on/off
individually
■Turn off VDD ■Reapply VDD
■Assertion of RESET#
Table 6. Entry and Exit Methods for Low-Power Modes (continued)
Low Power Mode Characteristics Methods of Entry Methods of Exit
CYUSB202X
Document Number: 001-87710 Rev. *A Page 8 of 27
Configuration Fuse
Fuse options are available for specific usage models. Contact
Cypress Applications/Marketing for details.
Digital I/Os
SD2 provides firmware controlled pull-up or pull-down resistors
internally on all digital I/O pins. The pins can be pulled high
through an internal 50-k resistor or can be pulled low through
an internal 10-k resistor to prevent the pins from floating. The
I/O pins may have the following states:
■Tristated (High-Z)
■Weak pull-up (through internal 50 k)
■Pull down (through internal 10 k)
■Hold (I/O hold its value) when in low power modes
All unused I/Os should be pulled high by using the internal
pull-up resistors. All unused outputs should be left floating. All
I/Os can be driven at full-strength, three-quarter strength,
half-strength, or quarter-strength. These drive strengths are
configured based on each interface.
EMI
SD2 meets EMI requirements outlined by FCC 15B (USA) and
EN55022 (Europe) for consumer electronics. SD2 can tolerate
reasonable EMI, conducted by aggressor, outlined by these
specifications and continue to function as expected.
System Level ESD
SD2 has built-in ESD protection on the D+, D–, GND pins on the
USB interface. The ESD protection levels provided on these
ports are:
■±2.2-KV human body model (HBM) based on JESD22-A114
Specification
■±6-KV contact discharge and ±8-KV air gap discharge based
on IEC61000-4-2 level 3A
■±8-KV contact discharge and ±15-KV air gap discharge based
on IEC61000-4-2 level 4C.
This protection ensures the device continues to function after
ESD events up to the levels stated.
The S0/S1_INS have up to ±2.2 KV HBM internal ESD
protection.
Pinout for BGA
Figure 2. SD2 BGA Ball Map (Top View)
12 3 4 56 78 91011
AU3VSSQ U3 RX V D DQ SSR X M SSR X P SSTX P SSTX M AVDD VSS DP DM NC
BVIO4 FSLC[0] R_USB3 FSLC[1] U3TXVDDQ CVDDQ AVSS VSS VSS VDD NC
CGPIO[54] GPIO[55] VDD GPIO[57] RESET# XTALIN XTALOUT R_USB2 OTG_ID NC VIO5
DGPIO[ 50 ] GPIO[ 51] GPIO[ 52 ] GPIO[ 53 ] GPIO[ 56 ] CLKIN_ 3 2 CLKIN V SS I2 C_ GPIO[ 58 ] I2 C_ GPIO[ 59 ] O[ 6 0 ]
EGPIO[ 4 7] VSS S1VDDQ GPIO[49] GPIO[48] FSLC[2] NC NC VDD VBATT VBUS
FS0 V DD Q GPIO[ 4 5] GPIO[ 4 4 ] GPIO[ 4 1] GPIO[ 4 6 ] N C GPIO[ 2 ] GPIO[ 5] GPIO[ 1] GPIO[ 0 ] V D D
GVSS GPIO[ 4 2] GPIO[ 4 3] GPIO[ 3 0] GPIO[ 2 5] GPIO[ 22 ] GPIO[ 21] GPIO[ 15] GPIO[ 4] GPIO[ 3] VSS
HV DD GPIO[ 3 9] GPIO[ 4 0] GPIO[ 3 1] GPIO[ 29 ] GPIO[ 26 ] GPIO[ 20 ] GPIO[ 24 ] GPIO[ 7] GPIO[ 6] S2 VDDQ
JGPIO[ 38 ] GPIO[ 3 6] GPIO[ 3 7] GPIO[ 34 ] GPIO[ 28 ] GPIO[ 16 ] GPIO[ 19 ] GPIO[ 14 ] GPIO[ 9] GPIO[ 8] V DD
KGPIO[ 3 5] GPIO[ 3 3 ] VSS VSS GPIO[27] GPIO[23] GPIO[18] GPIO[17] GPIO[13] GPIO[12] GPIO[10]
LVSS VSS VSS GPIO[ 3 2 ] V DD VSS V D D N C S 2 V D D Q G PI O[ 11] VSS
CYUSB202X
Document Number: 001-87710 Rev. *A Page 9 of 27
Pin Description for BGA
Table 7. Pin List
Pin
No.
Power
Domain I/O Name Description
S2-PORT (GPIO)
F10 VI01 I/O GPIO[0] GPIO
F9 VI01 I/O GPIO[1] GPIO
F7 VI01 I/O GPIO[2] GPIO
G10 VI01 I/O GPIO[3] GPIO
G9 VI01 I/O GPIO[4] GPIO
F8 VI01 I/O GPIO[5] GPIO
H10 VI01 I/O GPIO[6] GPIO
H9 VI01 I/O GPIO[7] GPIO
J10 VI01 I/O GPIO[8] GPIO
J9 VI01 I/O GPIO[9] GPIO
K11 VI01 I/O GPIO[10] GPIO
L10 VI01 I/O GPIO[11] GPIO
K10 VI01 I/O GPIO[12] GPIO
K9 VI01 I/O GPIO[13] GPIO
J8 VI01 I/O GPIO[14] GPIO
G8 VI01 I/O GPIO[15] GPIO
J6 VI01 I/O GPIO[16] GPIO
K8 VI01 I/O GPIO[17] GPIO
K7 VI01 I/O GPIO[18] GPIO
J7 VI01 I/O GPIO[19] GPIO
H7 VI01 I/O GPIO[20] GPIO
G7 VI01 I/O GPIO[21] GPIO
G6 VI01 I/O GPIO[22] GPIO
K6 VI01 I/O GPIO[23] GPIO
H8 VI01 I/O GPIO[24] GPIO
G5 VI01 I/O GPIO[25] GPIO
H6 VI01 I/O GPIO[26] GPIO
K5 VI01 I/O GPIO[27] GPIO
J5 VI01 I/O GPIO[28] GPIO
H5 VI01 I/O GPIO[29] GPIO
G4 VI01 I/O GPIO[30] PMODE[0]
H4 VI01 I/O GPIO[31] PMODE[1]
L4 VI01 I/O GPIO[32] PMODE[2]
L8 NC No Connect
C5 CVDDQ I RESET# Active Low. Hardware Reset.
8b MMC
Configuration
SD+GPIO
Configuration
GPIO
Configuration
K2 VI02 I/O GPIO[33] S0_SD0 S0_SD0 GPIO
J4 VI02 I/O GPIO[34] S0_SD1 S0_SD1 GPIO
K1 VI02 I/O GPIO[35] S0_SD2 S0_SD2 GPIO
J2 VI02 I/O GPIO[36] S0_SD3 S0_SD3 GPIO
J3 VI02 I/O GPIO[37] S0_SD4 GPIO GPIO
J1 VI02 I/O GPIO[38] S0_SD5 GPIO GPIO
CYUSB202X
Document Number: 001-87710 Rev. *A Page 10 of 27
H2 VI02 I/O GPIO[39] S0_SD6 GPIO GPIO
H3 VI02 I/O GPIO[40] S0_SD7 GPIO GPIO
F4 VI02 I/O GPIO[41] S0_CMD S0_CMD GPIO
G2 VI02 I/O GPIO[42] S0_CLK S0_CLK GPIO
G3 VI02 I/O GPIO[43] S0_WP S0_WP GPIO
F3 VI02 I/O GPIO[44] S0S1_INS S0S1_INS GPIO
F2 VI02 I/O GPIO[45] MMC0_RST_OUT GPIO GPIO
8b MMC SD+UART SD+SPI SD+GPIO GPIO
GPIO+
UART+I2S SD+I2S
UART+SPI+
I2S
F5 VI03 I/O GPIO[46] S1_SD0 S1_SD0 S1_SD0 S1_SD0 GPIO GPIO S1_SD0 UART_RTS
E1 VI03 I/O GPIO[47] S1_SD1 S1_SD1 S1_SD1 S1_SD1 GPIO GPIO S1_SD1 UART_CTS
E5 VI03 I/O GPIO[48] S1_SD2 S1_SD2 S1_SD2 S1_SD2 GPIO GPIO S1_SD2 UART_TX
E4 VI03 I/O GPIO[49] S1_SD3 S1_SD3 S1_SD3 S1_SD3 GPIO GPIO S1_SD3 UART_RX
D1 VI03 I/O GPIO[50] S1_CMD S1_CMD S1_CMD S1_CMD GPIO I2S_CLK S1_CMD I2S_CLK
D2 VI03 I/O GPIO[51] S1_CLK S1_CLK S1_CLK S1_CLK GPIO I2S_SD S1_CLK I2S_SD
D3 VI03 I/O GPIO[52] S1_WP S1_WP S1_WP S1_WP GPIO I2S_WS S1_WP I2S_WS
D4 VIO4 I/O GPIO[53] S1_SD4 UART_RTS SPI_SCK GPIO GPIO UART_RTS GPIO SPI_SCK
C1 VIO4 I/O GPIO[54] S1_SD5 UART_CTS SPI_SSN GPIO GPIO UART_CTS I2S_CLK SPI_SSN
C2 VIO4 I/O GPIO[55] S1_SD6 UART_TX SPI_MISO GPIO GPIO UART_TX I2S_SD SPI_MISO
D5 VIO4 I/O GPIO[56] S1_SD7 UART_RX SPI_MOSI GPIO GPIO UART_RX I2S_WS SPI_MOSI
C4 VIO4 I/O GPIO[57] MMC1_RST_OUT GPIO GPIO GPIO GPIO I2S_MCLK I2S_MCLK I2S_MCLK
C9 NC No Connect
A3 NC USB 3.0 SuperSpeed Receive Minus
A4 NC USB 3.0 SuperSpeed Receive Plus
A6 NC USB 3.0 SuperSpeed Transmit Minus
A5 NC USB 3.0 SuperSpeed Transmit Plus
A9 VBATT/
VBUS
I/O D+ USB (HS/FS) Data Plus
A10 VBATT/
VBUS
I/O D- USB (HS/FS) Data Minus
A11 NC No Connect
B2 CVDDQ I FSLC[0] FSLC[0]
C6 AVDD I/O XTALIN XTALIN
C7 AVDD I/O XTALOUT XTALOUT
B4 CVDDQ I FSLC[1] FSLC[1]
E6 CVDDQ I FSLC[2] FSLC[2]
D7 CVDDQ I CLKIN CLKIN
D6 CVDDQ I CLKIN_32 CLKIN_32
D9 VIO5 I/O I2C_GPIO[58] SCL (Serial Clock) for I2C Bus Interface
D10 VIO5 I/O I2C_GPIO[59] SDA (Serial Data) for I2C Bus Interface
E7 NC No Connect
C10 NC No Connect
B11 NC No Connect
E8 NC No Connect
F6 NC No Connect
D11 VIO5 O O[60] Output only
Table 7. Pin List (continued)
Pin
No.
Power
Domain I/O Name Description
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Document Number: 001-87710 Rev. *A Page 11 of 27
E10 PWR VBATT
B10 PWR VDD
A1 PWR VSS
E11 PWR VBUS
D8 PWR VSS
H11 PWR VIO1
E2 PWR VSS
L9 PWR VIO1
G1 PWR VSS
F1 PWR VIO2
G11 PWR VSS
E3 PWR VIO3
L1 PWR VSS
B1 PWR VIO4
L6 PWR VSS
B6 PWR CVDDQ
B5 NC
A2 NC
C11 PWR VIO5
L11 PWR VSS
A7 PWR AVDD
B7 PWR AVSS
C3 PWR VDD
B8 PWR VSS
E9 PWR VDD
B9 PWR VSS
F11 PWR VDD
H1 PWR VDD
L7 PWR VDD
J11 PWR VDD
L5 PWR VDD
K4 PWR VSS
L3 PWR VSS
K3 PWR VSS
L2 PWR VSS
A8 PWR VSS
Precision Resistors
C8 VBUS/
VBATT
I/O R_usb2 Precision resistor for USB 2.0 (Connect a 6.04 k+/-1% resistor between this pin and GND)
B3 NC Precision resistor for USB 3.0 (Connect a 200 +/-1% resistor between this pin and GND)
Table 7. Pin List (continued)
Pin
No.
Power
Domain I/O Name Description
CYUSB202X
Document Number: 001-87710 Rev. *A Page 12 of 27
AC Timing Parameters
Storage Port Timing
The S0-Port and S1-Port support the MMC Specification Version 4.4 and SD Specification Version 2.0. Tab le 7 lists the timing
parameters for S0-Port and S1-Port of SD2.
Table 8. S-Port Timing Parameters[2]
Parameter Description Min Max Units
MMC-20
tSDIS CMD Host input setup time for CMD 4.8 – ns
tSDIS DAT Host input setup time for DAT 4.8 – ns
tSDIH CMD Host input hold time for CMD 4.4 – ns
tSDIH DAT Host input hold time for DAT 4.4 – ns
tSDOS CMD Host output setup time for CMD 5 – ns
tSDOS DAT Host output setup time for DAT 5 – ns
tSDOH CMD Host output hold time for CMD 5 – ns
tSDOH DAT Host output hold time for DAT 5 – ns
tSCLKR Clock rise time – 2 ns
tSCLKF Clock fall time – 2 ns
tSDCK Clock cycle time 50 – ns
SDFREQ Clock frequency 20 MHz
tSDCLKOD Clock duty cycle 40 60 %
MMC-26
tSDIS CMD Host input setup time for CMD 10 – ns
tSDIS DAT Host input setup time for DAT 10 – ns
tSDIH CMD Host input hold time for CMD 9 – ns
tSDIH DAT Host input hold time for DAT 9 – ns
tSDOS CMD Host output setup time for CMD 3 – ns
tSDOS DAT Host output setup time for DAT 3 – ns
tSDOH CMD Host output hold time for CMD 3 – ns
tSDOH DAT Host output hold time for DAT 3 – ns
tSCLKR Clock rise time – 2 ns
tSCLKF Clock fall time – 2 ns
tSDCK Clock cycle time 38.5 – ns
SDFREQ Clock frequency 26 MHz
tSDCLKOD Clock duty cycle 40 60 %
MC-HS
tSDIS CMD Host input setup time for CMD 4 – ns
tSDIS DAT Host input setup time for DAT 4 – ns
tSDIH CMD Host input hold time for CMD 3 – ns
tSDIH DAT Host input hold time for DAT 3 – ns
tSDOS CMD Host output setup time for CMD 3 – ns
tSDOS DAT Host output setup time for DAT 3 – ns
tSDOH CMD Host output hold time for CMD 3 – ns
tSDOH DAT Host output hold time for DAT 3 – ns
CYUSB202X
Document Number: 001-87710 Rev. *A Page 13 of 27
tSCLKR Clock rise time – 2 ns
tSCLKF Clock fall time – 2 ns
tSDCK Clock cycle time 19.2 – ns
SDFREQ Clock frequency – 52 MHz
tSDCLKOD Clock duty cycle 40 60 %
MMC-DDR52
tSDIS CMD Host input setup time for CMD 4 – ns
tSDIS DAT Host input setup time for DAT 0.56 – ns
tSDIH CMD Host input hold time for CMD 3 – ns
tSDIH DAT Host input hold time for DAT 2.58 – ns
tSDOS CMD Host output setup time for CMD 3 – ns
tSDOS DAT Host output setup time for DAT 2.5 – ns
tSDOH CMD Host output hold time for CMD 3 – ns
tSDOH DAT Host output hold time for DAT 2.5 – ns
tSCLKR Clock rise time – 2 ns
tSCLKF Clock fall time – 2 ns
tSDCK Clock cycle time 19.2 – ns
SDFREQ Clock frequency 52 MHz
tSDCLKOD Clock duty cycle 45 55 %
SD-Default Speed (SDR12)
tSDIS CMD Host input setup time for CMD 24 – ns
tSDIS DAT Host input setup time for DAT 24 – ns
tSDIH CMD Host input hold time for CMD 2.5 – ns
tSDIH DAT Host input hold time for DAT 2.5 – ns
tSDOS CMD Host output setup time for CMD 5 – ns
tSDOS DAT Host output setup time for DAT 5 – ns
tSDOH CMD Host output hold time for CMD 5 – ns
tSDOH DAT Host output hold time for DAT 5 – ns
tSCLKR Clock rise time – 2 ns
tSCLKF Clock fall time – 2 ns
tSDCK Clock cycle time 40 – ns
SDFREQ Clock frequency 25 MHz
tSDCLKOD Clock duty cycle 40 60 %
SD-High-Speed(SDR25)
tSDIS CMD Host input setup time for CMD 4 – ns
tSDIS DAT Host input setup time for DAT 4 – ns
tSDIH CMD Host input hold time for CMD 2.5 – ns
tSDIH DAT Host input hold time for DAT 2.5 – ns
tSDOS CMD Host output setup time for CMD 6 – ns
tSDOS DAT Host output setup time for DAT 6 – ns
tSDOH CMD Host output hold time for CMD 2 – ns
tSDOH DAT Host output hold time for DAT 2 – ns
Table 8. S-Port Timing Parameters[2] (continued)
Parameter Description Min Max Units
CYUSB202X
Document Number: 001-87710 Rev. *A Page 14 of 27
tSCLKR Clock rise time – 2 ns
tSCLKF Clock fall time – 2 ns
tSDCK Clock cycle time 20 – ns
SDFREQ Clock frequency – 50 MHz
tSDCLKOD Clock duty cycle 40 60 %
SD-SDR50
tSDIS CMD Host input setup time for CMD 1.5 – ns
tSDIS DAT Host input setup time for DAT 1.5 – ns
tSDIH CMD Host input hold time for CMD 2.5 – ns
tSDIH DAT Host input hold time for DAT 2.5 – ns
tSDOS CMD Host output setup time for CMD 3 – ns
tSDOS DAT Host output setup time for DAT 3 – ns
tSDOH CMD Host output hold time for CMD 0.8 – ns
tSDOH DAT Host output hold time for DAT 0.8 – ns
tSCLKR Clock rise time – 2 ns
tSCLKF Clock fall time – 2 ns
tSDCK Clock cycle time 10 – ns
SDFREQ Clock frequency 100 MHz
tSDCLKOD Clock duty cycle 40 60 %
SD-DDR50
tSDIS CMD Host input setup time for CMD 4 – ns
tSDIS DAT Host input setup time for DAT 0.92 – ns
tSDIH CMD Host input hold time for CMD 2.5 – ns
tSDIH DAT Host input hold time for DAT 2.5 – ns
tSDOS CMD Host output setup time for CMD 6 – ns
tSDOS DAT Host output setup time for DAT 3 – ns
tSDOH CMD Host output hold time for CMD 0.8 – ns
tSDOH DAT Host output hold time for DAT 0.8 – ns
tSCLKR Clock rise time – 2 ns
tSCLKF Clock fall time – 2 ns
tSDCK Clock cycle time 20 – ns
SDFREQ Clock frequency 50 MHz
tSDCLKOD Clock duty cycle 45 55 %
Table 8. S-Port Timing Parameters[2] (continued)
Parameter Description Min Max Units
Note
2. All parameters guaranteed by design and validated through characterization.
CYUSB202X
Document Number: 001-87710 Rev. *A Page 15 of 27
I2C Interface Timing
I2C Timing
Figure 3. I2C Timing Definition
Table 9. I2C Timing Parameters[3]
Parameter Description Min Max Units
I2C Standard Mode Parameters
fSCL SCL clock frequency 0 100 kHz
tHD:STA Hold time START condition 4 – µs
tLOW LOW period of the SCL 4.7 – µs
tHIGH HIGH period of the SCL 4 – µs
tSU:STA Setup time for a repeated START condition 4.7 – µs
tHD:DAT Data hold time 0 – µs
tSU:DAT Data setup time 250 – ns
tr Rise time of both SDA and SCL signals – 1000 ns
tf Fall time of both SDA and SCL signals – 300 ns
tSU:STO Setup time for STOP condition 4 – µs
tBUF Bus free time between a STOP and START condition 4.7 – µs
tVD:DAT Data valid time – 3.45 µs
tVD:ACK Data valid ACK – 3.45 µs
tSP Pulse width of spikes that must be suppressed by input filter n/a n/a
Note
3. All parameters guaranteed by design and validated through characterization.
CYUSB202X
Document Number: 001-87710 Rev. *A Page 16 of 27
I2C Fast Mode Parameters
fSCL SCL clock frequency 0 400 kHz
tHD:STA Hold time START condition 0.6 – µs
tLOW LOW period of the SCL 1.3 – µs
tHIGH HIGH period of the SCL 0.6 – µs
tSU:STA Setup time for a repeated START condition 0.6 – µs
tHD:DAT Data hold time 0 – µs
tSU:DAT Data setup time 100 – ns
tr Rise time of both SDA and SCL signals – 300 ns
tf Fall time of both SDA and SCL signals – 300 ns
tSU:STO Setup time for STOP condition 0.6 – µs
tBUF Bus-free time between a STOP and START condition 1.3 – µs
tVD:DAT Data valid time – 0.9 µs
tVD:ACK Data valid ACK – 0.9 µs
tSP Pulse width of spikes that must be suppressed by input filter 0 50 ns
I2C Fast Mode Plus Parameters (Not supported at I2C_VDDQ=1.2V)
fSCL SCL clock frequency 0 1000 kHz
tHD:STA Hold time START condition 0.26 – µs
tLOW LOW period of the SCL 0.5 – µs
tHIGH HIGH period of the SCL 0.26 – µs
tSU:STA Setup time for a repeated START condition 0.26 – µs
tHD:DAT Data hold time 0 – µs
tSU:DAT Data setup time 50 – µs
tr Rise time of both SDA and SCL signals – 120 ns
tf Fall time of both SDA and SCL signals – 120 ns
tSU:STO Setup time for STOP condition 0.26 – µs
tBUF Bus free time between a STOP and START condition 0.5 – µs
tVD:DAT Data valid time – 0.45 µs
tVD:ACK Data valid ACK – 0.55 µs
tSP Pulse width of spikes that must be suppressed by input filter 0 50 ns
Table 9. I2C Timing Parameters[3] (continued)
Parameter Description Min Max Units
CYUSB202X
Document Number: 001-87710 Rev. *A Page 17 of 27
I2S Timing Diagram
Figure 4. I2S Transmit Cycle
Table 10. I2S Timing Parameters[4]
Parameter Description Min Max Units
tT I2S transmitter clock cycle Ttr – ns
tTL I2S transmitter cycle LOW period 0.35 Ttr – ns
tTH I2S transmitter cycle HIGH period 0.35 Ttr – ns
tTR I2S transmitter rise time – 0.15 Ttr ns
tTF I2S transmitter fall time – 0.15 Ttr ns
tThd I2S transmitter data hold time 0 – ns
tTd I2S transmitter delay time – 0.8tT ns
Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).
Note
4. All parameters guaranteed by design and validated through characterization.
CYUSB202X
Document Number: 001-87710 Rev. *A Page 18 of 27
SPI Timing Specification
Figure 5. SPI Timing
LSB
LSB
MSB
MSB
LSB
LSB
MSB
MSB
tlead
tsck
tsdd
thoi
twsck twsck
tlag
td
v
trf
tssnh
tdis
tsdi
tlead
tsck
twsck twsck
tlag
trf
tssnh
tsdi
tdis
tdv
thoi
SSN
(output)
SCK
(CPOL=0,
Output)
SCK
(CPOL=1,
Output)
MISO
(input)
MOSI
(output)
SSN
(output)
SCK
(CPOL=0,
Output)
SCK
(CPOL=1,
Output)
MISO
(input)
MOSI
(output)
SPI Master Timing for CPHA = 0
SPI Master Timing for CPHA = 1
tdi
tdi
CYUSB202X
Document Number: 001-87710 Rev. *A Page 19 of 27
Table 11. SPI Timing Parameters[5]
Parameter Description Min Max Units
fop Operating frequency 0 33 MHz
tsck Cycle time 30 – ns
twsck Clock high/low time 13.5 – ns
tlead SSN-SCK lead time 1/2 tsck[6] - 5 1.5 tsck[6]+ 5 ns
tlag Enable lag time 0.5 1.5 tsck[6]+5 ns
trf Rise/fall time – 8 ns
tsdd Output SSN to valid data delay time – 5 ns
tdv Output data valid time – 5 ns
tdi Output data invalid 0 – ns
tssnh Minimum SSN high time 10 – ns
tsdi Data setup time input 8 – ns
thoi Data hold time input 0 – ns
tdis Disable data output on SSN high 0 – ns
Notes
5. All parameters guaranteed by design and validated through characterization.
6. Depends on LAG and LEAD setting in the SPI_CONFIG register.
CYUSB202X
Document Number: 001-87710 Rev. *A Page 20 of 27
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device.
Storage temperature .................................... –65 °C to +150 °C
Ambient temperature with
power supplied (Industrial) ............................ –40 °C to +85 °C
Supply voltage to ground potential
VDD, AVDDQ ..................................................................... 1.25 V
S2VDDQ,S1VDDQ, S0VDDQ, VIO4, VIO5 .............................. 3.6 V
U3TXVDDQ, U3RXVDDQ .................................................. 1.25 V
DC input voltage to any input pin .............................. VCC + 0.3
DC voltage applied to
outputs in High Z State ............................................. VCC + 0.3
(VCC is the corresponding I/O voltage)
Static discharge voltage ESD protection levels:
■±2.2-KV human body model (HBM) based on JESD22-A114
■Additional ESD Protection levels on D+, D–, VBUS, GND pins
U-port and GPIO pins LPP-Port
■±6-KV contact discharge, ±8-KV air gap discharge based on
IEC61000-4-2 level 3A, ±8-KV contact discharge, and ±15-KV
air gap discharge based on IEC61000-4-2 level 4C
Latch-up current ........................................................ > 200 mA
Maximum output short circuit current
for all I/O configurations. (Vout = 0 V) ........................ –100 mA
Operating Conditions
TA (ambient temperature under bias)
Industrial ........................................................ –40 °C to +85 °C
VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ
supply voltage .................................................. 1.15 V to 1.25 V
VBATT supply voltage .............................................. 3.2 V to 6 V
S2VDDQ, S1VDDQ, S0VDDQ, VIO4, CVDDQ
supply voltage ...................................................... 1.7 V to 3.6 V
VIO5 supply voltage ............................................ 1.15 V to 3.6 V
DC Specifications
Table 12. DC Specifications
Parameter Description Min Max Units Notes
VDD Core voltage supply 1.15 1.25 V 1.2-V typical
AVDD Analog voltage supply 1.15 1.25 V 1.2-V typical
VIO2 SD/ MMC/ CF I/O power supply domain 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical
VIO3 SD/MMC I/O power supply domain 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical
VIO1 GPIO/ CF I/O power supply domain 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical
VIO4 GPIO/ I/O power supply domain 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical
VBATT USB voltage supply 3.2 6 V 3.7-V typical
VBUS USB voltage supply 4.0 6 V 5-V typical
CVDDQ Clock voltage supply 1.7 3.6 V 1.8-, 3.3-V typical
VIO5 I2C voltage supply 1.2 3.3 V 1.2-,1.8-, 2.5-, and 3.3-V
typical
VIH1 Input HIGH voltage 1 0.625 × VCC VCC + 0.3 V For 2.0 V VCC 3.6 V (except
USB port).VCC is the corre-
sponding I/O voltage supply.
VIH2 Input HIGH voltage 2 VCC - 0.4 VCC + 0.3 V For 1.7 V VCC 2.0 V
(except USB port). VCC is the
corresponding I/O voltage
supply.
VIL Input LOW voltage –0.3 0.25 × VCC V VCC is the corresponding I/O
voltage supply.
VOH Output HIGH voltage 0.9 × VCC – V IOH (max) = –100 µA tested at
quarter drive strength. VCC is
the corresponding I/O voltage
supply.
VOL Output LOW voltage – 0.1 × VCC V IOL (min) = +100 µA tested at
quarter drive strength. VCC is
the corresponding I/O voltage
supply.
CYUSB202X
Document Number: 001-87710 Rev. *A Page 21 of 27
IIX Input leakage current for all pins except
SSTXP/SSXM/SSRXP/SSRXM
–1 1 µA All I/O signals held at VDDQ
(For I/Os that have a
pull-up/down resistor
connected, the leakage current
increases by VDDQ/Rpu or
VDDQ/RPD
IOZ Output High-Z leakage current for all pins
except SSTXP/SSXM/SSRXP/SSRXM
–1 1 µA All I/O signals held at VDDQ
ICC Core Core and Analog Voltage Operating
Current
– 150 mA Total current through AVDD,
VDD
ICC USB USB voltage supply operating current – 20 mA
ISB1 Total suspend current during Suspend
Mode with USB 3.0 PHY enabled (L1
mode)
– – mA Core current: 1.5 mA
I/O current: 20 uA
USB current: 2 mA
For typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25 C.)
ISB2 Total suspend current during Suspend
Mode with USB 3.0 PHYdisabled (L2
mode)
– – mA Core current: 250 uA
I/O current: 20 uA
USB current: 1.2 mA
For typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25 C.)
ISB3 Total Standby Current during Standby
Mode (L3 mode)
– – µA Core current: 60 uA
I/O current: 20 uA
USB current: 40 uA
For typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25 C.)
ISB4 Total Standby Current during Core Power
Down Mode (L4 mode)
– – µA Core current: 0 uA
I/O current: 20 uA
USB current: 40 uA
For typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25 C.)
VRAMP Voltage Ramp Rate on Core and I/O
Supplies
0.2 50 V/ms Voltage ramp must be
monotonic
VNNoise Level Permitted on VDD and I/O
Supplies
– 100 mV Max p-p noise level permitted
on all supplies except AVDD
VN_AVDD Noise Level Permitted on AVDD Supply – 20 mV Max p-p noise level permitted
on AVDD
Table 12. DC Specifications (continued)
Parameter Description Min Max Units Notes
CYUSB202X
Document Number: 001-87710 Rev. *A Page 22 of 27
Reset Sequence
The hard reset sequence requirements for SD2 are specified in the following table.
Figure 6. Reset Sequence
Table 13. Reset and Standby Timing Parameters
Parameter Definition Conditions Min (ms) Max (ms)
tRPW Minimum RESET# pulse width Clock Input 1 –
Crystal Input 1 –
tRH Minimum high on RESET# 5 –
tRR Reset Recovery Time (after which Boot loader begins
firmware download)
Clock Input 1 –
Crystal Input 5
tSBY Time to enter Standby/Suspend (from the time
MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)
–1
tWU Time to wakeup from standby Clock Input 1 –
Crystal Input 5 –
tWH Minimum time before Standby/Suspend source may
be reasserted
5–
VDD
(core)
xVDDQ
XTALIN/
CLKIN
RESET #
Mandatory
Reset Pulse Hard Reset
tRPW
tRh
Standby/
Suspend
Source
Standby/Suspend source Is asserted
(MAIN_POWER_EN/ MAIN_CLK_EN bit
is set)
Standby/Suspend
source Is deasserted
tSBY tWU
XTALIN/ CLKIN must be stable
before exiting Standby/Suspend
tRR
tWH
CYUSB202X
Document Number: 001-87710 Rev. *A Page 23 of 27
Package Diagram
Figure 7. 121-ball FBGA (10 × 10 × 1.20 mm) Package Outline, 001-54471
001-54471 *D
CYUSB202X
Document Number: 001-87710 Rev. *A Page 24 of 27
Ordering Information
Ordering Code Definitions
Table 14. Ordering Information
Ordering Code SD/eMMC SDIO Ports SRAM (KB) Package Type
CYUSB2024-BZXI 2 512 121-ball BGA
CYUSB2025-BZXI 2 512 121-ball BGA
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type:
BZ = 121-ball BGA
Marketing Part Number
Base Part Number for USB 2.0
Marketing Code: USB = USB Controller
Company ID: CY = Cypress
CY BZ X
USB 2XXX X
-
I
CYUSB202X
Document Number: 001-87710 Rev. *A Page 25 of 27
Acronyms Document Conventions
Units of Measure
Acronym Description
ACA accessory charger adaptor
BGA ball grid array
MMC multimedia card
PLL phase locked loop
SD secure digital
SDIO secure digital input / output
SLC single-level cell
USB universal serial bus
Symbol Unit of Measure
°C degree Celsius
µA microamperes
µs microseconds
mA milliamperes
Mbps Megabytes per second
MHz mega hertz
ms milliseconds
ns nanoseconds
ohms
pF pico Farad
Vvolts
CYUSB202X
Document Number: 001-87710 Rev. *A Page 26 of 27
Document History Page
Document Title: CYUSB202X, SD2™ USB and Mass Storage Peripheral Controller
Document Number: 001-87710
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 4016299 GSZ 05/31/2013 New data sheet.
*A 4114923 GSZ 09/05/2013 Changed status from “Company Confidential” to “Final”.
Updated in new template.
Document Number: 001-87710 Rev. *A Revised September 5, 2013 Page 27 of 27
SD3™ is the trademark of Cypress Semiconductor Corporation. All other products and company names mentioned in this document may be the trademarks of their respective holders.
CYUSB202X
© Cypress Semiconductor Corporation, 2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
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life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Use may be limited by and subject to the applicable Cypress software license agreement.
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